Low Cost 270 MHz
Differential Receiver Amplifiers
AD8129/AD8130
Rev. C
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FEATURES
High speed
AD8130: 270 MHz, 1090 V/μs @ G = +1
AD8129: 200 MHz, 1060 V/μs @ G = +10
High CMRR
94 dB min, dc to 100 kHz
80 dB min @ 2 MHz
70 dB @ 10 MHz
High input impedance: 1 MΩ differential
Input common-mode range ±10.5 V
Low noise
AD8130: 12.5 nV/√Hz
AD8129: 4.5 nV/√Hz
Low distortion, 1 V p-p @ 5 MHz
AD8130, −79 dBc worst harmonic @ 5 MHz
AD8129, −74 dBc worst harmonic @ 5 MHz
User-adjustable gain
No external components for G = +1
Power supply range +4.5 V to ±12.6 V
Power-down
APPLICATIONS
High speed differential line receivers
Differential-to-single-ended converters
High speed instrumentation amps
Level shifting
CONNECTION DIAGRAM
AD8129/
AD8130
1
2
3
4
+IN –IN
–
VS+VS
PD OUT
REF FB
8
7
6
5
+
02464-001
Figure 1.
The AD8129/AD8130 are differential-to-single-ended amplifiers
with extremely high CMRR at high frequency. Therefore, they
can also be effectively used as high speed instrumentation amps
or for converting differential signals to single-ended signals.
The AD8129 is a low noise, high gain (10 or greater) version
intended for applications over very long cables, where signal
attenuation is significant. The AD8130 is stable at a gain of 1
and can be used for applications where lower gains are required.
Both have user-adjustable gain to help compensate for losses in
the transmission line. The gain is set by the ratio of two resistor
values. The AD8129/AD8130 have very high input impedance
on both inputs, regardless of the gain setting.
GENERAL DESCRIPTION
The AD8129/AD8130 are designed as receivers for the
transmission of high speed signals over twisted-pair cables to
work with the AD8131 or AD8132 drivers. Either can be used
for analog or digital video signals and for high speed data
transmission.
120
110
100
90
80
70
60
50
40
3010k 100k 1M 10M 100M
FREQUENCY (Hz)
CMRR (dB)
02464-002
Figure 2. AD8129 CMRR vs. Frequency
The AD8129/AD8130 have excellent common-mode rejection
(70 dB @ 10 MHz), allowing the use of low cost, unshielded
twisted-pair cables without fear of corruption by external noise
sources or crosstalk. The AD8129/AD8130 have a wide power
supply range from single +5 V to ±12 V, allowing wide common-
mode and differential-mode voltage ranges while maintaining
signal integrity. The wide common-mode voltage range enables
the driver-receiver pair to operate without isolation transformers
in many systems where the ground potential difference between
drive and receive locations is many volts. The AD8129/AD8130
have considerable cost and performance improvements over
op amps and other multiamplifier receiving solutions.
R
F
V
OUT
V
IN
R
G
V
OUT
=V
IN
[1+(R
F
/R
G
)]
PD +V
S
–V
S
1
8
4
5
3
2
7
6
02464-003
Figure 3. Typical Connection Configuration
AD8129/AD8130
Rev. C | Page 2 of 40
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Connection Diagram ....................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
AD8129/AD8130 Specifications..................................................... 3
5 V Specifications ......................................................................... 3
±5 V Specifications....................................................................... 5
±12 V Specifications..................................................................... 7
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Typical Performance Characteristics ........................................... 10
AD8130 Frequency Response Characteristics........................ 10
AD8129 Frequency Response Characteristics........................ 13
AD8130 Harmonic Distortion Characteristics ...................... 16
AD8129 Harmonic Distortion Characteristics ...................... 18
AD8130 Transient Response Characteristics.......................... 23
AD8129 Transient Response Characteristics.......................... 26
Theory of Operation ...................................................................... 32
Op Amp Configuration............................................................. 32
Applications..................................................................................... 33
Basic Gain Circuits..................................................................... 33
Twisted-Pair Cable, Composite Video Receiver with
Equalization Using an AD8130................................................... 33
Output Offset/Level Translator ................................................ 34
Resistorless Gain of 2 ................................................................. 35
Summer ....................................................................................... 35
Cable-Tap Amplifier .................................................................. 35
Power-Down ............................................................................... 36
Extreme Operating Conditions................................................ 36
Power Dissipation....................................................................... 37
Layout, Grounding, and Bypassing.......................................... 38
Outline Dimensions ....................................................................... 39
Ordering Guide .......................................................................... 40
REVISION HISTORY
11/05—Rev. B to Rev. C
Changes to 5 V Specifications......................................................... 3
Changes to Table 4 and Maximum Power Dissipation Section.. 9
Changes to Figure 16...................................................................... 11
Changes to Figure 17...................................................................... 12
9/05—Rev. A to Rev. B
Extended Temperature Range...........................................Universal
Deleted Figure 5................................................................................ 5
Added Thermal Resistance Section ............................................... 9
Updated Outline Dimensions....................................................... 39
Changes to Ordering Guide .......................................................... 40
3/05—Rev. 0 to Rev. A
Changes to Specifications.................................................................2
Replaced Figure 3 ..............................................................................5
Changes to Ordering Guide.............................................................6
Updated Outline Dimensions....................................................... 27
Revision 0: Initial Version
AD8129/AD8130
Rev. C | Page 3 of 40
AD8129/AD8130 SPECIFICATIONS
5 V SPECIFICATIONS
AD8129 G = +10, AD8130 G = +1, TA = 25°C, +VS = 5 V, −VS = 0 V, REF = 2.5 V, PD ≥ VIH, RL = 1 kΩ, CL = 2 pF, unless otherwise noted.
TMIN to TMAX = −40°C to +125°C, unless otherwise noted.
Table 1.
Model AD8129 AD8130
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT ≤ 0.3 V p-p 160 185 220 250 MHz
V
OUT = 1 V p-p 160 185 180 205 MHz
Bandwidth for 0.1 dB
Flatness
VOUT ≤ 0.3 V p-p,
SOIC/MSOP
25/40 25 MHz
Slew Rate VOUT = 2 V p-p, 25%
to 75%
810 930 810 930 V/μs
Settling Time VOUT = 2 V p-p, 0.1% 20 20 ns
Rise and Fall Times VOUT ≤ 1 V p-p, 10%
to 90%
1.8 1.5 ns
Output Overdrive Recovery 20 30 ns
NOISE/DISTORTION
Second Harmonic/Third
Harmonic
VOUT = 1 V p-p, 5 MHz −68/−75 −72/−79 dBc
V
OUT = 2 V p-p, 5 MHz −62/−64 −65/−71 dBc
V
OUT = 1 V p-p, 10 MHz −63/−70 −60/−62 dBc
V
OUT = 2 V p-p, 10 MHz −56/−58 −68/−68 dBc
IMD VOUT = 2 V p-p, 10 MHz −67 −70 dBc
Output IP3 VOUT = 2 V p-p, 10 MHz 25 26 dBm
Input Voltage Noise (RTI) f ≥ 10 kHz 4.5 12.3 nV/√Hz
Input Current Noise (+IN, −IN) f ≥ 100 kHz 1 1 pA/√Hz
Input Current Noise
(REF, FB)
f ≥ 100 kHz 1.4 1.4 pA/√Hz
Differential Gain Error AD8130, G = +2, NTSC
100 IRE, RL ≥ 150 Ω
0.3 0.13 %
Differential Phase Error AD8130, G = +2, NTSC
100 IRE, RL ≥ 150 Ω
0.1 0.15 Degrees
INPUT CHARACTERISTICS
Common-Mode Rejection
Ratio
DC to 100 kHz,
VCM = 1.5 V to 3.5 V
86 96 86 96 dB
V
CM = 1 V p-p @ 1 MHz 80 80 dB
V
CM = 1 V p-p @ 10 MHz 70 70 dB
CMRR with VOUT = 1 V p-p VCM = 1 V p-p @ 1 kHz,
VOUT = ±0.5 V dc
80 72 dB
Common-Mode Voltage
Range
V+IN − V−IN = 0 V 1.25 to
3.7
1.25 to
3.8
V
Differential Operating Range ±0.5 ±2.5 V
Differential Clipping Level ±0.6 ±0.75 ±0.85 ±2.3 ±2.8 ±3.3 V
Resistance Differential 1 6 MΩ
Common mode 4 4 MΩ
Capacitance Differential 3 3 pF
Common mode 4 4 pF
AD8129/AD8130
Rev. C | Page 4 of 40
Model AD8129 AD8130
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Closed-Loop Gain Error VOUT = ±1 V, RL ≥ 150 Ω ±0.25 ±1.25 ±0.1 ±0.6 %
T
MIN to TMAX 20 20 ppm/°C
Open-Loop Gain VOUT = ±1 V 86 71 dB
Gain Nonlinearity VOUT = ±1 V 250 200 ppm
Input Offset Voltage 0.2 0.8 0.4 1.8 mV
T
MIN to TMAX 2 20 μV/°C
T
MIN to TMAX 1.4 3.5 mV
Input Offset Voltage vs.
Supply
+VS = 5 V, −VS = −0.5 V
to +0.5 V
−88 −80 −74 −70 dB
−VS = 0 V, +VS = +4.5 V
to +5.5 V
−100 −86 −90 −76 dB
Input Bias Current
(+IN, −IN)
±0.5 ±2 ±0.5 ±2 μA
Input Bias Current
(REF, FB)
±1 ±3.5 ±1 ±3.5 μA
TMIN to TMAX (+IN, −IN,
REF, FB)
5 5 nA/°C
Input Offset Current (+IN, −IN, REF, FB) ±0.08 ±0.4 ±0.08 ±0.4 μA
T
MIN to TMAX 0.2 0.2 nA/°C
OUTPUT PERFORMANCE
Voltage Swing RLOAD ≥ 150 Ω 1.1 3.9 1.1 3.9 V
Output Current 35 35 mA
Short-Circuit Current To common −60/+55 −60/+55 mA
T
MIN to TMAX −240 −240 μA/°C
Output Impedance PD ≤ VIL, in power-
down mode
10 10 pF
POWER SUPPLY
Operating Voltage Range Total supply voltage ±2.25 ±12.6 ±2.25 ±12.6 V
Quiescent Supply Current 9.9 10.6 9.9 10.6 mA
T
MIN to TMAX 33 33 μA/°C
PD ≤ VIL 0.65 0.85 0.65 0.85 mA
PD ≤ VIL, TMIN to TMAX 1 1 mA
PD PIN
VIH +VS − 1.5 +VS − 1.5 V
VIL +VS − 2.5 +VS − 2.5 V
IIH PD = min VIH −30 −30 μA
IIL PD = max VIL −50 −50 μA
Input Resistance PD ≤ +VS − 3 V 12.5 12.5 kΩ
PD ≥ +VS − 2 V 100 100 kΩ
Enable Time 0.5 0.5 μs
OPERATING TEMPERATURE
RANGE
−40 +125 −40 +125 °C
AD8129/AD8130
Rev. C | Page 5 of 40
±5 V SPECIFICATIONS
AD8129 G = +10, AD8130 G = +1, TA = 25°C, VS = ±5 V, REF = 0 V, PD ≥ VIH, RL = 1 kΩ, CL = 2 pF, unless otherwise noted. TMIN to TMAX
= −40°C to +125°C, unless otherwise noted.
Table 2.
AD8129 AD8130
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT ≤ 0.3 V p-p 175 200 240 270 MHz
V
OUT = 2 V p-p 170 190 140 155 MHz
Bandwidth for 0.1 dB
Flatness
VOUT ≤ 0.3 V p-p,
SOIC/MSOP
30/50 45 MHz
Slew Rate VOUT = 2 V p-p,
25% to 75%
925 1060 950 1090 V/μs
Settling Time VOUT = 2 V p-p, 0.1% 20 20 ns
Rise and Fall Times VOUT ≤ 1 V p-p,
10% to 90%
1.7 1.4 ns
Output Overdrive Recovery 30 40 ns
NOISE/DISTORTION
Second Harmonic/Third
Harmonic
VOUT = 1 V p-p, 5 MHz −74/−84 −79/−86 dBc
V
OUT = 2 V p-p, 5 MHz −68/−74 −74/−81 dBc
V
OUT = 1 V p-p, 10 MHz −67/−81 −74/−80 dBc
V
OUT = 1 V p-p, 10 MHz −61/−70 −74/−76 dBc
IMD VOUT = 2 V p-p, 10 MHz −67 −70 dBc
Output IP3 VOUT = 2 V p-p, 10 MHz 25 26 dBm
Input Voltage Noise (RTI) f ≥ 10 kHz 4.5 12.5 nV/√Hz
Input Current Noise
(+IN, −IN)
f ≥ 100 kHz 1 1 pA/√Hz
Input Current Noise
(REF, FB)
f ≥ 100 kHz 1.4 1.4 pA/√Hz
Differential Gain Error AD8130, G = +2, NTSC
200 IRE, RL ≥ 150 Ω
0.3 0.13 %
Differential Phase Error AD8130, G = +2, NTSC
200 IRE, RL ≥ 150 Ω
0.1 0.15 Degrees
INPUT CHARACTERISTICS
Common-Mode Rejection
Ratio
DC to 100 kHz,
VCM = −3 V to +3.5 V
94 110 90 110 dB
V
CM = 1 V p-p @ 2 MHz 80 80 dB
V
CM = 1 V p-p @ 10 MHz 70 70 dB
CMRR with VOUT = 1 V p-p VCM = 2 V p-p @ 1 kHz,
VOUT = ±0.5 V dc
100 83 dB
Common-Mode Voltage
Range
V+IN − V−IN = 0 V ±3.5 ±3.8 V
Differential Operating
Range
±0.5 ±2.5 V
Differential Clipping Level ±0.6 ±0.75 ±0.85 ±2.3 ±2.8 ±3.3 V
Resistance Differential 1 6 MΩ
Common mode 4 4 MΩ
Capacitance Differential 3 3 pF
Common mode 4 4 pF
AD8129/AD8130
Rev. C | Page 6 of 40
AD8129 AD8130
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Closed-Loop Gain Error VOUT = ±1 V, RL ≥ 150 Ω ±0.4 ±1.5 ±0.15 ±0.6 %
T
MIN to TMAX 20 10 ppm/°C
Open-Loop Gain VOUT = ±1 V 88 74 dB
Gain Nonlinearity VOUT = ±1 V 250 200 ppm
Input Offset Voltage 0.2 0.8 0.4 1.8 mV
T
MIN to TMAX 2 20 μV/°C
T
MIN to TMAX 1.4 3.5 mV
Input Offset Voltage vs.
Supply
+VS = +5 V, −VS = −4.5 V
to −5.5 V
−90 −84 −78 −74 dB
−VS = −5 V, +VS = +4.5 V
to +5.5 V
−94 −86 −80 −74 dB
Input Bias Current
(+IN, −IN)
±0.5 ±2 ±0.5 ±2 μA
Input Bias Current (REF, FB) ±1 ±3.5 ±1 ±3.5 μA
TMIN to TMAX (+IN, −IN,
REF, FB)
5 5 nA/°C
Input Offset Current (+IN, −IN, REF, FB) ±0.08 ±0.4 ±0.08 ±0.4 μA
T
MIN to TMAX 0.2 0.2 nA/°C
OUTPUT PERFORMANCE
Voltage Swing RLOAD = 150 Ω/1 kΩ 3.6/4.0 3.6/4.0 ±V
Output Current 40 40 mA
Short-Circuit Current To common −60/+55 −60/+55 mA
T
MIN to TMAX −240 −240 μA/°C
Output Impedance PD ≤ VIL, in power-
down mode
10 10
pF
POWER SUPPLY
Operating Voltage Range Total supply voltage ±2.25 ±12.6 ±2.25 ±12.6 V
Quiescent Supply Current 10.8 11.6 10.8 11.6 mA
T
MIN to TMAX 36 36 μA/°C
PD ≤ VIL 0.68 0.85 0.68 0.85 mA
PD ≤ VIL, TMIN to TMAX 1 1 mA
PD PIN
VIH +VS − 1.5 +VS − 1.5 V
VIL +VS − 2.5 +VS − 2.5 V
IIH PD = min VIH −30 −30 μA
IIL PD = max VIL −50 −50 μA
Input Resistance PD ≤ +VS − 3 V 12.5 12.5 kΩ
PD ≥ +VS − 2 V 100 100 kΩ
Enable Time 0.5 0.5 μs
OPERATING TEMPERATURE
RANGE
−40 +125 −40 +125 °C
AD8129/AD8130
Rev. C | Page 7 of 40
±12 V SPECIFICATIONS
AD8129 G = +10, AD8130 G = +1, TA = 25°C, VS = ±12 V, REF = 0 V, PD ≥ VIH, RL = 1 kΩ, CL = 2 pF, unless otherwise noted. TMIN to
TMAX = −40°C to +85°C, unless otherwise noted.
Table 3.
AD8129 AD8130
Parameter Conditions Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth VOUT ≤ 0.3 V p-p 175 200 250 290 MHz
V
OUT = 2 V p-p 170 195 150 175 MHz
Bandwidth for 0.1 dB Flatness VOUT ≤ 0.3 V p-p,
SOIC/MSOP
50/70 110 MHz
Slew Rate VOUT = 2 V p-p, 25%
to 75%
935 1070 960 1100 V/μs
Settling Time VOUT = 2 V p-p, 0.1% 20 20 ns
Rise and Fall Times VOUT ≤ 1 V p-p, 10%
to 90%
1.7 1.4 ns
Output Overdrive Recovery 40 40 ns
NOISE/DISTORTION
Second Harmonic/Third
Harmonic
VOUT = 1 V p-p, 5 MHz −71/−84 −79/−86 dBc
V
OUT = 2 V p-p, 5 MHz −65/−74 −74/−81 dBc
V
OUT = 1 V p-p, 10 MHz −65/−82 −74/−80 dBc
V
OUT = 2 V p-p, 10 MHz −59/−70 −74/−74 dBc
IMD VOUT = 2 V p-p, 10 MHz −67 −70 dBc
Output IP3 VOUT = 2 V p-p, 10 MHz 25 26 dBm
Input Voltage Noise (RTI) f ≥ 10 kHz 4.6 13 nV/√Hz
Input Current Noise
(+IN, −IN)
f ≥ 100 kHz 1 1 pA/√Hz
Input Current Noise
(REF, FB)
f ≥ 100 kHz 1.4 1.4 pA/√Hz
Differential Gain Error AD8130, G = +2, NTSC
200 IRE, RL ≥ 150 Ω
0.3 0.13 %
Differential Phase Error AD8130, G = +2, NTSC
200 IRE, RL ≥ 150 Ω
0.1 0.2 Degrees
INPUT CHARACTERISTICS
Common-Mode Rejection
Ratio
DC to 100 kHz,
VCM = ±10 V
92 105 88 105 dB
V
CM = 1 V p-p @ 2 MHz 80 80 dB
V
CM = 1 V p-p @ 10 MHz 70 70 dB
CMRR with VOUT = 1 V p-p VCM = 4 V p-p @ 1 kHz,
VOUT = ±0.5 V dc
93 80 dB
Common-Mode Voltage
Range
V+IN − V–IN = 0 V ±10.3 ±10.5 V
Differential Operating Range ±0.5 ±2.5 V
Differential Clipping Level ±0.6 ±0.75 ±0.85 ±2.3 ±2.8 ±3.3 V
Resistance Differential 1 6 MΩ
Common mode 4 4 MΩ
Capacitance Differential 3 3 pF
Common mode 4 4 pF
AD8129/AD8130
Rev. C | Page 8 of 40
AD8129 AD8130
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Closed-Loop Gain Error VOUT = ±1 V, RL ≥ 150 Ω ±0.8 ±1.8 ±0.15 ±0.6 %
T
MIN to TMAX 20 10 ppm/°C
Open-Loop Gain VOUT = ±1 V 87 73 dB
Gain Nonlinearity VOUT = ±1 V 250 200 ppm
Input Offset Voltage 0.2 0.8 0.4 1.8 mV
T
MIN to TMAX 2 20 μV/°C
T
MIN to TMAX 1.4 3.5 mV
Input Offset Voltage vs. Supply +VS = +12 V, −VS =
–11.0 V to −13.0 V
−88 −82 −77 −70 dB
−VS = −12 V, +VS =
+11.0 V to +13.0 V
−92 −84 −88 −70 dB
Input Bias Current (+IN, −IN) ±0.25 ±2 ±0.25 ±2 μA
Input Bias Current (REF, FB) ±0.5 ±3.5 ±0.5 ±3.5 μA
TMIN to TMAX
(+IN, −IN, REF, FB)
2.5 2.5 nA/°C
Input Offset Current (+IN, −IN, REF, FB) ±0.08 ±0.4 ±0.08 ±0.4 μA
T
MIN to TMAX 0.2 0.2 nA/°C
OUTPUT PERFORMANCE
Voltage Swing RLOAD = 700 Ω ±10.8 ±10.8 V
Output Current 40 40
mA
Short-Circuit Current To common −60/+55 −60/+55 mA
T
MIN to TMAX −240 −240 μA/°C
Output Impedance PD ≤ VIL, in power-
down mode
10 10
pF
POWER SUPPLY
Operating Voltage Range Total supply voltage ±2.25 ±12.6 ±2.25 ±12.6 V
Quiescent Supply Current 13 13.9 13 13.9 mA
T
MIN to TMAX 43 43 μA°C
PD ≤ VIL 0.73 0.9 0.73 0.9 mA
PD ≤ VIL, TMIN to TMAX 1.1 1.1 mA
PD PIN
VIH +VS − 1.5 +VS − 1.5 V
VIL +VS − 2.5 +VS − 2.5 V
IIH PD = min VIH −30 −30 μA
IIL PD = max VIL −50 −50 μA
Input Resistance PD ≤ +VS − 3 V 3 3 kΩ
PD ≥ +VS − 2 V 100 100 kΩ
Enable Time 0.5 0.5 μs
OPERATING TEMPERATURE
RANGE
−40 +85 −40 +85 °C
AD8129/AD8130
Rev. C | Page 9 of 40
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage 26.4 V
Power Dissipation Refer to Figure 4
Input Voltage (Any Input) −VS − 0.3 V to +VS + 0.3 V
Differential Input Voltage (AD8129)
VS ≥ ±11.5 V ±0.5 V
Differential Input Voltage (AD8129)
VS < ±11.5 V ±6.2 V
Differential Input Voltage (AD8130) ±8.4 V
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
Table 5. Thermal Resistance
Package Type θJA Unit
8-Lead SOIC/4-Layer 121 °C/W
8-Lead MSOP/4-Layer 142 °C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8129/AD8130
packages is limited by the associated rise in junction temp-
erature (TJ) on the die. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit can change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8129/AD8130.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in the silicon devices, potentially
causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive. The quiescent power is the
voltage between the supply pins (VS) times the quiescent
current (IS). The power dissipated due to the load drive
depends upon the particular application. The power due to
load drive is calculated by multiplying the load current by the
associated voltage drop across the device. RMS voltages and
currents must be used in these calculations.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces through holes, ground,
and power planes reduces the θJA.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(121°C/W) and MSOP (θJA = 142°C/W) packages on a JEDEC
standard 4-layer board. θJA values are approximations.
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
1.75
1.50
1.00
1.25
0.50
0.25
0.75
0
–40–30 –20–10 0 10 20 30 40 50 60 70 80 90 100110120
SOIC
MSOP
02464-005
Figure 4. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD8129/AD8130
Rev. C | Page 10 of 40
TYPICAL PERFORMANCE CHARACTERISTICS
AD8130 FREQUENCY RESPONSE CHARACTERISTICS
G = +1, RL = 1 kΩ, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25°C, unless otherwise noted.
GAIN (dB)
3
0
–3
–4
–5
–6
–7
–2
–1
1
2
FREQUENCY (MHz)
1 10 100 400
02464-006
V
OUT
= 0.3V p-p V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
Figure 5. AD8130 Frequency Response vs. Supply, VOUT = 0.3 V p-p
FREQUENCY (MHz)
GAIN (dB)
3
1
0
–3
–4
–5
–6
–7
–2
–1
1
2
10 100 300
02464-007
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
V
OUT
= 1V p-p
Figure 6. AD8130 Frequency Response vs. Supply, VOUT = 1 V p-p
FREQUENCY (MHz)
GAIN (dB)
1
–3
–4
–5
–6
–7
–2
–1
10 100 300
3
0
1
2
02464-008
V
OUT
= 2V p-p
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
Figure 7. AD8130 Frequency Response vs. Supply, VOUT = 2 V p-p
FREQUENCY (MHz)
GAIN (dB)
6
1
3
0
–1
–2
–3
–4
1
2
4
5
10 100 300
02464-009
C
L
= 2pF
V
S
=
±
5V C
L
= 20pF
C
L
= 10pF
C
L
= 5pF
Figure 8. AD8130 Frequency Response vs. Load Capacitance
FREQUENCY (MHz)
GAIN (dB)
0.7
1
0.4
0.1
0
–0.1
–0.2
–0.3
0.2
0.3
0.5
0.6
10 100 300
02464-010
VS = ±2.5V
VS = ±12V
VS = ±5V
R
L
= 1kΩ
Figure 9. AD8130 Fine Scale Response vs. Supply, RL = 1 kΩ
FREQUENCY (MHz)
GAIN (dB)
0.5
1
0.2
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.1
0.3
0.4
10 100 300
02464-011
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
RL = 150Ω
Figure 10. AD8130 Fine Scale Response vs. Supply, RL = 150 Ω
AD8129/AD8130
Rev. C | Page 11 of 40
FREQUENCY (MHz)
GAIN (dB)
3
1
0
–3
–4
–5
–6
–7
–2
–1
1
2
10 100 400
02464-012
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
R
L
= 150Ω
Figure 11. AD8130 Frequency Response vs. Supply, RL = 150 Ω
FREQUENCY (MHz)
GAIN (dB)
3
1
0
–3
–4
–5
–6
–7
–2
–1
1
2
10 100 300
02464-013
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
G = +2
V
OUT
= 0.3V p-p
Figure 12. AD8130 Frequency Response vs. Supply,
G = +2, VOUT = 0.3 V p-p
FREQUENCY (MHz)
GAIN (dB)
3
1
0
–3
–4
–5
–6
–7
–2
–1
1
2
10 100 300
02464-014
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
G = +2
V
OUT
= 2V p-p
Figure 13. AD8130 Frequency Response vs. Supply,
G = +2, VOUT = 2 V p-p
FREQUENCY (MHz)
GAIN (dB)
3
1
0
–3
–4
–5
–6
–7
–2
–1
1
2
10 100 300
02464-015
R
F
= R
G
= 1kΩ
R
F
= R
G
= 750Ω
R
F
= R
G
= 499Ω
R
F
= R
G
= 250Ω
G = +2
V
S
= ±5V
Figure 14. AD8130 Frequency Response for Various RF/RG
FREQUENCY (MHz)
GAIN (dB)
0.3
1 10 100
0
–0.3
–0.4
–0.5
–0.6
–0.7
–0.2
–0.1
0.1
0.2
02464-016
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
G = +2
RL = 1kΩ
Figure 15. AD8130 Fine Scale Response vs. Supply,
G = +2, RL = 1 kΩ
FREQUENCY (MHz)
GAIN (dB)
0.3
110
0
–0.3
–0.4
–0.5
–0.6
–0.7
–0.2
–0.1
0.1
0.2
100
02464-017
V
S
=±2.5V
V
S
=±12V
V
S
=±5V
G=+2
R
L
= 150
Ω
Figure 16. AD8130 Fine Scale Response vs. Supply,
G = +2, RL = 150 Ω
AD8129/AD8130
Rev. C | Page 12 of 40
FREQUENCY (MHz)
GAIN (dB)
3
1 30010 100
0
–3
–4
–5
–6
–7
–2
–1
1
2
02464-018
V
S
= ±2.5V
V
S
=±12V
V
S
=±5V
G=+2
R
L
= 150Ω
FREQUENCY (MHz)
GAIN (dB)
3
1 10 100
0
–3
–4
–5
–6
–7
–2
–1
1
2
0.1
02464-021
V
S
= ±2.5V
R
L
= 150
Ω
V
S
= ±5V, ±12V
G = +10 G = +5
V
S
= ±5V, ±12V
Figure 17. AD8130 Frequency Response vs. Supply,
G = +2, RL = 150 Ω
Figure 20. AD8130 Frequency Response vs. Supply,
G = +5, G = +10, RL = 150 Ω
FREQUENCY (MHz)
GAIN (dB)
0.3
0.1
0
–0.3
–0.4
–0.5
–0.6
–0.7
–0.2
–0.1
0.1
0.2
110
FREQUENCY (MHz)
OUTPUT VOLTAGE (dBV)
12
10
6
0
–6
–12
–18
–24
–30
–36
–42
–48 100 400
0dB = 1V rms
02464-022
V
S
=
±
5V
30
02464-019
V
OUT
= 2V p-p
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
V
S
= ±5V, ±12V
V
S
= ±2.5V
G = +10 G = +5
Figure 18. AD8130 Fine Scale Response vs. Supply,
G = +5, G = +10, VOUT = 2 V p-p
Figure 21. AD8130 Frequency Response for Various Output Levels
FREQUENCY (MHz)
GAIN (dB)
3
1 10 100
0
–3
–4
–5
–6
–7
–2
–1
1
2
0.1
02464-020
V
OUT
= 2V p-p
V
S
= ±12V
V
S
= ±5V, ±12V
V
S
= ±2.5V
G = +10
G = +5
02464-023
1
8
4
5
6
TEK P6245
FET PROBE
R
L
C
L
R
G
R
F
50Ω
G
1
2
5
10
R
F
0Ω
499Ω
8.06kΩ
4.99kΩ
R
G
–
499Ω
2kΩ
549Ω
Figure 19. AD8130 Frequency Response vs. Supply,
G = +5, G = +10, VOUT = 2 V p-p
Figure 22. AD8130 Basic Frequency Response Test Circuit
AD8129/AD8130
Rev. C | Page 13 of 40
AD8129 FREQUENCY RESPONSE CHARACTERISTICS
G = +10, RL = 1 kΩ, CL = 2 pF, VOUT = 0.3 V p-p, TA = 25°C, unless otherwise noted.
FREQUENCY (MHz)
GAIN (dB)
3
1 30010 100
0
–3
–4
–5
–6
–7
–2
–1
1
2
02464-024
V
OUT
= 0.3V p-p
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
Figure 23. AD8129 Frequency Response vs. Supply, VOUT = 0.3 V p-p
FREQUENCY (MHz)
GAIN (dB)
3
1 30010 100
0
–3
–4
–5
–6
–7
–2
–1
1
2
02464-025
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
V
OUT
= 1V p-p
Figure 24. AD8129 Frequency Response vs. Supply, VOUT = 1 V p-p
FREQUENCY (MHz)
GAIN (dB)
1
–3
–4
–5
–6
–7
–2
–1
10 100 300
3
0
1
2
02464-026
V
OUT
= 2V p-p V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
Figure 25. AD8129 Frequency Response vs. Supply, VOUT = 2 V p-p
FREQUENCY (MHz)
GAIN (dB)
4
1
1
–2
–3
–4
–5
–6
–1
0
2
3
10 100 300
02464-027
V
S
=
±
5V C
L
= 20pF
C
L
= 10pF
C
L
= 5pF
C
L
= 2pF
Figure 26. AD8129 Frequency Response vs. Load Capacitance
02464-028
FREQUENCY (MHz)
GAIN (dB)
0.5
0.2
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.3
0.4
1 30010 100
R
L
= 1kΩV
S
= ±2.5V
V
S
= ±5V
V
S
= ±12V
0.1
Figure 27. AD8129 Fine Scale Response vs. Supply, RL = 1 kΩ
02464-029
FREQUENCY (MHz)
GAIN (dB)
30010 100
0.3
0
–0.3
–0.4
–0.5
–0.6
–0.7
–0.2
–0.1
0.1
0.2
1
R
L
= 150ΩV
S
= ±2.5V
V
S
= ±5V
V
S
= ±12V
Figure 28. AD8129 Fine Scale Response vs. Supply, RL = 150 Ω
AD8129/AD8130
Rev. C | Page 14 of 40
02464-030
FREQUENCY (MHz)
GAIN (dB)
30010010
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
R
L
= 150Ω
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±12V
Figure 29. AD8129 Frequency Response vs. Supply, RL = 150 Ω
02464-031
FREQUENCY (MHz)
GAIN (dB)
3001001
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
G = +20
V
OUT
= 0.3V p-p
V
S
= ±5V, ±12V
V
S
= ±2.5V
10
Figure 30. AD8129 Frequency Response vs. Supply,
G = +20, VOUT = 0.3 V p-p
02464-032
FREQUENCY (MHz)
GAIN (dB)
3001001
3
2
1
0
–1
–2
–3
–4
–5
–6
–7 10
G = +20
V
OUT
= 2V p-p
V
S
= ±2.5V
V
S
= ±5V, ±12V
Figure 31. AD8129 Frequency Response vs. Supply,
G = +20, VOUT = 2 V p-p
02464-033
FREQUENCY (MHz)
GAIN (dB)
300100110
0.8
0.6
0.4
0.2
0
–0.2
0.2
0
–0.2
–0.4
–0.6
G = +10
V
S
= ±5V 2k
Ω
/221
Ω
909
Ω
/100
Ω
499
Ω
/54.9
Ω
2k
Ω
/221
Ω
909
Ω
/100
Ω
499
Ω
/54.9
Ω
SOIC
μ
SOIC
Figure 32. AD8129 Fine Scale Response vs. SOIC and MSOP
for Various RF/RG
02464-034
FREQUENCY (MHz)
GAIN (dB)
30110
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
G = +20
R
L
= 1k
Ω
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±12V
Figure 33. AD8129 Fine Scale Response vs. Supply
02464-035
FREQUENCY (MHz)
GAIN (dB)
30110
0.1
0.3
0
–0.3
–0.4
–0.5
–0.6
–0.7
–0.2
–0.1
0.1
0.2
G = +20
R
L
= 150
Ω
V
S
= ±5V, ±12V
V
S
= ±2.5V
Figure 34. AD8129 Fine Scale Response vs. Supply
AD8129/AD8130
Rev. C | Page 15 of 40
02464-036
FREQUENCY (MHz)
GAIN (dB)
1 30010 100
3
0
–3
–4
–5
–6
–7
–2
–1
1
2
V
S
= ±5V, ±12V
V
S
= ±2.5V
G = +20
R
L
= 150
Ω
Figure 35. AD8129 Frequency Response vs. Supply,
G = +20, RL = 150 Ω
02464-037
FREQUENCY (MHz)
GAIN (dB)
0.1 1 10
0.2
–0.1
–0.4
–0.5
–0.6
–0.7
–0.8
–0.3
–0.2
0
0.1
V
S
= ±2.5V
V
S
=±12V
V
S
=±12V
V
S
= ±5V
V
OUT
= 2V p-p
G = +50
G = +100
Figure 36. AD8129 Fine Scale Response vs. Supply,
G = +50, G = +100, VOUT = 2 V p-p
02464-038
FREQUENCY (MHz)
GAIN (dB)
0.1 1 10
3
0
–3
–4
–5
–6
–7
–2
–1
1
2
50
V
OUT
= 2V p-p
G = +100G = +50
V
S
= ±2.5V
V
S
= ±5V
V
S =
±12V
Figure 37. AD8129 Frequency Response vs. Supply,
G = +50, G = +100, VOUT = 2 V p-p
02464-039
FREQUENCY (MHz)
GAIN (dB)
0.1 1 10
3
0
–3
–4
–5
–6
–7
–2
–1
1
2
50
R
L
= 150
Ω
G = +100G = +50
V
S
= ±5V
V
S
= ±2.5V
V
S =
±12V
Figure 38. AD8129 Frequency Response vs. Supply,
G = +50, G = +100, RL = 150 Ω
02464-040
FREQUENCY (MHz)
OUTPUT VOLTAGE (dBV)
12
6
0
–6
–12
–18
–24
–30
–36
–42
–4810 100 400
0dB = 1V rms
V
S
= ±5V
Figure 39. AD8129 Frequency Response for Various Output Levels
1
8
4
5
6
R
F
R
G
TEK P6245
FET PROBE
10
20
50
100
R
F
G2kΩ
2kΩ
2kΩ
2kΩ
221Ω
105Ω
41.2Ω
20Ω
R
L
C
L
50Ω
02464-041
R
G
Figure 40. AD8129 Basic Frequency Response Test Circuit
AD8129/AD8130
Rev. C | Page 16 of 40
AD8130 HARMONIC DISTORTION CHARACTERISTICS
RL = 1 kΩ, CL = 2 pF, TA = 25°C, unless otherwise noted.
V
S
= ±12V
02464-042
1
–90
–84
–78
–72
–66
–60
40
FREQUENCY (MHz)
HD2 (dBc)
10
V
OUT
= 1V p-p
G = +1
G = +2
V
S
= ±12V
V
S
= ±5V
Figure 41. AD8130 Second Harmonic Distortion vs. Frequency
G = +2
02464-043
1
–84
–78
–72
–66
–60
–54
40
FREQUENCY (MHz)
HD2 (dBc)
10
V
OUT
= 2V p-p
G = +1
V
S
= ±5V
V
S
= ±12V
V
S
= ±5V G = +1
V
S
= ±12V
Figure 42. AD8130 Second Harmonic Distortion vs. Frequency
02464-044
0.5
–91
–85
–79
–73
–67
–61
1
V
OUT
(V p-p)
HD2 (dBc)
10
–55
G = +2
f
C
= 5MHz
G = +1
V
S
= ±5V
V
S
= ±12V
V
S
= ±5V
V
S
= ±12V
Figure 43. AD8130 Second Harmonic Distortion vs. Output Voltage
1
–99
–93
–87
–81
–75
–69
10
FREQUENCY (MHz)
HD3 (dBc)
40
–63
–57
–51 G = +1
V
S
= ±5V
V
S
= ±5V
G = +2
G = +1
G = +1
V
S
= ±12V
V
OUT
= 1V p-p
V
S
= ±12V
02464-045
Figure 44. AD8130 Third Harmonic Distortion vs. Frequency
1
–93
–87
–81
–75
–69
–63
10
FREQUENCY (MHz)
HD3 (dBc)
40
–57
–51
–45
G = +1
02464-046
V
OUT
= 2V p-p
G = +2
V
S
= ±5V
G = +2, V
S
= ±12V
G = +2, V
S
= ±5V
V
S
= ±12V
Figure 45. AD8130 Third Harmonic Distortion vs. Frequency
02464-047
0.5
–94
–88
–82
–76
–70
–64
1
V
OUT
(V p-p)
HD3 (dBc)
10
–58
–52
–46
G = +1
f
C
= 5MHz V
S
= ±12V
V
S
= ±5V
G = +2
V
S
= ±12V
V
S
= ±5V
Figure 46. AD8130 Third Harmonic Distortion vs. Output Voltage
AD8129/AD8130
Rev. C | Page 17 of 40
02464-048
1
–79
–73
–67
–61
–55
–49
10
FREQUENCY (MHz)
HD2 (dBc)
40
–43
G = +1
V
S
= ±2.5V
G = +1
G = +2
G = +2
V
OUT
= 2V p-p
V
OUT
= 1V p-p
02464-050
0 0.5 1.0 1.5 2.0 2.5 3.0
–94
–88
–82
–76
–70
–64
V
OUT
(V p-p)
HD (dBc)
–58
–52
–46 V
S
= ±2.5V
fC
= 5MHz G = +2, HD3
G = +2, HD3
G = +1, HD3
G = +1, HD2
G = +2, HD2
G = +2, HD2
Figure 49. AD8130 Harmonic Distortion vs. Output Voltage
Figure 47. AD8130 Second Harmonic Distortion vs. Frequency
02464-049
1
–96
–90
–84
–78
–72
–66
10
FREQUENCY (MHz)
HD3 (dBc)
40
–60
–54
–48
–42 V
S
= ±2.5V
V
OUT
= 2V p-p
V
OUT
= 1V p-p
G = +1
G = +2
G = +2
G = +1
Figure 48. AD8130 Third Harmonic Distortion vs. Frequency
AD8129/AD8130
Rev. C | Page 18 of 40
AD8129 HARMONIC DISTORTION CHARACTERISTICS
RL = 1 kΩ, CL = 2 pF, TA = 25°C, unless otherwise noted.
FREQUENCY (MHz)
HD2 (dBc)
–51
1
–57
–63
–69
–75
–81
–87 10 40
V
OUT
= 1V p-p
G = +10,
V
S
= ±12V
G = +20,
V
S
= ±12V
02464-051
G = +10,
V
S
= ±5V
G = +20,
V
S
= ±5V
Figure 50. AD8129 Second Harmonic Distortion vs. Frequency
FREQUENCY (MHz)
HD2 (dBc)
–42
1
–48
–54
–60
–66
–72
–78
10 40
V
OUT
= 2V p-p
–84
G = +10
G = +20
02464-052
G = +10,
V
S
= ±12V
G = +20,
V
S
= ±12V
G = +10,
V
S
= ±5V
G = +20,
V
S
= ±5V
Figure 51. AD8129 Second Harmonic Distortion vs. Frequency
V
OUT
(V p-p)
HD2 (dBc)
1 10
–62
–68
–74
–80
–86
–56
–50
f
C
= 5MHz
0.5
02464-053
G = +10,
V
S
= ±12V
G = +20,
V
S
= ±12V
G = +10,
V
S
= ±5V
G = +20,
V
S
= ±5V
Figure 52. AD8129 Second Harmonic Distortion vs. Output Voltage
FREQUENCY (MHz)
HD3 (dBc)
1 10 40
–96
–66
–72
–78
–84
–90
–60
–54 V
OUT
= 1V p-p
02464-054
G = +10,
V
S
= ±12V
G = +20,
V
S
= ±12V
G = +10,
V
S
= ±5V
G = +20,
V
S
= ±5V
Figure 53. AD8129 Third Harmonic Distortion vs. Frequency
FREQUENCY (MHz)
HD3 (dBc)
1
–45
–51
–57
–63
–69
–75
–81
–87 10 40
V
OUT
= 2V p-p
02464-055
G = +10,
V
S
= ±12V
G = +20,
V
S
= ±12V
G = +10,
V
S
= ±5V
G = +20,
V
S
= ±5V
G = +10,
V
S
= ±12V
G = +10,
V
S
= ±5V
Figure 54. AD8129 Third Harmonic Distortion vs. Frequency
V
OUT
(
V p-p)
–48
–84
0.5
–54
–60
–66
–72
–78
11
0
f
C
= 5MHz
–90
–96
HD3 (dBc)
02464-056
G = +20,
V
S
= ±12V
G = +20,
V
S
= ±5V
G = +10,
V
S
= ±12V
G = +10,
V
S
= ±5V
Figure 55. AD8129 Third Harmonic Distortion vs. Output Voltage
AD8129/AD8130
Rev. C | Page 19 of 40
FREQUENCY (MHz)
HD2 (dBc)
1
–44
–50
–56
–62
–68
–74
–80 10 40
V
S
= ±2.5V
G = +20
G = +10
V
OUT
= 1V p-p
02464-057
V
OUT
= 2V p-p
Figure 56. AD8129 Second Harmonic Distortion vs. Frequency
FREQUENCY (MHz)
HD3 (dBc)
1
–42
–48
–54
–60
–66
–72
–78
–84
10 40
V
S
= ±2.5V
–90
G = +20
G = +10
V
OUT
= 1V p-p
02464-058
V
OUT
= 2V p-p
Figure 57. AD8129 Third Harmonic Distortion vs. Frequency
V
OUT
(V p-p)
–50
0
–56
–62
–68
–74
–80
–86 0.5 1.0 1.5 2.0 2.5 3.0
V
S
= ±2.5V
f
C
= 5MHz
G = +10
HD3
HD (dBc)
02464-059
G = +20
HD3
G = +10
HD2
G = +20
HD2
Figure 58. AD8129 Harmonic Distortion vs. Output Voltage
02464-060
–87
–81
–75
–69
–63
–57
V
CM
(V)
DISTORTION (dBc)
–51
–45
–39
–5 –4 –3 –2 –1 0 1 2 34
5
HD2
HD3
G = +1
V
OUT
= 2V p-p
V
S
= ±5V
R
L
= 1k
Ω
f
C
= 5MHz
Figure 59. AD8130 Harmonic Distortion vs. Common-Mode Voltage
02464-061
–97
–91
–85
–79
–73
–67
R
L
(Ω)
DISTORTION (dBc)
–61
100
1k
G = +1
f
C
= 5MHz V
OUT
= 1V p-p
V
S
= ±5V
V
S
= ±2.5V
HD2
HD3
V
S
= ±12V
HD3
HD3
V
S
= ±5V, ±12V
HD2
V
S
= ±2.5V
Figure 60. AD8130 Harmonic Distortion vs. Load Resistance
02464-062
–86
–80
–74
–68
–62
–56
R
L
(Ω)
DISTORTION (dBc)
–50
100
1k
G = +1
f
C
= 5MHz V
OUT
= 2V p-p
HD2
V
S
= ±2.5V
V
S
= ±5V, ±12V
HD2
V
S
= ±2.5V
HD3
V
S
= ±5V, ±12V
HD3
Figure 61. AD8130 Harmonic Distortion vs. Load Resistance
AD8129/AD8130
Rev. C | Page 20 of 40
02464-063
–78
–72
–66
–60
–54
–48
V
CM
(V)
DISTORTION (dBc)
–42
–36
–5 –4 –3 –2 –1 0 1 2 3 4
5
HD3
HD2
G = +10
V
OUT
= 2V p-p
V
S
= ±5V
R
L
= 1kΩ
f
C
= 5MHz
Figure 62. AD8129 Harmonic Distortion vs. Common-Mode Voltage
02464-064
–90
–84
–78
–72
–68
–60
R
L
(
Ω
)
DISTORTION (dBc)
–54
100
1k
HD3
V
S
= ±2.5V
–48 G = +10
f
C
= 5MHz V
OUT
= 1V p-p
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±12V
V
S
= ±5V
V
S
= ±5V
HD2
Figure 63. AD8129 Harmonic Distortion vs. Load Resistance
02464-065
–80
–74
–68
–62
–56
–50
R
L
(
Ω
)
DISTORTION (dBc)
–44
100
1k
HD3
G = +10
fC
= 5MHz V
OUT
= 2V p-p
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
Figure 64. AD8129 Harmonic Distortion vs. Load Resistance
02464-066
V
CM
200Ω
1:2
1
2
10
20
R
F
GR
G
0Ω
499Ω
2kΩ
2kΩ
–
499Ω
221Ω
105Ω
MINI-CIRCUITS
®
:
# T4-6T,
f
C
≤ 10MHz
# TC4-1W,
f
C
> 10MHz
R
G
R
F
R
L
R
L
C
L
Figure 65. AD8129/AD8130 Basic Distortion Test Circuit,
VCM = 0 V, Unless Otherwise Noted
02464-067
0.1
1.0
10
FREQUENCY (Hz)
100
10 100k100 1k 10k 1M 10M
CURRENT NOISE (pA/
√
Hz)
Figure 66. AD8129/AD8130 Input Current Noise vs. Frequency
02464-068
1
10
FREQUENCY (Hz)
100
CURRENT NOISE (nV/
√
Hz)
10 100k100 1k 10k 1M 10M
AD8130
AD8129
Figure 67. AD8129/AD8130 Input Voltage Noise vs. Frequency
AD8129/AD8130
Rev. C | Page 21 of 40
FREQUENCY (Hz)
COMMON-MODE REJECTION (dB)
–30
10k 100M
100k 1M 10M
–40
–50
–60
–70
–80
–90
–100
–110
–120
V
S
= ±5V,±12V
02464-069
V
S
= ±2.5V
Figure 68. AD8130 Common-Mode Rejection vs. Frequency
FREQUENCY (Hz)
POWER SUPPLY REJECTION (dB)
0
1k
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 10k 100k 1M 10M 100M
V
S
= ±2.5V
02464-070
V
S
= ±5V
V
S
= ±12V
Figure 69. AD8130 Positive Power Supply Rejection vs. Frequency
FREQUENCY (Hz)
POWER SUPPLY REJECTION (dB)
0
1k
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10k 100k 1M 10M 100M
V
S
= ±12V
02464-071
V
S
= ±5V
V
S
= ±2.5V
Figure 70. AD8130 Negative Power Supply Rejection vs. Frequency
FREQUENCY (Hz)
COMMON-MODE REJECTION (dB)
–30
10k 100M
100k 1M 10M
–40
–50
–60
–70
–80
–90
–100
–110
–120
V
S
= ±5V,±12V
V
S
= ±2.5V
02464-072
Figure 71. AD8139 Common-Mode Rejection vs. Frequency
FREQUENCY (Hz)
POWER SUPPLY REJECTION (dB)
0
1k
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 10k 100k 1M 10M 100M
02464-073
V
S
= ±12V
V
S
= ±5V
V
S
= ±2.5V
Figure 72. AD8129 Positive Power Supply Rejection vs. Frequency
FREQUENCY (Hz)
POWER SUPPLY REJECTION (dB)
0
1k
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100 10k 100k 1M 10M 100M
V
S
= ±5V
V
S
= ±2.5V
02464-074
V
S
= ±12V
Figure 73. AD8129 Negative Power Supply Rejection vs. Frequency
AD8129/AD8130
Rev. C | Page 22 of 40
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
80
1k
70
60
50
40
30
20
10
0
–10 10k 100k 1M 10M 100M 300M
180
135
90
45
0
PHASE MARGIN (Degrees)
φ
M
= 58°
2pF
+
–
+
–
PHASE
GAIN
02464-075
1k
Ω
V
OUT
100
Ω
V
IN
1k
Ω
Figure 74. AD8130 Open-Loop Gain and Phase vs. Frequency
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
80
1k
70
60
50
40
30
20
10
0
90
10k 100k 1M 10M 100M 300M
180
135
90
45
0
PHASE MARGIN (Degrees)
2pF
1k
Ω
V
OUT
100
Ω
V
IN
1k
Ω
PHASE
GAIN
02464-076
φ
M
= 56°
Figure 75. AD8129 Open-Loop Gain and Phase vs. Frequency
FREQUENCY (Hz)
OUTPUT IMPEDANCE (
Ω
)
100
1k
10
1
100m
10m
1m 10k 100k 1M 10M 100M
AD8130, G = +1
AD8129, G = +10
V
S
= ±5V
02464-077
Figure 76. Closed-Loop Output Impedance vs. Frequency
AD8129/AD8130
Rev. C | Page 23 of 40
AD8130 TRANSIENT RESPONSE CHARACTERISTICS
G = +1, RL = 1 kΩ, CL = 2 pF, VS = ±5 V, TA = 25°C, unless otherwise noted.
02464-078
5.00ns250mV
V
OUT
= 1V p-p
V
S
= ±2.5V
Figure 77. AD8130 Transient Response, VS = ±2.5 V, VOUT = 1 V p-p
02464-079
5.00ns250mV
VOUT = 1V p-p
VS = ±5V
Figure 78. AD8130 Transient Response, VS = ±5 V, VOUT = 1 V p-p
02464-080
5.00ns250mV
VOUT = 1V p-p
VS = ±12V
Figure 79. AD8130 Transient Response, VS = ±12 V, VOUT = 1 V p-p
02464-081
5.00ns50mV
VOUT = 0.2V p-p
VS = ±2.5V
VS = ±12V
VS = ±5V
Figure 80. AD8130 Transient Response vs. Supply, VOUT = 0.2 V p-p
02464-082
VOUT = 1V p-p
CL = 5pF
VS = ±2.5V VS = ±5V
VS = ±12V
5.00ns250mV
Figure 81. AD8130 Transient Response vs. Supply, VOUT = 1 V p-p, CL = 5 pF
02464-083
5.00ns500mV
V
S
= ±2.5V
V
S
= ±12V
V
S
= ±5V
V
OUT
= 2V p-p
C
L
= 5pF
Figure 82. AD8130 Transient Response vs. Supply, VOUT = 2 V p-p, CL = 5 pF
AD8129/AD8130
Rev. C | Page 24 of 40
02464-084
10.00ns50mV
V
OUT
= 0.2 V p-p
C
L
= 10pF C
L
= 5pF
C
L
= 2pF
Figure 83. AD8130 Transient Response vs. Load Capacitance,
VOUT = 0.2 V p-p
02464-085
5.00ns500mV
0.5V p-p
2V p-p
1V p-p
Figure 84. AD8130 Transient Response vs. Output Amplitude,
VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p
02464-086
5.00ns1.00V
1V p-p
2V p-p
4V p-p
Figure 85. AD8130 Transient Response vs. Output Amplitude,
VOUT = 1 V p-p, 2 V p-p, 4 V p-p
250mV 5.00ns
V
OUT
= 1V p-p
G = +2 V
S
= ±5V, C
L
= 10pF
02464-087
V
S
= ±5V, C
L
= 2pF
Figure 86. AD8130 Transient Response vs. Load Capacitance,
VOUT = 1 V p-p, G = +2
500mV 5.00ns
02464-088
V
OUT
= 2V p-p
G = +2 V
S
= ±5V
V
S
= ±12V
Figure 87. AD8130 Transient Response vs. Supply, VOUT = 2 V p-p, G = +2
2.00V 5.00ns
02464-089
V
OUT
= 8V p-p
C
L
= 10pF
C
L
= 2pF
G = +2
V
S
= ±5V
Figure 88. AD8130 Transient Response vs. Load Capacitance,
VOUT = 8 V p-p
AD8129/AD8130
Rev. C | Page 25 of 40
1.00V 10.0ns
4V p-p
2V p-p
1V p-p
02464-093
G = +5
V
S
= ±5V
C
L
= 10pF
1.00V 5.00ns
V
OUT
V
IN
02464-090
Figure 89. AD8130 Transient Response with +3 V Common-Mode Input
Figure 92. AD8130 Transient Response vs. Output Amplitude
2.00V 10.0ns
V
OUT
= 8V p-p
02464-094
G = +5
V
S
= ±5V
C
L
= 10pF
1.00V 5.00ns
V
OUT
V
IN
02464-091
Figure 90. AD8130 Transient Response with −3 V Common-Mode Input
Figure 93. AD8130 Transient Response, VOUT = 8 V p-p, G = +5, VS = ±5 V
2.50V 5.00ns
G = +2
V
S
= ±12V
V
OUT
= 10V p-p
02464-092
5.00V 10.0ns
V
OUT
= 20V p-p
02464-095
G = +5
V
S
= ±12V
C
L
= 10pF
Figure 94. AD8130 Transient Response, VOUT = 20 V p-p, G = +5, VS = ±12 V
Figure 91. AD8130 Transient Response, VOUT = 10 V p-p, G = +2, VS = ±12 V
AD8129/AD8130
Rev. C | Page 26 of 40
AD8129 TRANSIENT RESPONSE CHARACTERISTICS
G = +10, RF = 2 kΩ, RG = 221 Ω, RL = 1 kΩ, CL = 1 pF, VS = ±5 V, TA = 25°C, unless otherwise noted.
250mV 5.00ns
V
OUT
= 1V p-p
V
S
= ±2.5V
02464-096
Figure 95. AD8129 Transient Response, VS = ±2.5 V, VOUT = 1 V p-p
250mV 5.00ns
V
OUT
= 1V p-p
V
S
= ±5V
02464-097
Figure 96. AD8129 Transient Response, VS = ±5 V, VOUT = 1 V p-p
250mV 5.00ns
02464-098
V
OUT
= 1V p-pV
S
= ±12V
Figure 97. AD8129 Transient Response, VS = ±12 V, VOUT = 1 V p-p
100mV 5.00ns
V
OUT
= 0.4V p-p
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±12V
02464-099
Figure 98. AD8129 Transient Response vs. Supply, VOUT = 0.4 V p-p
250mV 5.00ns
V
OUT
= 1V p-p
C
L
= 5pF
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±12V
02464-100
Figure 99. AD8129 Transient Response vs. Supply, VOUT = 1 V p-p, CL = 5 pF
02464-101
250mV 5.00ns
V
OUT
= 2V p-p
C
L
= 5pF
V
S
= ±5V
V
S
= ±2.5V
V
S
= ±12V
Figure 100. AD8129 Transient Response vs. Supply, VOUT = 2 V p-p, CL = 5 pF
AD8129/AD8130
Rev. C | Page 27 of 40
100mV 5.00ns
V
OUT
= 0.4V p-p
C
L
= 10pF
C
L
= 5pF
C
L
= 2pF
02464-102
Figure 101 Transient Response vs. Load Capacitance, VOUT = 0.4 V p-p
500mV 5.00ns
V
O
= 2V p-p
V
O
= 1V p-p
V
O
= 0.5V p-p
02464-103
Figure 102. Transient Response vs. Output Amplitude,
VOUT = 0.5 V p-p, 1 V p-p, 2 V p-p
1.00V 5.00ns
V
O
= 4V p-p
V
O
= 2V p-p
V
O
= 1V p-p
02464-104
Figure 103. Transient Response vs. Output Amplitude,
VOUT = 1 V p-p, 2 V p-p, 4 V p-p
250mV 5.00ns
G = +20
C
L
= 20pF
V
OUT
= 1V p-p
02464-105
Figure 104. AD8129 Transient Response, VOUT = 1 V p-p, VS = ±2.5 V to ±12 V
500mV 5.00ns
G = +20
C
L
= 20pF
V
OUT
= 2V p-p
02464-106
Figure 105. AD8129 Transient Response, VOUT = 2 V p-p, VS = ±5 V
2.00V 5.00ns
G = +20
C
L
= 20pF
02464-107
V
OUT
= 8V p-p
Figure 106. AD8129 Transient Response, VOUT = 8 V p-p, VS = ±5 V
AD8129/AD8130
Rev. C | Page 28 of 40
1.00V 5.00ns
V
IN
V
OUT
02464-108
Figure 107. AD8129 Transient Response
with +3.5 V Common-Mode Input
V
OUT
V
IN
02464-109
Figure 108. AD8129 Transient Response
with −3.5 V Common-Mode Input
2.50V 5.00ns
G = +20
V
S
= ±12V
C
L
= 20pF
V
OUT
= 10V p-p
02464-110
Figure 109. AD8129 Transient Response, VOUT = 10 V p-p, G = +20
1.00V 12.5ns
4V p-p
2V p-p
1V p-p
02464-111
G = +50
V
S
= ±5V
C
L
= 20pF
Figure 110. AD8129 Transient Response vs. Output Amplitude,
VOUT = 1 V p-p, 2 V p-p, 4 V p-p
2.00V 12.5ns
V
OUT
= 8V p-p
02464-112
G = +50
V
S
= ±5V
C
L
= 20pF
Figure 111. AD8129 Transient Response, VOUT = 8 V p-p, G = +50, VS = ±5 V
5.00V 12.5ns
VOUT = 20V p-p
02464-113
G = +50
VS = ±12V
CL = 10pF
Figure 112. AD8129 Transient Response, VOUT = 20 V p-p, G = +50, VS = ±12 V
AD8129/AD8130
Rev. C | Page 29 of 40
G = +1
V
S
= ±5V
23
20
17
14
11
–5–4–3–2–1012345
DIFFERENTIAL INPUT (V)
SUPPLY CURRENT (mA)
02464-114
Figure 113. AD8130 DC Power Supply Current vs. Differential Input Voltage
37
31
25
19
13
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
DIFFERENTIAL INPUT (V)
SUPPLY CURRENT (mA)
02464-115
G = +1
V
S
= ±10V
Figure 114. AD8129 DC Power Supply Current vs. Differential Input Voltage
TEMPERATURE(°C)
DIFFERENTIAL INPUT (V)
3.0
–50
0
–1.0
–2.0
–3.0
1.0
2.0
–35 –20 –5 10 25 40 55 70 85 100
AD8130
AD8129
AD8130
V
OUT
= 100mV AC @ 1kHz
02464-116
AD8129
Figure 115. AD8129/AD8130 Input Differential Voltage Range vs.
Temperature, 1% Gain Compression
G = +1
V
S
= ±5V
R
L
= 1kΩ
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
OUTPUT VOLTAGE (V)
GAIN NONLINEARITY (0.005%/DIV)
02464-117
Figure 116. AD8130 Gain Nonlinearity, VOUT = 2 V p-p
–2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5
OUTPUT VOLTAGE (V)
GAIN NONLINEARITY (0.08%/DIV)
02464-118
G = +1
V
S
= ±5V
R
L
= 1kΩ
Figure 117. AD8130 Gain Nonlinearity, VOUT = 5 V p-p
4
2
0
–2
–4–5–4–3–2–1012345
DIFFERENTIAL INPUT (V)
V
OUT
(V)
3
1
–1
–3
02464-119
V
S
= ±5V
Figure 118. AD8130 Differential Input Clipping Level
AD8129/AD8130
Rev. C | Page 30 of 40
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
OUTPUT VOLTAGE (V)
GAIN NONLINEARITY (0.005%/DIV)
02464-120
G = +10
V
S
= ±5V
R
L
= 1kΩ
Figure 119. AD8129 Gain Nonlinearity, VOUT = 2 V p-p
–5 –4 –3 –2 –1 0 1 2 3 4 5
OUTPUT VOLTAGE (V)
GAIN NONLINEARITY (0.2%/DIV)
02464-121
G = +10
V
S
= ±12V
R
L
= 1kΩ
Figure 120. AD8129 Gain Nonlinearity, VOUT = 10 V p-p
8
4
0
–4
–8
–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
DIFFERENTIAL INPUT (V)
OUTPUT VOLTAGE (V)
6
2
–2
–6
V
S
= ±10V
02464-122
Figure 121. AD8129 Differential Input Clipping Level
TOTAL SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
15
903
0
10 15 20 25
14
13
12
11
10
02464-123
5
Figure 122. Quiescent Power Supply Current vs. Total Supply Voltage
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
17
–50
16
15
14
13
12
11
10
9
8
7–35 –20 –5 10 25 40 55 70 85 100
V
S
= ±2.5
02464-124
V
S
=±5
V
S
= ±12
115
125
Figure 123. Quiescent Power Supply Current vs. Temperature
TEMPERATURE (°C)
INPUT BIAS CURRENT (μA)
0.60
0.15
–50
0.45
0.30
–35 –20 –5 10 25 40 55 70 85 100
INPUT OFFSET CURRENT (nA)
40
10
30
20
I
B
I
OS
02464-125
Figure 124. Input Bias Current and Input Offset Current vs. Temperature
AD8129/AD8130
Rev. C | Page 31 of 40
V
OUT
= 100mV
AC AT 1kHz
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
INPUT COMMON MODE (V)
–50–35–20–5102540557085100
TEMPERATURE (°C)
AD8130
AD8129
AD8130
AD8129
V
S
= 5V
02464-126
Figure 125. Common-Mode Voltage Range vs. Temperature,
Typical 1% Gain Compression
TEMPERATURE (°C)
INPUT COMMON MODE (V)
4.00
–50
3.75
3.50
3.25
3.00
2.75
–3.00
–3.25
–3.50
–3.75
–4.00 –35 –20 –5 10 25 40 55 70 85 100
AD8130
AD8129
AD8130
AD8129
02464-127
VS = ±5V
VOUT = 100mV
AC AT 1kHz
Figure 126. Common-Mode Voltage Range vs. Temperature,
Typical 1% Gain Compression
TEMPERATURE (°C)
INPUT COMMON MODE (V)
11.0
–50
10.5
10.0
9.5
9.0
8.5
–9.0
–9.5
–10.0
–10.5
–11.0 –35 –20 –5 10 25 40 55 70 85 100
AD8130
AD8129
V
S
= ±12V
AD8130
AD8129
V
OUT
= 100mV
AC AT 1kHz
02464-128
Figure 127. Common-Mode Voltage Range vs. Temperature,
Typical 1% Gain Compression
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
4.0
0
3.5
3.0
2.0
1.5
1.0 5 10152025303540
SINKING
V
S
= 5V
SOURCING
02464-129
V
OUT
= 100mV
AC AT 1kHz
+25°C–40°C+100°C
Figure 128. Output Voltage Range vs. Output Current,
Typical 1% Gain Compression
OUTPUT CURRENT (mA)
OUTPUT VOLTAGE (V)
4.0
0
3.5
3.0
–3.0
–3.5
–4.0 40
02464-130
V
S
= ±5V
V
OUT
= 100mV
AC AT 1kHz
5 101520253035
+25°C
–40°C
+100°C
Figure 129. Output Voltage Range vs. Output Current,
Typical 1% Gain Compression
OUTPUT CURRENT (mA)
11
0
10
9
–9
–10
–11 5 10152025303540
V
S
= ±12V
02464-131
OUTPUT VOLTAGE (V)
+25°C–40°C+100°C
Figure 130. Output Voltage Range vs. Output Current,
Typical 1% Gain Compression
AD8129/AD8130
Rev. C | Page 32 of 40
THEORY OF OPERATION
The AD8129/AD8130 use an architecture called active feedback,
which differs from that of conventional op amps. The most
obvious differentiating feature is the presence of two separate
pairs of differential inputs compared with a conventional op
amp’s single pair. Typically, for the active feedback architecture,
one of these input pairs is driven by a differential input signal,
while the other is used for the feedback. This active stage in the
feedback path is where the term active feedback is derived.
The active feedback architecture offers several advantages over a
conventional op amp in many types of applications. Among these
are excellent common-mode rejection, wide input common-mode
range, and a pair of inputs that are high impedance and completely
balanced in a typical application. In addition, while an external
feedback network establishes the gain response as in a conventional
op amp, its separate path makes it completely independent of
the signal input. This eliminates any interaction between the
feedback and input circuits, which traditionally causes problems
with CMRR in conventional differential-input op amp circuits.
Another advantage is the ability to change the polarity of the
gain merely by switching the differential inputs. A high input-
impedance inverting amplifier can be made. Besides a high
input impedance, a unity-gain inverter with the AD8130 has
a noise gain of unity. This produces lower output noise and
higher bandwidth than op amps that have noise gain equal
to 2 for a unity-gain inverter.
The two differential input stages of the AD8129/AD8130 are
each transconductance stages that are well matched. These stages
convert the respective differential input voltages to internal
currents. The currents are then summed and converted to a
voltage, which is buffered to drive the output. The compensation
capacitor is in the summing circuit.
When the feedback path is closed around the part, the output
drives the feedback input to the voltage that causes the internal
currents to sum to 0. This occurs when the two differential
inputs are equal and opposite; that is, their algebraic sum is 0.
In a closed-loop application, a conventional op amp has its
differential input voltage driven to near 0 under nontransient
conditions. The AD8129/AD8130 generally has differential
input voltages at each of its input pairs, even under equilibrium
conditions. As a practical consideration, it is necessary to limit
the differential input voltage internally with a clamp circuit.
Therefore, the input dynamic ranges are limited to about
2.5 V for the AD8130 and 0.5 V for the AD8129 (see the
AD8129/AD8130 Specifications section for more detail). For
this and other reasons, it is not recommended to reverse the
input and feedback stages of the AD8129/AD8130, even though
some apparently normal functionality may be observed under
some conditions. A few simple circuits can illustrate how the
active feedback architecture of the AD8129/AD8130 operates.
OP AMP CONFIGURATION
If only one of the input stages of the AD8129/AD8130 is used, it
functions very much like a conventional op amp (see Figure 131).
Classical inverting and noninverting op amps circuits can be
created, and the basic governing equations are the same as for a
conventional op amp. The unused input pins form the second
input and should be shorted together and tied to ground or a
midsupply voltage when they are not used.
–V
S
PD +V
S
+
+
R
F
R
G
–V
V
OUT
V
IN
+V
6
2
5
4
8
1
37
0.1
μ
F
10
μ
F
0.1
μ
F
10
μ
F
02464-132
NOTES
1. THIS CIRCUIT IS PROVIDED TO DEMONSTRATE
DEVICE OPERATION. IT IS NOT RECOMMENDED
TO USE THIS CIRCUIT IN PLACE OF AN OP AMP.
Figure 131. With Both Inputs Grounded, the Feedback Stage Functions like
an Op Amp: VOUT = VIN (1 + RF/RG).
With the unused pair of inputs shorted, there is no differential
voltage between them. This dictates that the differential input
voltage of the used inputs is also 0 for closed-loop applications.
Because this is the governing principle of conventional op amp
circuits, an active feedback amplifier can function as a
conventional op amp under these conditions.
Note that this circuit is presented only for illustration purposes
to show the similarities of the active feedback architecture
functionality to conventional op amp functionality. If it is
desired to design a circuit that can be created from a conven-
tional op amp, it is recommended to choose a conventional
op amp with specifications that are better suited to that application.
These op amp principles are the basis for offsetting the output,
as described in the Output Offset/Level Translator section.
AD8129/AD8130
Rev. C | Page 33 of 40
APPLICATIONS
BASIC GAIN CIRCUITS
The gain of the AD8129/AD8130 can be set with a pair of
feedback resistors. The basic configuration is shown in Figure 132.
The gain equation is the same as that of a conventional op amp:
G = 1 + RF/RG. For unity-gain applications using the AD8130,
RF can be set to 0 (short circuit), and RG can be removed (see
Figure 133). The AD8129 is compensated to operate at gains of
10 and higher; therefore, shorting the feedback path to obtain
unity gain causes oscillation.
R
F
R
G
–V
V
OUT
+V
V
IN
–V
S
PD +V
S
+
+
AD8129/
AD8130
6
2
5
4
8
1
37
0.1
μ
F
10
μ
F
0.1
μ
F
10
μ
F
02464-133
Figure 132. Basic Gain Circuit: VOUT = VIN (1 + RF/RG)
0.1
μ
F
–V
V
OUT
+V
0.1
μ
F10
μ
F
V
IN
AD8130
–V
S
PD +V
S
+
+
6
2
5
4
8
1
37
10
μ
F
02464-134
Figure 133. An AD8130 with Unity Gain
The input signal can be applied either differentially or in a
single-ended fashion—all that matters is the magnitude of the
differential signal between the two inputs. For single-ended
input applications, applying the signal to the +IN with −IN
grounded creates a noninverting gain, while reversing these
connections creates an inverting gain. Because the two inputs
are high impedance and matched, both of these conditions
provide the same high input impedance. Thus, an advantage of
the active feedback architecture is the ability to make a high
input impedance inverting op amp. If conventional op amps are
used, a high impedance buffer followed by an inverting stage is
needed. This requires two op amps.
TWISTED-PAIR CABLE, COMPOSITE VIDEO
RECEIVER WITH EQUALIZATION USING AN AD8130
The AD8130 has excellent common-mode rejection at its
inputs. This makes it an ideal candidate for a receiver for signals
that are transmitted over long distances on twisted-pair cables.
Category 5 cables are very common in office settings and are
extensively used for data transmission. These cables can also be
used for the analog transmission of signals such as video.
These long cables pick up noise from the environment they pass
through. This noise does not favor one conductor over another
and therefore is a common-mode signal. A receiver that rejects
the common-mode signal on the cable can greatly enhance the
signal-to-noise ratio performance of the link.
The AD8130 is also very easy to use as a differential receiver,
because the differential inputs and the feedback inputs are
entirely separate. This means that there is no interaction
between the feedback network and the termination network,
as there would be in conventional op amp types of receivers.
Another issue with long cables is that there is more attenuation
of the signal at longer distances. Attenuation is also a function
of frequency; it increases to roughly the square root of frequency.
For good fidelity of video circuits, the overall frequency
response of the transmission channel should be flat vs.
frequency. Because the cable attenuates the high frequencies, a
frequency-selective boost circuit can be used to undo this effect.
These circuits are called equalizers.
An equalizer uses frequency-dependent elements (Ls and Cs) to
create a frequency response that is the opposite of the rest of the
channel’s response to create an overall flat response. There are
many ways to create such circuits, but a common technique is to
put the frequency-selective elements in the feedback path of an
op amp circuit. The AD8130 in particular makes this easier
than other circuits, because, once again, the feedback path is
completely independent of the input path and there is no
interaction.
The circuit in Figure 134 was developed as a receiver/equalizer
for transmitting composite video over 300 meters of Category 5
cable. This cable has an attenuation of approximately 20 dB at
10 MHz for 300 meters. At 100 MHz, the attenuation is
approximately 60 dB (see Figure 135).
AD8129/AD8130
Rev. C | Page 34 of 40
R
F
1k
Ω
0.1
μ
F10
μ
F
–V
V
OUT
+V
0.1
μ
F10
μ
F
V
IN
R1
100
Ω
R
G
499
Ω
–V
S
PD +V
S
+
+
C1
2
00pF
AD8130
100
Ω
6
2
5
4
8
1
37
02464-135
Figure 134. An Equalizer Circuit for Composite Video Transmissions
over 300 Meters of Category-5 Cable
20
10
–10
–20
–30
–40
–50
–60
–70
–80
FREQUENCY (Hz)
I/O RESPONSE
0
10k 100k 1M 10M 100M
02464-136
Figure 135. Transmission Response of 300 Meters of Category-5 Cable
The feedback network is between Pin 6 and Pin 5 and from
Pin 5 to ground. C1 and RF create a corner frequency of about
800 kHz. The gain increases to provide about 15 dB of boost
at 8 MHz. The response of this circuit is shown in Figure 136.
20
10
–10
–20
–30
–40
–50
–60
–70
–80
FREQUENCY (Hz)
I/O RESPONSE
0
10k 100k 1M 10M 100M
02464-137
Figure 136. Frequency Response of Equalizer Circuit
It is difficult to calculate the exact component values via strictly
mathematical means, because the equations for the cable
attenuation are approximate and have functions that are not
simply related to the responses of RC networks. The method
used in this design was to approximate the required response
via graphical means from the frequency response and then
select components that would approximate this response. The
circuit was then built, measured, and finally adjusted to obtain
an acceptable response—in this case, flat to 9 MHz to within
approximately 1 dB (see Figure 137).
20
10
–10
–20
–30
–40
–50
–60
–70
–80
FREQUENCY (Hz)
I/O RESPONSE
0
10k 100k 1M 10M 100M
02464-138
Figure 137. Combined Response of Cable Plus Equalizer
OUTPUT OFFSET/LEVEL TRANSLATOR
The circuit in Figure 133 has the reference input (Pin 4) tied to
ground, which produces a ground-referenced output signal. If it
is desired to offset the output voltage from ground, the REF
input can be used (see Figure 138). The level VOFFSET appears at
the output with unity gain.
0.1
μ
F
–V
V
OUT
= V
IN
+V
OFFSET
+V
0.1μF10μF
V
IN
V
OFFSET
–V
S
PD +V
S
+
+
AD8130
10μF
6
2
5
4
8
1
37
02464-139
Figure 138. The Voltage Applied to Pin 4 to the Unity-Gain Output Voltage
Produced by VIN
If the circuit has a gain higher than unity, the gain must be
factored in. If RG is connected to ground, the voltage applied to
REF is multiplied by the gain of the circuit and appears at the
output—just like a noninverting conventional op amp. This
situation is not always desirable; the user may want VOFFSET to
appear at the output with unity gain.
AD8129/AD8130
Rev. C | Page 35 of 40
One way to accomplish this is to drive both REF and RG with
the desired offset signal (see Figure 139). Superposition can be
used to solve this circuit. First, break the connection between
VOFFSET and RG. With RG grounded, the gain from Pin 4 to VOUT
is 1 + RF/RG. With Pin 4 grounded, the gain though RG to VOUT
is −RF/RG. The sum of these is 1. If VREF is delivered from a low
impedance source, this works fine. However, if the delivered
offset voltage is derived from a high impedance source, such as
a voltage divider, its impedance affects the gain equation. This
makes the circuit more complicated because it creates an
interaction between the gain and offset voltage.
V
OUT =
VIN ×(1 + RF/RG)+V
OFFSET
–V
+V
V
IN
V
OFFSET
–V
S
PD +V
S
+
+
R
F
R
G
AD8129/
AD8130
6
2
5
4
8
1
37
0.1
μ
F10
μ
F
0.1
μ
F10
μ
F
02464-140
Figure 139. In this Circuit, VOFFSET Appears at the Output with Unity Gain. This
Circuit Works Well if the VOFFSET Source Impedance Is Low.
A way around this is to apply the offset voltage to a voltage
divider whose attenuation factor matches the gain of the
amplifier and then apply this voltage to the high impedance
REF input. This circuit first divides the desired offset voltage
by the gain, and the amplifier multiplies it back up to unity (see
Figure 140).
V
OUT
=
V
IN
×(1 + R
F
/R
G
)+V
OFFSET
–V
+V
V
IN
–V
S
PD +V
S
+
+
R
F
R
G
R
G
V
OFFSET
R
F
AD8129/
AD8130
6
2
5
4
8
1
37
0.1
μ
F10
μ
F
0.1
μ
F10
μ
F
02464-141
Figure 140. Adding an Attenuator at the Offset Input Causes It to Appear at
the Output with Unity Gain.
RESISTORLESS GAIN OF 2
The voltage applied to the REF input (Pin 4) can also be a high
bandwidth signal. If a unity-gain AD8130 has both +IN and
REF driven with the same signal, there is unity gain from VIN
and unity gain from VREF. Thus, the circuit has a gain of 2 and
requires no resistors (see Figure 141).
V
OUT
–V
+V
V
IN
–V
S
PD +V
S
+
+
AD8130
6
2
5
4
8
1
37
0.1
μ
F10
μ
F
0.1
μ
F10
μ
F
02464-142
Figure 141. Gain-of-2 Connections with No Resistors
SUMMER
A general summing circuit can be made by the previous
technique. A unity-gain configured AD8130 has one signal
applied to +IN, while the other signal is applied to REF. The
output is the sum of the two input signals (see Figure 142).
V
OUT
= V1 + V2
V1
V2
–V
+V
–V
S
+V
S
+
+
AD8130
6
2
5
4
8
1
37
0.1
μ
F10
μ
F
0.1
μ
F10
μ
F
02464-143
PD
Figure 142. A Summing Circuit that is Noninverting
with High Input Impedance
This circuit offers several advantages over a conventional op
amp inverting summing circuit. First, the inputs are both high
impedance and the circuit is noninverting. It would require
significant additional circuitry to make an op amp summing
circuit that has high input impedance and is noninverting.
Another advantage is that the AD8130 circuit still preserves the
full bandwidth of the part. In a conventional summing circuit,
the noise gain is increased for each additional input, so the
bandwidth response decreases accordingly. By this technique,
four signals can be summed by applying them to two AD8130s
and then summing the two outputs by a third AD8130.
CABLE-TAP AMPLIFIER
It is often desirable to have a video signal drive several pieces of
equipment. However, the cable should only be terminated once at
its endpoint; therefore, it is not appropriate to have a termination
at each device. A loop-through connection allows a device to tap
the video signal while not disturbing it by any excessive loading.
AD8129/AD8130
Rev. C | Page 36 of 40
Such a connection, also referred to as a cable-tap amplifier, can
be simply made with an AD8130 (see Figure 143). The circuit is
configured with unity gain, and if no output offset is desired,
the REF pin is grounded. The negative differential input is
connected directly to the shield of the cable (or an associated
connector) at the point at which it wants to be tapped.
75Ω
75Ω
VIDEO
IN
V
OUT
–V
+V
–V
S
PD +V
S
+
+
AD8130
6
2
5
4
8
1
37
0.1
μ
F10
μ
F
0.1
μ
F10
μ
F
02464-144
Figure 143. The AD8130 Can Tap the Video Signal at Any Point Along the
Cable Without Loading the Signal.
The center conductor connects to the positive differential input
of the AD8130. The amplitude of the video signal at this point is
unity, because it is between the two termination resistors. The
AD8130 provides a high impedance to this signal so that the
signal is not disturbed. A buffered unity-gain version of the
video signal appears at the output.
POWER-DOWN
The AD8129/AD8130 have a power-down pin that can be used
to lower the quiescent current when the amplifier is not being
used. A logic low level on the PD pin causes the part to power
down. Because there is no ground pin on the AD8129/AD8130,
there is no logic reference to interface to standard logic levels.
For this reason, the reference level for the PD input is VS. If
the AD8129/AD8130 are run with VS = 5 V, there is direct
compatibility with logic families. However, if VS is higher than
this, a level-shift circuit is needed to interface to conventional
logic levels. A simple level-shifting circuit that is compatible
with common logic families is presented in Figure 144.
AD8129/
AD8130
7
+V
S
+V
S
3PD
1k
Ω
4.99k
Ω
LOW =
POWER-DOWN 2N2222
OR EQ
02464-145
Figure 144. Circuit that Shifts the Logic Level When VS Is Not Equal to
Approximately 5 V.
EXTREME OPERATING CONDITIONS
The AD8129/AD8130 are designed to provide high
performance over a wide range of supply voltages. However,
there are some extremes of operating conditions that have
been observed to produce suboptimal results. One of these
conditions occurs when the AD8130 is operated at unity gain
with low supply voltage—less than approximately ±4 V.
At unity gain, the output drives FB directly. With supplies of
±VS less than approximately ±4 V at unity gain, the output can
drive FB’s voltage too close to the rail for the circuit to stay
properly biased. This can lead to a parasitic oscillation.
A way to prevent this is to limit the input signal swing with
clamp diodes. Common silicon-junction signal diodes like the
1N4148 have a forward bias of approximately 0.7 V when about
1 mA of current flows through them. Two series pairs of such
diodes connected antiparallel across the differential inputs can
be used to clamp the input signal and prevent this condition. It
should be noted that the REF input can also shift the output
signal; therefore, this technique only works when REF is at
ground or close to it (see Figure 145).
AD8130
V
OUT
–V
+V
–V
S
PD +V
S
+
+
V
IN
1N4148
V
IN
6
2
5
4
8
1
37
0.1
μ
F10
μ
F
0.1
μ
F10
μ
F
02464-146
Figure 145. Clamping Diodes at the Input Limits the Input Swing Amplitude
AD8129/AD8130
Rev. C | Page 37 of 40
Another problem can occur with the AD8129 operating
at a supply voltage of greater than or equal to ±12 V. The
architecture causes the supply current to increase as the input
differential voltage increases. If the AD8129 differential inputs
are overdriven too far, excessive current can flow into the device
and potentially cause permanent damage.
A practical means to prevent this from occurring is to clamp the
inputs differentially with a pair of antiparallel Schottky diodes
(see Figure 146). These diodes have a lower forward voltage of
approximately 0.4 V. If the differential voltage across the inputs
is restricted to these conditions, no excess current is drawn by
the AD8129 under these operating conditions.
If the supply voltage is restricted to less than ±11 V, the internal
clamping circuit limits the differential voltage and excessive
supply current is not drawn. The external clamp circuit is not
needed.
V
IN
AGILENT
HSMS 2822
12
3
V
OUT
–V
+V
–V
S
PD +V
S
+
+
V
IN
AD8129
6
2
5
4
8
1
37
0.1
μ
F10
μ
F
0.1
μ
F10
μ
F
02464-147
Figure 146. Schottky Diodes Across the Inputs
Limits the Input Differential Voltage
In both circuits, the input series resistors function to limit the
current through the diodes when they are forward biased. As a
practical matter, these resistors must be matched so that the
CMRR is preserved at high frequencies. These resistors have
minimal effect on the CMRR at low frequency.
POWER DISSIPATION
The AD8129/AD8130 can operate with supply voltages from
+5 V to ±12 V. The major reason for such a wide supply range is
to provide a wide input common-mode range for systems that
can require this. This would be encountered when significant
common-mode noise couples into the input path. For applications
that do not require a wide dynamic range for the input or output, it
is recommended to operate with lower supply voltages.
The AD8129/AD8130 is also available in a very small 8-lead
MSOP package. This package has higher thermal impedance
than larger packages and operates at a higher temperature with
the same amount of power dissipation. Certain operating
conditions that are within the specifications range of the parts can
cause excess power dissipation. Caution should be exercised.
The power dissipation is a function of several operating
conditions, including the supply voltage, the input differential
voltage, the output load, and the signal frequency.
A basic starting point is to calculate the quiescent power
dissipation with no signal and no differential input voltage.
This is just the product of the total supply voltage and the
quiescent operating current. The maximum operating supply
voltage is 26.4 V, and the quiescent current is 13 mA. This
causes a quiescent power dissipation of 343 mW. For the
MSOP package, the θJA specification is 142°C/W. Therefore,
the quiescent power causes about a 49°C rise above ambient
in the MSOP package.
The current consumption is also a function of the differential
input voltage (see Figure 113 and Figure 114). This current
should be added onto the quiescent current and then multiplied
by the total supply voltage to calculate the power.
The AD8129/AD8130 can directly drive loads of as low as
100 Ω, such as a terminated 50 Ω cable. The worst-case power
dissipation in the output stage occurs when the output is at
midsupply. As an example, for a 12 V supply with the output
driving a 250 Ω load to ground, the maximum power dissipation
in the output occurs when the output voltage is 6 V. The load
current is 6 V/250 Ω = 24 mA. This same current flows through
the output across a 6 V drop from VS. It dissipates 144 mW. For
the 8-lead MSOP package, this causes a temperature rise of
20°C above ambient. Although this is a worst-case number, it is
apparent that this can be a considerable additional amount of
power dissipation.
Several changes can be made to alleviate this. One is to use the
standard 8-lead SOIC package. This lowers the thermal impedance
to 121°C/W, which is a 15% improvement. Another is to use a
lower supply voltage unless absolutely necessary.
Finally, do not use the AD8129/AD8130 when it is operating on
high supply voltages to directly drive a heavy load. It is best to
use a second op amp after the output stage. Some of the gain
can be shifted to this stage so that the signal swing at the output
of the AD8129/AD8130 is not too large.
AD8129/AD8130
Rev. C | Page 38 of 40
LAYOUT, GROUNDING, AND BYPASSING
The AD8129/AD8130 are very high speed parts that can be
sensitive to the PCB environment in which they operate.
Realizing their superior specifications requires attention to
various details of standard high speed PCB design practice.
The first requirement is for a good solid ground plane that
covers as much of the board area around the AD8129/AD8130
as possible. The only exception to this is that the ground plane
around the FB pin should be kept a few millimeters away, and
the ground should be removed from the inner layers and the
opposite side of the board under this pin. This minimizes the
stray capacitance on this node and helps preserve the gain
flatness vs. frequency.
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high frequency
ceramic chip capacitors should be used, and the bypassing
should be done with a capacitance value of 0.01 μF to 0.1 μF for
each supply. Farther away, low frequency bypassing should be
provided with 10 μF tantalum capacitors from each supply to
ground.
The signal routing should be short and direct to avoid parasitic
effects. Where possible, signals should be run over ground
planes to avoid radiating or to avoid being susceptible to other
radiation sources.
AD8129/AD8130
Rev. C | Page 39 of 40
OUTLINE DIMENSIONS
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)× 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 147. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1 0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 148. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
AD8129/AD8130
Rev. C | Page 40 of 40
ORDERING GUIDE
Model Temperature Range1Package Description Package Option Branding
AD8129AR −40°C to +85°C 8-Lead SOIC R-8
AD8129AR-REEL −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8
AD8129AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8
AD8129ARZ2−40°C to +85°C 8-Lead SOIC R-8
AD8129ARZ-REEL2−40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8
AD8129ARZ-REEL72−40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8
AD8129ARM −40°C to +85°C 8-Lead MSOP RM-8 HQA
AD8129ARM-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HQA
AD8129ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HQA
AD8129ARMZ2−40°C to +85°C 8-Lead MSOP RM-8 HQA#
AD8129ARMZ-REEL2−40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HQA#
AD8129ARMZ-REEL72−40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HQA#
AD8130AR −40°C to +85°C 8-Lead SOIC R-8
AD8130AR-REEL −40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8
AD8130AR-REEL7 −40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8
AD8130ARZ2−40°C to +85°C 8-Lead SOIC R-8
AD8130ARZ-REEL2−40°C to +85°C 8-Lead SOIC, 13" Tape and Reel R-8
AD8130ARZ-REEL72−40°C to +85°C 8-Lead SOIC, 7" Tape and Reel R-8
AD8130ARM −40°C to +85°C 8-Lead MSOP RM-8 HPA
AD8130ARM-REEL −40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HPA
AD8130ARM-REEL7 −40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HPA
AD8130ARMZ2 −40°C to +85°C 8-Lead MSOP RM-8 HPA#
AD8130ARMZ-REEL2−40°C to +85°C 8-Lead MSOP, 13" Tape and Reel RM-8 HPA#
AD8130ARMZ-REEL72−40°C to +85°C 8-Lead MSOP, 7" Tape and Reel RM-8 HPA#
1 Operating temperature range for ±5 V or +5 V operation is −40°C to +125°C.
2 Z = Pb-free part; # indicates lead-free, may be top or bottom marked.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02464–0–11/05(C)
