MT18HTS25672PKY-667XX - Micron Technology, Inc.

DDR2 SDRAM Mini-RDIMM

MT18HTS25672PKY – 2GB

MT18HTS51272PKY – 4GB

Features

•244-pin, mini registered dual in-line memory

module

•Fast data transfer rates: PC2-5300, PC2-4200, or

PC2-3200

•2GB (256 Meg x 72) or 4GB (512 Meg x 72)

•Supports ECC error detection and correction

•Dual-rank, TwinDie™ (2COB) DRAM devices

•VDD = VDDQ = 1.8V

•VDDSPD = 1.7–3.6V

•JEDEC-standard 1.8V I/O (SSTL_18-compatible)

•Differential data strobe (DQS, DQS#) option

•4n-bit prefetch architecture

•Multiple internal device banks for concurrent

operation

•Programmable CAS latency (CL)

•Posted CAS additive latency (AL)

•WRITE latency = READ latency - 1 tCK

•Programmable burst length (BL) 4 or 8

•Adjustable data-output drive strength

•64ms, 8192-cycle refresh

•On-die termination (ODT)

•Serial presence-detect (SPD) with EEPROM

•Phase-lock loop (PLL) to reduce loading on system

clock

•Gold edge contacts

•Lead-free

Figure 1: 244-Pin Mini-RDIMM (MO-244 R/C X)

Module height: 30mm (1.18in)

Options Marking

•Parity P

•Operating temperature

–Commercial (0°C ≤ TA ≤ 70°C) None

–Industrial (–40°C ≤ TA ≤ 85°C)1I

•Package

–244-pin DIMM (lead-free) Y

•Frequency/CL2

–2.5ns @ CL = 5 (DDR2-800) -80E

–3.0ns @ CL = 5 (DDR2-667) -667

Notes: 1. Contact Micron for industrial temperature

module offerings.

2. CL = CAS (READ) latency; registered mode

will add one clock cycle to CL.

Table 1: Key Timing Parameters

Speed

Grade

Industry

Nomenclature

Data Rate (MT/s) tRCD

(ns)

tRP

(ns)

tRC

(ns)CL = 6 CL = 5 CL = 4 CL = 3

-80E PC2-6400 800 800 533 400 12.5 12.5 55

-800 PC2-6400 800 667 533 400 15 15 55

-667 PC2-5300 –667 553 400 15 15 55

-53E PC2-4200 – – 553 400 15 15 55

-40E PC2-3200 – – 400 400 15 15 55

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

Features

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Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 2GB 4GB

Refresh count 8K 8K

Row address 16K A[13:0] 32K A[14:0]

Device bank address 8 BA[2:0] 8 BA[2:0]

TwinDie device configuration 2Gb TwinDie (256 Meg x 8) 4Gb TwinDie (512 Meg x 8)

Column address 1K A[9:0] 1K A[9:0]

Module rank address 2 S#[1:0] 2 S#[1:0]

Table 3: Part Numbers and Timing Parameters – 2GB

Base Device: MT47H256M8THN,1 2Gb TwinDie DDR2 SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT18HTS25672PK(I)Y-80E__ 2GB 256 Meg x 72 6.4 GB/s 2.5ns/800MT/s 5-5-5

MT18HTS25672PK(I)Y-667__ 2GB 256 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Table 4: Part Numbers and Timing Parameters – 4GB

Base Device: MT47H512M8THM,1 4Gb TwinDie DDR2 SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT18HTS51272PK(I)Y-80E__ 4GB 512 Meg x 72 6.4 GB/s 2.5ns/800MT/s 5-5-5

MT18HTS51272PK(I)Y-667__ 4GB 512 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5

Notes: 1. Data sheets for the base devices can be found on Micron’s Web site.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Con-

sult factory for current revision codes. Example: MT18HTS25672PKY-667E1.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

Features

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Pin Assignments

Table 5: Pin Assignments

244-Pin Mini-RDIMM Front 244-Pin Mini-RDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1 VREF 32 VSS 63 VDDQ 94 DQS5# 123 VSS 154 DQ28 185 A3 216 NF/

RDQS5#

2 VSS 33 DQ24 64 A2 95 DQS5 124 DQ4 155 DQ29 186 A1 217 VSS

3 DQ0 34 DQ25 65 VDD 96 VSS 125 DQ5 156 VSS 187 VDD 218 DQ46

4 DQ1 35 VSS 66 VSS 97 DQ42 126 VSS 157 DM3/

RDQS3

188 CK0 219 DQ47

5 VSS 36 DQS3# 67 VSS 98 DQ43 127 DM0/

RDQS0

158 NF/

RDQS3#

189 CK0# 220 VSS

6 DQS0# 37 DQS3 68 Par_In 99 VSS 128 NF/

RDQS0#

159 VSS 190 VDD 221 DQ52

7 DQS0 38 VSS 69 VDD 100 DQ48 129 VSS 160 DQ30 191 A0 222 DQ53

8 VSS 39 DQ26 70 A10 101 DQ49 130 DQ6 161 DQ31 192 BA1 223 VSS

9 DQ2 40 DQ27 71 BA0 102 VSS 131 DQ7 162 VSS 193 VDD 224 RFU

10 DQ3 41 VSS 72 VDD 103 SA2 132 VSS 163 CB4 194 RAS# 225 RFU

11 VSS 42 CB0 73 WE# 104 NC 133 DQ12 164 CB5 195 VDDQ 226 VSS

12 DQ8 43 CB1 74 VDDQ 105 VSS 134 DQ13 165 VSS 196 S0# 227 DM6/

RDQS6

13 DQ9 44 VSS 75 CAS# 106 DQS6# 135 VSS 166 DM8/

RDQS8

197 VDDQ 228 NF/

RDQS6#

14 VSS 45 DQS8# 76 VDDQ 107 DQS6 136 DM1/

RDQS1

167 NF/

RDQS8#

198 ODT0 229 VSS

15 DQS1# 46 DQS8 77 S1# 108 VSS 137 NF/

RDQS1#

168 VSS 199 A13 230 DQ54

16 DQS1 47 VSS 78 ODT1 109 DQ50 138 VSS 169 CB6 200 VDD 231 DQ55

17 VSS 48 CB2 79 VDDQ 110 DQ51 139 NC 170 CB7 201 NC 232 VSS

18 NC 49 CB3 80 NC 111 VSS 140 NC 171 VSS 202 VSS 233 DQ60

19 NC 50 VSS 81 VSS 112 DQ56 141 VSS 172 NC 203 DQ36 234 DQ61

20 VSS 51 NC 82 DQ32 113 DQ57 142 DQ14 173 VDDQ 204 DQ37 235 VSS

21 DQ10 52 VDDQ 83 DQ33 114 VSS 143 DQ15 174 CKE1 205 VSS 236 DM7/

RDQS7

22 DQ11 53 CKE0 84 VSS 115 DQS7# 144 VSS 175 VDD 206 DM4/

RDQS4

237 NF/

RDQS7#

23 VSS 54 VDD 85 DQS4# 116 DQS7 145 DQ20 176 A15 207 NF/

RDQS4#

238 VSS

24 DQ16 55 BA2 86 DQS4 117 VSS 146 DQ21 177 NF/A141208 VSS 239 DQ62

25 DQ17 56 Err_Out# 87 VSS 118 DQ58 147 VSS 178 VDDQ 209 DQ38 240 DQ63

26 VSS 57 VDDQ 88 DQ34 119 DQ59 148 DM2/

RDQS2

179 A12 210 DQ39 241 VSS

27 DQS2# 58 A11 89 DQ35 120 VSS 149 NF/

RDQS2#

180 A9 211 VSS 242 SDA

28 DQS2 59 A7 90 VSS 121 SA0 150 VSS 181 VDD 212 DQ44 243 SCL

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

Pin Assignments

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Table 5: Pin Assignments (Continued)

244-Pin Mini-RDIMM Front 244-Pin Mini-RDIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

29 VSS 60 VDD 91 DQ40 122 SA1 151 DQ22 182 A8 213 DQ45 244 VDDSPD

30 DQ18 61 A5 92 DQ41 152 DQ23 183 A6 214 VSS

31 DQ19 62 A4 93 VSS 153 VSS 184 VDDQ 215 DM5/

RDQS5

Note: 1. Pin 177 is NF for 2GB and A14 for 4GB.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

Pin Assignments

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Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR2

modules. All pins listed may not be supported on this module. See Pin Assignments for

information specific to this module.

Table 6: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command. See the Pin Assignments Table for density-specific

addressing information.

BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA define which mode register (MR0, MR1,

MR2, and MR3) is loaded during the LOAD MODE command.

CKx,

CK#x

Input Clock: Differential clock inputs. All control, command, and address input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#.

CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-

try and clocks on the DDR2 SDRAM.

DMx, Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data

is masked when DM is sampled HIGH, along with that input data, during a write ac-

cess. Although DM pins are input-only, DM loading is designed to match that of the

DQ and DQS pins.

ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-

nation resistance internal to the DDR2 SDRAM. When enabled in normal operation,

ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input

will be ignored if disabled via the LOAD MODE command.

Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This

signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z.

S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command

decoder.

SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C

bus.

SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the

SPD EEPROM on the I2C bus.

CBx I/O Check bits. Used for system error detection and correction.

DQx I/O Data input/output: Bidirectional data bus.

DQSx,

DQS#x

I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the con-

troller. Output with read data; input with write data for source synchronous opera-

tion. DQS# is only used when differential data strobe mode is enabled via the LOAD

MODE command.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

Pin Descriptions

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Table 6: Pin Descriptions (Continued)

Symbol Type Description

SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on

the I2C bus.

RDQSx,

RDQS#x

Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD

MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS

is output with read data only and is ignored during write data. When RDQS is disa-

bled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled

and differential data strobe mode is enabled.

Err_Out# Output

(open drain)

Parity error output: Parity error found on the command and address bus.

VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the mod-

ule VDD.

VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V.

VREF Supply Reference voltage: VDD/2.

VSS Supply Ground.

NC –No connect: These pins are not connected on the module.

NF –No function: These pins are connected within the module, but provide no functionality.

NU –Not used: These pins are not used in specific module configurations/operations.

RFU –Reserved for future use.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

Pin Descriptions

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Functional Block Diagram

Figure 2: Functional Block Diagram

Par_In

S0#

S1#

BA[2:0]

A[15:0]

RAS#

CAS#

WE#

CKE0

CKE1

ODT0

ODT1

RESET#

Err_Out#

RS0#: Rank 0

RS1#: Rank 1

RBA[2/1:0]: DDR2 SDRAM

RA[14/13:0]: DDR2 SDRAM

RRAS#: DDR2 SDRAM

RCAS#: DDR2 SDRAM

RWE#: DDR2 SDRAM

RCKE0: Rank 0

RCKE1: Rank 1

RODT0: Rank 0

RODT1: Rank 1

U4, U10

VREF

VSS

DDR2 SDRAM

VDD/VDDQ

VDDSPD SPD EEPROM

DDR2 SDRAM

SPD EEPROM

A1 A2

SA0 SA1 SA2

SDA

SCL

PLL

CK0

CK0#

DDR2 SDRAM x 2

RESET#

U11

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U1b

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U1t

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U5b

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U5t

DQS0

DQS0#

DM0/RDQS0

NF/RDQS0#

DQS4

DQS4#

DM4/RDQS4

NF/RDQS4#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U13b

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U13t

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U9b

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U9t

DQS1

DQS1#

DM1/RDQS1

NF/RDQS1#

DQS5

DQS5#

DM5/RDQS5

NF/RDQS5#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U2b

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U2t

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U6b

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U6t

DQS2

DQS2#

DM2/RDQS2

NF/RDQS2#

DQS6

DQS6#

DM6/RDQS6

NF/RDQS6#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U3b

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U3t

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U8b

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U8t

DQS3

DQS3#

DM3/RDQS3

NF/RDQS3#

DQS7

DQS7#

DM7/RDQS7

NF/RDQS7#

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U12b

DM/ NF/ CS# DQS DQS#

RDQS RDQS#

U12t

DQS8

DQS8#

DM8/RDQS8

NF/RDQS8#

RS1#

RS0#

Rank 0 = U1b–U3b, U5b , U6b, U8b, U9b, U12b, U13b

Rank 1 = U1t–U3t, U5t , U6t, U8t, U9t, U12t, U13t

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

Functional Block Diagram

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General Description

DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory mod-

ules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM

modules use DDR architecture to achieve high-speed operation. DDR2 architecture is

essentially a 4n-prefetch architecture with an interface designed to transfer two data

words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM

module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the

internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-

fers at the I/O pins.

DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK

and CK# to capture commands, addresses, and control signals. Differential clocks and

data strobes ensure exceptional noise immunity for these signals and provide precise

crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is trans-

mitted externally, along with data, for use in data capture at the receiver. DQS is a

strobe transmitted by the DDR2 SDRAM device during READs and by the memory con-

troller during WRITEs. DQS is edge-aligned with data for READs and center-aligned

with data for WRITEs.

DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of

CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Com-

mands (address and control signals) are registered at every positive edge of CK. Input

data is registered on both edges of DQS, and output data is referenced to both edges of

DQS, as well as to both edges of CK.

Serial Presence-Detect EEPROM Operation

DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a

256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the mod-

ule type and various SDRAM organizations and timing parameters. The remaining 128

bytes of storage are available for use by the customer. System READ/WRITE operations

between the master (system logic) and the slave EEPROM device occur via a standard

I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect

(WP) is connected to VSS, permanently disabling hardware write protection.

DDR2 SDRAM modules operate in registered mode, where the command/address input

signals are latched in the registers on the rising clock edge and sent to the DDR2

SDRAM devices on the following rising clock edge (data access is delayed by one clock

cycle). A phase-lock loop (PLL) on the module receives and redrives the differential

clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize

system and clock loading. PLL clock timing is defined by JEDEC specifications and en-

sured by use of the JEDEC clock reference board. Registered mode will add one clock

cycle to CL.

Parity Operations

The registering clock driver can accept a parity bit from the system’s memory control-

ler, providing even parity for the control, command, and address bus. Parity errors are

flagged on the Err_Out# pin. Systems not using parity are expected to function without

issue if Par_In and Err_Out# are left as no connects (NC) to the system.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

General Description

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Electrical Specifications

Stresses greater than those listed may cause permanent damage to the DRAM devices

on the module. This is a stress rating only, and functional operation of the module at

these or any other conditions outside those indicated on each device’s data sheet is not

implied. Exposure to absolute maximum rating conditions for extended periods may

adversely affect reliability.

Table 7: Absolute Maximum DC Ratings

Symbol Parameter Min Max Units

VDD/VDDQ VDD/VDDQ supply voltage relative to VSS –0.5 2.3 V

VIN, VOUT Voltage on any pin relative to VSS –0.5 2.3 V

IIInput leakage current; Any input 0V ≤ VIN ≤ VDD;

VREF input 0V ≤ VIN ≤ 0.95V (All other pins not under

test = 0V)

Address inputs: RAS#,

CAS#, WE# S#, CKE,

BA, ODT

–5 5 µA

CK, CK# –250 250

DM –10 10

IOZ Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs and

ODT are disabled

DQ, DQS, DQS# –10 10 µA

IVREF VREF leakage current; VREF = valid VREF level –36 36 µA

TAModule ambient operating temperature Commercial 0 70 °C

Industrial –40 85 °C

TC1DDR2 SDRAM component case operating tempera-

ture2

Commercial 0 85 °C

Industrial –40 95 °C

Notes: 1. The refresh rate is required to double when 85°C < TC ≤ 95°C.

2. For further information, refer to technical note TN-00-08: “Thermal Applications,” avail-

able on Micron’s Web site.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

Electrical Specifications

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DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR2 component data sheets.

Component specifications are available on Micron's Web site. Module speed grades cor-

relate with component speed grades.

Table 8: Module and Component Speed Grades

DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades

Module Speed Grade Component Speed Grade

-1GA -187E

-80E -25E

-800 -25

-667 -3

-53E -37E

-40E -5E

Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully de-

signed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level. Mi-

cron encourages designers to simulate the signal characteristics of the system's memo-

ry bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to en-

sure the required supply voltage is maintained.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

DRAM Operating Conditions

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IDD Specifications

Table 9: IDD Specifications and Conditions – 2GB

Values are shown for the MT47H256M8 DDR2 SDRAM only and are computed from values specified in the 2Gb TwinDie

(256 Meg x 8) component data sheet

Parameter/Condition Symbol -80E -667 Units

Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC

(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are switching

ICDD0 918 873 mA

Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL

= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =

tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data pattern is same as IDD4W

ICDD1 1098 1008 mA

Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is

LOW; Other control and address bus inputs are stable; Data bus inputs are floating

ICDD2P 126 126 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-

puts are floating

ICDD2Q 513 423 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH,

S# is HIGH; Other control and address bus inputs are switching; Data bus inputs

are switching

ICDD2N 558 468 mA

Active power-down current: All device banks open; tCK =

tCK (IDD); CKE is LOW; Other control and address bus inputs are

stable; Data bus inputs are floating

Fast PDN exit

MR[12] = 0

ICDD3P 333 333 mA

Slow PDN exit

MR[12] = 1

153 153 mA

Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS

MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are switching

ICDD3N 648 603 mA

Operating burst write current: All device banks open; Continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =

tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data bus inputs are switching

ICDD4W 1548 1323 mA

Operating burst read current: All device banks open; Continuous burst reads;

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),

tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

ICDD4R 1548 1323 mA

Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD)

interval; CKE is HIGH, S# is HIGH between valid commands; Other control and

address bus inputs are switching; Data bus inputs are switching

ICDD5 2223 2043 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address

bus inputs are floating; Data bus inputs are floating

ICDD6 126 126 mA

Operating bank interleave read current: All device banks interleaving reads;

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD),

tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH be-

tween valid commands; Address bus inputs are stable during deselects; Data bus

inputs are switching

ICDD7 3123 2628 mA

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

IDD Specifications

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Table 10: IDD Specifications and Conditions – 4GB

Values are shown for the MT47H512M8 DDR2 SDRAM only and are computed from values specified in the 4Gb TwinDie

(512 Meg x 8) component data sheet

Parameter/Condition Symbol -80E -667 Units

Operating one bank active-precharge current: tCK = tCK (IDD), tRC = tRC

(IDD), tRAS = tRAS MIN (IDD); CKE is HIGH, S# is HIGH between valid commands;

Address bus inputs are switching; Data bus inputs are switching

ICDD0 1017 1035 mA

Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL

= CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD =

tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data pattern is same as IDD4W

ICDD1 1620 1440 mA

Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is

LOW; Other control and address bus inputs are stable; Data bus inputs are floating

ICDD2P 180 180 mA

Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus in-

puts are floating

ICDD2Q 675 585 mA

Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH,

S# is HIGH; Other control and address bus inputs are switching; Data bus inputs

are switching

ICDD2N 765 675 mA

Active power-down current: All device banks open; tCK =

tCK (IDD); CKE is LOW; Other control and address bus inputs are

stable; Data bus inputs are floating

Fast PDN exit

MR[12] = 0

ICDD3P 432 432 mA

Slow PDN exit

MR[12] = 1

162 162 mA

Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS

MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands;

Other control and address bus inputs are switching; Data bus inputs are switching

ICDD3N 720 630 mA

Operating burst write current: All device banks open; Continuous burst

writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP =

tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs

are switching; Data bus inputs are switching

ICDD4W 1755 1485 mA

Operating burst read current: All device banks open; Continuous burst reads;

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),

tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus

inputs are switching; Data bus inputs are switching

ICDD4R 1845 1665 mA

Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD)

interval; CKE is HIGH, S# is HIGH between valid commands; Other control and

address bus inputs are switching; Data bus inputs are switching

ICDD5 2835 2655 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address

bus inputs are floating; Data bus inputs are floating

ICDD6 180 180 mA

Operating bank interleave read current: All device banks interleaving reads;

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD),

tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH be-

tween valid commands; Address bus inputs are stable during deselects; Data bus

inputs are switching

ICDD7 3645 3295 mA

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

IDD Specifications

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Table 11: Register Specifications

SSTU32866 devices or equivalent

Parameter Symbol Pins Condition Min Max Units

DC high-level

input voltage

VIH(DC) Control, command,

address

SSTL_18 VREF(DC) + 125 VDDQ + 250 mV

DC low-level

input voltage

VIL(DC) Control, command,

address

SSTL_18 0 VREF(DC) - 125 mV

AC high-level

input voltage

VIH(AC) Control, command,

address

SSTL_18 VREF(DC) + 250 –mV

AC low-level

input voltage

VIL(AC) Control, command,

address

SSTL_18 –VREF(DC) - 250 mV

Output high

voltage

VOH Parity output LVCMOS 1.2 –V

Output low voltage VOL Parity output LVCMOS –0.5 V

Input current IIAll pins VI = VDD or VSS –0.5 µA

Static standby IDD All pins RESET# = VSSQ (Io = 0) –5 5 mA

Static operating IDD All pins RESET# = VSS; VI = VIH(AC)

or VIL(DC) Io = 0

–100 mA

Dynamic operating

(clock tree)

IDDD N/A RESET# = VDD;

VI = VIH(DC) or VIL(AC),

IO = 0; CK and CK# switch-

ing 50% duty cycle

–Varies by

manufacturer

µA

Dynamic operating

(per each input)

IDDD N/A RESET# = VDD;

VI = VIH(AC) or VIL(DC), IO =

0; CK and CK#

switching 50% duty cy-

cle; One data in/out

switching at tCK/2, 50%

duty cycle

–Varies by

manufacturer

µA

Input capacitance

(per device, per pin)

CIN All inputs except

RESET#

VI = VREF ±250mV;

VDD = 1.8V

2.5 3.5 pF

Input capacitance

(per device, per pin)

CIN RESET# VI = VDD or VSS Varies by

manufacturer

Varies by

manufacturer

Note: 1. Timing and switching specifications for the register listed are critical for proper opera-

tion of the DDR2 SDRAM RDIMMs. These are meant to be a subset of the parameters for

the specific device used on the module. Detailed information for this register is available

in JEDEC standard JESD82.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

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hts18c256_512x72pky.pdf - Rev. C 3/10 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 12: PLL Specifications

CU877 device or equivalent

Parameter Symbol Pins Condition Min Max Units

DC high-level

input voltage

VIH RESET# LVCMOS 0.65 × VDD –V

DC low-level

input voltage

VIL RESET# LVCMOS –0.35 × VDD V

Input voltage (limits) VIN RESET#, CK, CK# –0.3 VDD + 0.3 V

DC high-level

input voltage

VIH CK, CK# Differential input 0.65 × VDD –V

DC low-level

input voltage

VIL CK, CK# Differential input –0.35 × VDD V

Input differential-pair

cross voltage

VIX CK, CK# Differential input (VDDQ/2) - 0.15 (VDD/2) - 0.15 V

Input differential

voltage

VID(DC) CK, CK# Differential input 0.3 VDD - 0.4 V

Input differential

voltage

VID(AC) CK, CK# Differential input 0.6 VDD - 0.4 V

Input current IIRESET# VI = VDD or VSS –10 10 µA

CK, CK# VI = VDD or VSS –250 250 µA

Output disabled

current

IODL RESET# = VSS; VI = VIH(AC)

or VIL(DC)

100 –µA

Static supply current IDDLD CK = CK# = LOW –500 µA

Dynamic supply IDD N/A CK, CK# = 270 MHz, all

outputs open (not con-

nected to PCB)

–300 mA

Input capacitance CIN Each input VI = VDD or VSS 2 3 pF

Table 13: PLL Clock Driver Timing Requirements and Switching Characteristics

Parameter Symbol Min Max Units

Stabilization time tL–15 μs

Input clock slew rate slr(i) 1.0 4.0 V/ns

SSC modulation frequency –30 33 kHz

SSC clock input frequency deviation –0.0 –0.5 %

PLL loop bandwidth (–3dB from unity gain) –2.0 –MHz

Note: 1. PLL timing and switching specifications are critical for proper operation of the DDR2

DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information

is available in JEDEC standard JESD82.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

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hts18c256_512x72pky.pdf - Rev. C 3/10 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice.

Serial Presence-Detect

For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.

Table 14: SPD EEPROM Operating Conditions

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 1.7 3.6 V

Input high voltage: logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V

Input low voltage: logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V

Output low voltage: IOUT = 3mA VOL –0.4 V

Input leakage current: VIN = GND to VDD ILI 0.1 3 µA

Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA

Standby current ISB 1.6 4 µA

Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA

Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA

Table 15: SPD EEPROM AC Operating Conditions

Parameter/Condition Symbol Min Max Units Notes

SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1

Time bus must be free before a new transition can start tBUF 1.3 –µs

Data-out hold time tDH 200 –ns

SDA and SCL fall time tF–300 ns 2

SDA and SCL rise time tR–300 ns 2

Data-in hold time tHD:DAT 0 –µs

Start condition hold time tHD:STA 0.6 –µs

Clock HIGH period tHIGH 0.6 –µs

Noise suppression time constant at SCL, SDA inputs tI–50 µs

Clock LOW period tLOW 1.3 –µs

SCL clock frequency tSCL –400 kHz

Data-in setup time tSU:DAT 100 –ns

Start condition setup time tSU:STA 0.6 –µs 3

Stop condition setup time tSU:STO 0.6 –µs

WRITE cycle time tWRC –10 ms 4

Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1

and the falling or rising edge of SDA.

2. This parameter is sampled.

3. For a restart condition or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a

write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the

WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-

up resistance, and the EEPROM does not respond to its slave address.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

Serial Presence-Detect

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Module Dimensions

Figure 3: 244-Pin DDR2 Mini-RDIMM

82.127 (3.233)

81.873 (3.223)

Front view

30.152 (1.187)

29.848 (1.175)

20.0 (0.787)

TYP

10.0 (0.394)

TYP

1.0 (0.039)

TYP

2.0 (0.079) R

1.0 (0.039) R

0.50 (0.02) R

1.80 (0.071) D

6.0 (0.236)

TYP

2.0 (0.079)

TYP

78.0 (3.071)

TYP

0.60 (0.024)

TYP

0.45 (0.018)

TYP

Pin 1 Pin 122

42.9 (1.689)

TYP

Back view

3.3 (0.130)

TYP

3.6 (0.142) TYP

33.6 (1.323)

TYP

38.4 (1.512)

TYP

3.2 (0.126)

TYP

3.80 (0.150)

MAX

1.10 (0.043)

0.90 (0.035)

Pin 244 Pin 123

U1 U2 U3

U5 U6

U8 U9

U10

U11

U12 U13

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for

additional design dimensions.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

www.micron.com/productsupport Customer Comment Line: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

2GB, 4GB (x72, DR) 244-Pin DDR2 Mini-RDIMM

Module Dimensions

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hts18c256_512x72pky.pdf - Rev. C 3/10 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice.