Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - (c) NXP N.V. (year). All rights reserved or (c) Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - (c) Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia DISCRETE SEMICONDUCTORS DATA SHEET BSP230 P-channel enhancement mode vertical D-MOS transistor Product specification Supersedes data of 1997 Jun 17 File under Discrete Semiconductors, SC13b 1997 Oct 21 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP230 FEATURES * Direct interface to C-MOS, TTL, etc. * High-speed switching * No secondary breakdown. 4 handbook, halfpage d APPLICATIONS * Line current interruptor in telephone sets g * Relay, high speed and line transformer drivers. 1 2 3 Top view s MAM121 DESCRIPTION P-channel enhancement mode vertical D-MOS transistor in a SOT223 plastic SMD package. Fig.1 Simplified outline and symbol. PINNING - SOT223 PIN SYMBOL DESCRIPTION 1 g gate CAUTION 2 d drain 3 s source 4 d drain The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. - MAX. -300 UNIT VDS drain-source voltage (DC) VGSO gate-source voltage (DC) open drain - 20 V VGSth gate-source threshold voltage ID = -1 mA; VDS = VGS -1.95 -2.8 V ID drain current (DC) - -210 mA RDSon drain-source on-state resistance ID = -170 mA; VGS = -10 V - 17 Ptot total power dissipation Tamb 25 C - 1.5 W 1997 Oct 21 2 V Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP230 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT - -300 V - 20 V - -210 mA - -0.75 A - 1.5 W storage temperature -65 +150 C operating junction temperature - 150 C VDS drain-source voltage (DC) VGSO gate-source voltage (DC) ID drain current (DC) IDM peak drain current Ptot total power dissipation Tstg Tj open drain Tamb 25 C; note 1 THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 83.3 K/W note 1 Note to the Limiting values and Thermal characteristics 1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm; mounting pad for drain lead minimum 6 cm2. CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL PARAMETER CONDITIONS V(BR)DSS drain-source breakdown voltage VGS = 0; ID = -10 A MIN. -300 TYP. - MAX. - UNIT V VGSth gate-source threshold voltage VDS = VGS ; ID = -1 mA -1.95 - -2.8 V IDSS drain-source leakage current VGS = 0; VDS = -240 V - - -100 nA IGSS gate leakage current VGS = 20 V; VDS = 0 - - 100 nA RDSon drain-source on-state resistance VGS = -10 V; ID = -170 mA - - 17 yfs forward transfer admittance VDS = -25 V; ID = -170 mA 100 - - mS Ciss input capacitance VGS = 0; VDS = -25 V; f = 1 MHz - 60 90 pF Coss output capacitance VGS = 0; VDS = -25 V; f = 1 MHz - 15 30 pF Crss reverse transfer capacitance VGS = 0; VDS = -25 V; f = 1 MHz - 5 15 pF Switching times (see Figs 2 and 3) ton turn-on time VGS = 0 to -10 V; VDD = -50 V; ID = -250 mA - 5 10 ns toff turn-off time VGS = -10 to 0 V; VDD = -50 V; ID = -250 mA - 15 30 ns 1997 Oct 21 3 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP230 VDD = -50 V handbook, halfpage handbook, halfpage 10 % INPUT 90 % 10 % 0V ID -10 V OUTPUT 50 90 % MBB689 ton toff MBB690 Fig.2 Switching time test circuit. Fig.3 Input and output waveforms. MLC687 1.6 MLC694 -1 handbook, halfpage handbook, halfpage Ptot (W) tp = (1) ID (A) 10 s 100 s 1.2 1 ms -10-1 10 ms 100 ms 0.8 -10-2 = P 1s tp T 0.4 DC t tp -10-3 -1 0 0 50 100 150 200 Tamb (C) T -10 -102 = 0.01. Tamb = 25 C. (1) RDSon limitation. Fig.4 Power derating curve. 1997 Oct 21 Fig.5 DC SOAR. 4 VDS (V) -103 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP230 MLC688 100 MLC690 -800 handbook, halfpage handbook, halfpage C (pF) ID (mA) 80 VGS= -10 V -7 V -6 V P = 1.5 W -600 Ciss -5 V 60 -400 40 -4 V -200 Coss 20 -3.5 V Crss 0 -10 0 -20 -3 V VDS (V) 0 -30 -2 0 -4 -8 -6 -12 -10 VDS (V) VGS = 0. Tj = 25 C. f = 1 MHz. Fig.6 Tj = 25 C. Capacitance as a function of drain source voltage; typical values. Fig.7 Typical output characteristics. MLC689 -800 MLC691 80 handbook, halfpage handbook, halfpage RDSon () ID (mA) -600 60 -400 40 -200 20 0 0 -2 -4 -6 0 -8 -10 VGS (V) -2 0 -4 -6 -8 -10 VGS (V) ID = -170 mA. Tj = 25 C. VDS = -25 V. Tj = 25 C. Fig.9 Fig.8 Typical transfer characteristics. 1997 Oct 21 5 Drain-source on-state resistance as a function of gate-source voltage; typical values. Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP230 MLC692 60 RDSon () 50 MLC696 1.1 handbook, halfpage handbook, halfpage VGS = -3 V -4 V -5 V k 1.0 40 30 0.9 20 -6 V -7 V -10 V 10 0 -10 1 -102 ID (mA) 0.8 -50 -103 0 50 100 150 Tj (C) V GSth at T j k = ------------------------------------V GSth at 25C Tj = 25 C. Typical VGSth at ID = -1 mA; VDS = VGS. Fig.10 Drain-source on-state resistance as a function of drain current; typical values. Fig.11 Temperature coefficient of gate-source threshold voltage. MLC695 2.5 handbook, halfpage k 2 1.5 1 0.5 0 -50 0 50 100 150 Tj (C) R DSon at T j k = ---------------------------------------R DSon at 25 C Typical RDSon at ID = -170 mA; VGS = -10 V. Fig.12 Temperature coefficient of drain-source on-state resistance. 1997 Oct 21 6 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP230 MLC693 102 handbook, full pagewidth Rth j-a (K/W) = 0.75 0.5 0.2 10 0.1 0.05 0.02 0.01 1 tp = T P 0 t tp T 10-1 10-5 10-4 10-3 10-2 10-1 1 10 102 t p (s) 103 Tamb = 25 C. Fig.13 Transient thermal resistance from junction to ambient as a function of pulse time; typical values. 1997 Oct 21 7 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP230 PACKAGE OUTLINE Plastic surface mounted package; collector pad for good heat transfer; 4 leads D SOT223 E B A X c y HE v M A b1 4 Q A A1 1 2 3 Lp bp e1 w M B detail X e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y mm 1.8 1.5 0.10 0.01 0.80 0.60 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 4.6 2.3 7.3 6.7 1.1 0.7 0.95 0.85 0.2 0.1 0.1 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 96-11-11 97-02-28 SOT223 1997 Oct 21 EUROPEAN PROJECTION 8 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP230 DEFINITIONS Data Sheet Status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1997 Oct 21 9 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP230 NOTES 1997 Oct 21 10 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP230 NOTES 1997 Oct 21 11 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 137107/00/03/pp12 Date of release: 1997 Oct 21 Document order number: 9397 750 02975