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DATA SH EET
Product specification
Supersedes data of 1997 Jun 17
File under Discrete Semiconductors, SC13b
1997 Oct 21
DISCRETE SEMICONDUCTORS
BSP230
P-channel enhancement mode
vertical D-MOS transistor
1997 Oct 21 2
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSP230
FEATURES
•Direct interface to C-MOS, TTL, etc.
•High-speed switching
•No secondary breakdown.
APPLICATIONS
•Line current interruptor in telephone sets
•Relay, high speed and line transformer drivers.
DESCRIPTION
P-channel enhancement mode vertical D-MOS transistor
in a SOT223 plastic SMD package.
PINNING - SOT223
PIN SYMBOL DESCRIPTION
1 g gate
2 d drain
3 s source
4 d drain
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
Fig.1 Simplified outline and symbol.
handbook, halfpage
MAM121
4
123
Top view s
d
g
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage (DC) −−300 V
VGSO gate-source voltage (DC) open drain −±20 V
VGSth gate-source threshold voltage ID=−1 mA; VDS =V
GS −1.95 −2.8 V
IDdrain current (DC) −−210 mA
RDSon drain-source on-state resistance ID=−170 mA; VGS =−10 V −17 Ω
Ptot total power dissipation Tamb ≤25 °C−1.5 W
1997 Oct 21 3
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSP230
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
THERMAL CHARACTERISTICS
Note to the Limiting values and Thermal characteristics
1. Device mounted on an epoxy printed-circuit board, 40 ×40 ×1.5 mm; mounting pad for drain lead minimum 6 cm2.
CHARACTERISTICS
Tj=25°C unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage (DC) −−300 V
VGSO gate-source voltage (DC) open drain −±20 V
IDdrain current (DC) −−210 mA
IDM peak drain current −−0.75 A
Ptot total power dissipation Tamb ≤25 °C; note 1 −1.5 W
Tstg storage temperature −65 +150 °C
Tjoperating junction temperature −150 °C
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to ambient note 1 83.3 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS drain-source breakdown voltage VGS = 0; ID=−10 µA−300 −−V
V
GSth gate-source threshold voltage VDS =V
GS; ID=−1mA −1.95 −−2.8 V
IDSS drain-source leakage current VGS = 0; VDS =−240 V −−−100 nA
IGSS gate leakage current VGS =±20 V; VDS =0 −−±100 nA
RDSon drain-source on-state resistance VGS =−10 V; ID=−170 mA −−17 Ω
yfsforward transfer admittance VDS =−25 V; ID=−170 mA 100 −−mS
Ciss input capacitance VGS = 0; VDS =−25 V; f = 1 MHz −60 90 pF
Coss output capacitance VGS = 0; VDS =−25 V; f = 1 MHz −15 30 pF
Crss reverse transfer capacitance VGS = 0; VDS =−25 V; f = 1 MHz −515pF
Switching times (see Figs 2 and 3)
ton turn-on time VGS =0to−10 V; VDD =−50 V;
ID=−250 mA −510ns
t
off turn-off time VGS =−10 to 0 V; VDD =−50 V;
ID=−250 mA −15 30 ns
1997 Oct 21 4
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSP230
Fig.2 Switching time test circuit.
handbook, halfpage
MBB689
50 Ω
VDD = −50 V
ID
0 V
−10 V
Fig.3 Input and output waveforms.
handbook, halfpage
MBB690
10 %
90 %
90 %
10 %
ton toff
OUTPUT
INPUT
Fig.4 Power derating curve.
handbook, halfpage
0 200
0
0.4
0.8
1.2
1.6
MLC687
Tamb (°C)
50 100 150
Ptot
(W)
δ= 0.01.
Tamb =25°C.
(1) RDSon limitation.
Fig.5 DC SOAR.
handbook, halfpage
MLC694
VDS (V)
ID
(A)
−1
−1−10
−10
−1
−10
−2
−10
2
−10
3
−10
−3
tp
tp
T
P
t
T
δ
=1 s
100 µs
1 ms
10 ms
100 ms
DC
(1) tp =
10 µs
1997 Oct 21 5
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSP230
Fig.6 Capacitance as a function of drain source
voltage; typical values.
VGS =0.
T
j=25°C.
f = 1 MHz.
handbook, halfpage
0
100
60
80
40
20
0−10 −20 −30
MLC688
C
(pF)
VDS (V)
Ciss
Coss
Crss
Fig.7 Typical output characteristics.
Tj=25°C.
handbook, halfpage
0−2−4−10
−800
−600
−200
0
−400
MLC690
−6
ID
(mA)
VDS (V)
−12−8
P = 1.5 W VGS= −10 V
−7 V
−6 V
−5 V
−4 V
−3.5 V
−3 V
Fig.8 Typical transfer characteristics.
VDS =−25 V.
Tj=25°C.
handbook, halfpage
0−2−4−10
−800
−600
−200
0
−400
MLC689
−6
ID
(mA)
VGS (V)
−8
Fig.9 Drain-source on-state resistance as a
function of gate-source voltage; typical
values.
ID=−170 mA.
Tj=25°C.
handbook, halfpage
0
20
40
60
80
0−2−4−6−8−10
RDSon
(Ω)
VGS (V)
MLC691
1997 Oct 21 6
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSP230
Fig.10 Drain-source on-state resistance as a
function of drain current; typical values.
Tj=25°C.
handbook, halfpage
0
10
20
30
40
50
60
1−10 −10
2
−10
3
ID (mA)
VGS = −3 V −4 V −5 V
MLC692
−6 V
−7 V
−10 V
RDSon
(Ω)
Fig.11 Temperature coefficient of gate-source
threshold voltage.
Typical VGSth at ID=−1 mA; VDS =V
GS.
kVGSth at Tj
VGSth at 25°C
--------------------------------------
=
handbook, halfpage
0.8
0.9
1.0
1.1
0 50 100 150−50
k
Tj (°C)
MLC696
Fig.12 Temperature coefficient of drain-source
on-state resistance.
Typical RDSon at ID=−170 mA; VGS =−10 V.
kRDSon at Tj
RDSon at 25 °C
-----------------------------------------
=
handbook, halfpage
0
0.5
1
1.5
2
2.5
0 50 100 150
k
Tj (°C)
MLC695
−50
1997 Oct 21 7
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSP230
Fig.13 Transient thermal resistance from junction to ambient as a function of pulse time; typical values.
Tamb =25°C.
handbook, full pagewidth
1
10
0.5
0.2
0.1
0.05
0.02
0.01
0
110
102
MLC693
tp (s)
δ =
0.75
tp
tp
T
P
t
T
δ=
Rth j-a
(K/W)
10−1
10−510−410−310−210−1102103
1997 Oct 21 8
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSP230
PACKAGE OUTLINE
UNIT A1bpcDEe
1H
EL
pQywv
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.10
0.01
1.8
1.5 0.80
0.60
b1
3.1
2.9 0.32
0.22 6.7
6.3 3.7
3.3 2.3
e
4.6 7.3
6.7 1.1
0.7 0.95
0.85 0.1 0.10.2
DIMENSIONS (mm are the original dimensions)
SOT223 96-11-11
97-02-28
wM
bp
D
b1
e1
e
A
A1
Lp
Q
detail X
HE
E
vMA
AB
B
c
y
0 2 4 mm
scale
A
X
132
4
Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223
1997 Oct 21 9
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSP230
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data Sheet Status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
1997 Oct 21 10
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSP230
NOTES
1997 Oct 21 11
Philips Semiconductors Product specification
P-channel enhancement mode
vertical D-MOS transistor BSP230
NOTES
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© Philips Electronics N.V. 1997 SCA55
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Printed in The Netherlands 137107/00/03/pp12 Date of release: 1997 Oct 21 Document order number: 9397 750 02975
