1. General description
The HEF4053B is a triple single-po le double-throw (SPDT) analog switch, suitable for use
as an analog or digital multiplexer/demultiplexer. Each switch has a digital select input
(Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All
three switches sh ar e an enab le inp ut (E ). A HIGH on E causes all switches into the
high-impedance OFF-state, independent of Sn.
VDD and VSS are the supply voltage connections for the digital control inputs (Sn and E).
The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0, nY1 and nZ) can
swing between VDD as a positive limit and VEE as a negative limit. VDD VEE may not
exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For
operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically
ground). VEE and VSS are the supply voltage connections for the switches.
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +125 C
Complies with JEDEC standard JESD 13-B
3. Applications
Analog multiplexing and demultiplexing
Digital multiplexing and demultiplexing
Signal gating
4. Ordering information
HEF4053B
Triple single-pole double-throw analog switch
Rev. 11 — 11 September 2014 Product data sheet
Table 1. Ordering information
All types operate from
40
C to +125
C.
Type number Package
Name Description Version
HEF4053BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4053BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
HEF4053BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 2 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
5. Functional diagram
Fig 1. Logic symbol Fig 2. Functional diagram
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LOGIC
LEVEL
CONVERSION
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16
VDD
13 1Y1
S1
LOGIC
LEVEL
CONVERSION
DECODER
LOGIC
LEVEL
CONVERSION
12 1Y0
14 1Z
1 2Y1
2 2Y0
15 2Z
3 3Y1
5 3Y0
43Z
10
S2
9
87
VEE
VSS
S3
6
E
Fig 3. Logic diagram (one multiplexer/demultiplexer)
001aae645
nY1
nZ
nY0
LEVEL
CONVERTER
LEVEL
CONVERTER to other multiplexers/demultiplexers
Sn
E
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 3 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 4. Schematic diagram (on e sw itc h)
001aae644
nYn
nZ
VEE
from decoder
and enable logic
VDD VDD
Fig 5. Pin configuration for SOT38-4 (DIP16) and
SOT109-1 (SO16) Fig 6. Pin configuration for SOT403-1 (TSSOP16)
HEF4053B
2Y1 VDD
2Y0 2Z
3Y1 1Z
3Z 1Y1
3Y0 1Y0
ES1
VEE S2
VSS S3
001aae643
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
HEF4053B
2Y1 V
DD
2Y0 2Z
3Y1 1Z
3Z 1Y1
3Y0 1Y0
ES1
V
EE
S2
V
SS
S3
001aaj899
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
E6 enable input (active LOW)
VEE 7 supply voltage
VSS 8 ground supply voltage
S1, S2, S3 11, 10, 9 select input
1Y0, 2Y0, 3Y0 12, 2, 5 independent input or output
1Y1, 2Y1, 3Y1 13, 1, 3 independent input or output
1Z, 2Z, 3Z 14, 15, 4 independent output or input
VDD 16 supply voltage
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 4 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
[1] To avoid drawing VDD current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional
switch must not exceed 0.4 V . If the switch current flows into terminal Z, no VDD current will flow out of terminals Y, and in this case there
is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed VDD or VEE.
[2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
9. Recommended operating conditions
Table 3. Function table [1]
Inputs Channel on
ESn
LLnY0 to nZ
L H nY1 to nZ
H X switches OFF
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +18 V
VEE supply voltage referenced to VDD [1] 18 +0.5 V
IIK input clamping current pins Sn and E;
VI<0.5 V or VI>V
DD + 0.5 V -10 mA
VIinput voltage 0.5 VDD + 0.5 V
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +125 C
Ptot total power dissipation Tamb = 40 C to +125 C[2]
DIP16 package - 750 mW
SO16 package - 500 mW
TSSOP16 package - 500 mW
P power dissipation per output - 100 mW
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage see Figure 7 3- 15V
VIinput voltage 0 - VDD V
Tamb ambient temperature in fre e air 40 - +125 C
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 5 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
10. Static characteristics
t/V input transition rise and fall
rate VDD = 5 V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
Table 5. Recommended operating con ditions …continued
Symbol Parameter Conditions Min Typ Max Unit
Fig 7. Operating area as a function of the supply voltages
VDD − VEE (V)
015510
001aae646
10
5
15
VDD − VSS
(V)
0
operating area
Table 6. Static characteristics
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 CUnit
Min Max Min Max Min Max Min Max
VIH HIGH-level
input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - 11.0 - V
VIL LOW-level
input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 - 4.0 V
IIinput leakage
current 15 V - 0.1 - 0.1 - 1.0 - 1.0 A
IS(OFF) OFF-state
leakage
current
Z port;
all channels OFF;
see Figure 8
15 V - - - 1000 - - - - nA
Y port;
per channel;
see Figure 9
15 V - - - 200 - - - - nA
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 6 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
10.1 Test circuits
10.2 ON resistance
IDD supply current IO = 0 A 5 V - 5 - 5 - 150 - 150 A
10 V - 10 - 10 - 300 - 300 A
15 V - 20 - 20 - 600 - 600 A
CIinput
capacitance Sn, E inputs - - - - 7.5 - - - - pF
Table 6. Static characteristics …continued
VSS = VEE = 0 V; VI = VSS or VDD unless otherwise specified.
Symbol Parameter Conditions VDD Tamb = 40 C Tamb = 25 C Tamb = 85 C Tamb = 125 CUnit
Min Max Min Max Min Max Min Max
Fig 8. Test circuit for measuring OFF-state leakage current Z port
IS
001aaj900
VDD
VI
switch
VSS = VEE
S1 to S3
E
nZ
nY0
VDD or VSS
VDD
nY1
1
2
VO
Fig 9. Test circuit for measuring OFF-state leakage current nYn port
Table 7. ON resistance
Tamb = 25
C; ISW =200
A; VSS = VEE = 0 V.
Symbol Parameter Conditions VDD VEE Typ Max Unit
RON(peak) ON resistance (peak) VI = 0 V to VDD VEE;
see Figure 10 and Figure 11 5 V 350 2500
10 V 80 245
15 V 60 175
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 7 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
10.2.1 ON resistance waveform and test circuit
RON(rail) ON resistance (rail) VI = 0 V; see Figure 10 and Figure 11 5 V 115 340
10 V 50 160
15 V 40 115
VI = VDD VEE;
see Figure 10 and Figure 11 5 V 120 365
10 V 65 200
15 V 50 155
RON ON resistance mismatch
between channel s VI = 0 V to VDD VEE; see Figure 10 5 V 25 -
10 V 10 -
15 V 5 -
Table 7. ON resistance …continued
Tamb = 25
C; ISW =200
A; VSS = VEE = 0 V.
Symbol Parameter Conditions VDD VEE Typ Max Unit
RON =V
SW /I
SW.
Fig 10. Test circuit for measuring RON
V
001aaj902
V
SS
VI
VSW
ISW
switch
V
SS
= V
EE
S1 to S3
E
nZ
nY0
V
DD
or V
SS
V
DD
nY1
1
2
Fig 11. Typical RON as a function of input voltage
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HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 8 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
11. Dynamic characteristics
11.1 Waveforms and test circuit
Table 8. Dynamic characteristics
Tamb = 25
C; VSS = VEE = 0 V; for test circuit see Figure 15.
Symbol Parameter Conditions VDD Typ Max Unit
tPHL HIGH to LOW propagation delay nYn, nZ to nZ, nYn; see Figure 12 5 V 1020ns
10 V 5 10 ns
15 V 5 10 ns
Sn to nYn, nZ; see Figure 13 5 V 200 400 ns
10 V 85 170 ns
15 V 65 130 ns
tPLH LOW to HIGH propagation delay nYn, nZ to nZ, nYn; see Figure 12 5 V 1530ns
10 V 5 10 ns
15 V 5 10 ns
Sn to nYn, nZ; see Figure 13 5 V 275 555 ns
10 V 100 200 ns
15 V 65 130 ns
tPHZ HIGH to OFF-state
propagation delay Eto nYn, nZ; see Figure 14 5 V 200 400 ns
10 V 115 230 ns
15 V 110 220 ns
tPZH OFF-state to HIGH
propagation delay Eto nYn, nZ; see Figure 14 5 V 260 525 ns
10 V 95 190 ns
15 V 65 130 ns
tPLZ LOW to OFF-state
propagation delay Eto nYn, nZ; see Figure 14 5 V 200 400 ns
10 V 120 245 ns
15 V 110 215 ns
tPZL OFF-stat e to LOW
propagation delay Eto nYn, nZ; see Figure 14 5 V 280 565 ns
10 V 105 205 ns
15 V 70 140 ns
Measurement points are given in Table 9. Measurement points are given in Table 9.
Fig 12. nYn, nZ to nZ, nYn propagation delays Fig 13. Sn to nYn, nZ propagation de la ys
001aac290
nYn or nZ
input
nZ or nYn
output
tPLH tPHL
VDD
VEE
VM
VM
VO
VEE
001aac291
switch ON
tPLH tPHL
switch OFF
VDD
VSS
VO
VEE
nYn or nZ
output
Sn input
switch OFF
10 %
90 %
VM
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 9 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
Measurement points are given in Table 9.
Fig 14. Enabl e and disable times
001aac292
tPLZ
tPHZ
switch OFF switch ONswitch ON
nYn or nZ output
LOW-to-OFF
OFF-to-LOW
nYn or nZ output
HIGH-to-OFF
OFF-to-HIGH
E input
VO
VO
VEE
VEE
VDD
VSS
VM
tPZL
tPZH
90 %
90 %
10 %
10 %
Table 9. Measurement points
Supply voltage Input Output
VDD VMVM
5 V to 15 V 0.5VDD 0.5VDD
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 10 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
[1] For nYn to nZ or nZ to nYn propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD.
Test data is given in Table 10.
Definitions:
DUT = Device Under Test.
RT= Termination resistance should be equal to output impedance Zo of the pulse generator.
CL= Load capacitance including test jig and probe.
RL= Load resistance.
Fig 15. Test circuit for measuring switching times
001aaj903
VIVO
RTCL
RLS1
DUT
PULSE
GENERATOR
tW
VM
VI
VI
VDD VDD
VSS
VEE
open
0 V
negative
pulse
VI
0 V
positive
pulse
10 %
90 %
90 %
10 % VM
VM
VM
tW
tftf
tr
tr
Table 10. Test data
Input Load S1 position
nYn, nZ Sn and E tr, tfVMCLRLtPHL[1] tPLH tPZH, tPHZ tPZL, tPLZ other
VDD or VEE VDD or VSS 20 ns 0.5VDD 50 pF 10 kVDD or VEE VEE VEE VDD VEE
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 11 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
11.2 Additional dynamic parameters
[1] fi is biased at 0.5 VDD; VI=0.5V
DD (p-p).
11.2.1 Test circuits
Table 11. Additional dynamic characteristics
VSS = VEE = 0 V; Tamb = 25
C.
Symbol Parameter Conditions VDD Typ Max Unit
THD total harmonic distortion see Figure 16; RL=10k; CL=15pF;
channel ON; VI=0.5V
DD (p-p);
fi=1kHz
5 V [1] 0.25 - %
10 V [1] 0.04 - %
15 V [1] 0.04 - %
f(3dB) 3 dB frequency response see Figure 17; RL = 1 k; CL = 5 pF;
channel ON; VI=0.5V
DD (p-p) 5 V [1] 13 - MHz
10 V [1] 40 - MHz
15 V [1] 70 - MHz
iso isolation (OFF-state) see Figure 18; fi= 1 MHz; RL = 1 k;
CL = 5 pF; channel OFF;
VI=0.5V
DD (p-p)
10 V [1] 50 - dB
Vct crosstalk voltage digital inputs to switch; see Figure 19;
RL = 10 k; CL=15pF;
Eor Sn = VDD (square-wave)
10 V 50 - mV
Xtalk crosstalk between switches; see Figure 20;
fi= 1 MHz; RL=1 k;
VI=0.5V
DD (p-p)
10 V [1] 50 - dB
Table 12. Dynamic power dissipation PD
PD can be calculated from the formulas shown; VEE = VSS =0 V; t
r = tf
20 ns; Tamb = 25
C.
Symbol Parameter VDD Typical formula for P D (W) where:
PDdynamic power
dissipation 5V P
D = 2500 fi + (fo CL) VDD2fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VDD = supply voltage in V;
(CL fo) = sum of the outputs.
10 V PD = 115 00 fi + (fo CL) VDD2
15 V PD = 29000 fi + (fo CL) VDD2
Fig 16. Test circuit for measuring total harmonic
distortion Fig 17. Test circuit for measuring frequency respons e
D
001aaj904
V
SS
fi
RLCL
switch
V
SS
= V
EE
S1 to S3
E
nZ
nY0
V
DD
or V
SS
V
DD
nY1
1
2
dB
001aaj905
V
SS
fi
RLCL
switch
V
SS
= V
EE
S1 to S3
E
nZ
nY0
V
DD
or V
SS
V
DD
nY1
1
2
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 12 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
Fig 18. Test circuit for meas urin g is ol ati on (OFF-state)
dB
001aaj906
V
SS
fi
RLCL
switch
V
SS
= V
EE
S1 to S3
E
nZ
nY0
V
DD
or V
SS
V
DD
nY1
1
2
a. Test circuit
b. Input and output pulse definitions
Fig 19. Test circuit for measuring crosstalk voltage between digital inputs and switch
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HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 13 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
a. Switch closed condition b. Switch open condition
Fig 20. Test circuit for measuring cros stalk between switches
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V
SS VO
RLRL
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SS
= V
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E
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nY0
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DD
or V
SS
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DD
nY1
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nY0
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VDD
nY1
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HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 14 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
12. Package outline
Fig 21. Package outline SOT38-4 (DIP16)
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HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 15 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
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HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 16 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
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HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 17 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
13. Abbreviations
14. Revision history
Table 13. Abbreviations
Acronym Description
DUT Device Under Test
Table 14. Revision history
Document ID Release date Data sheet status Change notice Supersedes
HEF4053B v.11 20140911 Product data sheet - HEF4053B v.10
Modifications: •Figure 19: Test circuit modified
HEF4053B v.10 20111117 Product data sheet - HEF4053B v.9
Modifications: •Legal pages updated.
•Changes in “General description”, “Features and benefits” and “Applications”.
HEF4053B v.9 20100325 Product data sheet - HEF4053B v.8
HEF4053B v.8 20100224 Product data sheet - HEF4053B v.7
HEF4053B v.7 20091127 Product data sheet - HEF4053B v.6
HEF4053B v.6 20090924 Product data sheet - HEF4053B v.5
HEF4053B v.5 20090825 Product data sheet - HEF4053B v.4
HEF4053B v.4 20090713 Produ ct data sheet - HEF4053B_CNV v.3
HEF4053B_CNV v.3 19950101 Product specification - HEF4053B_CNV v.2
HEF4053B_CNV v.2 19950101 Produ ct specification - -
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 18 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond tho se described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, lif e-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by cust omer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product develop ment.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 Se ptember 2014 19 of 20
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims result ing from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a docume nt is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors HEF4053B
Triple single-pole double-throw analog switch
© NXP Semiconductors N.V. 2014. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 11 September 2014
Document iden tifier: HEF4053B
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
10.2 ON resistance. . . . . . . . . . . . . . . . . . . . . . . . . . 6
10.2.1 ON resistance waveform and test circuit . . . . . 7
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11.1 Waveforms and test circuit . . . . . . . . . . . . . . . . 8
11.2 Additional dynamic parameters . . . . . . . . . . . 11
11.2.1 Test circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 17
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 17
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16 Contact information. . . . . . . . . . . . . . . . . . . . . 19
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20