SN74CBTLV3257 www.ti.com SCDS040J - DECEMBER 1997 - REVISED JANUARY 2013 Low-Voltage 4-Bit 1-of-2 FET Multiplexer/Demultiplexer Check for Samples: SN74CBTLV3257 FEATURES 1 1B1 1B2 1A 2B1 2B2 2A 15 3 14 4 13 5 12 6 11 7 10 8 9 S VCC 5 13 4B2 12 4A 6 11 7 10 3B2 4 3B1 3A 9 RSV PACKAGE (TOP VIEW) VCC OE 4B1 4B2 4A 3B1 3B2 3A 12 11 10 3B1 16 2 15 OE 14 4B1 3 4A 1 16 8 D, DBQ, DGV, OR PW PACKAGE (TOP VIEW) S 1B1 1B2 1A 2B1 2B2 2A GND 1 2 GND * RGY PACKAGE (TOP VIEW) 4B2 * 5- Switch Connection Between Two Ports Rail-to-Rail Switching on Data I/O Ports Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) 4B1 * * * 9 OEB 13 8 3B2 VCC 14 7 3A SEL 15 6 GND 1B1 16 5 2A 1 2 3 1B2 1A 2B1 4 2B2 DESCRIPTION The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the outputenable (OE) input is high. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA -40C to 85C (1) (2) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING QFN - RSV Reel of 3000 SN74CBTLV3257RSVR ZTR QFN - RGY Reel of 3000 SN74CBTLV3257RGYR CL257 Tube of 40 SN74CBTLV3257D Reel of 2500 SN74CBTLV3257DR SSOP (QSOP) - DBQ Reel of 2500 SN74CBTLV3257DBQR CL257 TSSOP - PW Reel of 2000 SN74CBTLV3257PWR CL257 TVSOP - DGV Reel of 2000 SN74CBTLV3257DGVR CL257 SOIC - D CBTLV3257 Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1997-2013, Texas Instruments Incorporated SN74CBTLV3257 SCDS040J - DECEMBER 1997 - REVISED JANUARY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Table 1. FUNCTION TABLE INPUTS /OE FUNCTION S L L A port = B1 port L H A port = B2 port H X Disconnect LOGIC DIAGRAM (POSITIVE LOGIC) 4 1A 2 1B1 SW 3 1B2 SW 7 2A 5 2B1 SW 6 2B2 SW 9 3A 11 3B1 SW 10 3B2 SW 14 12 4A 4B1 SW 13 SW 4B2 1 S 15 OE 2 Submit Documentation Feedback Copyright (c) 1997-2013, Texas Instruments Incorporated Product Folder Links :SN74CBTLV3257 SN74CBTLV3257 www.ti.com SCDS040J - DECEMBER 1997 - REVISED JANUARY 2013 SIMPLIFIED SCHEMATIC, EACH FET SWITCH A B (OE) ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE VCC VI MIN MAX Supply voltage range -0.5 4.6 (2) -0.5 Input voltage range Continuous channel current IIK Input clamp current (VI/O < 0) D package JA Package thermal impedance (3) (1) (2) (3) (4) V 4.6 V 128 mA -50 mA 73 C/W DBQ package (3) 90 C/W DGV package (3) 120 C/W PW package (3) 108 C/W 39 C/W 150 C RGY package Tstg UNIT (4) Storage temperature range -65 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage MIN MAX 2.3 3.6 VIH High-level control input voltage VCC = 2.3 V to 2.7 V VIL Low-level control input voltage VCC = 2.3 V to 2.7 V 0.7 VCC = 2.7 V to 3.6 V 0.8 TA Operating free-air temperature (1) 1.7 VCC = 2.7 V to 3.6 V 2 -40 UNIT V V 85 V C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright (c) 1997-2013, Texas Instruments Incorporated Product Folder Links :SN74CBTLV3257 3 SN74CBTLV3257 SCDS040J - DECEMBER 1997 - REVISED JANUARY 2013 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VCC = 3 V, II = -18 mA II VCC = 3.6 V, VI Ioff VCC = 0, ICC VCC = 3.6 V, VCC = 3.6 V, ICC (2) Ci Cio(OFF) Control inputs A port B port TYP (1) MAX UNIT -1.2 V 1 A VI or VO = 0 to 3.6 V 15 A IO = 0, VI = VCC or GND 10 A One input at 3 V, Other inputs at VCC or GND 300 A = VCC or GND VI = 3 V or 0 3 VO = 3 V or 0, OE = VCC VCC = 2.3 V, TYP at VCC = 2.5 V VI = 0 ron (3) pF 10.5 pF 5.5 II = 64 mA 5 8 II = 24 mA 5 8 VI = 1.7 V II = 15 mA 27 40 VI = 0 II = 64 mA 5 7 VCC = 3 V VI = 2.4 V (1) (2) (3) MIN II = 24 mA 5 7 II = 15 mA 10 15 All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25C. This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals SWITCHING CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (See Figure 1) PARAMETER A or B (1) B or A S A or B 1.8 6.1 1.8 5.3 ns S A or B 1.7 6.1 1.7 5.3 ns tdis S A or B 1 4.8 1 4.5 ns ten OE A or B 1.9 5.6 2 5 ns tdis OE A or B 1 5.5 1.6 5.5 ns ten 4 VCC = 3.3 V 0.3 V TO (OUTPUT) tpd (1) VCC = 2.5 0.2 V FROM (INPUT) MIN MAX MIN 0.15 MAX UNIT 0.25 The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). Submit Documentation Feedback Copyright (c) 1997-2013, Texas Instruments Incorporated Product Folder Links :SN74CBTLV3257 SN74CBTLV3257 www.ti.com SCDS040J - DECEMBER 1997 - REVISED JANUARY 2013 PARAMETER MEASUREMENT INFORMATION 2 x VCC S1 RL From Output Under Test Open GND CL (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 x VCC GND RL CL VCC 2.5 V 0.2 V 3.3 V 0.3 V 30 pF 50 pF LOAD CIRCUIT V 0.15 V 0.3 V RL 500 500 VCC Timing Input VCC/2 0V tw tsu th VCC VCC/2 Input VCC/2 VCC VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input VCC/2 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL VOH Output VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 Output Waveform 2 S1 at GND (see Note B) VCC/2 0V tPLZ t Output PZL Waveform 1 S1 at 2 x VCC (see Note B) tPLH tPHL VCC Output Control VCC/2 VCC VOL + V VOL tPHZ tPZH VCC/2 VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. t PZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright (c) 1997-2013, Texas Instruments Incorporated Product Folder Links :SN74CBTLV3257 5 SN74CBTLV3257 SCDS040J - DECEMBER 1997 - REVISED JANUARY 2013 www.ti.com REVISION HISTORY Changes from Revision I (OCTOBER 2003) to Revision J * 6 Page Added QFN ordering info and package pinout ..................................................................................................................... 1 Submit Documentation Feedback Copyright (c) 1997-2013, Texas Instruments Incorporated Product Folder Links :SN74CBTLV3257 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) 74CBTLV3257DBQRE4 ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL257 74CBTLV3257DBQRG4 ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL257 74CBTLV3257DGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257 74CBTLV3257DGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257 74CBTLV3257PWRE4 ACTIVE TSSOP PW 16 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257 74CBTLV3257PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257 74CBTLV3257RGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL257 SN74CBTLV3257D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257 SN74CBTLV3257DBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL257 SN74CBTLV3257DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257 SN74CBTLV3257DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257 SN74CBTLV3257DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257 SN74CBTLV3257DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257 SN74CBTLV3257DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257 SN74CBTLV3257DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257 SN74CBTLV3257PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257 SN74CBTLV3257PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257 Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 18-Oct-2013 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) SN74CBTLV3257PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257 SN74CBTLV3257PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 CL257 SN74CBTLV3257RGYR ACTIVE VQFN RGY 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL257 SN74CBTLV3257RSVR ACTIVE UQFN RSV 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ZTR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74CBTLV3257 : * Enhanced Product: SN74CBTLV3257-EP NOTE: Qualified Version Definitions: * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 10-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 5.6 1.6 8.0 12.0 Q1 74CBTLV3257PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 SN74CBTLV3257DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74CBTLV3257DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74CBTLV3257PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 SN74CBTLV3257RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 10-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) 74CBTLV3257PWRG4 SN74CBTLV3257DGVR TSSOP PW 16 2000 367.0 367.0 35.0 TVSOP DGV 16 2000 367.0 367.0 35.0 SN74CBTLV3257DR SOIC D 16 2500 333.2 345.9 28.6 SN74CBTLV3257PWR TSSOP PW 16 2000 364.0 364.0 27.0 SN74CBTLV3257RGYR VQFN RGY 16 3000 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0-8 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. 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