1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
1B1
1B2
1A
2B1
2B2
2A
GND
VCC
OE
4B1
4B2
4A
3B1
3B2
3A
1A
1B2
1B1
SEL
3A
3B2
3B1
4A
2B1
2A
3
2
1
4
VCC
5
OEB
6
16
7
15
4B1
9
10
11
12
13
4B2
8
14
2B2
GND
1 16
8 9
2
3
4
5
6
7
15
14
13
12
11
10
OE
4B1
4B2
4A
3B1
3B2
1B1
1B2
1A
2B1
2B2
2A
S
3A V
GND
CC
SN74CBTLV3257
www.ti.com
SCDS040J DECEMBER 1997REVISED JANUARY 2013
Low-Voltage 4-Bit 1-of-2 FET Multiplexer/Demultiplexer
Check for Samples: SN74CBTLV3257
1FEATURES
RGY PACKAGE
5-ΩSwitch Connection Between Two Ports (TOP VIEW)
Rail-to-Rail Switching on Data I/O Ports
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
D, DBQ, DGV, OR PW PACKAGE RSV PACKAGE
(TOP VIEW) (TOP VIEW)
DESCRIPTION
The SN74CBTLV3257 is a 4-bit 1-of-2 high-speed FET multiplexer/demultiplexer. The low on-state resistance of
the switch allows connections to be made with minimal propagation delay.
The select (S) input controls the data flow. The FET multiplexers/demultiplexers are disabled when the output-
enable (OE) input is high.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging
current will not backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TAPACKAGE(1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN RSV Reel of 3000 SN74CBTLV3257RSVR ZTR
QFN RGY Reel of 3000 SN74CBTLV3257RGYR CL257
Tube of 40 SN74CBTLV3257D
SOIC D CBTLV3257
–40°C to 85°C Reel of 2500 SN74CBTLV3257DR
SSOP (QSOP) DBQ Reel of 2500 SN74CBTLV3257DBQR CL257
TSSOP PW Reel of 2000 SN74CBTLV3257PWR CL257
TVSOP DGV Reel of 2000 SN74CBTLV3257DGVR CL257
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 1997–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
1B11A
OE
1B2
SW
SW
2B12A
2B2
SW
SW
3B13A
3B2
SW
SW
4B14A
4B2
SW
SW
S
4
7
9
12
1
15
2
3
5
6
11
10
14
13
SN74CBTLV3257
SCDS040J DECEMBER 1997REVISED JANUARY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. FUNCTION TABLE
INPUTS FUNCTION
/OE S
L L A port = B1 port
L H A port = B2 port
H X Disconnect
LOGIC DIAGRAM (POSITIVE LOGIC)
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Product Folder Links :SN74CBTLV3257
A
(OE)
B
SN74CBTLV3257
www.ti.com
SCDS040J DECEMBER 1997REVISED JANUARY 2013
SIMPLIFIED SCHEMATIC, EACH FET SWITCH
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted) VALUE UNIT
MIN MAX
VCC Supply voltage range –0.5 4.6 V
VIInput voltage range(2) –0.5 4.6 V
Continuous channel current 128 mA
IIK Input clamp current (VI/O < 0) –50 mA
D package(3) 73 °C/W
DBQ package(3) 90 °C/W
Package thermal
θJA DGV package(3) 120 °C/W
impedance PW package(3) 108 °C/W
RGY package(4) 39 °C/W
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) The package thermal impedance is calculated in accordance with JESD 51-5.
RECOMMENDED OPERATING CONDITIONS(1)
MIN MAX UNIT
VCC Supply voltage 2.3 3.6 V
VCC = 2.3 V to 2.7 V 1.7
High-level control input
VIH V
voltage VCC = 2.7 V to 3.6 V 2
VCC = 2.3 V to 2.7 V 0.7
Low-level control input
VIL V
voltage VCC = 2.7 V to 3.6 V 0.8
TAOperating free-air temperature 40 85 °C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 1997–2013, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links :SN74CBTLV3257
SN74CBTLV3257
SCDS040J DECEMBER 1997REVISED JANUARY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK VCC = 3 V, II=18 mA 1.2 V
IIVCC = 3.6 V, VI = VCC or GND ±1 µA
Ioff VCC = 0, VIor VO= 0 to 3.6 V 15 µA
ICC VCC = 3.6 V, IO= 0, VI= VCC or GND 10 µA
ICC(2) VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA
Control
inputs
CiVI= 3 V or 0 3 pF
A port 10.5
Cio(OFF) VO= 3 V or 0, OE = VCC pF
B port 5.5
VCC = 2.3 V, VI= 0 II= 64 mA 5 8
TYP at VCC = 2.5 V II= 24 mA 5 8
VI= 1.7 V II= 15 mA 27 40
ron(3)
VI= 0 II= 64 mA 5 7
VCC = 3 V II= 24 mA 5 7
VI= 2.4 V II= 15 mA 10 15
(1) All typical values are at VCC = 3.3 V (unless otherwise noted), TA= 25°C.
(2) This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND.
(3) Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is
determined by the lower of the voltages of the two (A or B) terminals
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted) (See Figure 1)
VCC = 2.5 ± 0.2 V VCC = 3.3 V ± 0.3 V
PARAMETER FROM (INPUT) TO (OUTPUT) UNIT
MIN MAX MIN MAX
A or B(1) B or A 0.15 0.25
tpd S A or B 1.8 6.1 1.8 5.3 ns
ten S A or B 1.7 6.1 1.7 5.3 ns
tdis S A or B 1 4.8 1 4.5 ns
ten OE A or B 1.9 5.6 2 5 ns
tdis OE A or B 1 5.5 1.6 5.5 ns
(1) The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
4Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated
Product Folder Links :SN74CBTLV3257
VCC/2
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
2×VCC
Open
GND
RL
RL
Data Input
Timing Input
VCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
Input
Output
Waveform 1
S1 at 2 ×VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
VOL + V
VOH V
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2×VCC
GND
TEST S1
NOTES: A. CLincludes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO= 50 , tr2 ns, tf2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
VCC/2
VCC
VCC/2
VCC/2
2.5 V ±0.2 V
3.3 V ±0.3 V
500
500
VCC RL
0.15 V
0.3 V
V
CL
30 pF
50 pF
SN74CBTLV3257
www.ti.com
SCDS040J DECEMBER 1997REVISED JANUARY 2013
PARAMETER MEASUREMENT INFORMATION
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 1997–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links :SN74CBTLV3257
SN74CBTLV3257
SCDS040J DECEMBER 1997REVISED JANUARY 2013
www.ti.com
REVISION HISTORY
Changes from Revision I (OCTOBER 2003) to Revision J Page
Added QFN ordering info and package pinout ..................................................................................................................... 1
6Submit Documentation Feedback Copyright © 1997–2013, Texas Instruments Incorporated
Product Folder Links :SN74CBTLV3257
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
74CBTLV3257DBQRE4 ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL257
74CBTLV3257DBQRG4 ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL257
74CBTLV3257DGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257
74CBTLV3257DGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257
74CBTLV3257PWRE4 ACTIVE TSSOP PW 16 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257
74CBTLV3257PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257
74CBTLV3257RGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL257
SN74CBTLV3257D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257
SN74CBTLV3257DBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL257
SN74CBTLV3257DE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257
SN74CBTLV3257DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257
SN74CBTLV3257DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257
SN74CBTLV3257DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257
SN74CBTLV3257DRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257
SN74CBTLV3257DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CBTLV3257
SN74CBTLV3257PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257
SN74CBTLV3257PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 2
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74CBTLV3257PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 CL257
SN74CBTLV3257PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 CL257
SN74CBTLV3257RGYR ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CL257
SN74CBTLV3257RSVR ACTIVE UQFN RSV 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 ZTR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 18-Oct-2013
Addendum-Page 3
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74CBTLV3257 :
Enhanced Product: SN74CBTLV3257-EP
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
74CBTLV3257PWRG4 TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74CBTLV3257DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74CBTLV3257DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74CBTLV3257PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1
SN74CBTLV3257RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Jul-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
74CBTLV3257PWRG4 TSSOP PW 16 2000 367.0 367.0 35.0
SN74CBTLV3257DGVR TVSOP DGV 16 2000 367.0 367.0 35.0
SN74CBTLV3257DR SOIC D 16 2500 333.2 345.9 28.6
SN74CBTLV3257PWR TSSOP PW 16 2000 364.0 364.0 27.0
SN74CBTLV3257RGYR VQFN RGY 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Jul-2013
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194