19-0025; Rev. 1: 12/92 General Description The MAX176 is a complete analog-to-digital converter (ADC) that achieves a 250k samples per second (ksps) sampling rate by combining a fast track/nold (0.4us max acquisition time), a 3.5us ADC, and a buried-zener volt- age reference. The device also saves space with serial interface and 8-pin DIP or 16-pin surface-mount SO pack- ages. Supply and reference decoupling capacitors are the only external components needed. Tne CLOCK input can be driven from an external divided-down microprocessor clock or from the serial-clock output of a microcontroller. The MAX176 works with +5V and -12V to -15V supply voltages (148mW typ power dissipation). The MAX176s 3-wire serial interface works with general- purpose serial-to-parallel converters, such as the 74HC595, as well as with digital-signal processors and microcontrollers. Its 3-wire serial interface is fully com- patible with SPI, QSPI and Microwire interface stan- dards. Applications Telecommunications Digital-Signal Processing (DSP) Sonar/Radar Signal Processing Industrial Data Acquisition Functional Diagram MAAALNVI Serial-Output, 250ksps 12-Bit ADC with T/H and Reference Features 12-Bit Resolution and Linearity @ 0.48 Track/Hold Acquisition Time @ 3.5s Max Conversion Time @ 250ksps Sampling Rate @ SPI-, QSPI- and Microwire '-Compatible Serial Output @ +5V Input Voltage Range @ On-Chip Voltage Reference @ Low Power (148mW) @ Easy to Opto- or Transformer-Isolate @ Small-Footprint 8-Pin DIP, 16-Pin SO Ordering Information | PART TEMP.RANGE PIN-PACKAGE ERROR (LSB) MAX176ACPA OC to+70C 8 Plastic DIP +1/2 MAXI76BCPA O'Cto+70C 8 PlasticDIP_ #1 | MAX MAXI76ACWE OCto+70C 16 WideSQ_ 41/2 MAXI76BCWE OCto+70C 16WideSO +1 MAX176BC/D OCto+70C Dice +1 Ordering Information continued on last page. * Contact factory for dice specitications Pin Configurations 4 2 1 ys ARAL _ 0 DD AIN Wp | ay KE VREF 3] ss 4 GND 12-BIT DAC _/ Maxim | REFERENCE SS MAXITE convst 4 CONTROL | ap clock 44 Locie | pata PIN CONFIGURATION IS 8-PIN DIP TOP VIEW . wT veo | 4 g | Vs AIN|2| AAAXLAA |7 | CONVSI VREF | 3 MAX176 6 | CLOCK GND | 4 5 | DATA DIP e von [4 6] Vss ne. [2 15] NC MAXUM | NC.|3] > yaxi7e 14! NO AIN | 4 3 CONVST vrer | 5 | 12 CLOCK GND [6] 11 NG GND [7 10 NC GND [ 8] @ DATA WIDE SO nm Microwire is a registered trademark of National Semiconductor, MAXIAA Maxim Integrated Products 1 Call toll free 1-800-998-8800 for free samples or literature. 9ZLXVINMAX176 Serial-Output, 25O0ksps 12-Bit ADC with T/H and Reference ABSOLUTE MAXIMUM RATINGS VpptoGND .......... -0.3V to +7V Operating Temperature Ranges Vss toGND .0. 0... +0.3V to -17V MAX176_C_ _ AINtoGND 0.0... 0. ee . 15V MAX176_E _ Digital Input Voltage toGND ............ -0 3y, VDD + 0.3V MAX176_MJA Digital Output Voltage to GND Continuous Power Dissipation (Ta = +70C) 8-Pin Plastic DIP (derate 9. 09mMW/'C above +70C) .. 16-Pin Wide SO (derate 9. 52mW/'C above +70C) .. 8-Pin CERDIP (derate 8.00mW/"C above +70C) .... -0.3V, VDD + 0.3V Storage Temperature Range Lead Temperature (soldering, 10 sec) 727mW 762mW 640mW OC to +70 C -40'C to +85 C -55C to +125 C -65C to +160 C +300'C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are siress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implicd. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ELECTRICAL CHARACTERISTICS (VDD = +5V 5%, Vss = -11.4V to -15.75V, foLK = 4MHz for MAX176_C/E and feLk = 3MHz for MAX176_M, Ta = TMIN to TMAX, unless otherwise noted.) _ PARAMETER , SYMBOL | CONDITIONS MIN TYP MAX UNITS ADC ACCURACY Resolution Guaranteed monotonic over temp 12 Bits MAX176AC/AE ; _ +1/2 Integral Nonlinearity (Note 1} INL Ta=TMIn to Tmax | MAXT76BC/BE/EM - LSB MAX176AM +3/4 TA = +25C MAX176AM +1/2 ; MAX176A +3/4 Differential Nonlinearity (Note 1) DNL > a LSB _ MAX176B 7 4H Offset Error (Notes 1, 2) # +3 LSB Offset Tempco 0.5 ppm/ C Full-Scale Error (Note 3) Ta = +25C +8 LSB Full-Scale Tempco (Note 4) Excluding reference drift +1 ppm/ C ANALOG INPUT 7 . ; _ ; Input Voltage Range _ So 5 Vv Input Current 25 mA Input Capacitance (Note 5) 10 pF INTERNAL REFERENCE | VREF Output Voltage | - [| -4.98 -5.00 -5.02 V MAX176_C +30 VREF Output Tempco (Note 6) -_ 7 ppm/ C a. MAX176_E/M | +40 Load Regulation (Note 7) OmA < IL < 5mMA 5 mv POWER-SUPPLYREJECTION Positive Supply Rejection Vbb FS change, Vss = -15V or -12V, Vop = 5V +5% _ 41/2 LSB Negative Supply Rejection Vss FS change, Vob = 5V Vss = -15V 57 [ fue LSB Vss = -12V 45% +1/2 LOGIC INPUTS (CLK, CONVST) _ _ Input High Voltage VIH 2.4 Vv Inout Low Voltage VIL 0.8 V Input Capacitance (Note 5) CIN ; | _ 10 pF _ Input Current lin Input voltage = OV to Vop [ +5 WA 2 MAXIMSerial-Output, 25O0ksps 12-Bit ADC with T/H and Reference ELECTRICAL CHARACTERISTICS (continued) (VoD = +5V 5%, Vss = -11.4V to -15.75V, foLk = 4MHz for MAX176_C/E and fcLk = 3MHz for MAX176_M, Ta = TMIN to TMAX unless otherwise noted.) | PARAMETER | SYMBOL | CONDITIONS [MIN | TYP MAX | UNITS DYNAMIC TESTS (AIN = 10Vp-p, fain = 50.17kKHz, fSAMPLING = 250ksps for MAX176_C/E, fSAMPLING = 200ksps for MAX176_M) Signal-to-Noise plus Distortion SAN+D) | 70 72 dB Total Harmonic Distortion THD _ -90 -80 dB Peak Harmonic or Spurious Noise - / -90 -80 dB Input Slew Rate 1.5 Vips T : MAX176_C/E 3.5 Conversion Time {CONV 14 clock cycles > Hs | MAX176_M 47 Acquisition Time (Note 5) tag 400 ns MAX176_C/E 0.1 40 Clock Frequency fcLk _ . MHz | MAX176_M 01 3.0 LOGIC OUTPUT (DATA) Output Low Voltage VOL ISINK = 1.6mA o4 , 1 Output High Voltage VOH | ISOURCE = 200A 4.0 | POWER REQUIREMENTS _ ee Positive Supply Voltage VDD +5% for specified performance 9 | Vv Negative Supply Voltage Vss +5% for specified performance -15to-12 v Positive Supply Current IDD CONVST = Vpp, AIN = 0V 5.5 8 mA Negative Supply Current Iss CONVST = Vpp, AIN = OV ; -8 11 mA Power Dissipation Vopb = 5V. Vss = -12V 123 172 | mw TIMING CHARACTERISTICS (Note 8) (VoD = +5V +5%, Vgs = -11.4V to 15.75V. Ta = TMIN to TMAX, unless otherwise noted.) | PARAMETER SYMBOL CONDITIONS | MIN TYP MAX UNITS Clock Pulse Width High 'CH 50 . MAX176_C/E 80 ns Low {CL ___ r : | MAX176_M 100 CONVST Pulse Width High tSH ; 50 _ - | MAXx176_C/E 120 ns Low {SL [ MAX176_M 150 CONVST-to-CLOCK Skew Leading Clock Sco - 30 MAX176_C/E 120 ns Leading Clock +1 tsc1 |_maxi7e ~ | MAX176_M 160 MAX176_C/E 20 130 Clock-to-Data Delay (Note 9) tpD ~ ns _ MAX176_M 20 170 __ Acquisition Time (Note 5) taa FS change at AIN 400 ns MAAXILAA 9ZLXVINMAX176 Serial-Output, 250Oksps 12-Bit ADC with T/H and Reference TIMING CHARACTERISTICS (Note 8) (continued) (Vop = +5V +5%, Vss = -11.4V to -15,75V, Ta = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS | Aperture Delay (Note 5) a 10 | ns CONVST Rise Time (Note 5) 100 ns MAX176C/E , 100 Output Float Delay (Note 10) _ ns [ MAX176M 120 Note 1: These tests are performed at VoD = +5V, Vss = -15V. Operation over supply is guaranteed by supply rejection tests Note 2: Offset measured at 0...00 to 0...01 digital output code. Note 3: FS = 5.000V. Ideal last-code transition = FS - 3/2LSB. Adjusted for offset error Note 4: Full-Scale Tempco = (A VFs)/(A T), where A Ves is Full-Scale voltage change from Ta = +25C to TmINn or TMAXx Note 5: Guaranteed by design, not subject to test Note 6: VREF Tempco = (A VREF)/(A T), where A VREF is reference-voltage change from Ta = +25C to TMIN Or TMAX Note 7: Output current should not change during conversion. Note 8: Timing specifications are 100% tested. All input control signals are specified with tr = tt = Sns (10% to 90% of +5V) and timed from a voltage level of +1.6V. Output delays are measured to 0.8V if going low and 2.4V if going high. Note 9: DATA pin is loaded with 50pF to GND. Note 10: DATA pin is loaded with 10pF 1 | 3kQ. Defined as the time required for data lines to change 0.5V Pin Description r PIN NAME FUNCTION DIP so 1 1 Vpp | Positive Supply, +5V +5% 2 4 AIN Analog Input, +5V bipolar input range 3 5 VREF | Reference Voltage Output, -5.0V _= | 67.8 | eno | Groune, Conect al 3 ps t 4 GND | Ground 8 DGND | Digital Ground D5 9, DATA | Serial Data Output | 6 12 |CLOCK] Clock input. TTL/+5V CMOS compatible 7 13 OONVST! Conversion Start Input 8 16 Vss Negative Supply, -11.4V to -15.75V Sy e N.C. | NoConnect. Not internally connected. Detailed Description Converter Operation The MAX176 uses a Successive-approximation technique to convert an unknown analog input to a 12-bit digital output code. The digital interface requires only three digital lines: CLOCK and CONVST are both inputs, and the DATA output provides the conversion result in serial form. Figure 1 shows the typical operating circuit. Figure 2 shows the MAX176 analog-equivalent circuit, which illustrates the basic functional blocks within the device. Note that after the input voltage is sampled, AIN is disconnected from the MAX176s converter portion This removes the possibility of the converter demanding current spikes from the device driving AIN. A conversion is intiated by the convert start rising edge. Once started, a conversion cannot be stopped and tran- sitions at the CONVST input have no effect until the current conversion is completed. The result of a conver- sion is available at the DATA output in twos-complement, serial format. A high bit followed by the data bits (MSB first) make up the serial data stream. Conversions may be done one at atime (burst mode) or on arepetitive basis (continuous-conversion mode). 1 Vop Vss 8 15V 1OuF [4 Our MAXIM if svTosyp OTH 2) MAXI76 17 | CONVERS- ANALOG AIN CONVST ION START INPUT 5 5 eo 3 | ype CLOCK ally eturt | oe (BV) | + SERIAL Lig to GND DATA L Surat O4pF we (Opt pote . / Figure 1. MAX176 Operational Configuration MAKIMSerial-Output, 25Oksps 12-Bit ADC with T/H and Reference 3k 12-BIT DAC | ie erent | GND convst ff [ CONTROL 6 LOGIC SA clock 4 SAMPLING en COMPARATOR BUFFER r,s veer | GND 10pF MAXLAA nL MAX176 R | > D. Figure 2. MAX176 Analog Equivalent Circuit Burst Mode Figure 3 illustrates the timing relationship between the convert start, clock, and data waveforms when the MAX176 operates in burst mode. Convert starts rising edge causes the internal track/hold (T/H) circuit to hold ihe analog input voltage and initiates the conversion. The T/H returns to track mode after the 13th falling clock edge. When burst mode is used, clock edges typically appear after convert starts rising edge. Thus, Figure 4 shows the recommended placement of clocks falling edge after the rising edge of convert start; this placement ensures that the serial outputs leading high bit appears at the first falling clock edge after convert start rises. The convert start to clock skew specification, tsc1, dictates the suggested positioning of clocks falling edge. No problem occurs if clocks falling edge ap- pears earlier than suggested; the serial data stream is simply delayed by a clock cycle. Note, however, that a high-speed clock edge occurring within 40ns of convert starts rising edge could cause a small inaccuracy in the sampled voltage. This is due to the ground bounce induced by the clock edge speed. Each bit of the serial data stream appears after a clock falling edge. Since there are 12 data bits and one leading high bit, at least 13 falling clock edges are needed to shift out these bits. Rising edges are usually used to strobe the serial data into a register. Pay attention to the clock- to-data delay (tpg) specification at the highest clock MAMXLAA frequencies when using a rising clock edge to strobe a data bit into a register. Extra clock pulses prior to a new convert start rising edge have no effect on the converter operation. Continuous-Conversion Mode Figure 5 shows the timing relationship between the con- vert start, clock, and data waveforms when the MAX176 is operated in continuous-conversion mode. As in the burst mode, convert starts rising edge places the T/H circuit in hold mode and initiates the conversion. Here also, the 13th falling clock edge puts the T/H in track mode. In continuous-conversion mode, convert starts rising edge must be correctly positioned with respect to clocks falling edges to satisfy the tsco and tsc1 specifications (Figure 6). These specifications must be met if the serial data stream high bit is to appear after the first falling clock edge. One caution: A high-speed clock edge may cause ground bounce; if the rising edge of convert start is within 40ns of a clock edge, the voltage stored in the T/H may be slightly inaccurate because of this ground bounce. A conversion period of 15 clock cycles minimum is rec- ommended. Most systems will be 16 cycles since such counters are more common. Extra clock pulses between conversions have no effect. If the clock frequency is below 2.5MHz, a minimum period of 14 cycles can also be used. 9ZLELEXVINMAX176 Serial-Output, 250ksps 12-Bit ADC with T/H and Reference const _ 88 1 2 3 2 8 4 1% 46 a PLL rrr i DATA nz \ any Din bio D8 X OB X OY X 05 KX bs XDA OFX 2X VX oo) - At; @THINTRACK MODE Figure 3. MAX176 Timing in Burst Mode cost t 1 2 tg 3 te cuock J | Nee : 1 tc t- {scr a oH feo a, << $$ nt ip ote) wage on Figure 4. Recommended Placement of Clock Falling Edge in Burst Mode CONVST we oe 1 2 3 4 5 6 7 8 9 0 1 12 143 14 1 2 3 4 = 5 eSIPUUFUUUUUE SU UUW Ua MSB Hl- . . . pata"? _riar\ DX BIO DAY OB YX OFX DEX BEX BEX ORY G2 TY! B)HZ_ yar or1Y 010 X 09 YX ~at T/HIN TRACK i : MODE Figure 5, MAX176 Timing in Continuous Mode 6 MAXIMSerial-Output, 250ksps 12-Bit ADC with T/H and Reference PLACE RISING EDGE OF CONVST IN THIS REGION CONVST /' / \ i! 1 tscl | sot <i <P | 21 cLock / ey J \ _/ i wien DAW sy HBT. = OTT * 14TH FALLING CLOCK EDGE OF PREVIOUS CONVERSION, OR FALLING EDGE OF AN IDLE CLOCK PULSE, JUST PRIOR TO STARTING A NEW CONVERSION MOTOROLA . MC68HC16 PCSO; TO OTHER SERIAL ~ PERIPHERAL DEVICES - CONVST AAAXIAA 7 CLOCK MAXI76 t- +f DATA QSPI INTERFACE Figure 6. Recommended Placement of CONVST Rising Edge in Continuous Mode Upper and Lower Clock Frequencies It is possible to operate the MAX176 at clock rates up to AMHz (8MHz for the military version) and down to 100KHz (for both the commercial and military devices). The lower clock limit is necessary because of the internal T/H circuit's droop. Connection to Standard Serial Interfaces The MAX 176 serial interface is fully compatible with SPI and Microwire standard serial interfaces. Common im- plementations of these interfaces in microprocessors (Ps) limit the MAX176s throughput rate; the uP simply can't keep up with the serial data stream. The Motorola QSPI interface can handle the MAX176's 250ksps conversion rate; SCK from the MC68HC 16 (shown in Figure 7) can operate at the MAX176s 4MHz maximum clock rate. Output Coding and Transfer Function Data output from the MAX176 is in twos-complement format. The first bit appearing at DATA is always high, followed by the 12 data bits (inverted most significant bit (MSB) first: O for positive analog inputs, 1 for negative, followed by the remaining noninverted 11 data bits). Figure 8 shows the MAX176 nominal transfer function. Code transitions occur halfway between successive inte- ger LSB values; one LSB = 10V/4096 = 2.44mV. Applications Information Offset and Full-Scale Adjustment In applications where the offset and full-scale ranges nave to be adjusted for the ADC, use Figure 9s circuit This circuit allows adjustment of both the offset and full-scale (gain) errors. Adjust the offset first. Apply MA AXILAA Figure 7, MAX176 Connected to QSPI Interface 1/2LSB (1.22mV) at the analog input and adjust the amplifiers offset until the digital output code changes between 0000 0000 0000 and 0000 0000 0001. Changes in the +5V supply affect the offset adjustment slightly. If significant supply variation is expected, connect a refer- ence to RS in place of the +5V supply. To adjust the negative full-scale range, apply -FS + 1/2LSB (-2.49939V, remembering the amplifier has a gain of approximately 2) at the analog input, and adjust R2 until the output code changes between 1000 0000 0000 and 1000 0000 0001. Once this adjustment is made, the positive full-scale reading will be dictated by the integral nonlinearity (INL) specification; thus, this reading will be no further away from the optimal value than the maximum INL specification. The value of potentiometer R5 can be increased in order to decrease the circuit's current consumption. However, increasing this resistor value decreases the adjustment sensitivity when in the middle range of pot R5, and causes relatively large changes in the op amps output when at either end of the pot range. Adding a voltage divider at the noninverting input allows a wider input voltage range. See the Driving the Analog Input section for recommended op amps for this circuit. Figure 10 shows an alternative inverting configuration for gain and offset adjustment. Serial-to-Paralle! Data Conversion Figure 11a shows a MAX176 with a serial-to-parallel converter. The analog input is referred to signal ground at the MAX176 GND pin. The parallel data outputs are updated at the convert start signals rising edge. See Figure 11b for the circuit timing. 9OZLELXVINMAX176 Serial-Output, 250ksps 12-Bit ADC with T/H and Reference OUTPUT CODE ee O.1pF a O...1 | 8 ee , I I ro Rt U 1 * OtpF S 1504, 1% o0...007f ------------- ; | MAAXIAA 00. .000L-__________ ' ! R2. 5k a bo FULL-SCALE MAX176 1... 111 , ADJUST Ju oS / roy R Z Io4 45V << 10k 1% ~ 1 | 1! 2 Ra L R6 10.010 a i 10k YN NN OFFSET Bg 10... 001 ot , 4 . rod 14 ADJUST 7 iF nom a we BS ss GA = 2 28 g . 2S A BB AIN, INPUT VOTLAGE * Figure 8. MAX176 Transfer Function Figure 9. Noninverting Offset and Full-Scale Adjustment This circuit is configured to operate in continuous-conver- sion mode. However, it may be modified for burst-mode operation by controlling the shift register RCK inputs with R32.21k, 0.1% a signal other than convert start. When continuous-con- version mode is used, convert start must go high at the otur 14th falling clock edge to prevent shifting of data past the n shift register outputs shown; convert. start's rising edge latches the data that has been serially loaded into the two SHO 8 aie 8 ? Pan 74HC595 shift registers. Clock frequency is restricted INPUT Rd MAAXIM because of the clock-to-data delay (see Electrical Char- 680k. 5% MAX176 acteristics); the correct data must be present at the SER OFFSET == ADJUST b Figure 10. inverting Offset and Full-Scale Adjustment pin when clock rising edges strobe the data into the shift registers. The clock frequency is thus limited to 3.3MHz for the commercial version of the MAX176, unless the clock signal to the shift registers is delayed or inverted. This limitation also accounts for the 20ns shift-register setup time. Note that for clock frequencies above 2.5MHz, each conversion requires 15 clock cycles or more to allow sufficient T/H acquisition time. If 15 or 16 clock pulses occur between each convert start pulse, this circuit still functions, but the data at the shift register outputs is shifted up one or two positions, respectively, so that the MSB appears at the top shift registers QE or QF output. Figure 11b illustrates the timing for this shift reg- ister circuit. MAXIMSerial-Output, 250ksps 12-Bit ADC with T/H and Reference ~ CONVST ~~ LOCK (3.3MHz 3-WIRE g R LESS) DIGITAL a J? INTERFACE 14 OH SER OG Fe 74HC595 QF ih 4 SCK QE 3 10uF ev MAAXIAA 12 QD > D11 (MSB} Jk MAX176 -15V RCK ac } 010 OApF 1 8 10 QB 5 Dg *_- >] Yoo Vss +5| SCLR QA D8 ANALOG 2 7 "3 sy INPUT AIN CONVST ? a H dt Veer crack{& i 3). 8) 4 5 4 Vue TE GND DATA L 9 + J => Our 1*_ ory QH i . OH H D/ 14 a "41 sep aG . D6 74HC595 OF - D5 i 4 SCK Qt 3 D4 12 ay, 08 . RCK ac f | be 10 OB, OT sv 4 SCLR OA} = 00(1$8) + +5V - ai ~ Ole a) + + Figure 11a. 3-Wire interface to Parallel Port CONVST [ to 11 12 13 14 1 2 3 ow PF SEPLA Po ae DaTAY Di YX bo tM rer \ on 010 (09 X oe 07 de X 05 pa X 03 X 02 X 01 X OO \ "7 sian \ ony Figure 11b, Timing for Serial-to-Parallel Converter MAMNXLAA 9 9ZLXVWNMAX176 Serial-Output, 25O0ksps 12-Bit ADC with T/H and Reference +8+ 16 +5V 1.5k aa : IGITAL ; INTERFACE 7 QH gy |? SER QG 6 |, | 74HC595 or : 011 (MSB) ~ 7 SCK Qe], 10 1ouF -5 AA AXLAA o oD 5 09 + MAX176 15V RK oc H ba OF QB. 07 1 8 1 tl Yoo Vss ov sour QA a D6 ANALOG 2 7 . INPUT AIN CONST ee 3 6 2 H | YaEF Stock re | TOF Ope 5 ae Nae ( Gno DATA = = Lao 8 OIF t 4 QH D5 oy SER 3 ke D4 74HC595 D3 | 0 (pF . sck bp D1 2) ack D0(LSB) ' ot RESET GND asv 12. scir DO(LS8) MAXIM _ 5V 1CM7240 13 8] OTF Figure 12. 3-Wire Interface to Parallel Port Using Timer Chip In Figure 12s circuit, the clock and convert start signals are generated by an ICM7240 timer/converter, allowing stand-alone MAX176 operation. The ICM7240 provides a convert start pulse for every 16 clock cycles it generates. Due to the ICM7240s upper frequency limit. this circults clock frequency is 1MHz maximum. If CON- VST is capacitively loaded with greater than 80pF, the maximum allowable convert start rise-time specification might be exceeded. Using a logic buffer between the ICM7240 and CONVST of the MAX176 eliminates this problem. Check that none of the timing characteristics are violated when longer rise times occur due to capaci- tive loading of CONVST or CLOCK. MAX176 with Opto-Isolators Transducer outputs often require electrical isolation to separate the control electronics from hazardous electrical conditions, provide noise immunity, or bridge large dif- ferences in ground potential. Isolation amplifiers typically 10 used for accomplishing this are expensive. In cases where the signal is eventually converted to a digital form, itis cost effective to isolate the input using opto-isolaters ina serial data link. The MAX176 is ideal in this application because it includes both T/H amplifier and voltage refer- ence, and because of its low power consumption (Figure 13a). The ADC results are transmitted across a 1500V isolation barrier provided by three 6N136 opto-isclators. Note that isolated power must be provided to the con- verter and the isolated side of the opto-isolators. 74HC595 three-state shift registers are used to construct a 12-bit parallel data output. (For those who prefer even greater space savings and do not need a T/H, Maxim's MAX171 combines the MAX170, three opto-isolators, and load resistors in a 16-pin DIP package.) Figure 13b shows the timing diagram for this application Conversion speed is limited by the delay through the opto-isolators. With a 140kHz clock, conversion time is 100us. MAXI/WVISerial-Output, 250ksps 12-Bit ADC with T/H and Reference +5V AND -15V ON THIS SIDE OF BARRIER MUST BE ISOLATED POWER 15V -15V 6N136 sv 7 3k _| 4 5 MAX176 8 Von Vss gf l aw cowsr[7 | oa 1 6 3] veer crock 2 e St 5 5 GND DATA T7002 4 OtuED Our SIGNAL 8 7 < GROUND a S _ Ly BS 74HC04 74HC04 a START ee INPUT CLOCK 7 QH 14 cee acl | 740595 oF |? SCK OF} 4 1 ao 5 D11 (MSB} RCK ac}, D190 ' OB F 7 D9 +5V] SCLR QA 08 1 @ 5V IgE Oa et 9 aH 14 QHy SER aG 74HC595 Ot - SCK ae| . 1 ap - RCK ac QB 10 SV I SCLR OA 134 8] Figure 13a, 12-Bit isolated A/D Converter 100us Conversion Time ANALOG N Cony | > N+1 CONV > me Ne2 CONY INPUT 12 13 14 1 ? wm (UO LU LP ee START PARALLEL DATA N-1DATA ATA bia oF x ND Xo Net DATA Figure 13b. Timing for isolated A/D Interface MANXIAA VW 9ZELXVINMAX176 Serial-Output, 250ksps 12-Bit ADC with T/H and Reference In this circuit, the 74HC04 inverters must sink the current flowing through the opto-isolators. However, maximum VoL for these parts is specified for lighter sink Currents. If the 74HCO04 output resistance is calculated by dividing VOL max by the sink current used for this specification (this resistance is valid up to about 30mA of sink current), the resulting voltage can be calculated when the part sinks these higher currents. The same procedure can be applied to the MAX176 DATA output - the calculated maximum resistance (250Q) is valid up to 10mA of sink current. The rise time of the signal applied to the MAX176's CONVST pin must be less than 100ns (see Electrical Characteristics). Because it has an open-collector out- put, the rise time of CONVSTs opto-isolator is a function of its pull-up resistor and any stray capacitance. Mini- mize this stray capacitance to ensure a fast enough rise time. Another consideration is the delays through this circuit due primarily to the opto-isolators. The largest delay is between input clock and the appearance of data at the lower shift registers SER pin. It is caused by delay through the 74HC04, the MAX176's clock-to-data delay (see Flectrical Characteristics), and the delay from two opto-isolators. This delay must be less than one clock period (by the setup time of the 74HC595), and it determines the fastest allowable clock speed for the circult. Finally, noise pickup on the relatively slow opto-coupler transitions can cause false triggering at the converters edge-sensitive CONVST input. To avoid this problem, set the rising edge of start (falling edge of convert start) to occur when the CONVST input ignores transitions (i.e. before clocks 13th falling edge). Starts falling edge triggers the next conversion, and also causes the ore- vious conversions results to appear at the parallel data outputs. Physical Layout For best system performance, use printed circuit boards for the MAX176 - wire-wrap boards are not recom- mended. The board layout should ensure that digital and analog signal lines are kept separate, and that digital lines do not pass underneath the MAX176 package. Grounding Figure 14 shows the recommended system ground con- nections. A single-point analog STAR ground should be established at the MAX176 GND pin. All analog-circuitry grounds should be connected to this STAR ground. The ground return to the power supply from STAR ground should be low impedance for noise-free operation. Digi- 12 Vss SUPPLY Vob SUPPLY -12+15V GND GND +8V Py rr Vss GND Vop GND +5V AAAXLAA ciecuitay MAX176 * STAR GROUND **R 10 OPTIONAL FOR FILTERING A NOISY Voy SUPPLY, Figure 14. Power-Supply Grounding tal-circuitry grounds must be connected to the digital supply common. All ground pins of the small-outline version of the MAX176 should connect to the STAR ground. Power-Supply Bypassing The MAX176's high-speed comparator is sensitive to high-frequency noise in the VoD and Vss power supplies. Bypass these supplies to the analog STAR ground with O.1pF and 10nF capacitors with minimum lead length for supply-noise rejection. If the +5V power supply is very noisy, connect a small resistor (109) to filter external noise (Figure 14). internal Voltage Reference The MAX176 has an on-chip reference with a buffered and temperature-compensated buried-zener diode, laser-trimmed to -5V +0.4%. Its output is connected to the VREF pin and also drives the internal DAC. This output can be used as a reference voltage source for other components, and can sink up to 5mA. Decouple VREF with a low-ESR 10uF capacitor in parallel with a 0. 1uF capacitor. Driving the Analog Input The input signal connections to AIN and GND should be as short as possible to minimize noise pickup. If the leads must be long, use shielded cables. The ADC analog input range is nominally +5V. However, the analog input can be driven to +15V with no damage to the device. MAXISerial-Output, 25Oksps 12-Bit ADC Because the MAX176 includes a T/H, the drive require- ments of an op amp connected to AIN are less critical than those for a successive-approximation ADC without aT/H. This amplifier, however, must provide Current with an amplitude dependent on the signal level at AIN (Figure 2). Also, the amplifier bandwidth should be sufficient to handle the frequency of the signal applied to it. The MAX400 and OPO7 work well at lower frequencies. For higher-frequency operation, the MAX427 and OP27 are suitable choices. The allowed input frequency range is limited by the 250ksps sample rate of the MAX176. Thus, the maximum sinusoidal input frequency allowed is 125kHz. Higher-frequency signals cause aliasing prob- lems unless undersampling techniques are used. Dynamic Performance High-speed sampling capability and 250kHz throughput make the MAX176 ideal for wideband signal processing. To support these and other related applications, Fast Fourier Transform (FFT) test techniques are used to guar- antee the ADCs dynamic frequency response, distortion, and noise at the rated throughput. Specifically, this in- volves applying a low distortion sine wave to the ADC input and recording the digital conversion results for a specified time. The data is then analyzed using an FFT algorithm, which determines its spectral content. Conver- sion errors are then seen as spectral elements outside the fundamental input frequency. Figure 15 shows an FFT plot ADCs have traditionally been evaluated by specifications such as zero and full-scale error, integral nonlinearity (INL) and differential nonlinearity (DNL). Such parame- ters are widely accepted for specifying performance with DC and slowly varying signals, but are less useful in signal-processing applications where the ADCs impact on the system transfer function is the main concern. The significance of various DC errors does not translate well to the dynamic case, so different tests are required. Signal-to-Noise Ratio and Effective Number of Bits The signal-to-noise plus distortion ratio (S/N + D) is the ratio of the fundamental input frequency's RMS amplitude to the RMS amplitude of all other A/D output signals. The output band is limited to frequencies above DC and below one-half the A/D sample (conversion) rate. This includes distortion as well as noise components. with T/H and Reference The theoretical minimum A/D noise is cause by quantiza- tion error and is a direct result of the ADC's resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. A perfect 12-bit ADC can, therefore, do no better than 74dB. By transposing the equation that converts resolution to SNR, we can, from the measured SNR, determine the effective resolution, or effective number of bits, the ADC provides: N = (SNR - 1.76)/6.02. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal (in the frequency band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as: VV> FAV + Vaio + Vn Vi where V1 is the fundamental RMS amplitude and V2 to VN are the amplitudes of the 2nd through Nth harmonics. THD = 20log Peak Harmonic or Spurious Noise Peak harmonic (or spurious) noise is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually this peak occurs at some harmonic of the input frequency, but if the ADC is exceptionally linear, it may occur only at a random peak in the ADC's noise floor. 0.000 fsamplb - 230kKH7 -20.000 lin - 51.37kKH2 SNR 71./dB -40.000 THD - -88.0d8 -60.000 i -80.000 -100.000 MAGNITUDE (dB) -120.000 0 50 FREQUENCY (kHz) Figure 15. MAX176 FFT Plot 13 MAXIMA 9ZELXVINSerial-Output, 250ksps 12-Bit ADC with T/H and Reference __ Ordering Information (continued) Chip Topography MAX176 Contact factory for availability and processing to MIL-STD-883. 14 DATA 115" + -_ _ (2.92 mm) PART TEMP. RANGE PIN-PACKAGE isey MAXI76AEPA -40'C10+85C 8 Plastic DIP. 41/2 Voo Vss MAX176BEPA -40Cto+85C 8 Plastic DIP_ +1 MAXI76AEWE -40Cto 485C 16WideSO +1/2_=*SY| CONVST MAX176BEWE -40C to 485C 16WideSO +1 MAXI76AMJA -55C 10 +125C 8 CERDIP* 43/4 | AIN MAXI76BMJA -55C to +125C 8 CERDIP + * Contact factory for dice specifications. VREF CLOCK 145" (3.69 mm) MAXIWI