1
LTC2704
2704f
Quad 12-, 14- and 16-Bit
Voltage Output SoftSpan
DACs with Readback
■
Six Programmable Output Ranges:
Unipolar: 0V to 5V, 0V to 10V
Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V
■
Serial Readback of All On-Chip Registers
■
1LSB INL and DNL Over the Industrial
Temperature Range (LTC2704-14/LTC2704-12)
■
Force/Sense Outputs Enable Remote Sensing
■
Glitch Impulse: < 2nV-sec
■
Outputs Drive ±5mA
■
Pin Compatible 12-, 14- and 16-Bit Parts
■
Power-On and Clear to Zero Volts
■
44-Lead SSOP Package
■
Process Control and Industrial Automation
■
Direct Digital Waveform Generation
■
Software Controlled Gain Adjustment
■
Automated Test Equipment
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
SoftSpan is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
REFM1 REFG1 REF1
24
42 23
21
REFM2REFG2
2704 BD
REF2
43
44 2
V
+1
32
AGND
25
V
+2
V
–
1,8,15,22,31,36
12
SRO
SDI
11
SCK
13
LDAC
9
CLR
14
CS/LD
10
RFLAG
35
V
DD
34
GND
33
DAC C
DAC D
26
29
28
27
30
20
17
18
19
16
AGNDC
C1D
RFBD
OUTD
AGNDD
OUTC
RFBC
C1C
VOSC
VOSD
DAC A
AGNDA
OUTA
RFBA
C1A
VOSA
3
6
5
4
7
DAC B
C1B
RFBB
OUTB
AGNDB
VOSB
41
38
39
40
37
–1
–1
The LTC
®
2704-16/LTC2704-14/LTC2704-12 are serial in-
put, 12-, 14- or 16-bit, voltage output SoftSpan™ DACs
that operate from 3V to 5V logic and ±5V to ±15V analog
supplies. SoftSpan offers six output spans—two unipolar
and four bipolar—fully programmable through the 3-wire
SPI serial interface. INL is accurate to 1LSB (2LSB for the
LTC2704-16). DNL is accurate to 1LSB for all versions.
Readback commands allow verification of any on-chip
register in just one 24- or 32- bit instruction cycle. All other
commands produce a “rolling readback” response from
the LTC2704, dramatically reducing the needed number of
instruction cycles.
A Sleep command allows any combination of DACs to be
powered down. There is also a reset flag and an offset
adjustment pin for each channel.
SI PLIFIED
W
BLOCK DIAGRA
W
LTC2704-16
Integral Nonlinearity (INL)
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2704 TA01b
–0.6
0.6
0.8
0.2
49152 65535
V+/V
–
= ±15V
V
REF
= 5V
±10V RANGE
ALL 4 DACS
SUPERIMPOSED
2
LTC2704
2704f
ORDER PART
NUMBER
(Note 1)
Total Supply Voltage V
+1
, V
+2
to V
–
........... –0.3V to 36V
V
+1
, V
+2
, REF1, REF2, REFM1, REFM2,
OUTx, RFBx, V
OSx
to GND, AGND,
AGNDx, C1x, REFG1, REFG2 ................................... 18V
GND, AGND, AGNDx, C1x, REFG1, REFG2 to V
+1
,
V
+2
, V
–
, REF1, REF2, REFM1, REFM2, OUTx,
RFBx, V
OSx
............................................................... 18V
OUTA, RFBA, V
OSA
, OUTB, RFBB, VOSB, REF1,
REFM1 to GND, AGND ............... V
–
– 0.3V to V
+1
+ 0.3V
OUTC, RFBC, V
OSC
, OUTD, RFBD, V
OSD
, REF2, REFM2
to GND, AGND ........................... V
–
– 0.3V to V
+2
+ 0.3V
V
DD
, Digital Inputs/Outputs to GND ............. –0.3V to 7V
Digital Inputs/Outputs to V
DD
................................. 0.3V
GND, AGNDx, REFG1, REFG2 to AGND ................ ±0.3V
C1x to AGNDx ....................................................... ±0.3V
V
–
to Any Pin .......................................................... 0.3V
Maximum Junction Temperature ......................... 150°C
Operating Temperature Range
LTC2704C ............................................... 0°C to 70°C
LTC2704I............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
LTC2704CGW-16
LTC2704IGW-16
LTC2704CGW-14
LTC2704IGW-14
LTC2704CGW-12
LTC2704IGW-12
T
JMAX
= 125°C, θ
JA
= 80°C/W
ABSOLUTE MAXIMUM RATINGS
W
WW
U
PACKAGE/ORDER INFORMATION
W
UU
Consult LTC Marketing for parts specified with wider operating temperature ranges.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
TOP VIEW
GW PACKAGE
44-LEAD PLASTIC SSOP
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V–
REFG1
AGNDA
VOSA
C1A
OUTA
RFBA
V–
LDAC
CS/LD
SDI
SRO
SCK
CLR
V–
RFBD
OUTD
C1D
VOSD
AGNDD
REFG2
V–
REFM1
REF1
V+1
AGNDB
VOSB
C1B
OUTB
RFBB
V–
RFLAG
VDD
GND
AGND
V–
RFBC
OUTC
C1C
VOSC
AGNDC
V+2
REF2
REFM2
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C,
V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V.
ELECTRICAL CHARACTERISTICS
LTC2704-12 LTC2704-14 LTC2704-16
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
Accuracy
Resolution ●12 14 16 Bits
Monotonicity ●12 14 16 Bits
INL Integral Nonlinearity V
REF
= 5V ●±1±1±2 LSB
DNL Differential Nonlinearity V
REF
= 5V ●±1±1±1 LSB
GE Gain Error V
REF
= 5V ●±0.5 ±2±1±5±4±20 LSB
Gain Temperature ∆Gain/∆Temperature ●±2±2±2 ppm/°C
Coefficient
V
OS
Unipolar Zero-Scale Error Span = 0V to 5V, T
A
= 25°C±80 ±200 ±80 ±200 ±80 ±200 µV
Span = 0V to 10V, T
A
= 25°C±100 ±300 ±100 ±300 ±100 ±300 µV
Span = 0V to 5V ●±140 ±400 ±140 ±400 ±140 ±400 µV
Span = 0V to 10V ●±150 ±600 ±150 ±600 ±150 ±600 µV
3
LTC2704
2704f
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C,
V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V.
LTC2704-12 LTC2704-14 LTC2704-16
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
V
OS
Temperature 0V to 5V Range ●±2±2±2µV/°C
Coefficient 0V to 10V Range ●±2±2±2µV/°C
BZE Bipolar Zero All Bipolar Ranges ±0.25 ±1±0.5 ±2±2±8LSB
Error ●±2±2.5 ±10 LSB
PSRR Power Supply V
DD
= 5V ±10% (Note 3) ±0.003 ±0.013 ±0.05 LSB/V
Rejection Ratio V
DD
= 3V ±10% (Note 3) ±0.006 ±0.025 ±0.1 LSB/V
0V to 10V Range, Code = 0
V
+
/V
–
= ±15V ±10% (Note 2) ●±0.001 ±0.06 ±0.005 ±0.25 ±0.02 ±1 LSB/V
V
+
/V
–
= ±5V ±10%, V
REF
= 2V (Note 2) ●±0.002 ±0.05 ±0.01 ±0.13 ±0.04 ±0.5 LSB/V
Analog Outputs (Note 4)
Settling Time 0V to 5V Range, 5V Step, to ±1LSB 3 3.5 4 µs
0V to 10V or ±5V Range,
10V Step, to ±1LSB 5 5.5 6 µs
±10V Range, 20V Step, to ±1LSB 8 9 10 µs
Output Swing V
+
/V
–
= ±15V, V
REF
= ±7.25V, ●–14.5 14.5 –14.5 14.5 –14.5 14.5 V
0V to 10V Range, I
LOAD
= ±3mA (Note 2)
V
+
/V
–
= ±5V, V
REF
= ±2.25V, ●–4.5 4.5 –4.5 4.5 –4.5 4.5 V
0V to 10V Range, I
LOAD
= ±3mA (Note 2)
Load Current V
+
/V
–
= ±10.8V to ±16.5V, V
REF
= ±5V, ●±5±5±5mA
0V to 10V Range, V
OUT
= ±10V (Note 2)
V
+
/V
–
= ±4.5V to ±16.5V, V
REF
= ±2V, ●±3±3±3mA
0V to 10V Range, V
OUT
= ±4V (Note 2)
Load Regulation V
+
/V
–
= ±15V, V
REF
= 5V, ●±0.005 ±0.01 ±0.04 LSB/mA
0V to 10V Range, Code = 0, ±5mA Load
(Note 2)
V
+
/V
–
= ±5V, V
REF
= 2V, ●±0.01 ±0.013 ±0.05 LSB/mA
0V to 10V Range, Code = 0, ±3mA Load
(Note 2)
Output V
REF
= 5V, 0V to 10V Range, ●0.015 0.006 0.006 Ω
Impedance Code = 0, ±5mA Load
I
SC
Short-Circuit V
+
/V
–
= ±16.5V, V
REF
= 5V, ±10V Range
Current Code = 0, V
OUT
Shorted to V
+
(Note 2) ●38 38 38 mA
Code = Full Scale, V
OUT
Shorted to V
–
●–36 –36 –36 mA
V
+
/V
–
= ±5.5V, V
REF
= 2V, ±10V Range
Code = 0, V
OUT
Shorted to V
+
(Note 2) ●38 38 38 mA
Code = Full Scale, V
OUT
Shorted to V
–
●–36 –36 –36 mA
SR Slew Rate R
L
= 2k, V
+
/V
–
= ±15V (Note 2) ●2.2 3 2.2 3 2.2 3 V/µs
R
L
= 2k, V
+
/V
–
= ±5V (Note 2) ●2.0 2.8 2.0 2.8 2.0 2.8 V/µs
Capacitive Load Within Maximum Load Current 1000 1000 1000 pF
Driving
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C,
V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Reference Inputs
REF1, REF2 Input Voltage V
+
/V
–
= ±15V, 0V to 5V Span (Note 2) ●–14.5 14.5 V
Resistances
R
REF1,
R
REF2
Reference Input Resistance ● 57 kΩ
R
FBx
Output Feedback Resistance ●710 kΩ
R
VOSX
Offset Adjust Input Resistance ●700 1000 kΩ
4
LTC2704
2704f
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C,
V+1 = V+2 = 15V, V– = –15V, VDD = 5V, REF1 = REF2 = 5V, AGND = AGNDx = REFG1 = REFG2 = GND = 0V.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AC Performance (Note 4)
Glitch Impulse 0V to 5V Range, Midscale Transition 2 nV-s
Crosstalk 10V Step on V
OUTA
DAC B: 0V to 5V Range, Full Scale 2 nV-s
DAC B: 0V to 10V Range, Full Scale 3 nV-s
Digital Feedthrough ±10V Range, Midscale 0.2 nV-s
Multiplying Feedthrough Error 0V to 10V Range, V
REF
= ±5V, 10kHz Sine Wave 0.35 mV
P-P
Multiplying Bandwidth Span = 0V to 5V, Full Scale 300 kHz
Span = 0V to 10V, Full Scale 250 kHz
Output Noise Voltage Density 10kHz
Span = 0V to 5V, Midscale 30 nV/√Hz
Span = 0V to 10V, Midscale 50 nV/√Hz
Output Noise Voltage 0.1Hz to 10Hz
Span = 0V to 5V, Midscale 0.8 µV
RMS
Span = 0V to 10V, Midscale 1.2 µV
RMS
Power Supply
I
DD
Supply Current, V
DD
Digital Inputs = 0V or V
DD
●0.5 2 µA
I
S
Supply Current, V
+
/V
–
V
+
/V
–
= ±15V, ±10%; V
REF
= 5V, V
OUT
= 0V (Note 2) ●17.5 20 mA
V
+
/V
–
= ±5V, ±10%; V
REF
= 2V, V
OUT
= 0V (Note 2) ●17.0 18 mA
Sleep Mode—All DACs (Note 4) ●1mA
V
DD
Logic Supply Voltage ●2.7 5.5 V
V
+1
/V
+2
Positive Analog Supply Voltage ●4.5 16.5 V
V
–
Negative Analog Supply Voltage ●–16.5 –4.5 V
Digital Inputs/Outputs
V
IH
Digital Input High Voltage V
DD
= 2.7V to 5.5V ●2.4 V
V
DD
= 2.7V to 3.3V ●2.0 V
V
IL
Digital Input Low Voltage V
DD
= 2.7V to 5.5V ●0.6 V
V
DD
= 4.5V to 5.5V ●0.8 V
V
OH
Digital Output High Voltage I
OH
= 200µA●V
CC
– 0.4 V
V
OL
Digital Output Low Voltage I
OL
= 200µA●0.4 V
I
IN
Digital Input Current ●0.001 ±1µA
C
IN
Digital Input Capacitance V
IN
= 0V (Note 3) ●5pF
TI I G CHARACTERISTICS
UW
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
DD
= 4.5V to 5.5V
t
1
SDI Valid to SCK Setup ●7ns
t
2
SDI Valid to SCK Hold ●7ns
t
3
SCK High Time ●11 ns
t
4
SCK Low Time ●11 ns
t
5
CS/LD Pulse Width ●9ns
t
6
LSB SCK High to CS/LD High ●0ns
t
7
CS/LD Low to SCK Positive Edge ●12 ns
t
8
CS/LD High to SCK Positive Edge ●12 ns
t
9
SRO Propagation Delay C
LOAD
= 10pF ●18 ns
t
10
CLR Pulse Width ●50 ns
5
LTC2704
2704f
TI I G CHARACTERISTICS
UW
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The notation V
+
is used to denote both V
+1
and V
+2
when the same
voltage is applied to both pins.
Note 3: Guaranteed by design, not subject to test.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC2704-16
Integral Nonlinearity (INL)
CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2704 G01
–0.6
0.6
0.8
0.2
49152 65535
V+/V– = ±15V
VREF = 5V
±10V RANGE
CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
16384 32768
2704 G02
–0.6
0.6
0.8
0.2
49152 65535
V+/V– = ±15V
VREF = 5V
±10V RANGE
V
REF
(V)
–10
INL (LSB)
0.2
0.6
1.0
6
2704 G03
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0 –6–8 –2–4 24 8
010
V+/V
–
= ±15V
±5V RANGE
MAX MAX
MIN MIN
Differential Nonlinearity (DNL) INL vs VREF
Note 4: Measured in unipolar 0V to 5V mode.
Note 5: When using SRO, maximum SCK frequency f
MAX
is limited by
SRO propagation delay as follows:
ftt
MAX S
=+
()
⎛
⎝
⎜⎞
⎠
⎟
1
2
9
, where t
s
is the setup time of the receiving
device.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
11
LDAC Pulse Width ●15 ns
t
12
CLR Low to RFLAG Low C
LOAD
= 10pF (Note 3) ●50 ns
t
13
CS/LD High to RFLAG High C
LOAD
= 10pF (Note 3) ●40 ns
SCK Frequency 50% Duty Cycle (Note 5) ●40 MHz
V
DD
= 2.7V to 3.3V
t
1
SDI Valid to SCK Setup ●9ns
t
2
SDI Valid to SCK Hold ●9ns
t
3
SCK High Time ●15 ns
t
4
SCK Low Time ●15 ns
t
5
CS/LD Pulse Width ●12 ns
t
6
LSB SCK High to CS/LD High ●0ns
t
7
CS/LD Low to SCK Positive Edge ●12 ns
t
8
CS/LD High to SCK Positive Edge ●12 ns
t
9
SRO Propagation Delay C
LOAD
= 10pF ●26 ns
t
10
CLR Pulse Width ●90 ns
t
11
LDAC Pulse Width ●20 ns
t
12
CLR Low to RFLAG Low C
LOAD
= 10pF ●70 ns
t
13
CS/LD High to RFLAG High C
LOAD
= 10pF ●60 ns
SCK Frequency 50% Duty Cycle (Note 5) ●25 MHz
6
LTC2704
2704f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Bipolar Zero vs Temperature Gain Error vs Temperature
TEMPERATURE (°C)
–50
LSB
4
90
2704 G07
–8 –30 –10 10 30 50 70
8
2
6
0
–4
–6
–2
V+/V
–
= ±15V
V
REF
= 5V
±10V RANGE
TEMPERATURE (°C)
–50
GAIN ERROR (LSB)
12
16
–16
–12
30
2704 G08
0
4
–4
8
–8
–30 –10 10 50 70 90
V+/V– = ±15V
VREF = 5V
±10V RANGE
INL vs Temperature Offset vs Temperature
TEMPERATURE (°C)
–50
INL (LSB)
0.2
0.6
1.0
30
2704 G04
–0.2
–O.6
0
0.4
0.8
–0.4
–0.8
–1.0 –30 –10 10 50 70 90
V+/V– = ±15V
VREF = 5V
±10V RANGE
MAX
MIN
DNL vs Temperature
TEMPERATURE (°C)
–50
DNL (LSB)
0.2
0.6
1.0
30
2704 G05
–0.2
–O.6
0
0.4
0.8
–0.4
–0.8
–1.0 –30 –10 10 50 70 90
V+/V– = ±15V
VREF = 5V
±10V RANGE
MAX
MIN
TEMPERATURE (°C)
–50
OFFSET (µV)
200
400
600
30
2704 G06
–200
–600
0
–400
–30 –10 10 50 70 90
V+/V– = ±15V
VREF = 5V
0V TO 10V RANGE
LTC2704-16
2.5µs/DIV
V
OUT
5V/DIV
V
OUT
1mV/DIV
CS/LD
5V/DIV
2704 G18
Settling 0V to 5V
2.5µs/DIV
V
OUT
5V/DIV
V
OUT
1mV/DIV
CS/LD
5V/DIV
2704 G19
2.5µs/DIV
V
OUT
10V/DIV
V
OUT
1mV/DIV
CS/LD
5V/DIV
2704 G20
Settling 0V to 10V Settling ±10V
7
LTC2704
2704f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC2704-16/LTC2704-14/LTC2704-12
Positive Slew Negative Slew
2.5µs/DIV
5V/DIV
2704 G13
V+/V
–
= ±15V
V
REF
= 5V
±10V RANGE
20V STEP
2.5µs/DIV
5V/DIV
2704 G14
V+/V
–
= ±15V
V
REF
= 5V
±10V RANGE
20V STEP
2.5µs/DIV
CS/LD
5V/DIV
V
OUT
2mV/DIV
2704 G15
Midscale Glitch
LTC2704-14
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
CODE
0
–1.0
LSB
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192
2704 G09
–0.6
0.6
0.8
0.2
12288 16383
V+/V
–
= ±15V
V
REF
= 5V
±10V RANGE
CODE
0
–1.0
LSB
–0.8
–0.4
–0.2
0
1.0
0.4
4096 8192
2704 G10
–0.6
0.6
0.8
0.2
12288 16383
V+/V
–
= ±15V
V
REF
= 5V
±10V RANGE
LTC2704-12
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
CODE
0
–1.0
LSB
–0.8
–0.4
–0.2
0
1.0
0.4
1536 2048
2704 G11
–0.6
0.6
0.8
0.2
3072
512 1024 2560 3584 4095
V+/V– = ±15V
VREF = 5V
±10V RANGE
CODE
0
–1.0
LSB
–0.8
–0.4
–0.2
0
1.0
0.4
1536 2048
2704 G12
–0.6
0.6
0.8
0.2
3072
512 1024 2560 3584 4095
V+/V
–
= ±15V
V
REF
= 5V
±10V RANGE
8
LTC2704
2704f
UU
U
PI FU CTIO S
V
–
(Pins 1, 8, 15, 22, 31, 36): Analog Negative Supply,
Typically –15V. –4.5V to –16.5V Range.
REFG1 (Pin 2): Reference 1 Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
AGNDA (Pin 3): DAC A Signal Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
VOSA (Pin 4): Offset Adjust for DAC A. Nominal input
range is ±5V. VOS(DAC A) = –0.01• V(VOSA) [0V to 5V,
±2.5V modes]. See Operation section.
C1A (Pin 5): Feedback Capacitor Connection for DAC A
Output. This pin provides direct access to the negative
input of the channel A output amplifier.
OUTA (Pin 6): DAC A Voltage Output Pin. For best load
regulation, this open-loop amplifier output is connected to
RFBA as close to the load as possible.
RFBA (Pin 7): DAC A Output Feedback Resistor Pin.
LDAC (Pin 9): Asynchronous DAC Load Input. When
LDAC is a logic low, all DACs are updated.
CS/LD (Pin 10): Synchronous Chip Select and Load Pin.
SDI (Pin 11): Serial Data Input. Data is clocked in on the
rising edge of the serial clock when CS/LD is low.
SRO (Pin 12): Serial Readback Data Output. Data is clocked
out on the falling edge of SCK. Readback data begins clock-
ing out after the last address bit A0 is clocked in.
SCK (Pin 13): Serial Clock.
CLR (Pin 14): Asynchronous Clear Pin. When this pin is
low, all code and span B2 registers are cleared to zero. All
DAC outputs are cleared to zero volts.
RFBD (Pin 16): DAC D Voltage Output Feedback Resistor
Pin.
OUTD (Pin 17): DAC D Voltage Output Pin. For best load
regulation, this open-loop amplifier output is connected to
RFBD as close to the load as possible.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LTC2704-16/LTC2704-14/LTC2704-12
0.1Hz to 10Hz Noise
VCC Supply Current
vs Logic Voltage
1s/DIV
1µV/DIV
2704 G16
V+/V
–
= ±15V
V
REF
= 5V
0V TO 5V RANGE
CODE = 0
LOGIC VOLTAGE (V)
0
0
I
CC
(mA)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.5 2.5 3.5
2704 G17
2.0 4.5 5.0
1.0 1.5 3.0 4.0
V
DD
= 5V
SCK, SDI, CS/LD, LDAC
CLR TIED TOGETHER
9
LTC2704
2704f
UU
U
PI FU CTIO S
C1D (Pin 18): Feedback Capacitor Connection for DAC D
Output.
This pin provides direct access to the negative
input of the channel D output amplifier.
VOSD (Pin 19): Offset Adjust for DAC D. Nominal input
range is ±5V. VOS(DAC D) = –0.01• V(VOSD) [0V to 5V,
±2.5V modes]. See Operation section.
AGNDD (Pin 20):
DAC D Signal Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
REFG2 (Pin 21): Reference 2 Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
REFM2 (Pin 23): Reference 2 Inverting Amp Output. The
gain from REF2 to REFM2 is –1. Can swing to within 0.5V
of the analog supplies V
+
/V
–
.
REF2 (Pin 24): DAC C and DAC D Reference Input.
V
+2
(Pin 25): Analog Positive Supply for DACs C and D.
Typically 15V. 4.5V to 16.5V Range. Can be different from
V
+1
.
AGNDC (Pin 26):
DAC C Signal Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
VOSC (Pin 27): Offset Adjust for DAC C. Nominal input
range is ±5V. VOS(DAC C) = –0.01• V(VOSC) [0V to 5V,
±2.5V modes]. See Operation section.
C1C (Pin 28): Feedback Capacitor Connection for DAC C
Output. This pin provides direct access to the negative
input of the channel C output amplifier.
OUTC (Pin 29): DAC C Voltage Output Pin. For best load
regulation, this open-loop amplifier output is connected to
RFBC as close to the load as possible.
RFBC (Pin 30): DAC C Output Feedback Resistor Pin.
AGND (Pin 32):
Analog Ground Pin. Tie to clean analog
ground.
GND (Pin 33):
Ground Pin. Tie to clean analog ground.
V
DD
(Pin 34):
Logic Supply. 2.7V to 5.5V Range.
RFLAG (Pin 35): Reset Flag Pin. An active low output is
asserted when there is a power on reset or a clear event.
Returns high when an update command is executed.
RFBB (Pin 37): DAC B Output Feedback Resistor Pin.
OUTB (Pin 38): DAC B Voltage Output Pin. For best load
regulation, this open-loop amplifier output is connected to
RFBB as close to the load as possible.
C1B (Pin 39): Feedback Capacitor Connection for DAC B
Output. This pin provides direct access to the negative
input of the channel B output amplifier.
VOSB (Pin 40): Offset Adjust for DAC B. Nominal input
range is ±5V. VOS(DAC B) = –0.01 • V(VOSB) [0V to 5V,
±2.5V modes]. See Operation section.
AGNDB (Pin 41): DAC B Signal Ground. High impedance
input, does not carry supply currents. Tie to clean analog
ground.
V
+1
(Pin 42): Analog Positive Supply for DACs A DND B.
Typically 15V. 4.5V to 16.5V Range. Can be different from
V
+2
.
REF1 (Pin 43): DAC A and DAC B Reference Input.
REFM1 (Pin 44): Reference 1 Inverting Amp Output. The
gain from REF1 to REFM1 is –1. Can swing to within 0.5V
of the analog supplies V
+
/V
–
.
10
LTC2704
2704f
BLOCK DIAGRA
W
42
12
SRO
2704 BD
32
AGND
25
V+2
V–
1,8,15,22,31,36
COMMAND
DECODE
INPUT
SHIFT REGS
READBACK
SHIFT REGS
DAC
BUFFERS
SDI
11
SCK
13
LDAC
9
CLR
14
CS/LD
10
RFLAG
35
VDD
34
GND POR
33
REF1
43
V+1
AGNDA
OUTA
RFBA
C1A
VOSA
3
6
5
4
7
DAC A
+
–
AGNDB
OUTB
RFBB
C1B
VOSB
41
REFM1
44
REFG1
AGNDC
OUTC
RFBC
C1C
VOSC
REF2
AGNDD
OUTD
RFBD
C1D
VOSD
REFM2
REFG2
2
38
39
40
37
26
29
28
24
27
30
20
23
21
17
18
19
16
DAC B
+
–
–
+
+
–
+
–
–
+
DAC C
DAC D
SDI
SRO Hi-Z
CS/LD
SCK
LSB
2704 TD
LSB
t2
t9
t8
t5t7
1 2 31 32
t6
t1
LDAC
t3t4
t11
TI I G DIAGRA
UWW
11
LTC2704
2704f
OPERATIO
U
SERIAL INTERFACE
When the CS/LD pin is taken low, the data on the SDI pin
is loaded into the shift register on the rising edge of the
clock signal (SCK pin). The minimum (24-bit wide) load-
ing sequence required for the LTC2704 is a 4-bit com-
mand word (C3 C2 C1 C0), followed by a 4-bit address
word (A3 A2 A1 A0) and 16 data (span or code) bits, MSB
first. Figure 1 shows the SDI input word syntax to use
when writing a code or span. If a 32-bit input sequence is
needed, the first eight bits must be zeros, followed by the
same sequence as for a 24-bit wide input. Figure 2 shows
the input and readback sequences for both 24-bit and
32-bit operations.
When CS/LD is low, the Serial Readback Output (SRO) pin
is an active output. The readback data begins after the
command (C3-C0) and address (A3-A0) words have been
shifted into SDI. For a 24-bit load sequence, the 16
readback bits are shifted out on the falling edges of clocks
8-23, suitable for shifting into a microprocessor on the
rising edges of clocks 9-24. For a 32-bit load sequence,
add 8 to these clock cycle counts; see Figure 2b.
When CS/LD is high, the SRO pin presents a high imped-
ance (three-state) output. At the beginning of a load
sequence, when CS/LD is taken low, SRO outputs a logic
low until the readback data begins.
When the asynchronous load pin, LDAC, is taken low, all
DACs are updated with code and span data (data in B1
buffers is copied into B2 buffers). CS/LD must be high
during this operation. The use of LDAC is functionally
identical to the “Update B1→B2” commands.
The codes for the command word (C3-C0) are defined in
Table 1; Table 2 defines the codes for the address word
(A3-A0).
READBACK
Each DAC has two pairs of double-buffered digital regis-
ters, one pair for DAC code and the other for the output
span (four buffers per DAC). Each double-buffered pair
comprises two registers called buffer 1 (B1) and buffer 2
(B2).
B1 is the holding buffer. When data is shifted into B1 via
a write operation, DAC outputs are not affected. The
contents of B2 can only be changed by copying the
contents of B1 into B2 via an update operation (B1 and B2
can be changed together, see commands 0110-1001 in
Table 1). The contents of B2 (DAC code or DAC span)
directly control the DAC output voltage or the DAC output
range.
Additionally each DAC has one readback register associ-
ated with it. When a readback command is issued to a DAC,
the contents of one of its four buffers is copied into its
readback register and serially shifted out onto the SRO pin.
Figure 2 shows the loading and readback sequences. In
the 16-bit data field (D15-D0 for the LTC2704-16, see
Figure 2a) of any write or update command, the readback
pin (SRO) shifts out the contents of the buffer which was
specified in the preceding command. This “rolling
readback” mode of operation can be used to reduce the
number of operations, since any command can be verified
during succeeding commands with no additional over-
head. Table 1 shows the location (readback pointer) of the
data which will be output from SRO during the next
instruction.
For readback commands, the data is shifted out during the
readback instruction itself (on the 16 falling SCK edges
immediately after the last address bit is shifted in on SDI).
When programming the span of a DAC, the span bits are
the last four bits shifted in; and when checking the span of
a DAC using SRO, the span bits are likewise the last four
bits shifted out. Table 3 shows the span codes.
When span information is read back on SRO, the sleep
status of the addressed DAC is also output. The sleep
status bit, SLP, occurs sequentially just before the four
span bits. The sequence is shown in Figures 2a and 2b. See
Table 4 for SLP codes. Note that SLP is an output bit only;
sleep is programmed by using command code 1110 along
with the desired address. Any update command, including
the use of LDAC, wakes the addressed DAC(s).
12
LTC2704
2704f
OPERATIO
U
CODE
Table 2. Address Codes
A3 A2 A1 A0 n READBACK POINTER n
0 0 0 0 DAC A DAC A
0 0 1 0 DAC B DAC B
0 1 0 0 DAC C DAC C
0 1 1 0 DAC D DAC D
1 1 1 1 All DACs DAC A
Codes not shown are reserved and should not be used.
Table 3. Span Codes
S3 S2 S1 S0 SPAN
0000 Unipolar 0V to 5V
0001 Unipolar 0V to 10V
0010 Bipolar –5V to 5V
0011 Bipolar –10V to 10V
0100 Bipolar – 2.5V to 2.5V
0101 Bipolar –2.5V to 7.5V
Codes not shown are reserved and should not be used.
Table 1. Command Codes
READBACK POINTER— READBACK POINTER—
C3 C2 C1 C0 COMMAND CURRENT INPUT WORD W
0
NEXT INPUT WORD W
+1
0010 Write to B1 Span DAC n Set by Previous Command B1 Span DAC n
0011 Write to B1 Code DAC n Set by Previous Command B1 Code DAC n
0100 Update B1→B2 DAC n Set by Previous Command B2 Span DAC n
0101Update B1→B2 All DACs Set by Previous Command B2 Code DAC A
0110 Write to B1 Span DAC n Set by Previous Command B2 Span DAC n
Update B1→B2 DAC n
0111 Write to B1 Code DAC n Set by Previous Command B2 Code DAC n
Update B1→B2 DAC n
1000 Write to B1 Span DAC n Set by Previous Command B2 Span DAC n
Update B1→B2 All DACs
1001 Write to B1 Code DAC n Set by Previous Command B2 Code DAC n
Update B1→B2 All DACs
1010 Read B1 Span DAC n B1 Span DAC n
1011 Read B1 Code DAC n B1 Code DAC n
1100 Read B2 Span DAC n B2 Span DAC n
1101 Read B2 Code DAC n B2 Code DAC n
1110 Sleep DAC n (Note 1) Set by Previous Command B2 Span DAC n
1111 No Operation Set by Previous Command B2 Code DAC n
Codes not shown are reserved and should not be used.
Note 1: Normal operation can be resumed by issuing any update B1→B2 command to the sleeping DAC.
OUTPUT RANGES
The LTC2704 is a quad DAC with software-programmable
output ranges. SoftSpan provides two unipolar output
ranges (0V to 5V and 0V to 10V), and four bipolar ranges
(±2.5V, ±5V, ±10V and – 2.5V to 7.5V). These ranges are
obtained when an external precision 5V reference and
analog supplies of ±12V to ±15V are used. When a
reference voltage of 2V and analog supplies of ±5V are
used, the SoftSpan ranges become: 0V to 2V, 0V to 4V,
±1V, ±2V, ±4V and –1V to 3V. The output ranges are
linearly scaled for references other than 2V and 5V (appro-
priate analog supplies should be used within the range
±5V to ±15V). Each of the four DACs can be programmed
to any one of the six output ranges. DAC outputs can swing
to ±10V on ±10.8V supplies (±12V supplies with ±10%
tolerance) while sourcing or sinking 5mA of load current.
13
LTC2704
2704f
OPERATIO
U
C2 C1 C0 A3 A2 A1 A0 D15
MSB
D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LSB
C3
LTC2704-16
(WRITE CODE)
CONTROL WORD ADDRESS WORD 16-BIT CODE
C2 C1 C0 A3 A2 A1 A0 D13
MSB
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0
LSB
C3
LTC2704-14
(WRITE CODE)
CONTROL WORD
SDI ADDRESS WORD 14-BIT CODE 2 ZEROS
C2 C1 C0 A3 A2 A1 A0 D11
MSB
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0
LSB
C3
LTC2704-12
(WRITE CODE)
CONTROL WORD ADDRESS WORD 12-BIT CODE 4 ZEROS
C2C1C0A3A2A1A00000 00000000S3S2S1S0C3
LTC2704-12
LTC2704-14
LTC2704-16
(WRITE SPAN)
CONTROL WORD ADDRESS WORD 12 ZEROS SPAN
2704 F01
Figure 1. Input Words
14
LTC2704
2704f
OPERATIO
U
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C3
0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D00
CS/LD
SCK
SDI
SRO Hi-Z
Hi-Z
CONTROL WORD
READBACK CODE
0000 00 00000 0000000SLPS3S2S1S00
SRO
READBACK SPAN
ADDRESS WORD DAC CODE OR DAC SPAN
24-BIT DATA STREAM
2704 F02a
SLEEP
STATUS
SPAN
Figure 2a. 24-Bit Load Sequence
12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0C300000000
CS/LD
SCK
SDI
CONTROL WORD ADDRESS WORD DAC CODE OR DAC SPAN
32-BIT DATA STREAM
0 0 0 0 0 0 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0000000000
SRO
t2
t3t4
t1
t8
D15
17
SCK
SDI
SRO D14D15
18
D14
8 ZEROS
Hi-Z
Hi-Z
READBACK CODE
2704 F02b
0000 00 00000 0000000SLPS3S2S1S0000000000
SRO
READBACK SPAN
SLEEP
STATUS
SPAN
Figure 2b. 32-Bit Load Sequence
15
LTC2704
2704f
OPERATIO
U
Examples
1. Using a 24-bit loading sequence, load DAC A with the
unipolar range of 0V to 10V, output at zero volts and all
other DACs with the bipolar range of ±10V, outputs at
zero volts. Note all DAC outputs should change at the
same time.
a) CS/LD↓
b) Clock SDI = 0010 1111 0000 0000 0000 0011
c) CS/LD↑
B1-Range of all DACs set to bipolar ±10V.
d) CS/LD↓
Clock SDI = 0010 0000 0000 0000 0000 0001
e) CS/LD↑
B1-Range of DAC A set to unipolar 0V to 10V.
f) CS/LD↓
Clock SDI = 0011 1111 1000 0000 0000 0000
g) CS/LD↑
B1-Code of all DACs set to midscale.
h) CS/LD↓
Clock SDI = 0011 0000 0000 0000 0000 0000
i) CS/LD↑
B1-Code of DAC A set to zero code.
j) CS/LD↓
Clock SDI = 0100 1111 XXXX XXXX XXXX XXXX
k) CS/LD↑
Update all DACs B1s into B2s for both Code and
Range.
l) Alternatively steps j and k could be replaced with
LDAC .
2. Using a 32-bit load sequence, load DAC C with bipolar
±2.5V and its output at zero volts. Use readback to
check B1 contents before updating the DAC output (i.e.,
before copying B1 contents into B2).
a) CS/LD↓ (Note that after power-on, the Code in B1 is
zero)
b) Clock SDI = 0000 0000 0011 0100 1000 0000 0000
0000
c) CS/LD↑
B1-Code of DAC C set to midscale setting.
d) CS/LD↓
Clock SDI = 0000 0000 0010 0100 0000 0000 0000
0100
e) Read Data out on SRO = 1000 0000 0000 0000
Verifies that B1-Code DAC C is at midscale setting.
f) CS/LD↑
B1-Range of DAC C set to Bipolar ±2.5V range.
g) CS/LD↓
Clock SDI = 0000 0000 1010 0100 xxxx xxxx xxxx
xxxx
Data Out on SRO = 0000 0000 0000 0100
Verifies that B1-Range of DAC C set to Bipolar ±2.5V
Range.
CS/LD↑
h) CS/LD↓
Clock SDI = 0000 0000 0100 0100 xxxx xxxx xxxx
xxxx
i) CS/LD↑
Update DAC C B1 into B2 for both Code and Range
j) Alternatively steps h and i could be replaced with
LDAC .
16
LTC2704
2704f
System Offset Adjustment
Many systems require compensation for overall system
offset, which may be an order of magnitude or more
greater than the excellent offset of the LTC2704.
The LTC2704 has individual offset adjust pins for each of
the four DACs. VOSA, VOSB, VOSC and VOSD are referred
to their corresponding signal grounds, AGNDA, AGNDB,
AGNDC and AGNDD. For noise immunity and ease of
adjustment, the control voltage is attenuated to the DAC
output:
V
OS
= –0.01 • V(VOSx) [0V to 5V, ±2.5V spans]
V
OS
= –0.02 • V(VOSx) [0V to 10V, ±5V,
–2.5V to 7.5V spans]
V
OS
= –0.04 • V(VOSx) [±10V span]
The nominal input range of these pins is ±5V; other
reference voltages of up to ±15V may be used if needed.
The VOSx pins have an input impedance of 1MΩ. To
preserve the settling performance of the LTC2704, these
pins should be driven with a Thevenin-equivalent imped-
ance of 10kΩ or less. If not used, they should be shorted
to their respective signal grounds, AGNDx.
POWER-ON RESET AND CLEAR
When power is first applied to the LTC2704, all DACs
power-up in 5V unipolar mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
are zero volts.
When the CLR pin is taken low, a system clear results. The
command and address shift registers, and the code and
configuration B2 buffers, are reset to 0; the DAC outputs
are all reset to zero volts. The B1 buffers are left intact, so
that any subsequent “Update B1→B2” command (includ-
ing the use of LDAC) restores the addressed DACs to their
respective previous states.
If CLR is asserted during an operation, i.e., when CS/LD is
low, the operation is aborted. Integrity of the relevant input
(B1) buffers is not guaranteed under these conditions,
therefore the contents should be checked using readback
or replaced.
The RFLAG pin is used as a flag to notify the system of a
loss of data integrity. The RFLAG output is asserted low at
power-up, system clear, or if the logic supply V
DD
dips
below approximately 2V; and stays asserted until any valid
update command is executed.
SLEEP MODE
When a sleep command (C3 C2 C1 C0 = 1110) is issued,
the addressed DAC or DACs go into power-down mode.
DACs A and B share a reference inverting amplifier as do
DACs C and D. If either DAC A or DAC B (similarly for DACs
C and D) is powered down, its shared reference inverting
amplifier remains powered on. When both DAC A and
DAC B are powered down together, their shared reference
inverting amplifier is also powered down (similarly for
DACs C and D). To determine the sleep status of a
particular DAC, a direct read span command is performed
by addressing the DAC and reading its status on the
readback pin SRO. The fifth LSB is the sleep status bit (see
Figures 2a and 2b). Table 4 shows the sleep status bit’s
functionality.
Table 4. Readback Sleep Status Bit
SLP STATUS
0 DAC n Awake
1 DAC n in Sleep Mode
OPERATIO
U
17
LTC2704
2704f
APPLICATIO S I FOR ATIO
WUUU
Overview
The LTC2704 is a highly integrated device, greatly simpli-
fying design and layout as compared to a design using
multiple current output DACs and separate amplifiers. A
similar design using four separate current output DACs
would require six precision op amps, compensation ca-
pacitors, bypass capacitors for each amplifier, several
times as much PCB area and a more complicated serial
interface. Still, it is important to avoid some common
mistakes in order to achieve full performance. DC752A is
the evaluation board for the LTC2704. It is designed to
meet all data sheet specifications, and to allow the LTC2704
to be integrated into other prototype circuitry. All force/
sense lines are available to allow the addition of current
booster stages or other output circuits.
The DC752A design is presented as a tutorial on properly
applying the LTC2704. This board shows how to properly
return digital and analog ground currents, and how to
compensate for small differences in ground potential
between the two banks of two DACs. There are other ways
to ground the LTC2704, but the one requirement is that
analog and digital grounds be connected at the LTC2704
by a very low impedance path. It is NOT advisable to split
the ground plane and connect them with a jumper or
inductor. When in doubt, use a single solid ground plane
rather than separate planes.
The LTC2704 does allow the ground potential of the DACs
to vary by ±300mV with respect to analog ground, allow-
ing compensation for ground return resistance.
Power Supply Grounding and Noise
LTC2704 V
+
and V
–
pins are the supplies to all of the output
amplifiers, ground sense amplifiers and reference inver-
sion amplifiers. These amplifiers have good power supply
rejection, but the V
+
and V
–
supplies must be free from
wideband noise. The best scheme is to prefilter low noise
regulators such as the LT
®
1761 (positive) and LT1964
(negative). Refer to Linear Technology Application Note
101, Minimizing Switching Regulator Residue in Linear
Regulator Outputs.
The LTC2704 V
DD
pin is the supply for the digital logic and
analog DAC switches and is very sensitive to noise. It must
be treated as an analog supply. The evaluation board uses
an LT1790 precision reference as the V
DD
supply to mini-
mize noise.
The GND pin is the return for digital currents and the AGND
pin is a bias point for internal analog circuitry. Both of these
pins must be tied to the same point on a quiet ground plane.
Each DAC has a separate ground sense pin that can be
used to compensate for small differences in ground poten-
tial within a system. Since DACs A and B are associated
with REF1 and DACs C and D are associated with REF2, the
grounds must be grouped together as follows:
AGNDA, AGNDB and REFG1 tied together (“GND1” on
DC752A)
AGNDC, AGNDD and REFG2 tied together (“GND2” on
DC752A)
This scheme allows compensation for ground return IR
drops, as long as the resistance is shared by both DACs in
a group. This implies that the ground return for DACs A
and B must be as close as possible, and GND1 must be
connected to this point through a low current, low resis-
tance trace. (Similar for DACs C and D.)
Figure 3 shows the top layer of the evaluation board. The
GND1 trace connects REFG1, AGNDA, AGNDB and the
ground pin of the LT1236 precision reference (U4.) This
point is the ground reference for DACs A and B. The GND2
trace connects REFG2, AGNDC, AGNDD and the ground
pin of the other LT1236 precision reference (U5). This
point is the ground reference for DACs C and D.
Voltage Reference
A high quality, low noise reference such as the LT1236 or
LT1027 must be used to achieve full performance. The
ground terminal of this reference must be connected
directly to the common ground point. If GND1 and GND2
are separate, then two references must be used.
18
LTC2704
2704f
APPLICATIO S I FOR ATIO
WUUU
Voltage Output/Feedback and Compensation
The LTC2704 provides separate voltage output and feed-
back pins for each DAC. This allows compensation for
resistance between the output and load, or a current
boosting stage such as an LT1970 may be inserted with-
out affecting accuracy. When OUTx is connected directly
GND1 TRACE,
SEPARATED FROM
AGND UNDER LTC2704
EXPOSED GROUND PLANE AROUND EDGE
ALLOWS GROUNDING TO PROTOTYPE CIRCUITS
2704 F03
GND2 TRACE,
SEPARATED FROM
AGND UNDER LTC2704
CUTOUT PREVENTS DIGITAL RETURN CURRENTS
FROM COUPLING INTO ANALOG GROUND PLANE. NOTE
THAT THERE IS A PLANE IN THIS REGION ON LAYER 3
2704 F04
DIGITAL RETURN CURRENTS
FLOW IN THIS REGION
2704 F05
V
OUTA
AND V
OUTB
LOAD
RETURN CURRENTS FLOW
IN THIS REGION WHEN
JP8 IS SET TO “TIE”
V
OUTC
AND V
OUTD
LOAD
RETURN CURRENTS FLOW
IN THIS REGION WHEN
JP9 IS SET TO “TIE”
POWER AND LOAD RETURN
CURRENTS FLOW IN THIS REGION
SMALL GROUND POUR ALLOWS
LOW IMPEDANCE BYPASSING
OF V+ AND V–
2704 F06
Figure 3. DC752 Top Layer
Figure 4. DC752 Analog Ground Layer. No Currents are Returned
to this Plane, so it May be Used as a Reference Point for Precise
Voltage Measurements
Figure 5. DC752A Load Return, Power Return and Digital Return
Figure 6. DC752A Routing, Bypass
to RFBx and no additional capacitance is present, the
internal frequency compensation is sufficient for stability
and is optimized for fast settling time. If a low bandwidth
booster stage is used, then a compensation capacitor
from OUTx to C1x may be required. Similarly, extra com-
pensation may be required to drive a heavy capacitive load.
19
LTC2704
2704f
U
PACKAGE DESCRIPTIO
GW Package
44-Lead Plastic SSOP (Wide .300 Inch)
(Reference LTC DWG # 05-08-1642)
G44 SSOP 0204
0° – 8° TYP
0.355
REF
0.231 – 0.3175
(.0091 – .0125)
0.40 – 1.27
(.015 – .050)
7.417 – 7.595**
(.292 – .299)
× 45°
0.254 – 0.406
(.010 – .016)
2.286 – 2.388
(.090 – .094)
0.1 – 0.3
(.004 – .0118)
2.44 – 2.64
(.096 – .104)
0.800
(.0315)
BSC
0.28 – 0.51
(.011 – .02)
TYP
17.73 – 17.93*
(.698 – .706)
1 2 3 4 5 6 7 8 9 101112131415161718192021
10.11 – 10.55
(.398 – .415)
22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.152mm (0.006") PER SIDE
*
DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE
**
MILLIMETERS
(INCHES)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
2. DIMENSIONS ARE IN
10.804 MIN
RECOMMENDED SOLDER PAD LAYOUT
7.75 – 8.258
2344
221
0.800 BSC0.520 ±0.0635
1.40 ±0.127
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20
LTC2704
2704f
© LINEAR TECHNOLOGY CORPORATION 2006
LT/LWI 0806 • PRINTED IN THE USA
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
PART NUMBER DESCRIPTION COMMENTS
LT®1019 Precision Reference Ultralow Drift, 3ppm/°C, 0.05% Accuracy
LT1236 Precision Reference Ultralow Drift, 10ppm/°C, 0.05% Accuracy
LTC1588/LTC1589 12-/14-/16-Bit, Serial, SoftSpan I
OUT
DACs Software-Selectable Spans, ±1LSB INL/DNL
LTC1592
LTC1595 16-Bit Serial Multiplying I
OUT
DAC in SO-8 ±1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade
LTC1596 16-Bit Serial Multiplying I
OUT
DAC ±1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade
LTC1597 16-Bit Parallel, Multiplying DAC ±1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors
LTC1650 16-Bit Serial V
OUT
DAC Low Power, Low Gritch, 4-Quadrant Multiplication
LTC1857/LTC1858 12-/14-/16-Bit, Serial 100ksps SoftSpan ADC Software-Selectable Spans, 40mW, Fault Protected to ±25V
LTC1859
LT1970 500mA Power Op Amp Adjustable Sink/Source Current Limits
TYPICAL APPLICATIO
U
Evaluation Board Schematic. Force/Sense Lines Allow for Remote Sensing and Optimal Grounding
LDAC
CS/LD
SDI
SRO
SCK
CLR
RFLAG
REFG1
REF1
REFM1
REFG2
REF2
REFM2
VDD
GND
AGND
CS/LD
SDI
SRO
SCK
VOSA
C1A
RFBA
OUTA
AGNDA
VOSB
C1B
RFBB
OUTB
AGNDB
VOSC
C1C
RFBC
OUTC
AGNDC
VOSD
C1D
RFBD
OUTD
AGNDD
9
10
11
12
13
14
35
4
5
7
6
3
40
39
37
38
41
27
28
30
29
26
19
18
16
17
20
2
43
44
21
24
23
14
33
32
V+1
25 42 1,8,15,22,31,36
V+2V–
LTC2704
LDAC VOSA
VOSB
GND1
GND1
GND2
OUTA
1
2
3
BAV99LT1
BAV99LT1
BAV99LT1
TIE
REMOTE
OUTSA
OUTA
OUTSB
OUTB
OUTSC
OUTC
10k
VDD
10k
VDD
VDD
VDD
BAT54S
0.1µF
1µF
1µF
15V –15V
1µF1µF
CLR
REFM1
GND1
GND2
REFM2
SPI
INTERFACE
RFLAG
1k
VDD
1
2
3
1
2
3
1
2
3
VDD
5VREGULATOR
REF
REF2
REF1
REMOTE
VOSx
5V
REMOTE
5V 5VREF2
5VREF1
1
12
12
VS
24.7µF0.1µF
7V
15V
12
3
VIN
64 VOUT
LT1790ACS6-5
GND GND
VOSC
OUTB
TIE
REMOTE
OUTC
TIE
REMOTE
1
2
3
1
2
3
GND2
BAV99LT1
OUTSD
OUTD
VOSD
OUTD
TIE
REMOTE
1
2
3
GND2
TIE
REMOTE
BAT54S
GND2
1
2
3
3
21
GND1
TIE
REMOTE
BAT54S
GND1
1
2
3
3
21
VIN
6
5
4
2VOUT
TRIM
LT1236ACS8-5
GND
0.1µF4.7µF
GND1
VS5VREF1
15V
15V
–15V
–15V
4.7µF
25V
4.7µF
25V
VIN
6
5
4
2VOUT
TRIM
LT1236ACS8-5
GND
0.1µF4.7µF
GND2
VS5VREF2
REFx
OFFSET ADJUSTMENT
FOR VOSA, VOSB,
VOSC, VOSC
20k
REFMx
