MB86276 'LIME' Graphics Display Controller Specifications Revision 1.1a 17th May, 2010 Copyright (c) FUJITSU SEMICONDUCTOR LIMITED 2005-2010 ALL RIGHTS RESERVED FUJITSU SEMICONDUCTOR CONFIDENTIAL Notes The specifications in this manual are subject to change without notice. Contact our Sales Department before purchasing the product described in this manual. Information and circuit diagrams in this manual are only examples of device applications, they are not intended to be used in actual equipment. Also, Fujitsu accepts no responsibility for infringement of patents or other rights owned by third parties caused by use of the information and circuit diagrams. The contents of this manual must not be reprinted or duplicated without permission of Fujitsu. Fujitsu's semiconductor devices are intended for standard uses (such as office equipment (computers and OA equipment), industrial/communications/measuring equipment, and personal/home equipment). Customers using semiconductor devices for special applications (including aerospace, nuclear, military and medical applications) in which a failure or malfunction might endanger life or limb and which require extremely high reliability must contact our Sales Department first. If damage is caused by such use of our semiconductor devices without first consulting our Sales Department, Fujitsu will not assume any responsibility for the loss. Semiconductor devices fail with a known probability. Customers must use safety design (such as redundant design, fireproof design, over-current prevention design, and malfunction prevention design) so that failures will not cause accidents, injury or death). If the products described in this manual fall within the goods or technologies regulated by the Foreign Exchange and Foreign Trade Law, permission must be obtained before exporting the goods or technologies. CAUTION Burns There is a danger of burns because the IC surface is heated depending on the IC operating conditions. In this case, take safety measures. All Rights Reserved * The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering. * The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information. * Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. * The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). MB86276 'LIME' GDC Specifications Rev1.1a 1 FUJITSU SEMICONDUCTOR CONFIDENTIAL Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. * Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. * Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws. * The company names and brand names herein are the trademarks or registered trademarks of their respective owners. MB86276 'LIME' GDC Specifications Rev1.1a 2 FUJITSU SEMICONDUCTOR CONFIDENTIAL Revision history Date Version Page count Change 2005.2.10 0.1 176 First edition 2005.3.12 0.2 225 The description of Video Capture is added. 2005.6.15 0.92 237 The pin list and the description of modeis are added. 2005.7.14 0.93b 278 DC, AC characteristics are added. The description of Memory Map, Dual Monitor, and the capacity of SDRAM are updated. The table of the pin multiplex is updated. Other update. 2005.8.17 0.93c 278 The description of the unimplemented functions, the geometry registers and the analog RGB output, were deleted. 2005.9.19 0.93d 278 Misprint correction. 2005.10.17 0.94 282 P.14 The pin list of thermal balls is added. P.15-16 Several pins are renamed to "TESTH" or "TESTL". P.26 "TESTL" is added in the table of test pins. P.30 RDY_MODE, ENDIAN signals are added. P.31 The table of GMODE is updated. P.249 The lost character is displayed. 2006.1.18 0.95 281 P.18-19 The description "TOP VIEW" is inserted in Pin diagram. P.28 The description was doubled about RDY_MODE and BS_MODE is deleted. P.29-30 P.31 "Connection to CPU" is updated. The paragraph "Graphics memory interface" is moved from Chapter 3. P.64 The table of "Resolution and Display Frequency" is updated. P.150-151 The LOWD field of MMR register is updated. Other: Misprint correction. 2006.1.27 0.96 297 P.10 Connectable Memoey configuration is updated. P.21 The description of the symbol regarding VDD/GND is added. P.30 The connection between CPU and Lime is updated. P.31 The pin information of serial host interface is added. P.66 Connection with memory is updated. P.81 Chapter 6.8 in previous version is removed. P.153 The description of CCF register is added. P.160 The description of I2C I/F register is added. P.291 The note about AC timing specification of Host I/F is added. Other: Misprint correction. MB86276 'LIME' GDC Specifications Rev1.1a 3 FUJITSU SEMICONDUCTOR CONFIDENTIAL Date Version Page count 2006.2.14 0.97 327 2006.3.30 0.97a Change P.23 The description "TESTL" is updated. P.47 The protocol for general call address is updated. P.47 Misprint about Acknowledge in the protocol for SCI are corrected. P.51 Line transfer of SCI is updated. P.52 The description of I2C interface was added at ver.0.96. P.138 SCI register list is added. P.160 The description of SCI registers are added. P.177 DCM,DCE,DCEE registers are changed to DCM0/1/2/3 registers. P.279 Timing chart of Host interface for SH3/4, V832, SPARClite are added. P.295 Timing chart of Host interface for 16bit CPU, 16bit AD-MUX CPU, 32bit AD-MUX CPU are added. Other: Misprint correction. 2006.6.5 1.0 P.28 Note of XRDY signal is updated. P.33 Connection of XWE1 signal is updated. P.47 Description of 16-bit CPU mode is added. P.161 Host register descriptions are added, DMA_ST_ADR, DMA_ED_ADR, ERR_ADR, ERR_DETECT, INT_MSK. P.172 Add Revision Register :PIO Base + 0x84 P.316 Video Capture AC Timing Hold 2ns => 0ns P.321 Clear the meaning of tr,tf 2010.3.20 1.1 Remove spec of I2C slave Add explanations and revise typos. 2010.5.17 1.1a Clear the setting of reserverd area MB86276 'LIME' GDC Specifications Rev1.1a 4 FUJITSU SEMICONDUCTOR CONFIDENTIAL Contents 1 1.1 GENERAL...........................................................................................................11 Features...................................................................................................................................11 1.2 Functional Overview.............................................................................................................. 12 1.2.1 Host CPU interface ........................................................................................................... 12 1.2.2 External memory interface............................................................................................... 13 1.2.3 Display controller.............................................................................................................. 14 1.2.4 2D Drawing ....................................................................................................................... 16 1.2.5 Special effects .................................................................................................................... 18 2 PINS................................................................................................................... 21 2.1 Pin assignment diagram........................................................................................................ 21 2.2 Pin assignment table ............................................................................................................. 23 2.3 Pin mutiplex table.................................................................................................................. 25 2.4 Host CPU interface ................................................................................................................ 29 2.4.1 Ready signal mode ............................................................................................................ 31 2.4.2 BS signal mode.................................................................................................................. 32 2.4.3 Endian................................................................................................................................ 32 2.4.4 Note about the connection to CPU................................................................................... 33 2.5 Graphics memory interface ................................................................................................... 37 2.6 Video output interface............................................................................................................ 38 2.7 Video capture interface .......................................................................................................... 39 2.8 I2C interface ........................................................................................................................... 40 2.9 GPIO interface ....................................................................................................................... 40 2.10 General purpose mode pins ................................................................................................... 40 2.11 Clock input ............................................................................................................................. 41 2.12 Test pins ................................................................................................................................. 42 2.13 Reset sequence ....................................................................................................................... 42 2.14 How to switch internal operating frequency......................................................................... 42 3 PROCEDURE OF THE HARDWARE INITIALIZATION..................................... 43 3.1 Hardware reset ...................................................................................................................... 43 3.2 Re-reset................................................................................................................................... 43 3.3 Software reset ........................................................................................................................ 43 MB86276 'LIME' GDC Specifications Rev1.1a 5 FUJITSU SEMICONDUCTOR CONFIDENTIAL 4 HOST INTERFACE ............................................................................................ 44 4.1 Access Mode ........................................................................................................................... 45 4.1.1 SRAM interface ................................................................................................................. 45 4.1.2 FIFO interface (fixed transfer destination address)....................................................... 45 4.2 DMA Transfer......................................................................................................................... 46 4.2.1 Data transfer unit ............................................................................................................. 46 4.2.2 Address mode .................................................................................................................... 46 4.2.3 Bus mode ........................................................................................................................... 47 4.2.4 DMA transfer request ....................................................................................................... 47 4.2.5 Ending DMA transfer ....................................................................................................... 47 4.3 Transfer of Local Display List ............................................................................................... 48 4.4 Interrupt................................................................................................................................. 49 4.4.1 Address Error Interrupt ................................................................................................... 49 4.5 SH3 Mode ............................................................................................................................... 49 4.6 Wait ........................................................................................................................................ 49 4.7 16-bit CPU mode .................................................................................................................... 49 5 5.1 I2C INTERFACE CONTROLLER ....................................................................... 51 Features.................................................................................................................................. 51 5.2 Block diagram ........................................................................................................................ 52 5.2.1 Block Diagram................................................................................................................... 52 5.2.2 Block Function Overview.................................................................................................. 53 5.3 Example application .............................................................................................................. 54 5.3.1 Connection Diagram ......................................................................................................... 54 5.3.2 START condition ............................................................................................................... 55 5.3.3 STOP condition ................................................................................................................. 55 5.3.4 Addressing ......................................................................................................................... 56 5.3.5 Synchronization of SCL .................................................................................................... 56 5.3.6 Arbitration......................................................................................................................... 57 5.3.7 Acknowledge...................................................................................................................... 57 5.3.8 Bus error............................................................................................................................ 57 5.3.9 Initialize............................................................................................................................. 58 5.3.10 1-byte transfer from master to slave ............................................................................... 59 5.3.11 1-byte transfer from slave to master ............................................................................... 60 5.3.12 Recovery from bus error ................................................................................................... 61 5.4 6 Note ........................................................................................................................................ 62 GRAPHICS MEMORY ....................................................................................... 63 6.1 Configuration ......................................................................................................................... 63 6.1.1 Data type ........................................................................................................................... 63 6.1.2 Memory Mapping .............................................................................................................. 64 6.1.3 Data Format ...................................................................................................................... 66 6.2 Frame Management............................................................................................................... 67 6.2.1 Single Buffer...................................................................................................................... 67 6.2.2 Double Buffer .................................................................................................................... 67 MB86276 'LIME' GDC Specifications Rev1.1a 6 FUJITSU SEMICONDUCTOR CONFIDENTIAL 6.3 Memory Access ....................................................................................................................... 67 6.3.1 Priority of memory accessing ........................................................................................... 67 6.4 Connection with memory ....................................................................................................... 68 6.4.1 Connection with memory.................................................................................................. 68 7 7.1 DISPLAY CONTROLLER .................................................................................. 69 Overview................................................................................................................................. 69 7.2 Display Function .................................................................................................................... 70 7.2.1 Layer configuration........................................................................................................... 70 7.2.2 Overlay............................................................................................................................... 71 7.2.3 Display parameters........................................................................................................... 73 7.2.4 Display position control .................................................................................................... 74 7.3 Display Color.......................................................................................................................... 76 7.4 Cursor ..................................................................................................................................... 77 7.4.1 Cursor display function .................................................................................................... 77 7.4.2 Cursor control.................................................................................................................... 77 7.5 Display Scan Control ............................................................................................................. 78 7.5.1 Applicable display ............................................................................................................. 78 7.5.2 Interlace display................................................................................................................ 79 7.6 The external synchronous signal........................................................................................... 80 7.7 An example of the external synchronization circuit ............................................................. 80 7.8 Programmable YCbCr/RGB conversion for L1-layer display ............................................... 83 7.9 DCLKO shift .......................................................................................................................... 85 7.10 Syncronous register update of display .................................................................................. 85 7.11 Dual Display........................................................................................................................... 86 7.11.1 Overview ............................................................................................................................ 86 7.11.2 Destination Control........................................................................................................... 86 7.11.3 Output Signal Control ...................................................................................................... 87 7.11.4 Output Circuit Example ................................................................................................... 88 7.11.5 Display Clock and Timing ............................................................................................... 90 7.11.6 Limitation.......................................................................................................................... 90 8 VIDEO CAPTURE.............................................................................................. 91 8.1 Video Capture function .......................................................................................................... 91 8.1.1 Input data Formats........................................................................................................... 91 8.1.2 Capturing of Video Signal ................................................................................................ 91 8.1.3 Non-interlace Transformation.......................................................................................... 91 8.2 Video Buffer............................................................................................................................ 92 8.2.1 Data Form ......................................................................................................................... 92 8.2.2 Synchronous Control......................................................................................................... 92 8.2.3 Area Allocation .................................................................................................................. 92 8.2.4 Window Display ................................................................................................................ 93 8.2.5 Interlace Display............................................................................................................... 93 8.2.6 RGB555 Mode.................................................................................................................... 93 MB86276 'LIME' GDC Specifications Rev1.1a 7 FUJITSU SEMICONDUCTOR CONFIDENTIAL 8.3 Scaling .................................................................................................................................... 94 8.3.1 Down-scaling Function ..................................................................................................... 94 8.3.2 Up-scaling Function.......................................................................................................... 94 8.3.3 Flow of image processing.................................................................................................. 96 8.4 External video signal input conditions.................................................................................. 99 8.4.1 RTB656 YUV422 input format......................................................................................... 99 8.4.2 RGB input format ........................................................................................................... 101 8.5 9 Input Video Signal Parameter Setup .................................................................................. 106 DRAWING PROCESSING ............................................................................... 107 9.1 Coordinate System ............................................................................................................... 107 9.1.1 Drawing coordinates ....................................................................................................... 107 9.1.2 Texture coordinates......................................................................................................... 108 9.1.3 Frame buffer.................................................................................................................... 108 9.2 Figure Drawing .................................................................................................................... 109 9.2.1 Drawing primitives ......................................................................................................... 109 9.2.2 Polygon drawing function............................................................................................... 109 9.2.3 Drawing parameters ....................................................................................................... 110 9.2.4 Anti-aliasing function ......................................................................................................111 9.3 Bit Map Processing ...............................................................................................................112 9.3.1 BLT................................................................................................................................... 112 9.3.2 Pattern data format ........................................................................................................ 112 9.4 Texture Mapping ...................................................................................................................113 9.4.1 Texture size...................................................................................................................... 113 9.4.2 Texture color .................................................................................................................... 113 9.4.3 Texture Wrapping ........................................................................................................... 113 9.4.4 Filtering ........................................................................................................................... 114 9.4.5 8.4.5 Texture blending .................................................................................................... 114 9.5 Rendering ..............................................................................................................................115 9.5.1 Tiling................................................................................................................................ 115 9.5.2 Alpha blending ................................................................................................................ 115 9.5.3 Logic operation ................................................................................................................ 116 9.5.4 Hidden plane management (Optional function) ........................................................... 116 9.6 Drawing Attributes ...............................................................................................................117 9.6.1 Line drawing attributes.................................................................................................. 117 9.6.2 Triangle drawing attributes ........................................................................................... 117 9.6.3 Texture attributes ........................................................................................................... 118 9.6.4 BLT attributes................................................................................................................. 118 9.6.5 Character pattern drawing attributes........................................................................... 118 10 DISPLAY LIST ...............................................................................................119 10.1 Overview................................................................................................................................119 10.1.1 Header format ................................................................................................................. 120 10.2 Rendering Command ........................................................................................................... 121 10.2.1 Command list .................................................................................................................. 121 10.2.2 Details of rendering commands ..................................................................................... 125 11 GDC REGISTER MAP .................................................................................. 135 MB86276 'LIME' GDC Specifications Rev1.1a 8 FUJITSU SEMICONDUCTOR CONFIDENTIAL 11.1 Local memory register list ................................................................................................... 136 11.1.1 Host interface register list.............................................................................................. 136 11.1.2 I2C interface register list ................................................................................................ 138 11.1.3 GPIO register list............................................................................................................ 139 11.1.4 Graphics memory interface register list........................................................................ 139 11.1.5 Display controller register list ....................................................................................... 140 11.1.6 Video capture register list .............................................................................................. 146 11.1.7 Drawing engine register list........................................................................................... 148 12 EXPLANATION OF GDC REGISTERS ........................................................ 154 12.1 Host interface registers........................................................................................................ 155 12.1.1 GPIO control registers .................................................................................................... 162 12.1.2 Peripheral Interrupt related registers........................................................................... 164 12.1.3 I2C Interface Registers.................................................................................................... 168 12.2 Graphics memory interface registers .................................................................................. 174 12.3 Display control registers...................................................................................................... 177 12.4 Video capture registers ........................................................................................................ 232 12.5 Drawing registers................................................................................................................. 248 12.5.1 Drawing control registers ............................................................................................... 248 12.5.2 Drawing mode registers.................................................................................................. 251 12.5.3 Triangle drawing registers ............................................................................................. 266 12.5.4 Line drawing registers.................................................................................................... 269 12.5.5 Pixel drawing registers................................................................................................... 270 12.5.6 Rectangle drawing registers........................................................................................... 270 12.5.7 Blt registers ..................................................................................................................... 271 12.5.8 2D line with XY setup drawing registers ...................................................................... 272 12.5.9 2D triangle with XY setup drawing registers ............................................................... 273 12.5.10 Display list FIFO registers ......................................................................................... 274 13 TIMING DIAGRAM ....................................................................................... 275 13.1 Graphics Memory Interface ................................................................................................. 275 13.1.1 Timing of read access to same row address................................................................... 275 13.1.2 Timing of read access to different row addresses ......................................................... 276 13.1.3 Timing of write access to same row address ................................................................. 277 13.1.4 Timing of write access to different row addresses ........................................................ 278 13.1.5 Timing of read/write access to same row address ......................................................... 279 13.1.6 Delay between ACTV commands ................................................................................... 280 13.1.7 Delay between Refresh command and next ACTV command ...................................... 280 13.2 Display Timing ..................................................................................................................... 281 13.2.1 Non-interlace mode ......................................................................................................... 281 13.2.2 Interlace video mode ....................................................................................................... 282 13.2.3 Composite synchronous signal ....................................................................................... 283 13.3 Host interface Timing .......................................................................................................... 284 13.3.1 CPU read/write timing diagram in SH3 mode (Normally Not Ready Mode).............. 284 13.3.2 CPU read/write timing diagram in SH3 mode (Normally Ready Mode) ..................... 285 13.3.3 CPU read/write timing diagram in SH4 mode (Normally Not Ready Mode).............. 286 13.3.4 CPU read/write timing diagram in SH4 mode (Normally Ready Mode) ..................... 287 13.3.5 CPU read/write timing diagram in V832 mode (Normally Not Ready Mode) ............ 288 13.3.6 CPU read/write timing diagram in V832 mode (Normally Ready Mode).................... 289 13.3.7 CPU read/write timing diagram in SPARClite (Normally Not Ready Mode) ............. 290 MB86276 'LIME' GDC Specifications Rev1.1a 9 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.8 CPU read/write timing diagram in SPARClite (Normally Ready Mode) .................... 291 13.3.9 SH4 single-address DMA write (transfer of 1 long word) ............................................ 292 13.3.10 SH4 single-address DMA write (transfer of 8 long words) ....................................... 293 13.3.11 SH3/4 dual-address DMA (transfer of 1 long word) .................................................. 294 13.3.12 SH3/4 dual-address DMA (transfer of 8 long words) ................................................ 294 13.3.13 V832 DMA transfer ..................................................................................................... 295 13.3.14 SH4 single-address DMA transfer end timing .......................................................... 296 13.3.15 SH3/4 dual-address DMA transfer end timing.......................................................... 296 13.3.16 V832 DMA transfer end timing .................................................................................. 297 13.3.17 SH4 dual DMA write without ACK ............................................................................ 298 13.3.18 Dual-address DMA (without ACK) end timing.......................................................... 299 13.3.19 CPU write timing diagram in 16bit CPU mode (Normally Not Ready Mode) ........ 300 13.3.20 CPU read timing diagram in 16bit CPU mode (Normally Not Ready Mode) ......... 301 13.3.21 CPU write timing diagram in 16bit AD-MUX CPU mode (Normally Not Ready Mode) ....................................................................................... 302 13.3.22 CPU read timing diagram in 16bit AD-MUX CPU mode (Normally Not Ready Mode) ....................................................................................... 303 13.3.23 CPU write timing diagram in 32bit AD-MUX CPU mode (Normally Not Ready Mode) ....................................................................................... 304 13.3.24 CPU read timing diagram in 32bit AD-MUX CPU mode (Normally Not Ready Mode) ....................................................................................... 305 14 ELECTRICAL CHARACTERISTICS ............................................................ 306 14.1 Introduction.......................................................................................................................... 306 14.2 Maximum Rating ................................................................................................................. 306 14.3 Recommended Operating Conditions .................................................................................. 307 14.3.1 Recommended operating conditions .............................................................................. 307 14.3.2 Note at power-on ............................................................................................................. 308 14.4 DC Characteristics............................................................................................................... 309 14.4.1 DC Characteristics.......................................................................................................... 309 14.4.2 V-I characteristics diagram ............................................................................................ 310 14.5 AC Characteristics ................................................................................................................311 14.5.1 Host interface .................................................................................................................. 311 14.5.2 I2C Interface .................................................................................................................... 313 14.5.3 Video interface................................................................................................................. 314 14.5.4 Video capture interface ................................................................................................... 316 14.5.5 Graphics memory interface ............................................................................................ 316 14.5.6 PLL specifications ........................................................................................................... 320 14.6 AC Characteristics Measuring Conditions.......................................................................... 321 14.7 Timing Diagram ................................................................................................................... 322 14.7.1 Host interface .................................................................................................................. 322 14.7.2 Video interface................................................................................................................. 327 14.7.3 Video capture interface ................................................................................................... 329 14.7.4 Graphics memory interface ............................................................................................ 330 MB86276 'LIME' GDC Specifications Rev1.1a 10 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1 GENERAL 1.1 Features CMOS 0.18m technology Internal and memory frequency : 133MHz (generated by on-chip PLL) Base-clock for display clocks : 400.9MHz (generated by on-chip PLL) Display resolutions typically from 320x240 up to 1280x768 6 layers of overlay display (windows) Alpha Plane and constant alpha value for each layer Digital Video input (various formats including YUV,RGB) Video Scaler (up/down scaling) Brightness, Contrast, Saturation control for video input RGB digital output (8bit x 3) Built-in alpha blending, anti-aliasing and chroma-keying Rendering Engine for various kinds of 2D graphic acceleration functions Texture Mapping Unit for 2D polygon support up to 4096x4096 textures Bit-Blt Unit for transfers up to 4096x4096 areas Alpha Bit-Blt and ROP2 functions External 32-bit SDRAM interface for up to 64MB graphic memory Parallel host interface (FR,SH3,SH4,V850,SparcLite etc) New additional serial control interface as host interface (I2C based) Internal and external DMA support I2C interface and GPIO inputs/outputs Supply voltage 3.3V (I/O), 1.8V (Internal) BGA-320 Package (1.27mm pitch) Typical power consumption < 1.0W (estimated) Temperature range -40..+85 C MB86276 'LIME' GDC Specifications Rev1.1a 11 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1.2 Functional Overview 1.2.1 Host CPU interface Supported CPU LIME can be connected to SH3 and SH4 manufactured by RENESAS, V832 by NEC, CPU with address and data multiplex bus like PowerPC by Freescale, FR and SPARClite (MB86833) by Fujitsu. External Bus Clock Can be connected at max. 66 MHz (when using SH4 interface) Ready Mode Supports normal ready/not ready. Endian Supports little endian. Big endian is also available in 16bit mode. Access Mode SRAM interface FIFO interface (transfer destination address fixed) DMA transfer Supports 1-double word (32 bits) /8-double word (32 bytes) (only SH4) for transfer unit. ACK used/unused mode can be selected as protocol (only for DAM in dual address mode) Supports dual address/mode single address mode (only SH4). Supports cycle steel/burst. Supports local display list transfer. Interrupt Vertical (frame) synchronous detection Field synchronous detection External synchronous error detection Drawing command error Drawing command execution end MB86276 'LIME' GDC Specifications Rev1.1a 12 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1.2.2 External memory interface LIME can connect SDRAM that data bus width is 32 bits. Max. 133 MHz is available for operating frequency. Connectable memory configuration is as shown below. External Memory Configuration Type Data bus width Use count Total capacity SDRAM 64 Mbits (x32 Bits) 32 Bits 1 8 Mbytes SDRAM 64 Mbits (x16 Bits) 32 Bits 2 16 Mbytes SDRAM 128 Mbits (x32 Bits) 32 Bits 1 16 Mbytes SDRAM 128 Mbits (x16 Bits) 32 Bits 2 32 Mbytes SDRAM 256 Mbits (x32 Bits) 32 Bits 1 32 Mbytes SDRAM 256 Mbits (x16 Bits) 32 Bits 2 64 Mbytes SDRAM 512 Mbits (x32 Bits) 32 Bits 1 64 Mbytes Please note that EMRS of SDRAM is not supported by LIME. MB86276 'LIME' GDC Specifications Rev1.1a 13 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1.2.3 Display controller Video data output Only digital RGB video output is provided. Screen resolution LCD panels with wide range of resolutions are supported by using a programmable timing generator as follows: Screen Resolutions Resolutions 1280 x 768 1024 x 768 1024 x 600 800 x 600 854 x 480 640 x 480 480 x 234 400 x 234 320 x 234 Note: These resolutions are mentioned for the sake of giving examples. In practice, any resolution corresponding to a pixel clock value of up to 80MHz can be supported. Note that higher resolution increases memory bandwidth consumption. Hardware cursor The LIME GDC supports two hardware cursor functions. Each of these hardware cursors is specified as a 64 x 64-pixel area. Each pixel of these hardware cursors is 8 bits and uses the same look-up table as indirect color mode. Double buffer method Double buffer method in which drawing window and display window is switched in units of 1 frame enables the smooth animation. Flipping (switching of display window area) is performed in synchronization with the vertical blanking period using program. Scroll method Independent setting of drawing and display windows and their starting position enables the smooth scrolling. Display colors Supports indirect color mode which uses the look-up table (color palette) in 8 bits/pixels. Entry for look-up table (color palette) corresponds to color code for 8 bits, in other words, 256. Color data is each 6 bits of RGB. Consequently, 256 colors can be displayed out of 260,000 colors. Supports direct color mode which specifies RGB with 16 bits/pixels. Supports direct color mode which specifies RGB with 24 bits/pixels. Note: Rendering is not supported in 24bpp color mode. The host CPU will have to write directly to the memory buffer in this color mode. MB86276 'LIME' GDC Specifications Rev1.1a 14 FUJITSU SEMICONDUCTOR CONFIDENTIAL Overlay Traditional compatibility mode Up to four extra layers (C, W, M and B) can be displayed overlaid. The overlay position for the hardware cursors is above/below the top layer (C). The transparent mode or the blend mode can be selected for overlay. The M- and B-layers can be split into separate windows. Window display can be performed for the W-layer. Two palettes are provided: C-layer and M-/B-layer. The W-layer is used as the video input layer. L0, L2, L4 (0,0) L3, L5 (HDB+1, 0) L1 (WX, WY) Window mode * Up to six screens (L0 to 5) can be displayed overlaid. * The overlay sequence of the L0- to L5-layers can be changed arbitrarily. * The overlay position for the hardware cursors is above/below the L0-layer. * The transparent mode or the blend mode can be selected for overlay. * The L5-layer can be used as the blend coefficient plane (8 bits/pixel). * Window display can be performed for all layers. * Four palettes corresponded to L0 to 3 are provided. * The L1-layer is used as the video input layer. * Background color display is supported in window display for all layers. L0 (L0WX, L0WY) L4 (L4WX, L4WY) L2 (L2WX, L2WY) L1 (L1WX, L1WY) L5 (L5WX, L5WY) L3 (L3WX, L3WY) MB86276 'LIME' GDC Specifications Rev1.1a 15 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1.2.4 2D Drawing 2D Primitives The LIME GDC can perform 2D drawing for graphics memory (drawing plane) in direct color mode or indirect color mode. Bold lines with width and broken lines can be drawn. With anti-aliasing smooth diagonal lines also can be drawn. A triangle can be tiled in a single color or 2D pattern (tiling), or mapped with a texture pattern by specifying coordinates of the 2D pattern at each vertex (texture mapping). At texture mapping, drawing/non-drawing can be set in pixel units. Moreover, transparent processing can be performed using alpha blending. When drawing in single color or tiling without Gouraud shading or texture mapping, 2D Line with XY setup and 2D Triangle with XY setup can be used. Only vertex coordinates are set for these primitives. 2D Triangle with XY setup is also used to draw polygons. 2D Primitives Primitive type Point Line Triangle 2D Line with XY setup 2D Triangle with XY setup Arbitrary polygon Description Plots point Draws line Draws triangle Draws lines Compared to line, this reduces the host CPU processing load. Draws ltriangles Compared to tiangle, this reduces the host CPU processing load. Draws arbitrary closed polygon containing concave shapes consisting of vertices Arbitrary polygon drawing Using this function, arbitrary closed polygon containing concave shapes consisting of vertices can be drawn. (There is no restriction on the count of vertices, however, the polygon with its sides crossed are not supported.) In this case, as a work area for drawing, polygon drawing flag buffer is used on the graphics memory. In drawing polygon, draw triangle for polygon drawing flag buffer using 2D Triangle with XY setup. Decide any vertex as a starting point to draw triangle along the periphery. It enables you to draw final polygon form in single color or with tiling. MB86276 'LIME' GDC Specifications Rev1.1a 16 FUJITSU SEMICONDUCTOR CONFIDENTIAL BLT/Rectangle drawing This function draws a rectangle using logic operations. It is used to draw pattern and copy the image pattern within the drawing frame. It is also used for clearing drawing frame and Z buffer. BLT Attributes Attribute Raster operation Transparent processing Alpha blending Description Selects two source logical operation mode Performs BLT without drawing pixel consistent with the transparent color. The alpha map and source in the memory is subjected to alpha blending and then copied to the destination. Pattern (Text) drawing This function draws a binary pattern (text) in a specified color. Pattern (Text) Drawing Attributes Attribute Enlarge Shrink Description Vertically x 2 Horizontally x 2 Vertically and Horizontally x 2 Vertically x 1/2 Horizontally 1/2 Vertically and Horizontally 1/2 Drawing clipping This function sets a rectangle frame in drawing frame to prohibit the drawing of the outside the frame. Hidden plane management (Optional function) LIME GDC supports the Z buffer for hidden plane management as a optional function. MB86276 'LIME' GDC Specifications Rev1.1a 17 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1.2.5 Special effects Anti-aliasing Anti-aliasing manipulates line borders of polygons in sub-pixel units and blend the pre-drawing pixel color with color to make the jaggies be seen smooth. It is used as a functional option for 2D drawing (in direct color mode only). Bold line and broken line drawing This function draws lines of a specific width and a broken line. Line Drawing Attributes Attribute Line width Broken line Description Selectable from 1 to 32 pixels Set by 32 bit or 24 bit of broken line pattern Not support the Anti-aliasing of dashed line patterns. MB86276 'LIME' GDC Specifications Rev1.1a 18 FUJITSU SEMICONDUCTOR CONFIDENTIAL Alpha blending Alpha blending blends two image colors to provide a transparent effect. LIME GDC supports two types of blending; blending two different colors at drawing, and blending overlay planes at display. Transparent color is not used for these blending options. Set a transparent coefficient to the register; the transparent coefficient is applied for transparency processing of one plane. In addition to the above, the following settings can be performed at texture mapping. When the most significant bit of each texture cell is 1, drawing or transparency can be set. When the most significant bit of each texture cell is 0, non-drawing can be set. Alpha Blending Type Description Drawing Transparent ratio set in particular register While one primitive (polygon, pattern, etc.), being drawn, registered transparent ratio applied Overlay display Blends top layer pixel color with lower layer pixel color Transparent coefficient set in particular register Registered transparent coefficient applied during one frame scan Gouraud Shading Gouraud shading can be used in the direct color mode to provide real shading and color gradation. MB86276 'LIME' GDC Specifications Rev1.1a 19 FUJITSU SEMICONDUCTOR CONFIDENTIAL Texture mapping LIME GDC supports texture mapping to map an image pattern onto the surface of plane. The texture pattern can be laid out in the graphics memory. In this case, max. 4096 x 4096 pixels can be used. Drawing of 8-/16- direct color is supported for the texture pattern. For drawing 8-bit direct color, only point sampling can be specified for texture interpolation; only de-curl can be specified for the blend mode. Texture Mapping Function Filtering Coordinates correction Blend Alpha blend Wrap Description Point sample Bi-linear filter Linear De-curl Modulate Stencil Normal Stencil Stencil alpha Repeat Clamp Border MB86276 'LIME' GDC Specifications Rev1.1a 20 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2 Pins 2.1 Pin assignment diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VSS VINF VINVS BI0 BI3 GI0 GI3 RI0 RI3 BO4 BO0 GO4 GO0 RO5 RO2 DCLKO VSS DCLKIVSYNC VSS RGBCK VSS VINHS BI1 BI4 GI1 GI4 RI1 RI4 BO5 BO1 GO5 GO1 RO6 RO3 RO0 HSYNCCSYNC VSS GMOD0 XPLLT XTST VSS BI5 GI2 GI5 RI2 RI5 BO6 BO2 GO6 GO2 RO7 RO4 RO1 DISP VSS GMOD1GMOD2 XSM SCL BI2 GV D31 D30 MD0 MD1 MD2 VDDE VDDE D29 D28 D27 MD3 MD4 MD5 VDDE VDDE D26 D25 D24 MD6 MD7 MD8 VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VDDI D23 D22 D21 MD9 MD10 MD11 VDDE VDDI VSS VSS VSS VSS VSS VSS VSS VDDE D20 D19 D18 MD12 MD13 MD14 VDDE VDDI VSS VSS VSS VSS VSS VSS VSS VDDE D17 D16 D15 MD15 MD16 MD17 MD18 VDDI VSS VSS VSS VSS VSS VSS VSS VDDE D14 D13 D12 MD19 MD20 MD21 VDDE VDDI VSS VSS VSS VSS VSS VSS VSS D10 D9 D8 MD22 MD23 MD24 VDDE VDDI VSS VSS VSS VSS VSS VSS VSS VDDE D7 D6 D5 MD25 MD26 MD27 VDDE VDDI VSS VSS VSS VSS VSS VSS VSS VDDE D4 D3 D2 MD28 MD29 MD30 VDDI VDDI VDDI VDDI VDDI VDDI VSS VSS VSS VDDI D0 DRACK MD31MDQM0MDQM1VDDE MCLKIMDQM2MDQM3VDDE SDA VSS VDDE VDDE VDDI VDDE VDDE BO7 BO3 GO7 GO3 VDDI VDDE VDDE VSS D11 TOP VIEW VDDEDTACKXWE3 XWE2 VDDE XWE1 XWE0 A23 VSS MA0 MA1 VSS VDDE VDDE VDDI PLLVSPLLVDMODE0 XINT VDDE VDDE VDDI VDDE VDDE VSS MCLKO MA2 VSS MA9 MA12 MRAS CLKS0 XRST CLKS1 BS_M XRDY XRD S RDY_MMODE2 XCS A21 A20 A4 A7 A10 A13 VSS A19 A18 A0 A3 A6 A9 A12 A15 VSS A17 A2 A5 A8 A11 A14 A16 VSS MA3 VSS MA6 MA8 MA11 MA14 MWE CKM VSS MA4 MA5 MA7 MA10 MA13 MCAS CLK VPD BCLKIMODE1DREQ XBS 21 A22 A1 MB86276 'LIME' GDC Specifications Rev1.1a D1 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 2 77 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 57 3 78 145 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 127 56 4 79 146 205 256 255 254 253 252 251 250 249 248 247 246 245 244 189 126 55 5 80 147 206 243 188 125 54 6 81 148 207 242 187 124 53 7 82 149 208 257 284 283 282 281 280 279 278 241 186 123 52 8 83 150 209 258 285 304 303 302 301 300 277 240 185 122 51 9 84 151 210 259 286 305 316 315 314 299 276 239 184 121 50 10 85 152 211 260 287 306 317 320 313 298 275 238 183 120 49 11 86 153 212 261 288 307 318 319 312 297 274 237 182 119 48 12 87 154 213 262 289 308 309 310 311 296 273 236 181 118 47 13 88 155 214 263 290 291 292 293 294 295 272 235 180 117 46 14 89 156 215 264 265 266 267 268 269 270 271 234 179 116 45 15 90 157 216 233 178 115 44 16 91 158 217 232 177 114 43 17 92 159 218 219 220 221 222 223 224 225 226 227 228 229 230 231 176 113 42 18 93 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 112 41 19 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 40 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 TOP VIEW MB86276 'LIME' GDC Specifications Rev1.1a 22 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.2 Pin assignment table Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 JEDEC Number 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 19 18 17 16 15 14 Name VSS RGBCK XPLLT XSM MD0 MD3 MD6 MD9 MD12 MD15 MD19 MD22 MD25 MD28 MD31 MCLKI VSS MCLKO MA3 VSS MA4 MA5 MA7 MA10 MA13 MCAS CLK VSS BCLKI MODE1 DREQ XBS A2 A5 A8 A11 A14 A16 VSS A17 A18 A20 A23 XWE2 DRACK D2 D5 D8 D12 D15 D18 D21 D24 D27 D30 GMOD2 GMOD0 VSS VSYNC DCLKI VSS DCLKO RO2 RO5 Pin Number 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 JEDEC Name Number GO0 13 GO4 12 BO0 11 BO4 10 9 RI3 8 RI0 7 GI3 6 GI0 5 BI3 4 BI0 3 VINVS 2 VINF 2 VSS 2 XTST 2 SCL 2 MD1 2 MD4 2 MD7 2 MD10 2 MD13 2 MD16 2 MD20 2 MD23 2 MD26 2 MD29 2 MDQM0 2 MDQM2 2 MA0 2 MA2 2 VSS 3 MA6 4 MA8 5 MA11 6 MA14 7 MWE 8 CKM 9 S 10 RDY_M 11 MODE2 XCS 12 A0 13 A3 14 A6 15 A9 16 A12 17 A15 18 VSS 19 A19 19 A21 19 19 XWE0 19 XWE3 D0 19 D3 19 D6 19 D9 19 D13 19 D16 19 D19 19 D22 19 D25 19 D28 19 D31 19 19 GMOD1 VSS 19 MB86276 'LIME' GDC Specifications Rev1.1a 23 Pin Number 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 JEDEC Name Number 18 CSYNC 17 HSYNC RO0 16 RO3 15 RO6 14 GO1 13 GO5 12 BO1 11 BO5 10 9 RI4 8 RI1 7 GI4 6 GI1 5 BI4 4 BI1 3 VINHS 3 VSS 3 SDA 3 MD2 3 MD5 3 MD8 3 MD11 3 MD14 3 MD17 3 MD21 3 MD24 3 MD27 3 MD30 3 MDQM1 3 MDQM3 3 MA1 3 VSS 4 MA9 5 MA12 6 MRAS 7 CLKS0 8 XRST 9 CLKS1 BS_M 10 11 XRDY XRD 12 A1 13 A4 14 A7 15 A10 16 A13 17 VSS 18 A22 18 18 XWE1 18 DTACK D1 18 D4 18 D7 18 D10 18 D14 18 D17 18 D20 18 D23 18 D26 18 D29 18 GV 18 VSS 18 DISP 17 RO1 16 Pin Number 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 JEDEC Number 15 14 13 12 11 10 9 8 7 6 5 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 6 7 8 9 10 11 12 13 14 15 16 17 17 17 17 17 17 17 17 17 17 17 17 17 17 16 15 14 13 12 11 10 9 8 7 6 5 Name RO4 RO7 GO2 GO6 BO2 BO6 RI5 RI2 GI5 GI2 BI5 BI2 VSS VDDE VDDE VDDI VDDE VDDE MD18 VDDE VDDE VDDE VDDI VDDE VDDE VSS VDDE VDDE VDDI PLLVS PLLVD MODE0 XINT VDDE VDDE VDDI VDDE VDDE VSS VDDE VDDE VDDI VDDE VDDE D11 VDDE VDDE VDDE VDDI VDDE VDDE VSS VDDE VDDE VDDI GO3 GO7 BO3 BO7 VDDE VDDE VDDI VDDE VDDE FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin Number 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 JEDEC Number G 7 H 7 J 7 K 7 L 7 M 7 N 7 P 7 P 8 P 9 P 10 P 11 P 12 P 13 P 14 N 14 M 14 L 14 K 14 J 14 H 14 G 14 G 13 G 12 G 11 G 10 G 9 G 8 H 8 J 8 K 8 L 8 M 8 N 8 N 9 N 10 N 11 N 12 N 13 M 13 L 13 K 13 J 13 H 13 H 12 H 11 H 10 H 9 J 9 K 9 L 9 M 9 M 10 M 11 M 12 L 12 K 12 J 12 J 11 J 10 K 10 L 10 L 11 K 11 Name VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VDDI VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Group Symbol description GND group: VSS/PLLVSS/Low Ground TESTL Connect Ground. VDDL/VDDI 1.8-V power supply PLLVDD PLL power supply (1.8 V) VDDH/VDDE 3.3-V power supply TESTH Input a 3.3 V-power supply 1.8V group: 3.3V group: MB86276 'LIME' GDC Specifications Rev1.1a 24 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.3 Pin mutiplex table MB86276 'LIME' GDC Specifications Rev1.1a 25 FUJITSU SEMICONDUCTOR CONFIDENTIAL MB86276 'LIME' GDC Specifications Rev1.1a 26 FUJITSU SEMICONDUCTOR CONFIDENTIAL MB86276 'LIME' GDC Specifications Rev1.1a 27 FUJITSU SEMICONDUCTOR CONFIDENTIAL MB86276 'LIME' GDC Specifications Rev1.1a 28 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.4 Host CPU interface 1) Parallel interface mode Table 2-1 Host CPU Interface Pins Pin name I/O Description MODE0-2 Input Host CPU mode select RDY_MODE Input Normally ready, Not ready select BS_MODE Input BS signal with/without select XRST Input Hardware reset ("L"=Reset, Set to low level when power-on) D0-31 In/Out Host CPU bus data A0-A23 Input Host CPU bus address (In the V832 mode, A[24] is connected to XMWR.) BCLKI Input Host CPU bus clock XBS Input Bus cycle start signal XCS Input Chip select signal XRD Input Read strobe signal XWE0 Input Write strobe for D0 to D7 signal XWE1 Input Write strobe for D8 to D15 signal XWE2 Input Write strobe for D16 to D23 signal XWE3 Write strobe for D24 to D31 signal XRDY Input Output Tri-state *(1) DREQ Output DMA request signal (This signal is low-active in both the SH mode and V832 mode.) DRACK/DMAAK Input Acknowledge signal in response to DMA request (DMAAK is used in the V832 mode; this signal is high-active in both the SH mode and V832 mode.) DTACK/XTC Input DMA transfer strobe signal (XTC is used in the V832 mode. In the SH mode, this signal is high-active; in the V832 mode, it is low-active.) XINT Output Interrupt signal issued to host CPU (In the SH mode, and SPARClite this signal is low-active; in the V832 mode, it is high-active) Wait request signal (In the SH3 mode, when this signal is "0", it indicates the wait state; in the SH4, V832 and SPARClite modes, when this signal is "1", it indicates the wait state.) With regard to BCLKI and XRST, the details, please refer "14.3.2 Note at power-on". *(1) Tri-state output of XRDY is valid in SH3, SH4, V832, and SPARClite. In 16-bit SRAM I/F, 16-bit AD I/F, and 32-bit AD I/F, it drives "High" or "Low". When more than two devices are connected to 16-bit SRAM I/F, 16-bit AD I/F, and 32-bit AD I/F, insert the tri-state buffer between XRDY of LIME and the CPU. Refer to the following note. Case 1: If there is no peripheral device to drive the hardware wait and it is possible for the CPU to ignore the XRDY signal in other than from Lime, then it is not necessary to account for this problem. Simply connect the XRDY of Lime to the XRDY of the CPU. MB86276 'LIME' GDC Specifications Rev1.1a 29 FUJITSU SEMICONDUCTOR CONFIDENTIAL Case 2: If the condition is other than the above, put the tri-state buffer between Lime's XRDY and CPU's XRDY as shown below. CPU Lime XCSx XCS XCSn Pullup/down Peripheral device XCS MB86276 'LIME' GDC Specifications Rev1.1a 30 FUJITSU SEMICONDUCTOR CONFIDENTIAL LIME can be connected to the Renesas SH4 (SH7750), SH3 (SH7709) NEC V832 and Fujitsu SPARClite (MB86833) without external circuit. In the SRAM interface mode, LIME can be used with any other CPU as well. The host CPU is specified by the MODE0 to 2 pins. MODE 2 MODE 1 MODE 0 CPU L L L SH3 L L H SH4 L H L V832 L H H SPARClite H L L General-purpose interface H L H General-porpose 16bit CPU with address and data multiplex interface H H L General-purpose 32bit CPU with address and data multiplex interface H H H Reserved 2.4.1 16bit CPU with SRAM Ready signal mode The MODE2 pin can be used to set the ready signal level when the bus cycle of the host CPU terminates. For the normally not ready mode, set the software wait to 0 or 1 cycles. When using this device in the normally ready mode, set the software wait to 2 cycles. When using this device in the normally not ready mode, set the software wait to one cycle. (When BS_MODE = H, three cycles are needed for the software wait.) The `normally not ready mode' is the mode in which the LIME XRDY signal is always in the wait state and Ready is returned only when read/write is ready. The `normal ready mode' is the mode in which the LIME XRDY signal is always in the Ready state and it is put into the wait state only when read/write cannot be performed immediately. Ready Signal Mode RDY_MODE L H Ready signal operation Recognizes XRDY signal as `not ready level' and terminates bus cycle (normally not ready mode) Recognizes XRDY signal as `ready level' and terminates bus cycle (normally ready mode) RDYSW is for an active signal level on 16bit SRAM I/F, 16bit A/D multiplexed I/F, and 32bit A/D multiplexed I/F modes. High active or low active can be selected. Active level of ready signal for 16bit CPU and A/D multiplexed CPU RDYSW L H RDYSW signal operation Recognizes XRDY signal as `not ready level' and terminates bus cycle (normally not ready mode) Recognizes XRDY signal as `ready level' and terminates bus cycle (normally ready mode) MB86276 'LIME' GDC Specifications Rev1.1a 31 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.4.2 BS signal mode Connection to a CPU without the BS signal can be made via the BS_MODE signal. This setting can be performed for all CPU modes. To connect to a CPU without the BS signal, set the BS_MODE signal to "High" level. When not using the BS signal, fix the BS pin of LIME at "High" level. When using the BS_MODE signal as "High" level, with the normally ready mode established, set the CPU software wait to three cycles. BS Signal Mode BS_MODE L H 2.4.3 Operation of BS signal Connects to CPU with BS signal Connects to CPU without BS signal Endian LIME has bi-endian mode for a halfword ordering of 16bit CPU. ENDIAN signal is for 16bit SRAM I/F and 16bit A/D multiplexed I/F modes.The half word ordering of Lime can be selected from either little or big. In the case of CPUs with the byte swapping, please note it. LIME operates in little-endian mode. All the register address descriptions in the specifications are byte address in little endian. When using a big-endian CPU, note that the byte-or word-addresses are different from these descriptions. Endian Mode for 16-bit CPU ENDIAN L H Operation of BS signal Little endian for the halfword ordering Big endian for the halfword ordering MB86276 'LIME' GDC Specifications Rev1.1a 32 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.4.4 Note about the connection to CPU The data signal is 32 bits (fixed). The address signal is 32 bits (per one double-word) x 24, and has a 64-Mbyte address field. (16MByte address space is provided for V832 and SPARClite.) The external bus operating frequency is up to 66 MHz. In the SH4, V832, and SPARClite modes, when the XRDY signal is low, it is in the ready state. However, in the SH3 mode, when the XRDY signal is low, it is in the wait state. This signal is a tristate output that is synchronized with the rising edge of BCLKI. DMA data transfer is supported using an external DMA controller. An interrupt signal is generated to the host CPU. The XRST input must be kept low for at least 300 s after setting the S (PLL reset) signal to high. In the V832 mode, LIME signals are connected to the V832 CPU as follows: LIME Pins A24 DTACK DRACK MB86276 'LIME' GDC Specifications Rev1.1a V832 Signals XMWR XTC DMAAK 33 FUJITSU SEMICONDUCTOR CONFIDENTIAL How to connect between Lime and CPUs is shown as the following table. Pin name In/Out SH4(SH7750) SH3(SH7709) V832 V832 BCLKI I CKIO CKIO CLKOUT CLKOUT A3-A0 I A5-A2 A5-A2 A5-A2 A5-A2 A11-A4 I A13-A6 A13-A6 A13-A6 A13-A6 A19-A12 I A21-A14 A21-A14 A21-A14 A21-A14 A21-A20 I A23-A22 A23-A22 A23-A22 A22 I A24 A24 - - A23 I A25 A25 - - XCS I A23-A22 CSn CSn CSn CSn D15-0 IO D15-D0 D15-D0 D15-D0 D15-D0 D31-16 IO D31-D16 D31-D16 D31-D16 D31-D16 RD RD IORD/MRD IORD/MRD WEn WEn IOWR/xxBEN/MWR IOWR/xxBEN/MWR XRD I XWE0 I XWE1 I XWE2 I XWE3 I XBS I BS BS BCYST BCYST XRDY O RDY WAIT READY READY DREQ O DREQ DREQ DMARQ DMARQ DRACK I DRAK DRAK DMAAK DMAAK DTACK I DACK DACK TC TC XINT O MODE0-2 I RDY_MODE I BS_MODE I MB86276 'LIME' GDC Specifications Rev1.1a 34 FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin name BCLKI A3-A0 A11-A4 A19-A12 A21-A20 A22 A23 XCS D15-0 D31-16 XRD XWE0 XWE1 XWE2 XWE3 XBS XRDY DREQ DRACK DTACK XINT MODE0-2 RDY_MODE BS_MODE In/Out MB90F334 I I I I I I I I IO IO I I I I I I O O I I O I I I MB86276 'LIME' GDC Specifications Rev1.1a MB91F46x (16-bit) MB90F37x SYSCLK A04-A01 A12-A05 A20-A13 A22-A21 A23 CSnX D31-D16 IORDX IOWRX ASX RDY - 35 MB91F46x (32-bit) SYSCLK A04-A01 A12-A05 A20-A13 A22-A21 A23 CSnX D31-D16 IORDX IOWRX ASX RDY - FUJITSU SEMICONDUCTOR CONFIDENTIAL Pin name BCLKI A0 A8-A1 A15-A9 A20-A16 A23-A21 XCS D7-D0 D15-D8 XRD XWE0 XWE1 XWE2 XWE3 XBS XRDY DREQ DRACK DTACK XINT MODE0 MODE1 MODE2 RDY_MODE BS_MODE ENDIAN RDTSW In/Out I I I I I I I IO IO I I I I I I O O I I O I I I I I I I MB90F38x 16-bit non-MUX CLK Open P11_7-P11_0 P12_6-P12_0 P03_3-P03_0 P08_6-P08_4 CS3 P00_7-P00_0 P02_7-P02_0 RDX WRLX WRHX ALE / ASX RDY GND GND VCC GND GND GND VCC Notes: Not supported: ARM7 MPC5200 M16C MB86276 'LIME' GDC Specifications Rev1.1a 36 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.5 Graphics memory interface Graphics memory interface pins Pin name I/O Description MD31 - MD0 I/O Graphics memory bus data MA14 - MA0 Output Graphics memory bus data MRAS Output Row address strobe MCAS Output Column address strobe MWE Output Write enable DQM3 - DQM0 Output Data mask MCLKI Input Graphics memory clock input MCLKO Output Graphics memory clock output Connect the interface to the external memory used as memory for image data. The interface can be connected to 64-/128-/256-Mbit SDRAM (16- or 32-bit length data bus) without using any external circuit. Connect MCLKI to MCLK0. Connect XCS of SDRAM to GND. Connect CKE of SDRAM to VCC 3V3. Important: The length of each PCB trace connecting Lime's MCLKI and MCLKO pins and SDRAM's CLK pin together should be the same. Please note that there could be just one piece of SDRAM used. The recommendation should be followed in that case as well. Please see below for a graphical description. Also, take note of the AC spec of graphics memory interface. Lime The length of each PCB trace connecting Lime's MCLKI and MCLKO pins and SDRAM's CLK pin together should be the same. Please note that there could be just one piece of SDRAM used. The recommendation should be followed in that case as well. MB86276 'LIME' GDC Specifications Rev1.1a 37 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.6 Video output interface Video Output Interface Pins Pin name DCKI DISPE DCLKI DCLKO HSYN I/O Input Output Input Output I/O VSYN I/O CSYN GV Output Output Description Dot clock signal input Display Enable Display Clock Input Display Clock Output Horizontal sync signal output Horizontal sync input <in external sync mode> Vertical sync signal output Vertical sync input <in external sync mode> Composite sync signal output Graphics/video switch Additional setting of external circuits can generate composite video signal. Synchronous to external video signal display can be performed. Either mode which is synchronous to DCLKI signal or one which is synchronous to dot clock, as for normal display can be selected. Since HSYNC and VSYNC signals are set to input state after reset, these signals must be pulled up LSI externally. The GV signal switches graphics and video at chroma key operation. When video is selected, the "Low" level is output. MB86276 'LIME' GDC Specifications Rev1.1a 38 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.7 Video capture interface 1) ITU-656 Input Signals Table 2-3 Video Capture Interface Pins Pin name I/O (CCLK) Input VIN7-0 Input VINFID Input Description Digital video input clock signal input This pin is multiplexed RGBCLK. Please see RGBCLK. ITU656 Digital video data input. These pins are multiplexed MD63MD56. Field Input (Pullup/Pulldown) Inputs ITU-RBT-656 format digital video signal 2)RGB Input Signals The signals used for video capture are not assigned on dedicated pins but share the same pins with other functions. There is a set of signals corresponding to the RGB capture modes. There is a possibility of sharing these pins with other pins. (TBD) Direct Input Mode Pin name I/O RGBCLK Input Description Clock for RGB input. This pin is multiplexed CCLK. RI5-0 Input Red component value. GI5-0 Input Green component value. BI5-0 Input Blue component value. VINSYNC Input Vertical sync for RGB capture. HINSYNC Input Horizontal sync for RGB capture. Note : - the RGB bit of VCM(video capture mode) register enables RGB input mode of video capture. MB86276 'LIME' GDC Specifications Rev1.1a 39 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.8 I2C interface Pin name I/O Description 2 SDA I/O I C serial data line. SCL I/O I2C serial clock line. Note) Input voltage level is 3.3V. Please be careful, it does not support to 5V input. (The device whose output voltage is 5V is not connectable.) 2.9 GPIO interface Pin name I/O Description GPIO4-0 I/O General-purpose IO pin. A direct value is controlled and read by the inside register. Moreover, interruption can be generated with the value of a pin. These pins are pull-up in the chip. 2.10 General purpose mode pins GMODE 2 GMODE 1 GMODE 0 PIN Multiplex Host Interface Primary RGB output Secondary RGB output Video Capture GPIO L L L 32bit CPU RGB888 -- Native RGB666 -- L L H 32bit CPU RGB888 -- RBT656/601 GPIO[4:0] L H L 16bit CPU RGB888 RGB666 RBT656/601 GPIO[2:0] L H H 16bit CPU RGB666 RGB666 H L L Reserved Reserved Reserved Reserved Reserved H L H Reserved Reserved Reserved Reserved Reserved H H L Reserved Reserved Reserved Reserved Reserved H H H Reserved Reserved Reserved Reserved Reserved MB86276 'LIME' GDC Specifications Rev1.1a 40 Native RGB666 -- FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.11 Clock input Pin name I/O Description CLK Input Clock input signal S Input PLL reset signal CKM Input Clock mode signal CLKSEL [1:0] Input Clock rate select signal Inputs source clock for internal operation clock and display dot clock. Normally, 4 Fsc (= 14.31818 MHz: NTSC) is input. An internal PLL generates the internal operation clock of 133 MHz/100 MHz and the display base clock of 400 MHz. Even if don't use an internal PLL (use BCLKI as internal clock and use DCLKI as dot clock), don't stop the PLL (Not fixed the S pin to low level). CKM Clock mode L Output from internal PLL selected H BLCKI clock selected When CKM = L, selects input clock frequency when built-in PLL used according to setting of CSL pins CSL1 Input clock frequency CSL0 Multiplication rate Display reference clock L L Inputs 13.5-MHz clock frequency x 29 391.5 MHz L H Inputs 14.32-MHz clock frequency x 28 400.96 MHz H L Inputs 17.73-MHz clock frequency x 22 390.06 MHz H H Inputs 33.33-MHz clock frequency x 12 399.96 Please connect the crystal oscillator directly with the terminal CLK. CLK value to -1% of it is supported. MB86276 'LIME' GDC Specifications Rev1.1a 41 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2.12 Test pins Table 2-5 Test Pins Pin name 2.13 I/O Description TESTL Input Input 0-V power. TESTH Input Input 3.3-V power. Reset sequence See 14.3.2 Note at power-on. 2.14 How to switch internal operating frequency Switch the operating frequency immediately after a reset (before rewriting MMR mode register of external memory interface). Any operating frequency can be selected from the combinations shown in Table 2-6. Table 2-6 Frequency Setting Combinations Clock for Rendering Engine and Memory interface 133 MHz 100 MHz MB86276 'LIME' GDC Specifications Rev1.1a 42 FUJITSU SEMICONDUCTOR CONFIDENTIAL 3 PROCEDURE OF THE HARDWARE INITIALIZATION 3.1 Hardware reset 1.Do the hardware reset. 2.After the hardware reset, set the CCF(Change of Frequency) register (section 12.1 Host interface registers). In being unstable cycle after the hardware reset, keep 32 bus cycles open. 3.Set the graphics memory interface register, MMR (Memory I/F Mode Register). After setting the CCF register, take 200 us to set the MMR register. In being unstable memory access cycle, keep 32 bus cycles open. 4.Other registers, except for the CCF register and the MMR register, should be set after setting the CCF register. In case of not using memory access, the MMR register could be set in any order after the CCF register is set. 3.2 Re-reset 1. Reset XRST signal. 2. See section x.x for registers setting after the procedure of re-reset. 3.3 Software reset 1. Set the value of the SRST register for re-reset. 2. It is not necessary to reset the CCF register and the MMR register again. MB86276 'LIME' GDC Specifications Rev1.1a 43 FUJITSU SEMICONDUCTOR CONFIDENTIAL 4 HOST INTERFACE Select the host CPU by setting the MODE0 to MODE2 signals as follows: Table 4-1 CPU Type Setting MODE 2 MODE 1 MODE 0 CPU L L L SH3 L L H SH4 L H L V832 L H H SPARClite H L L General 16bit CPU with SRAM interface H L H General 16bit CPU with address and data multiplex interface H H L General 32bit CPU with address and data multiplex interface H H H Reserved MB86276 'LIME' GDC Specifications Rev1.1a 44 FUJITSU SEMICONDUCTOR CONFIDENTIAL 4.1 Access Mode 4.1.1 SRAM interface Data can be transferred to/from LIME using SRAM access protocol. LIME internal registers and graphics memory are all mapped to the physical address area of the host processor. LIME uses hardware wait based on the XRDY signal, enabling the hardware wait setting of the host CPU. When using the normally not ready mode, set the software wait to "1". When using the normally ready mode, set the software wait to "2". (When using the BS_MODE signal as "High" level, with the normally ready mode established, set the CPU software wait to three cycles.) Switch the ready mode using the RDY_MODE signal. CPU Read The host processor reads data from internal registers and memory of LIME in double-word (32 bit) units. Valid data is output continuously while XRD and XCS are being asserted at a "Low" level after XRDY has been asserted. CPU Write The host CPU writes data to internal registers and memory of LIME in byte, word(16 bit) and doubleword( 32 bit) units. 4.1.2 FIFO interface (fixed transfer destination address) This interface transfers display lists stored in host memory. Display list information is transferred efficiently using a single address mode DMA transfer. Data can be transferred to FIFO in relation to FIFO buffer area mapped in memory area using SRAM interface or dual address mode. MB86276 'LIME' GDC Specifications Rev1.1a 45 FUJITSU SEMICONDUCTOR CONFIDENTIAL 4.2 DMA Transfer 4.2.1 Data transfer unit DMA transfer is performed in double-word (32 bits) units or 8 double-word (32 bytes) units. Byte and word access is not supported. Note: 8 double-word transfer is supported only in the SH4 mode. 4.2.2 Address mode Dual address mode (mode using ACK) DMA is performed at memory-to-memory transfer between host memory and registers mapped in memory space or graphics memory (destination). Both the host memory address and LIME is used. In the SH4 mode, the 1 double-word transfer (32 bits) and 8 double-word transfer (32 bytes) can be used. When the CPU transfer destination address is fixed, data can also be transferred to the FIFO interface. However, in this case, even the SH4 mode supports only the 1 double-word transfer. DREQ and DRACK pins and SRAM interface signals are used. In V832, the DREQ, DMAAK, and XTC pins and SRAM interface signals are used. Note: The SH3 mode supports the direct address mode; it does not support the indirect address mode. Dual address mode (mode not using ACK) When not using the ACK signal with the dual address mode established, set bit3 at HostBase+0004h (DNA: Dual address No Ack mode) to 1. When the ACK is not used, the DREQ signal is in the edge mode and the DREQ signal is negated per transfer and then reasserted it in the next cycle. If processing cannot be performed immediately inside LIME, the DREQ signal remains negated. The transfer count register (DTC) of LIME is not used, so in order to end DMA transfer, write "1" to the DMA transfer stop register (DTS) from the CPU. Note 1: In the dual DMA mode (mode without ACK), the destination address can be used only for the FIFO. In DMA transfer to the graphics memory, etc., use the dual DMA mode. Note 2: DMA read is not supported. Single address mode (FIFO interface) Data is transferred between host memory (source) and FIFO (destination). Only the address output from the host memory is used, and the data is transferred to the FIFO. This mode does not support data write to the host memory. When the FIFO is full, the DMA transfer is suspended. The 1 double-word transfer (32 bits) and the 8 double-word transfer (32 B) can be used. DREQ, DTACK, and DRACK signal are used. Note: The single-address mode is supported only in the SH4 mode. MB86276 'LIME' GDC Specifications Rev1.1a 46 FUJITSU SEMICONDUCTOR CONFIDENTIAL 4.2.3 Bus mode LIME supports the DMA transfer cycle steal mode and burst mode according to setting of external DMA mode. Cycle steal mode (In the V832 mode, the burst mode is called the single transfer mode.) In the cycle steal mode, the right to use the bus is obtained or released at every data transfer of 1 unit. The DMA transfer unit can be selected from between the 1 double-word (32 bits) and 8 double-words (32 B). Burst mode (In the V832 mode, the burst mode is called the demand transfer mode.) When DMA transfer is started, the right to use the bus is acquired and the transfer begins. The data transfer unit can be selected from between 1 double-word (32 bits) and 8 double-words. Note: When performing DMA transfer in the dual-address mode, a function for automatically negating DREQ is provided based on the setting of the DBMbit in DSU register. 4.2.4 DMA transfer request Single-address mode DMA is started when the LIME issues an external request to DMAC of the host processor. Set the transfer count in the transfer count register of the LIME and then issue DREQ. Fix the CPU destination address to the FIFO address. Dual-address mode DMA is started by two procedures: LIME issues an external request to DMAC of the host processor, or the CPU itself is started (auto request mode, etc.). In Ack use mode, set the transfer count in the transfer count register of LIME and then issue DREQ. Note: In the Ack unused mode and the V832 mode requires no setting of the transfer count register. 4.2.5 Ending DMA transfer SH3/SH4 When the LIME transfer count register is set to 0, DMA transfer ends and DREQ is negated. V832 When the XTC signal from the CPU is low-asserted while the DMAAK signal to S LIME is highasserted, the end of DMA transfer is recognized and DREQ is negated. The end of DMA transfer is detected in two ways: the DMA status register (DST) is polled, and an interrupt to end the drawing command (FD000000H) is added to the display list and the interrupt is detected. In the dual address mode (mode not using ACK), the DMA transfer count register (DTC) is not used, so the DMA ending cannot be determined. The DREQ signal can be negated to end DMA by writing 1 from the CPU to the DMA transfer stop register (DTS) of LIME at DMA transfer end. MB86276 'LIME' GDC Specifications Rev1.1a 47 FUJITSU SEMICONDUCTOR CONFIDENTIAL 4.3 Transfer of Local Display List This is the mode in which the LIME internal bus is used to transfer the display list stored in the graphics memory to the FIFO interface. During transfer of the local display list, the host bus can be used for CPU read/write. How to transfer list: Store the display list in the local memory of LIME, set the transfer source local address (LSA) and the transfer count (LCO), and then issue a request (LREQ). Whether or not the local display list is currently being transferred is checked using the local transfer status register (LSTA). CPU Host IF FIFO Memory IF SDRAM SDRAM Internal Bus CPU Bus Transfer Path for Local Display List MB86276 'LIME' GDC Specifications Rev1.1a 48 FUJITSU SEMICONDUCTOR CONFIDENTIAL 4.4 Interrupt LIME issues interrupt requests to the host CPU. Following shows the types of interrupt factor and they can be enabled/disabled by IMASK (Interrupt Mask Register). Vertical synchronization detect Field synchronization detect External synchronization error detect Drawing command error Drawing command execution end GPIO pinmonitoring 4.4.1 Address Error Interrupt Certain addresses are invalid depending on operation. For example the Burst Controller cannot access the Host Interface internal registers. If an attempt is made to do this then the access will be terminated and an Address Error Interrupt triggered. 4.5 SH3 Mode In the SH3 mode, operation is assured under the following conditions: Normally not ready mode BCLK (CPU bus clock) is 50 MHz or less. The XWAIT setup time is 9.0 ns or less. Normally ready mode Three cycles or more are set for the software wait. 4.6 Wait Software wait The software wait is a wait performed on the CPU side; this wait specifies how many cycles of the ready signal (XRDY) sampling timing is ignored. Hardware wait The hardware wait is a wait on the LIME side that occurs when LIME itself cannot read/write data immediately. 4.7 16-bit CPU mode In the 16-bit CPU mode (16-bit SRAM I/F, 16-bit AD I/F), the data is accessed in the following rules. MB86276 'LIME' GDC Specifications Rev1.1a 49 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1. The data is accessed in the following order, lower 16-bit of 32-bit and upper 16-bit of 32-bit continuosly. 2. The address is accessed ountinuosly. If those rules are not kept, it returns an error. Refer to the related Host Interface register in details. MB86276 'LIME' GDC Specifications Rev1.1a 50 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2 5 I C Interface Controller 5.1 Features - Master transmission and receipt - Slave transmission and receipt - Arbitration - Clock synchronization - Detection of slave address - Detection of general call address - Detection of transfer direction - Repeated generation and detection of START condition - Detection of bus error - Correspondence to standard-mode (100kbit/s ) / high-speed-mode (400kbit/s) MB86276 'LIME' GDC Specifications Rev1.1a 51 FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.2 5.2.1 Block diagram Block Diagram SDA SCL START condition/ST OP condition detecting circuit noise filter ADR Comparater Host Bus DAR Host IF BSR BCR CCR Arbitration Lost detecting circuit START condition/ST OP condition generating circuit Shift Clock generating circuit I2C UNIT MB86276 'LIME' GDC Specifications Rev1.1a 52 FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.2.2 Block Function Overview START condition / STOP condition detecting circuit This circuit performs detection of START condition and STOP condition from the state of SDA and SCL. START condition / STOP condition generating circuit This circuit performs generation of START condition and STOP condition by changing the state of SDA and SCL. Arbitration Lost detecting circuit This circuit compares the data output to the SDA line with the data input into the SDA line at the time of data transmission, and it checks whether the data is identical. If not identical, the circuit detects this as an arbitration lost state. Shift Clock generating circuit This circuit performs generating timing count of the clock for serial data transfer, and output control of SCL clock by setup of a clock control register. Comparater Comparater compares whether the received address and the self-address appointed to be the address register is in agreement, and whether the received address is a global address. ADR ADR is the 7-bit register which appoints a slave address. DAR DAR is the 8-bit register used by serial data transfer. BSR BSR is the 8-bit register for the state of I2C bus etc. This register has following functions: - detection of repeated START condition - detection of arbitration lost - storage of acknowledge bit - data transfer direction - detection of addressing - detection of general call address - detection of the 1st byte BCR BCR is the 8-bit register which performs control and interruption of I2C bus. This register has following functions: - request / permission of interruption - generation of START condition - selection of master / slave - permission to generate acknowledge MB86276 'LIME' GDC Specifications Rev1.1a 53 FUJITSU SEMICONDUCTOR CONFIDENTIAL CCR CCR is the 7-bit register used by serial data transfer. This register has following functions: - permission of operation - setup of a serial clock frequency - selection of standard-mode / high-speed-mode Noise filter This noise filter consists of a 3 step shift register. When all three value that carried out the continuation sampling of the SCL/SDA input signals is "1", the filter output is "1". Conversely when all three value is "0", the filter output is "0". To other samplings it holds the state before 1 clock. 5.3 5.3.1 Example application Connection Diagram 3.3V GDC Slave Device SDA SDA SCL SCL MB86276 'LIME' GDC Specifications Rev1.1a 54 FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.4 Function overview Two bi-directional buses, serial data line (SDA) and serial clock line (SCL), carry information at I2Cbus. Scarlet I2C interface has SDA input (SDAI) and SDA output (SDAO) for SDA and is connected to SDA line via open-drain I/O cell. And this interface also has SCL input (SCLI) and SCL output (SCLO) for SCL line and is connected to SCL line via open-drain I/O cell. The wired theory is used when the interface is connected to SDA line and SCL line. 5.3.2 START condition If "1" is written to MSS bit while the bus is free, this module will become a master mode and will generate START condition simultaneously. In a master mode, even if a bus is in a use state (BB=1), START condition can be generated again by writing "1" to SCC bit. There are two conditions to generate START condition. - "1" writing to MSS bit in the state where the bus is not used (MSS=0 & BB=0 & INT=0 & AL=0) - "1" writing to SCC bit in the interruption state in a master mode (MSS=1 & BB=1 & INT=1 & AL=0) If "1" writing is performed to MSS bit in an idol state, AL bit will be set to "1". "1" writing to MSS bit other than the above is disregarded. SDA SCL START condition 5.3.3 STOP condition If "0" is written to MSS bit in a master mode (MSS=1), this module will generate STOP condition and will become a slave mode. There is a condition to generate STOP condition. - "0" writing to MSS bit in the interruption state in a master mode (MSS=1 & BB=1 & INT=1 & AL=0) "0" writing to MSS bit other than the above is disregarded. SDA SCL STOP condition MB86276 'LIME' GDC Specifications Rev1.1a 55 FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.3.4 Addressing In a master mode, it is set to BB="1" and TRX="0" after generation of START condition, and the contents of DAR register are output from MSB. When this module receives acknowledge after transmission of address data, the bit-0 of transmitting data (bit-0 of DRA register after transmission) is reversed and it is stored in TRX bit. - Transfer format of slave address A transfer format of slave address is shown below: MSB A6 A5 A4 A3 slave address A2 A1 A0 LSB R/W ACK - Map of slave address A map of slave address is shown below: 1110 1111 1111 R/W 0 1 X X X X Description General call address START byte CBUS address Reserved Reserved Reserved ----- slave address 0000 000 0000 000 0000 001 0000 010 0000 011 0 0 0 0 1XX 0 0 0 1 XXX X Available slave address XXX 0 XX 1 XX X X 10-bit slave addressing*1 Reserved *1 This module does not support 10-bit slave address. 5.3.5 Synchronization of SCL When two or more I2C devices turn into a master device almost simultaneously and drive SCL line, each devices senses the state of SCL line and adjusts the drive timing of SCL line automatically in accordance with the timing of the latest device. MB86276 'LIME' GDC Specifications Rev1.1a 56 FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.3.6 Arbitration When other masters have transmitted data simultaneously at the time of master transmission, arbitration takes places. When its own transmitting data is "1" and the data on SDA line is "0", the master considers that the arbitration was lost and sets "1" to AL. And if the master is going to generate START condition while the bus is in use by other master, it will consider that arbitration was lost and will set "1" to AL. When the START condition which other masters generated is detected by the time the master actually generated START condition, even when it checked the bus is in nonuse state and wrote in MSS="1", it considers that the arbitration was lost and sets "1" to AL. When AL bit is set to "1", a master will set MSS="0" and TRX= "0" and it will be a slave receiving mode. When the arbitration is lost (it has no royalty of a bus), a master stops a drive of SDA. However, a drive of SCL is not stopped until 1 byte transfer is completed and interruption is cleared. 5.3.7 Acknowledge Acknowledge is transmitted from a reception side to a transmission side. At the time of data reception, acknowledge is stored in LRB bit by ACK bit. When the acknowledge from a master reception side is not received at the time of slave transmission, it sets TRX="0" and becomes slave receiving mode. Thereby, a master can generate STOP condition when a slave opens SCL. 5.3.8 Bus error When the following conditions are satisfied, it is judged as a bus error, and this interface will be in a stop state. - Detection of the basic regulation violation on I2C-bus under data transfer (including ACK bit) - Detection of STOP condition in a master mode - Detection of the basic regulation violation on I2C-bus at the time of bus idol SDA SCL D7 START 1 D6 D5 2 3 SDA changed under data transmission (SCL=H). It becomes bus error. MB86276 'LIME' GDC Specifications Rev1.1a 57 FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.3.9 Initialize Start ADR: write CCR: write CS[4:0]: write EN: 1write BCR: write BER: 0write BEIE: 1write INT: 0write INTE: 1write setup of slave address setup of clock frequency setup of macro enable setup of interruption End MB86276 'LIME' GDC Specifications Rev1.1a 58 FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.3.10 1-byte transfer from master to slave master DAR: write M SS: 1write Start slave START condition BB set,TRX reset BB set,TRX set Transfer of address data AAS set Acknowledge LRB reset INT set, TRX set DAR: write INT: 0write Interruption INT set,TRX reset ACK: 1write INT: 0write data transfer acknowledge LRB reset INT set M SS: 0write INT reset BB reset, TRX reset interruption STOP condition End MB86276 'LIME' GDC Specifications Rev1.1a 59 INT set DAR: read INT: 0write BB reset,TRX reset AAS reset FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.3.11 1-byte transfer from slave to master master DAR:write M SS:1write slave Start START condition BB set, TRX reset BB set, TRX set Transfer of address data AAS set Acknowledge LRB reset INT set, TRX set ACK: 0write INT: 0write INT set, TRX reset DAR: write INT: 0write Iterruption Data transfer Negative acknowledge LRB set, RTX set IN T set INT set DAR: read M SS: 0write INT reset BB reset, TRX reset Interruption INT: 0write STOP condition End MB86276 'LIME' GDC Specifications Rev1.1a 60 BB reset, TRX reset AAS reset FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.3.12 Recovery from bus error Start BCR: write BER: 0write BEIE: 1write Cancellation of error flag CCR: write CS[4:0]: write EN: 1write Setup of clock frequency Setup of macro enable BCR: write BER: 0write BEIE: 1write INT: 0write INTE: 1write Setup of interruption End MB86276 'LIME' GDC Specifications Rev1.1a 61 FUJITSU SEMICONDUCTOR CONFIDENTIAL 5.4 Note A ) About a 10-bit slave address This module does not support the 10-bit slave address. Therefore, please do not specify the slave address of from 78H to 7bH to this module. If it is specified by mistake, a normal transfer cannot be performed although acknowledge bit is returned at the time of 1 byte reception. B ) About competition of SCC, MSS, and INT bit Competition of the following byte transfer, generation of START condition, and generation of STOP condition happens by the simultaneous writing of SCC, MSS, and INT bit. At this time the priority is as follows. 1) The following byte transfer and generation of STOP condition If "0" is written to INT bit and "0" is written to MSS bit, priority will be given to "0" writing to MSS bit and STOP condition will be generated. 2) The following byte transfer and generation of START condition If "0" is written to INT bit and "1" is written to SCC bit, priority will be given to "1" writing to SCC bit and START condition will be generated. 3) Generation of START condition and generation of STOP condition The simultaneous writing of "1" in SCC bit and "0" to MSS bit is prohibition. C ) About setup of S serial transfer clock When the delay of the positive edge of SCL terminal is large or when the clock is extended by the slave device, it may become smaller than setting value (calculation value) because of generation of overhead. MB86276 'LIME' GDC Specifications Rev1.1a 62 FUJITSU SEMICONDUCTOR CONFIDENTIAL 6 Graphics Memory 6.1 Configuration The LIME GDC uses local external memory (Graphics memory) for drawing and display management. The configuration of this Graphics memory is described as follows: 6.1.1 Data type The LIME GDC handles the following types of data. Display list can be stored in the host (main) memory as well. Texture/tile pattern and text pattern can be defined by a display list as well. Drawing Frame This is a rectangular image data field for 2D drawing. The LIME GDC is able to have plural drawing frames and display a part of these area if it is set to be bigger than display size. The maximum size is 4096x4096 pixel in 32 pixel units. And both indirect color ( 8 bits / pixel) and direct color ( 16 bits / pixel) mode are applicable. Display Frame This is a rectangle picture area for display. The LIME GDC is able to set display layer up to 6 layers. Z Buffer Z buffer is required for eliminating hidden surfaces. In 16 bits modes, 2 bytes and in 8 bits mode, 1 byte are required per 1 pixel. This area has to be cleared before drawing. Polygon Drawing Flag Buffer This area is used for polygon drawing. It requires 1 bit of memory per 1 pixel and 1 x-axis line area both before and after it. Initially, this area has to be cleared. Frame buffer, Z buffer, Displaylist and etc By XRES size Base Address of Polygon Drawing Buffer(PFBR) By drawing frame sizy Polygon drawing flag area => (Y resolution + 2) * X resolution By XRES size Frame buffer, Z buffer, Displaylist and etc Specially, when you use Polygon with Shadow, required area is depending on geometory view volume clip parameter. (Normally depending on drawing clipping parameter) Above "Y resolution" is "Possible_view_clipped_Max_Ydc-Possible_view_clipped_Min_Ydc+1+6". (+6 mergin must be needed) Displaylist Buffer The displaylist is a list of drawing commands and parameters. Texture Pattern This pattern is used for texture mapping. The maximum size is up to 4096 x 4096 pixels. Cursor Pattern MB86276 'LIME' GDC Specifications Rev1.1a 63 FUJITSU SEMICONDUCTOR CONFIDENTIAL This is used for hardware cursor. The data format is indirect color ( 8 bits / pixel) mode. And the LIME GDC is able to display two cursor of 64 x 64 pixel size. 6.1.2 Memory Mapping A graphics memory is mapped linearly to host CPU address field. Each of these above data is able to be allocated anywhere in the Graphics memory according to the respective register setting. ( However there are some restrictions of an addressing boundary depending on a data type.) The following shows the memory map of LIME to the host CPU memory space. The address is mapped differently in SH3, SH4 , V832, 16bit CPU etc. 64 MB Space (SH3/SH4) 32 MB to 256 KB 256 KB 32 MB 16 MB Space (V832, 16bit CPU) Graphics memory area 0000000 to 1FBFFFF 16 MB to 256 KB Register area 1FC0000 to 1FFFFFF 256 KB Graphics memory area 2000000 to 3FFFFFF Graphics memory area 0000000 to 0FBFFFF Register area 0FC0000 to 0FFFFFF Fig. 5.1 Memory Map Table 5-1 Address Space in SH4, SH3 Mode Size Resource Base address 32 MB to 256 KB (Name) 00000000 64 KB Host interface registers 01FC0000 (HostBase) 32 KB Display registers 01FD0000 (DisplayBase) 32 KB Capture registers 01FD8000 (CaptureBase) 32 KB Drawing registers 01FF0000 (DrawBase) 32 KB Peripheral I/O registers 01FF8000 (PIOBase) 32 MB Graphics memory 02000000 Table 4-5 Address Space in V832, 16bit CPU Mode Size Resource Base address (Name) 16 MB to 256 KB Graphics memory 00000000 64 KB Host interface registers 00FC0000 (HostBase) 32 KB Display registers 00FD0000 (DisplayBase) 32 KB Capture registers 00FD8000 (CaptureBase) 32 KB Drawing registers 00FF0000 (DrawBase) 32 KB Peripheral I/O registers 00FF8000 (PIOBase) MB86276 'LIME' GDC Specifications Rev1.1a 64 FUJITSU SEMICONDUCTOR CONFIDENTIAL When the SH3 or SH4 mode is used, the register area can be moved by writing 1 to bit 0 at HostBase + 005Ch (RSW: Register location Switch). In the initial state, the register space is at the center (1FC0000) of the 64 MB space; access LIME after about 20 bus clocks after writing 1 to RSW. 64 MB space (SH3/SH4) 32 MB Graphics memory area 0000000 to 1FFFFFF 32 MB to 256 KB Graphics memory area 2000000 to 3FBFFFF Register area 256 KB 3FC0000 to 3FFFFFF Fig. 4.2 Memory Map Table 4-6 Address Mapping in SH3/SH4 Mode Size Resource Base address (Name) 64 MB to 256 KB Graphics memory 00000000 64 KB Host interface registers 03FC0000 (HostBase) 32 KB Display registers 03FD0000 (DisplayBase) 32 KB Capture registers 03FD8000 (CaptureBase) 32 KB Drawing registers 03FF0000 (DrawBase) 32 KB Peripheral I/O registers 03FF8000 (PIOBase) MB86276 'LIME' GDC Specifications Rev1.1a 65 FUJITSU SEMICONDUCTOR CONFIDENTIAL 6.1.3 Data Format Direct Color ( 16 bits / pixel ) This data format is described RGB as each 5 bit. Bit15 is used for alpha bit of layer blending. 15 14 13 A 12 11 10 9 8 R 7 6 5 4 3 G 2 1 0 1 0 B Indirect Color ( 8 bits / pixel ) This data format is a color index code for looking up table (palette). 7 6 5 4 3 2 1 0 Color Code Z Value(Optional function) It is possible to use Z value as 8 bits or 16 bits. These data format are unsigned integer. 1 ) 16 bits mode 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Unsigned Integer 2 ) 8 bits mode 7 6 5 4 3 2 1 0 Unsigned Integer Polygon Drawing Flag This data format is 1 bit per 1 pixel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 Texture / Tile Pattern It is possible to use a pattern as direct color mode ( 16 bits / pixel) or indirect color mode ( 8 bits / pixel). 1 ) Direct color mode ( 16 bits / pixel) This data format is described RGB as each 5 bit. Bit15 is used for alpha bit of stencil or stencil blending. ( Only texture mapping) 15 14 13 A 12 11 10 9 8 R 7 6 5 G 2) Indirect color mode ( 8 bits / pixel) This data format is a color index code for looking up table (palette). 7 6 5 4 3 2 1 0 Color Code Cursor Pattern This data format is a color index code for looking up table (palette). 7 6 5 4 3 2 1 Color Code MB86276 'LIME' GDC Specifications Rev1.1a 66 0 4 3 2 B 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 6.2 Frame Management 6.2.1 Single Buffer The entire or partial area of the drawing frame is assigned as a display frame. The display field is scrolled by relocating the position of the display frame. When the display frame crosses the border of the drawing frame, the other side of the drawing frame is displayed, assuming that the drawing frame is rolled over (top and left edges assumed logically connected to bottom and right edges, respectively). To avoid the affect of drawing on display, the drawing data can be transferred to the Graphics Memory in the blanking time period. 6.2.2 Double Buffer Two drawing frames are set. While one frame is displayed, drawing is done at the other frame. Flicker-less animation can be performed by flipping these two frames back and forth. Flipping is done in the blanking time period. There are two flipping modes: automatically at every scan frame period, and by user control. The double buffer is assigned independently for the L2, L3, L4, L5 layers. 6.3 Memory Access 6.3.1 Priority of memory accessing The priority of Graphics memory accessing is the follows: 1. 2. 3. 4. 5. Refresh Video Capture Display processing Host CPU accessing Drawing accessing MB86276 'LIME' GDC Specifications Rev1.1a 67 FUJITSU SEMICONDUCTOR CONFIDENTIAL 6.4 6.4.1 Connection with memory Connection with memory The memory controller of LIME GDC supports simple connection with SDRAM by setting MMR(Memory Mode Register). If there is N(=11 to 13) address pins in SDRAM, please connect the SDRAM address(A[n]) pin to the LIME's memory address(MA[n]) pin and SDRAM bank pin to the LIME's next address(MA[N]) pin. Then please set MMR by a number and type of memory. The follows are the connection table between LIME pin and SDRAM pin. 64M bit SDRAM(x16 bit) LIME pins SDRAM pins MA[11:0] A[11:0] MA12 BA0 MA13 BA1 64M bit SDRAM(x32 bit) LIME pins SDRAM pins MA[10:0] A[10:0] MA11 BA0 MA12 BA1 128M bit SDRAM(x16 bit) LIME pins SDRAM pins MA[11:0] A[11:0] MA12 BA0 MA13 BA1 128M bit SDRAM(x32 bit) LIME pins SDRAM pins MA[11:0] A[11:0] MA12 BA0 MA13 BA1 256M bit SDRAM(x16 bit) LIME pins SDRAM pins MA[12:0] A[12:0] MA13 BA0 MA14 BA1 256M bit SDRAM(x32 bit) LIME pins SDRAM pins MA[11:0] A[11:0] MA12 BA0 MA13 BA1 512M bit SDRAM(x32 bit) LIME pins SDRAM pins MA[12:0] A[12:0] MA13 BA0 MA14 BA1 MB86276 'LIME' GDC Specifications Rev1.1a 68 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7 DISPLAY CONTROLLER 7.1 Overview Display control Window display can be performed for six layers. Window scrolling, etc., can also be performed. Backward compatibility Backward compatibility with previous products is supported in the four-layer display mode or in the left/right split display mode. Video timing generator The video display timing is generated according to the display resolution (from 320 x 240 to 1280x768). Color look-up There are two sets of color look-up tables by palette RAM for the indirect color mode (8 bits/pixel). Cursor Two sets of hardware cursor patterns (8 bits/pixel, 64 x 64 pixels each) can be used. MB86276 'LIME' GDC Specifications Rev1.1a 69 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.2 Display Function 7.2.1 Layer configuration Six-layer window display is performed. Layer overlay sequence can be set in any order. A four-layer display mode and left/right split display mode are also provided, supporting backward compatibility with previous products. L0 (L0WX,L0WY) L4 (L4WX,L4WY) L2 (L2WX,L2WY) L0,L2,L4 (0,0) L1 (WX,WY) L3,L5 (HDB+1,0) L1 (L1WX,L1WY) L5 (L5WX,L5WY) background color L3 (L3WX,L3WY) (a) Six layerd window display (b) Four layered display for downward compatibility Configuration of Display Layers The correspondence between the display layers for this product and for previous products is shown below. Layer correspondence Coordinates of starting point Window mode Compatibility mode Width/height Window mode Compatibility mode L0 C (L0WX, L0WY) (0, 0) (L0WW, L0WH + 1) (HDP + 1, VDP + 1) L1 W (L1WX, L1WY) (WX, WY) (L1WW, L1WH + 1) (WW, WH + 1) L2 ML (L2WX, L2WY) (0, 0) (L2WW, L2WH + 1) (HDB + 1, VDP + 1) L3 MR (L3WX, L3WY) (HDB, 0) (L3WW, L3WH + 1) (HDP - HDB, VDP + 1) L4 BL (L4WX, L4WY) (0, 0) (L4WW, L4WH + 1) (HDB + 1, VDP + 1) L5 BR (L5WX, L5WY) (HDB, 0) (L5WW, L5WH + 1) (HDP - HDB, VDP + 1) C, W, ML, MR, BL, and BR above are layers provided for compatibility to previous products. The window mode or the compatibility mode can be selected for each layer. It is possible to set window mode or compatibility mode in layer base. However, if high resolutions are displayed, the count of layers that can be displayed simultaneously and pixel data may be restricted according to the graphics memory ability to supply data. MB86276 'LIME' GDC Specifications Rev1.1a 70 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.2.2 Overlay (1) Overview Image data for the six layers (L0 to L5) is processed as shown below. L0(C) data Cursor0 data Pallet-0 Cursor1 data L4(BL) data Pallet-1 YUV/RGB L5(BR) data L2 data L3 data Pallet-2 Blender L3(MR) data Layer Selector L2(ML) data Overlay L1(W) data Pallet-3 L4 data L5 data The fundamental flow is: Palette Layer selection Blending. The palettes convert 8-bit color codes to the RGB format. The layer selector exchanges the layer overlay sequence arbitrarily. The blender performs blending using the blend coefficient defined for each layer or overlays in accordance with the transparent-color definition. The L0 layer corresponds to the C layer for previous products and shares the palettes with the cursor. As a result, the L0 layer and cursor are overlaid before blend operation. The L1 layer corresponds to the W layer for previous products. To implement backward compatibility with previous products, the L1 layer and lower layers are overlaid before blend operation. The L2 to L5 layers have two paths; in one path, these layers are input to the blender separately and in the other, these layers and the L1 layer are overlaid and then are input to the blender. When performing processing using the extended mode, select the former; when performing the same processing as previous products, select the latter. It is possible to specify which one to select for each layer. MB86276 'LIME' GDC Specifications Rev1.1a 71 FUJITSU SEMICONDUCTOR CONFIDENTIAL (2) Overlay mode Image layer overlay is performed in two modes: simple priority mode, and blend mode. In the simple priority mode, processing is performed according to the transparent color defined for each layer. When the color is a transparent color, the value of the lower layer is used as the image value for the next stage; when the color is not a transparent color, the value of the layer is used as the image value for the next stage. Dview = Dnew (when Dnew does not match transparent color) = Dlower (when Dnew matches transparent color) When the L1 layer is in the YCbCr mode, transparent color checking is not performed for the L1 layer; processing is always performed assuming that transparent color is not used. In the blend mode, the blend ratio "r" defined for each layer is specified using 8-bit tolerance, and the following operation is performed: Dview = Dnew*r + Dlower*(1 - r) Blending is enabled for each layer by mode setting and a specific bit of the pixel is set to "1". For 8 bits/pixel, the MSB of RAM data enables blending; for 16 bits/pixel, the MSB of data of the relevant layer enables blending; for 24 bits/pixel, the MSB of the word enables blending. (3) Blend coefficient layer In the normal blend mode, the blend coefficient is fixed for each layer. However, in the blend coefficient layer mode, the L5 layer can be used as the blend coefficient layer. In this mode, the blend coefficient can be specified for each pixel, providing gradation, for example. When using this mode, set the L5 layer to 8 bits/pixel, widow display mode and extend overlay mode. MB86276 'LIME' GDC Specifications Rev1.1a 72 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.2.3 Display parameters The display area is defined according to the following parameters. independently at the respective register. Each parameter is set HTP HSP HDP HSW HDB VDP LnWX LnWW LnWH VTR VSP LnWY VSW Display Parameters Note: The actual parameter settings are little different from the above. The details, please refer "14.3.1 Interlaced mode". HTP Horizontal Total Pixels HSP Horizontal Synchronize pulse Position HSW Horizontal Synchronize pulse Width HDP Horizontal Display Period HDB Horizontal Display Boundary VTR Vertical Total Raster VSP Vertical Synchronize pulse Position VSW Vertical Synchronize pulse Width VDP Vertical Display Period LnWX Layer n Window position X LnWY Layer n Window position Y LnWW Layer n Window Width LnWH Layer n Window Height When not splitting the window, set HDP to HDB and display only the left side of the window. The settings must meet the following relationship: 0 < HDB HDP < HSP < HSP + HSW + 1 < HTP 0 < VDP < VSP < VSP + VSW + 1 < VTR MB86276 'LIME' GDC Specifications Rev1.1a 73 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.2.4 Display position control The graphic image data to be displayed is located in the logical 2D coordinates space (logical graphics space) in the Graphics Memory. There are six logical graphics spaces as follows: L0 layer L1 layer L2 layer L3 layer L4 layer L5 layer The relation between the logical graphics space and display position is defined as follows: Origin Address (OA) Display Address (DA) Display Position X,Y (DX,DY) Stride (W) Height (H) Logical Frame Display Frame VDP HDP Display Position Parameters OA Origin Address W Stride Origin address of logical graphics space. Memory address of top left edge pixel in logical frame origin Width of logical graphics space. Defined in 64-byte unit H Height Height of logical graphics space. Total raster (pixel) count of field DA Display Address DX DY Display Position Display origin address. Top left position address of display frame origin Display origin coordinates. Coordinates in logical frame space of display frame origin MB86276 'LIME' GDC Specifications Rev1.1a 74 FUJITSU SEMICONDUCTOR CONFIDENTIAL MB86276 scans the logical graphics space as if the entire space is rolled over in both the horizontal and vertical directions. Using this function, if the display frame crosses the border of the logical graphics space, the part outside the border is covered with the other side of the logical graphics space, which is assumed to be connected cyclically as shown below: Logical Frame Origin 64 w Previous display origin Additionally drawn area New display origin L Wrap Around of Display Frame The expression of the X and Y coordinates in the frame and their corresponding linear addresses (in bytes) is shown below. A(x,y) = x x bpp/8 + 64wy (bpp = 8 or 16) The origin of the displayed coordinates has to be within the frame. parameters are subject to the following constraints: To be more specific, the 0 DX < w x 64 x 8/bpp (bpp = 8 or 16) 0 DY < H DX, DY, and DA have to indicate the same point within the frame. In short, the following relationship must be satisfied. DA = OA + DX x bpp/8 + 64w x DY (bpp = 8 or 16) MB86276 'LIME' GDC Specifications Rev1.1a 75 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.3 Display Color Color data is displayed in the following modes: Indirect color (8 bits/pixel) In this mode, the index of the palette RAM is displayed. Data is converted to image data consisting of 6 bits for R, G, and B via the palette RAM and is then displayed. Direct color (16 bits/pixel) Each level of R, G, and B is represented using 5 bits. Direct color (24 bits/pixel) Each level of R, G, and B is represented using 8 bits. YCbCr color (16 bits/pixel) In this mode, image data is displayed with YCbCr = 4:2:2. Data is converted to image data consisting of 8 bits for R, G, and B using the operation circuit and is then displayed. The display colors for each layer are shown below. Layer Compatibility mode Extended mode L0 Direct color (16, 24), Indirect color (P0) Direct color (16, 24), Indirect color (P0) L1 Direct color (16, 24), Indirect color (P1), YCbCr Direct color (16, 24), Indirect color (P1), YCbCr L2 Direct color (16, 24), Indirect color (P1) Direct color (16, 24), Indirect color (P2) L3 Direct color (16, 24), Indirect color (P1) Direct color (16, 24), Indirect color (P3) L4 Direct color (16, 24), Indirect color (P1) Direct color (16, 24) L5 Direct color (16, 24), Indirect color (P1) Direct color (16, 24) "Pn" stands for the corresponding palette RAM. Four palettes are used as follows: Palette 0 (P0) This palette corresponds to the C-layer palette for previous products. This palette is used for the L0 layer. This palette can also be used for the cursor. Palette 1 (P1) This palette corresponds to the M/B layer palette for previous products. In the compatibility mode, this palette is common to layers L1 to 5. In the extended mode, this palette is dedicated to the L1 layer. Palette 2 (P2) This palette is dedicated to the L2 layer. This palette can be used only for the extended mode. Palette 3 (P3) This palette is dedicated to the L3 layer. This palette can be used only for the extended mode. MB86276 'LIME' GDC Specifications Rev1.1a 76 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.4 7.4.1 Cursor Cursor display function LIME GDC can display two hardware cursors. Each cursor is specified as 64 x 64 pixels, and the cursor pattern is set in the Graphics Memory. The indirect color mode (8 bits/pixel) is used and the L0 layer palette is used. However, transparent color control (handling of transparent color code and code 0) is independent of L0 layer. Blending with lower layer is not performed. 7.4.2 Cursor control The display priority for hardware cursors is programmable. The cursor can be displayed either on upper or lower the L0 layer using this feature. A separate setting can be made for each hardware cursor. If part of a hardware cursor crosses the display frame border, the part outside the border is not shown. Usually, cursor 0 is preferred to cursor 1. However, with cursor 1 displayed upper the L0 layer and cursor 0 displayed lower the L0 layer, the cursor 1 display is preferred to the cursor 0. MB86276 'LIME' GDC Specifications Rev1.1a 77 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.5 7.5.1 Display Scan Control Applicable display The following table shows typical display resolutions and their synchronous signal frequencies. The pixel clock frequency is determined by setting the division rate of the display reference clock. The display reference clock is either the internal PLL (400.9 MHz at input frequency of 14.318 MHz), or the clock supplied to the DCLKI input pin. The following table gives the clock division rate used when the internal PLL is the display reference clock: Resolution and Display Frequency Resolution Division rate of reference clock Pixel frequency Horizontal total pixel count Horizontal frequency Vertical total raster count Vertical frequency 320 x 240 1/60 6.7 MHz 424 15.76 kHz 263 59.9 Hz 400 x 240 1/48 8.4 MHz 530 15.76 kHz 263 59.9 Hz 480 x 240 1/40 10.0 MHz 636 15.76 kHz 263 59.9 Hz 640 x 480 1/16 25.1 MHz 800 31.5 kHz 525 59.7 Hz 854 x 480 1/12 33.4 MHz 1062 31.3 kHz 525 59.9 Hz 800 x 600 1/10 40.1 MHz 1056 38.0 kHz 633 60.0 Hz 1024 x 768 1/6 66.8 MHz 1389 48.1 kHz 806 59.9 Hz Pixel frequency = 14.318 MHz x 28 x reference clock division rate (when internal PLL selected) = DCLKI input frequency x reference clock division rate (when DCLKI selected) Horizontal frequency = Pixel frequency/Horizontal total pixel count Vertical frequency = Horizontal frequency/Vertical total raster count MB86276 'LIME' GDC Specifications Rev1.1a 78 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.5.2 Interlace display LIME GDC can perform both a non-interlace display and an interlace display. When the DCM register synchronization mode is set to interlace video (11), images in memory are output in odd and even rasters alternately to each field, and one frame (odd + even fields) forms one screen. When the DCM register synchronization mode is set to interlace (10), images in memory are output in raster order. The same image data is output to odd fields and even fields. Consequently, the count of rasters on the screen is half of that of interlace video. However, unlike the non-interlace mode, there is a distinction between odd and even fields depending on the phase relationship between the horizontal and vertical synchronous signals. Odd Eve Non-Interlace Interlace Video Interlace Display Difference between Synchronization Modes MB86276 'LIME' GDC Specifications Rev1.1a 79 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.6 The external synchronous signal The display scan can be performed by synchronizing horizontal/vertical synchronous signal from the external. In selecting the external synchronization mode, LIME is sampling the HSYNC signal and displays the synchronizing the external video signal. Either the internal PLL clock or the DCLKI input signal could be selected for the sampling clock. Also, the superimposed analog output is performed by the chroma key process. The following diagram shows an example of the external synchronization circuit. Display Timming Generator VSYNC L0 L1 L2 L3 L4 L5 3 states buffer Hsync Out L0 DAC Hsync In Vsync In ESY bit HSYNC Overlap External Sync Enable Cursor 0 Cursor 1 Vsync Out LIME CKM bit KEYC register Compare GV Latency compensation for DAC D-FFs Analog RGB In Video SW (Pedestal Clump Input) Superimposed Analog RGB Out 7.7 An example of the external synchronization circuit The external synchronization mode is performed by setting the ESY bit of the DCM register. In setting the external synchronization mode, HSYNC, VSYNC, and EO pin of LIME is changed to the input mode. After that it needs to be provided the synchronous signal by using the 3 state buffer from the external. When turning off the external synchronization mode, LIME internal ESY bit needs to be switched OFF after disconnecting the synchronous input signal from the external. The buffer of the external synchronization signal must not be switched ON when the synchronous output signal of LIME is ON. Follow the previous instruction to prevent simultaneous ON from occurring. In using the external synchronous signal with the display clock based on the internal PLL, LIME extends the clock period and fits the clock phase with the horizontal synchronous signal phase after inputting the horizontal synchronous pulse. The following caution is necessary. In case of connecting the high speed transmit signal, such as LVDS, with the digital RGB output, PLL with a built-in the high speed serial transmission is temporally unstable due to this connection. Therefore, the external synchronous signal based on the internal PLL must not be used with high speed synchronous transmit signal. MB86276 'LIME' GDC Specifications Rev1.1a 80 FUJITSU SEMICONDUCTOR CONFIDENTIAL The synchronization of the horizontal direction is controlled by the following state diagram. otherw ise otherwise counter = HTP The horizontal resolution B porch detecting the external horizontal synchronous signal or the horizontal synchronous pulse counter = H SW S ync otherwise W hen the horizontal resolution counter m atches the H TP , it is initialized. counter = HSP Fporch T he horizontal resolution counter = HDP The horizontal resolution D isp otherwise T he horizontal resolution counter is is halted, starts to count the horizontal synchronous pulse counter. The finite state diagram is controlled by the horizontal resolution counter. The period of outputting the signal is assigned the Disp state. When the value of the horizontal resolution counter matches that of the HDP register, it ends to output the signal and the current state is transmitted from Disp state to Fporch state (front porch). In the Fporch state, when the value of the vertical resolution register matches that of the HSP register, the current state is transmitted to the Sync state. In this state, it waits for the horizontal synchronous signal from the external. LIME detects the negative edge of the horizontal synchronous pulse from the external and synchronizes it. In detecting the horizontal synchronous signal from the external, the current state is transmitted to the Bporch state (back porch). The horizontal resolution register does not count in the Sync state, instead the horizontal synchronous counter is incremented from zero. When the value of this counter matches the setting value of the HSW register, the current state is transmitted to the Bporch state without detecting the horizontal synchronous signal form the external. When the value of the horizontal resolution counter matches that of the HTP register in the Bporch state, the horizontal resolution counter is reset, and also the current state is transmitted to the Disp state and it begins to display the next cluster. MB86276 'LIME' GDC Specifications Rev1.1a 81 FUJITSU SEMICONDUCTOR CONFIDENTIAL The synchronization of vertical direction is controlled by the following state diagram. o th erw ise o th erw ise D isp F porch pulse to be asserted vertical synchronous detecting the external = VTR The cluster counter T he clu ste r co un te r = V D P d e te ctin g th e n e ga tive e d ge of the e xte rna l ve rtica l syn ch ro n o u s p u lse B porch S ync o th erw ise o th erw ise W hen th e clu ste r cou n te r m atch e s the V T P , it is in itia lize d . The state diagram of the vertical direction is controlled by the value of the cluster counter. The period of outputting the signal is assigned the Disp state. When the value of the cluster counter matches the value of the VDP register, it ends to output the signal and the current state is transmitted from the Disp state to the Fporch state. In the Fporch state, it waits the external synchronous pulse to be asserted. In detecting the external synchronous pulse to be asserted, the current state is transmitted to the Sync state. In the Sync state, it waits for the negative edge of the external synchronous signal. In detecting the negative edge, the current state is transmitted to the Bporch state. When the value of the cluster counter matches the values of the VTR register, the cluster counter is reset, and also the current state is transmitted to the Disp state and it starts to display the next field. MB86276 'LIME' GDC Specifications Rev1.1a 82 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.8 Programmable YCbCr/RGB conversion for L1-layer display L1-layer can display video data in YCbCr format but RGB conversion coefficients are hard-wired and fixed about previous products. LIME can program RGB conversion coefficients by registers. YCbCr data is converted by following expression. R = a11*Y + a12*(Cb-128) + a13*(Cr-128) + b1 G = a21*Y + a22*(Cb-128) + a23*(Cr-128) + b2 B = a31*Y + a32*(Cb-128) + a33*(Cr-128) + b3 aij ---- 11bit signed real ( lower 8bit is fraction, two's complement ) bi ----- 9bit signed integer ( two's complement ) It is represended by matrix operation. R G B Y = A Cb-128 Cr-128 +b where A= a11 a21 a31 a12 a22 a32 a13 a23 a33 ,b= b1 b2 b3 These parameters are set on registers shown bellow. L1YCR0 (a12,a11), L1YCR1(b1,a13) L1YCG0 (a22,a21), L1YCG1(b2,a23) L1YCB0 (a32,a31), L1YCB1(b3,a33) Same conversion with previous products is applied by initial values of these registers after reset. The register values just after reset is as follow. a11 = 0x12b (299/256) , a12 = 0x0, a13 = 0x198 (408/256) a21 = 0x12b (299/256), a22 = 0x79c (-100/256), a23 = 0x72f (-209/256) a31 = 0x12b (299/256), a32 = 0x204 (516/256), a33 = 0x0 b1= b2= b3= 0x1f0 (-16) It is possible to control brightness, contrast, hue , color saturation by change these parameters. Addition of a constant value into b means inclease of brightness. Multiplication of a constant scalar value greater than one into A means increase of contrast. Two dimentional rotation of Cb-128 and Cr-128 means change of hue. Color saturation is intensity of color, relative to Y-component. New coefficients including these changes can be got by following expression. MB86276 'LIME' GDC Specifications Rev1.1a 83 FUJITSU SEMICONDUCTOR CONFIDENTIAL A = c1 A0 b = bo + 1 0 0 0 cos(t) sin(t) 0 -sin(t) cos(t) 1 0 0 0 c2 0 0 0 c2 = A0 c1 0 0 cos(t)c1c2 0 -sin(t)c1c2 0 sin(t)c1c2 cos(t)c1c2 c3 c3 c3 A0 , b0 : initial value c1: contrast parameter, 1 is standard. 1.2 is stronger, for example. c2: color saturation parameter, 1 is standard. 0 means mono chrome image. c3: brightness parameter, 0 is standard. t : hue rotation parameter, 0-deg is standard Note: new aij and bi should be clipped in valid range of value for corresponding registers. MB86276 'LIME' GDC Specifications Rev1.1a 84 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.9 DCLKO shift 1) Delay DCLKO delay function is available if internal PLL is used for DCLK. DCKD field in DCM3 register defines delay value by internal PLL clock cycle. DCKD delay 000000 No additional delay 000010 +2 PLL clock 000100 +3 PLL clock 000110 +4 PLL clock : 111110 : +33 PLL clock 2) Inversion DCLKO inversion is also available with/without delay function. This function is effective with no relation to DCLK clock source. CKinv-bit of DCM3 enables this function. 7.10 Syncronous register update of display To update position related parameters without disturbing display, it is need to update synchronously with VSYNC interrupt and finish at a time. This synchronous register update mode eases this limitation. In this mode, written parameters are hold in intermediate registers and update at once synchronously with VSYNC. RUM-bit of DCM2 register enables this mode. RUF-bit of DCM2 register controls start of update and shows whether update is done or not. MB86276 'LIME' GDC Specifications Rev1.1a 85 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.11 Dual Display 7.11.1 Overview This function enables to display two screens on two display devices. It is possible to control which layer is included in a screen. It is assumed here that display device "0" has screen "0" and display device "1" has screen "1". screen"0" display device"0" screen"1" display device"1" MB86276 7.11.2 Destination Control A layer or cursor can be included in both screens or one screen. If a layer is NOT included into a screen, this layer is treated as "transparent" . If all bits of a screen are set "0", then background color is displayed on the screen. This destination control can be thought virtually as crosspoint switch shown next background layer 0 color layer 1 layer 5 cur 0 cur 1 screen 0 SC0en0 SC0en1 SC0en5 SC0en6 SC0en7 SC1en0 SC1en1 SC1en5 SC1en6 SC1en7 screen 1 MDen (multi display enable) bit of MDC(multi display control) register enables this function. SC0en (screen"0" enable) field of MDC register defines which layers and cursors are included in screen "0". SC1en (screeen"1" enable) field of MDC register defines which layers and cursors are included in screen "1". bit-0 ---- L0 is included bit-1 ---- L1 is included : bit-5 ---- L5 is included bit-6 ---- Cursor0 is included bit-7 ---- Cursor1 is included MB86276 'LIME' GDC Specifications Rev1.1a 86 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.11.3 Output Signal Control There are two modes to output two screens. In parallel mode, one screen is output at digital RGB1 while another screen is output at digital RGB2. In multiplex mode, two screens are multiplexed and output at digital RGB1. (1) parallel output mode DCLKO (SE) DCLKO (BE) DE Digital RGB1 sc0 sc0 sc0 Digital RGB2 sc0 sc0 sc0 (2) multiplex output mode DCLKO (SE) DCLKO (BE) DE Digital RGB1 sc0 sc1 sc0 sc1 sc0 sc1 In BE (bi-edge) DCLKO mode, two ouput phases can be identified both edge of DCLKO. In SE (single-edge) DCLKO mode, two output phases cab be identified an edge of HSYNC or DE. DCLKO (SE) HSYNC ref edge sc0 is first Digital RGB sc0 sc1 DE even clocks POM(parallel output mode) bit in DCM3 register defines which output mode is used, parallel or multiplex. POM=0 means multiplex, POM=1 means parallel, respectively. DCKed( clock edge) bit in DCM3 register defines which DCLKO clock mode is used, BE(bi-edge) or SE(single-edge). DCKed=0 MB86276 'LIME' GDC Specifications Rev1.1a 87 FUJITSU SEMICONDUCTOR CONFIDENTIAL 7.11.4 Output Circuit Example There are three types of output circuit for dual display, primalry. Parallel, Digital Multiplex(SE), Digital Multiplex(BE) Here these three examples are described. (1) Parallel output Two screens are given as digital signals in this example. MB86276 (pallarel output) (BE mode) DCLKO R0 G0 B0 HSYNC0 VSYNC0 DCLKO DR[7:2] DG[7:2] DB[7:2] HSYNC display device"0" VSYNC R1 G1 B1 HSYNC1 VSYNC1 DR[7:2] DG[7:2] DB[7:2] (POM=1,DCKed=1) display device"1" (2) Multiplexed digital output with SE mode DCLKO In this case, CPLD can be used to demultiplex two digital streams of each screen. In following example, one economical CPLD demultiplexes RGB 6bit/component video data stream. MB86276 (mux output) DCLKO XC9572XL-TQ100 (SE mode) DCKi DCK0 HSYNC HSi HS0 VSYNC VSi VS0 DE Di[18] DR[7:2] DG[7:2] Di[17:0] D0[18] D0[17:0] R0,G0,B0 DCK1 DCLK1 HSYNC1 VSYNC1 DE1 DB[7:2] HS1 (POM=0,DCKed=0) VS1 D1[18] D1[17:0] MB86276 'LIME' GDC Specifications Rev1.1a DCLK0 HSYNC0 VSYNC0 DE0 88 R1,G1,B1 display device "0" display device "1" FUJITSU SEMICONDUCTOR CONFIDENTIAL module XC9572XL ( DCKi, HSi,VSi,Di, DCK0,HS0,VS0,D0, DCK1,HS1,VS1,D1 ); input DCKi,HSi,VSi; input[18:0] Di; output DCK0,HS0,VS0, DCK1,HS1,VS1; output[18:0] D0,D1; reg HS0,HS1, VS0,VS1, DCK0,DCK1; reg[18:0] D0,D1; always @(posedge DCKi) begin HS0 <= HSi; HS1 <= HS0; VS0 <= VSi; VS1 <= VS0; DCK0 <= (HS0&!HSi)? 0: !DCK0; // sync to ref edge : flip DCK1 <= DCK0; if(DCK0) D0 <= Di; if(DCK1) D1 <= Di; end endmodule DCLKi HSi Di ref edge even clocks sc0 sc1 sc0 sc1 sc1 DCK0 D0[18:0] sc0 sc0 read point DCK1 D1[18:0] sc1 read point MB86276 'LIME' GDC Specifications Rev1.1a 89 sc1 FUJITSU SEMICONDUCTOR CONFIDENTIAL (3) Multiplexed digital output with BE mode DCLKO If a receiving device can select data strobe edge, it can be used to demultiplex two screens with rising and falling edge of DCLKO. MB86276 (mux outpuut) DCLKO HSYNC VSYNC DE pos edge mode 1 (BE mode) mode display device"0" DR[7:2] DG[7:2] DB[7:2] (POM=0,DCKed=1) neg edge mode 0 mode display device"1" 7.11.5 Display Clock and Timing It is need to supply display clock of twice frequency for dual display function to work. VGA display uses 25MHz display clock, typically in single display mode while 50MHz display clock is need for dual display mode. The timing parameters such as HTP except scaling ratio (SC) are same. Maximum display clock frequency determines maximum available resolution. It is 800 x 480. 66MHz DCLK clock is need for it. 7.11.6 Limitation Two display devices has same scan rate and resolution with common sync signals. The external sync mode can not be used in dual display mode. MB86276 'LIME' GDC Specifications Rev1.1a 90 FUJITSU SEMICONDUCTOR CONFIDENTIAL 8 Video Capture 8.1 8.1.1 Video Capture function Input data Formats The digital video stream of ITU RBT-656 or RGB666 format conformity is inputted (for details refer to 8.5 external video signal input conditions). 8.1.2 Capturing of Video Signal "LIME" becomes effective when VIE of a video capture mode register (VCM) is 1, and it is CCLK. Synchronizing with a clock, video stream data is captured from 8-bit VI pin or 20-bit RGB input pin. 8.1.3 Non-interlace Transformation Captured video graphics can be displayed in non-interlaced format. Two modes (BOB and WEAVE) can be selected at non-interlace transformation. - BOB Mode In odd fields, the even-field raster generated by average interpolation are added to produce one frame. In even fields, the odd-field raster generated by average interpolation are added to produce one frame. In order to choose BOB mode, while enable vertical interpolation in VI bit of a VCM (Video Capture Mode) register, the L1IM bit of L1M (L1-layer Mode) register is set as 0. - WEAVE Mode Odd and even fields are merged in the video capture buffer to produce one frame. Vertical resolutions in the WEAVE mode are higher than those in the BOB mode but raster dislocation appears at moving places. In order to choose WEAVE mode, while disable vertical interpolation in VI bit of a VCM (Video Capture Mode) register, the L1IM bit of L1M (L1-layer Mode) register is set as 1. MB86276 'LIME' GDC Specifications Rev1.1a 91 FUJITSU SEMICONDUCTOR CONFIDENTIAL 8.2 8.2.1 Video Buffer Data Form The video capture unit of MB86276 "LIME" accepts YUV422 video data primarily, but RGB video data is also accepted via an internal RGB preprocessor which converts RGB to YUV422. Captured pixels are stored in YCbCr format in graphics memory, 16 bits per pixel. The video data is converted to RGB when it is displayed. 31 24 23 Y1 8.2.2 16 15 8 Cr 7 0 Y0 Cb 7 6 5 4 3 2 1 0 Y0,Y1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Cr,Cb C7 C6 C5 C4 C3 C2 C1 C0 Synchronous Control Writing to the graphics memory of video image data and scan for a display are performed independently. The graphics memory for video captures is controlled by the ring buffer system. It displays the frame, when the image data for one frame can be preparing on a memory. When the frame rate of a video capture differs from the frame rate of a display, the continuation display of top omission or the same frame occurs. 8.2.3 Area Allocation Allocate an area of about 2.2 frames to the video capture buffer. The size of this area is equivalent to the size that considers the margin equivalent to the double buffer of the frame. Set the starting address and upper-limit address of the area in the CBOA/CBLA registers. Here, specify the raster start position as the upper-limit address. To allocate n rasters as the video capture buffer, set the upper-limit value as follows: CBLA = CBOA + 64 (n-2) x CBW In addition, the head addresses of n+1 raster are 64nxCBW, and CBLA+2 raster becomes a buffer domain. For reduced display, allocate the buffer area of the reduced frame size. MB86276 'LIME' GDC Specifications Rev1.1a 92 FUJITSU SEMICONDUCTOR CONFIDENTIAL 8.2.4 Window Display The captured video picture is displayed using L1 layer. The whole or a part captured picture can be displayed as the whole screen or a window. When performing a capture display, L1 layer is set as capture synchronous mode (L1CS=1). In this mode, L1 layer display displays the newest frame in a video capture buffer. Usually, the display address used in the mode is disregarded. The stride of L1 layer needs to be in agreement with the stride of a video capture buffer. When not in agreement, the picture distorted aslant is displayed. The display size of L1 layer is made in agreement with the picture size after reduction of a video capture. Invalid data will be displayed if the display size of L1 layer is set up more greatly than capture picture size. Although selection of a RGB display and a YCbCr display can be performed in L1 layer, in performing a video capture, it chooses YcbCr form (L1YC=1). 8.2.5 Interlace Display It is possible to display the picture taken in to the video capture buffer in WEAVE mode in an interlace. A setup confirms WEAVE mode and chooses an interlace & video display with display scan. However, when display scan is asynchronous, flicker will come out in a scene with a motion. In order to prevent this, OO (Odd Only) bit of a CBM (Capture Buffer Mode) register is set as 1. When synchronizing display scan with a capture, a capture input and a display output can be made to correspond to 1 to 1. In this case, the difference of flicker of an input and an output is lost. Please refer to "8.8 Capture synchronous display." 8.2.6 RGB555 Mode As an alternative method, a special RGB555-mode can be used which is dedicated for applications where grabbed pictures should be processed further. In this mode, a single buffer is used instead of a ring buffer. In addition, data is directly stored in LIME's RGB555 format in the L1-Layer (see settings of the CBM register). This makes it possible to copy rectangular areas from the L1-layer directly to the texture buffer or to other memory locations using the BitBlt function. Note that the input and output frame rate should be identical if a single buffer method is used and that the lower bits are ignored to form the RGB555 format. MB86276 'LIME' GDC Specifications Rev1.1a 93 FUJITSU SEMICONDUCTOR CONFIDENTIAL 8.3 8.3.1 Scaling Down-scaling Function When the CM bits of the video capture mode register (VCM) are 11, LIME reduces the video screen size. The reduction can be set independently in the vertical and horizontal scales. The reduction is set per line in the vertical direction and in 2-pixel units in the horizontal direction. The scale setting value is defined by an input/output value. It is a 16-bit fixed fraction where the integer is represented by 5 bits and the fraction is represented by 11 bits. Valid setting values are from 0800H to FFFFH. Set the vertical direction at bit 31 to bit 16 of the capture scale register (CSC) and the horizontal direction at bits 15 to bit 00. The initial value for this register is 08000800H (once). An example of the expressions for setting a reduction in the vertical and horizontal directions is shown below (note 2048 is a fixed value): Reduction in vertical direction Reduction in horizontal direction 576 -> 490 lines 576/490 = 1.176 1.176x2048=2408 -> 0968H 720 -> 648 pixels 720/648 = 1.111 1.111x2048=2275 -> 08E3H Therefore, 096808E3H is set in CSC. The capture horizontal pixel register (CHP) is used to limit the number of pixels processed during scaling. It is not used to set scaling values. Clamp processing is performed on the video streaming data outside the values set in CHP. Usually, the defaults for these registers are used. 8.3.2 Up-scaling Function LIME is able to enlarge the size of a video capture picture by the factor of 2 in both the horizontal and vertical directions. This feature can be used to realize full-screen modes of video input streams which have a resolution less than actual display size. In order to use magnify (up-scaling) mode, the horizontal and vertical factor must be less than one. Do not specify different scaling ways (reduction/enlargement) for horizontal and vertical factors ! Also initialize the following registers as follows : Set the magnify flag in the L1-layer mode register of the display controller. Set the picture source size (before magnification) into CMSHP and CMSVL. Set the final picture size (after magnification) into CMDHP and CMDVL. An example of the expressions for setting an enlargement in the vertical and horizontal directions is shown below : If the input picture size is 480x360 and the display picture size is 640x480, then the parameters for each register are as follows. HSCALE=(480/640)*2048=0x0600 VSCALE=(360/480)*2048=0x0600 CMSHP=0x00f0 CMSVL=0x0168 CMDHP=0x0140 CMDVL=0x01e0 L1WW=0x0280 L1WH=0x01df MB86276 'LIME' GDC Specifications Rev1.1a 94 FUJITSU SEMICONDUCTOR CONFIDENTIAL Note: - Smooth continuation operation to Down Scaling mode and Up Scaling mode cannot be performed. The picture disorder of some arises at the time of a change. This is the restrictions for Up Scaling mode and Down Scaling mode using the same interpolate circuit. MB86276 'LIME' GDC Specifications Rev1.1a 95 FUJITSU SEMICONDUCTOR CONFIDENTIAL 8.3.3 Flow of image processing As for the capture image displayed on L1 layer window, image processing is performed by the following flow. VideoInput (656/RGB) Color conversion RGB YUV / RGB YUV422 matrix RGB MB86276 Non-interlace interpolation RGB 656(YUV422) On / Off horizontal vertical vertical LPF down scaling LPF down scaling horizontal interpolator Scaler Line Buffer vertical interpolator horizontal vertical up scaling up scaling VRAM horizontal Capture buffer controller RGB Video Output Display Controller Figure 8.1 Flow of image processing Non-interlace interpolation processing When VI of a video capture mode register (VCM) is 0, an interlace screen is interpolated vertically using the data in the same field. A screen is doubled vertically. When VI is 1, it is not interpolated vertically. Horizontal low-pass filter processing As a preprocessing when scaling down a picture horizontally, a low-pass filter can be covered horizontally. Regardless of scaling up and scaling down of a picture, ON/OFF is possible for a level low path filter (LPF). The horizontal low-pass filter consists of FIR filters of five taps. A coefficient is specified in the following register. CHLPF_Y Horizontal LPF Luminance element and RGB element coefficient code CHLPF_C Horizontal LPF chrominance element coefficient code The coefficient is specified by the coefficient code in two bits independently by luminance (Y) signal and chrominance (Cb and Cr) signals. The coefficient is a symmetric coefficient. MB86276 'LIME' GDC Specifications Rev1.1a 96 FUJITSU SEMICONDUCTOR CONFIDENTIAL CHLPF_x K0 K1 K2 K3 K4 00 0 0 1 0 0 01 0 1/4 2/4 1/4 0 10 0 3/16 10/16 3/16 0 11 3/32 8/32 10/32 10/32 3/32 Horizontal LPF becomes turning off (through) because of the setting of the coefficient code "00". Note: - In the case of Native RGB mode (NRGB=1), only a setup of CHLPF_Y code becomes effective. Down and Up scaling processing of horizontal direction Please set bit15-00 of capture scale register (CSC) to do the down and up scaling processing of horizontal direction. Horizontal direction is scaled down before writing in VRAM. Horizontal direction is scaled up after reading from VRAM. The interpolation filter processing of luminance (Y) signal is done by cubic interpolation (Cubic Interpolate) method. The interpolation filter processing of chrominance (Cb and Cr) signal is done by BiLinear interpolation (BiLinear Interpolate) method. The interpolation filter processing of Native-RGB signal is done by cubic interpolation (Cubic Interpolate) method. Vertical low-pass filter processing The low-pass filter can be put on the vertical direction as a preprocessing when the image is scaled down to the vertical direction. Vertical low-pass filter (LPF) can be set to turning on regardless of the scaling up or down of the vertical direction. A vertical low-pass filter is composed of the FIR filter of three taps. The coefficient is specified by the following register. CVLPF_Y Vertical LPF Luminance element and RGB element coefficient code CVLPF_C Vertical LPF chrominance element coefficient code The coefficient is specified by the coefficient code in two bits independently by luminance (Y) signal and chrominance (Cb and Cr) signals. The coefficient is a symmetric coefficient. MB86276 'LIME' GDC Specifications Rev1.1a 97 FUJITSU SEMICONDUCTOR CONFIDENTIAL CVLPF_x K0 K1 K2 00 0 1 0 01 1/4 2/4 1/4 10 3/16 10/16 3/16 11 Prohibition of setting Vertical LPF becomes turning off (through) because of the setting of the coefficient code "00". Note: - In the case of Native RGB mode (NRGB=1), only a setup of CVLPF_Y code becomes effective. Down and up scaling processing of Vertical direction Please set bit31-16 of capture scale register (CSC) to do the down and up scaling processing in the vertical direction. The vertical direction is scaled down before writing in VRAM. The vertical direction is scaled up after reading from VRAM. The interpolation filter processing of luminance (Y) signal is done by cubic interpolation (Cubic Interpolate) method. The interpolation filter processing of chrominance (Cb and Cr) signal is done by BiLinear interpolation (BiLinear Interpolate) method. The interpolation filter processing of Native-RGB signal is done by cubic interpolation (Cubic Interpolate) method. MB86276 'LIME' GDC Specifications Rev1.1a 98 FUJITSU SEMICONDUCTOR CONFIDENTIAL 8.4 External video signal input conditions 8.4.1 RTB656 YUV422 input format The ITU R.BT-656 format is widely used for digital transmission of NTSC and PAL signals. The format corresponds to YUV422. Interlaced video display signals can be captured and displayed noninterlaced with linear interpolation. When the VIE bit of the video capture mode register (VCM) is 1, LIME is able to capture video stream data from the 8-bit VI pin in synchronization with the CCLK clock. In this mode, only a digital video stream conforming to ITU-RBT656 can be processed. For this reason, a Y,Cb,Cr 4:2:2 format to which timing reference codes are added is used. The video stream is captured according to the timing reference codes; LIME automatically supports both NTSC and PAL. However, to detect error codes, set NTSC/PAL in the VS bit of VCM. If NTSC is not set, reference the number of data in the capture data count register (CDCN). If PAL is not set, reference the number of data in the capture data counter register (CDCP). If the reference data does not match the stream data, bit 4 to bit 0 of the video capture status register (VCS) will be values other than 00000. 1) RTB656 input format VI[7:0] Synchronous code and image data (Cb,Y,Cr,Y) are input as data of eight multiple bits synchronizing with 27MHz clock, and an valid pixel is transmitted while placed between a synchronous code named SAV and EAV. 4T VI[7:0] 4T Blanking data EAV SAV 80,10,80,10,80,. 8 bit Multiplexed video data EAV Cb,Y,Cr,Y,Cb,Y,Cr,Y,... .. H-BLANK 276T 288T ACTIVE-VIDEO 1440T [1440T] ACTIVE-VIDEO -LINE 1716T 1728T SAV : Beginning code of active video data (4 Byte) EAV : End code of active video data (4 Byte) T : 27MHz [ ] : 625/50 series (PAL) BLANKING BLANKING TIMING TIMING 720 PIXELS YUV4:2:2 DATA PERIOD PERIOD REF-CODE REF-CODE ... 80 10 FF 00 00 SAV Cb0 Y0 Cr0 Y1 Cb2 Y2 ... Cr718 Y719 FF 00 00 EAV 80 10 ... MB86276 'LIME' GDC Specifications Rev1.1a 99 FUJITSU SEMICONDUCTOR CONFIDENTIAL 2) RTB656 synchronous code (4 Byte) format SYNC code (static) Word Bit EAV/SAV first second third forth 7 1 0 0 1 (static) 6 1 0 0 F 0:first field 5 1 0 0 V 0:ACTIVE-VIDEO 1:VBI 4 1 0 0 H 0:SAV 1:EAV 3 1 0 0 P3 Guard bit 2 1 0 0 P2 Guard bit 1 1 0 0 P1 Guard bit 0 1 0 0 P0 Guard bit 1:second field 3) SAV/EAV timing base signal Bit 7 6 5 4 3 2 1 0 static F V H P3 P2 P1 P0 80 1 0 0 0 0 0 0 0 9D 1 0 0 1 1 1 0 1 AB 1 0 1 0 1 0 1 1 B6 1 0 1 1 0 1 1 0 C7 1 1 0 0 0 1 1 1 DA 1 1 0 1 1 0 1 0 EC 1 1 1 0 1 1 0 0 F1 1 1 1 1 0 0 0 1 Function 80 : SAV code of first field valid pixel period (Active-video) 9D : EAV code of first field valid pixel period (Active-video) AB : SAV code of first field vertical retrace line period B6 : EAV code of first field vertical retrace line period C7 : SAV code of second field valid pixel period (Active-video) DA : EAV code of second field valid pixel period (Active-video) EC : SAV code of second field vertical retrace line period F1 : EAV code of second field vertical retrace line period MB86276 'LIME' GDC Specifications Rev1.1a 100 FUJITSU SEMICONDUCTOR CONFIDENTIAL 8.4.2 RGB input format There are the two data-processing methods in RGB input video capture function. One is the method of processing with Native RGB. Another is the method of converting RGB into YUV422 by the internal RGB pre processor. RGB input function is suitable for relatively high speed non-interlaced video signals but the deinterlacing operation is not available in this mode. The maximum input rate is 66Mpixel/sec. RGB component data is 6bit. Note: - In Native RGB mode, NRGB=1 is set up. 1) RGB Input Signals The signals used for RGB video capture are not assigned dedicated terminals but share same pins with other functions. Name I/O Function RGBCLK Input Clock for RGB input RI5-0 Input Red component value GI5-0 Input Green component value BI5-0 Input Blue component value VSYNCI Input Vertical sync for RGB capture HSYNCI Input Horizontal sync for RGB capture Note : - input pins are shared with the ITU656 input and memory data bus. - the VIS bit of the VCM (video capture mode) register selects which mode (ITU656 or RGB) is used. 2) Captured Range Instead of embedded sync code method used in ITU656 mode, the capture range in RGB mode is specified by the following register parameters: a) RGB input mode of capture: Set RGB666 input flag(VIS) in VCM. In Native RGB mode, NRGB in VCM =1 is set up. b) HSYNC Cycle: Set the number of HSYNC Cycles in RGBHC. c) Horizontal Enable area: Set enables area start position and enable picture size into RGBHST and RGBHEN. d) Vertical Enable area: Set enables area start position and enable picture size into RGBVST and RGBVEN. The Captured area is defined according to the following parameters. Each parameter is set independently at the respective register.: MB86276 'LIME' GDC Specifications Rev1.1a 101 FUJITSU SEMICONDUCTOR CONFIDENTIAL RGBHC RGB input Hsync Cycle RGBHST RGB input Horizontal enable area STart position RGBHEN RGB input Horizontal enable area size RGBVST RGB input Vertical ENable area STart position RGBVEN RGB input Vertical ENable area size Note: The actual parameter settings are little different from the above. The details, please refer "Explanation of Registers". e) Convert Matrix Coefficient In order to change the color conversion matrix, set up RGBCMY, RGBCb, RGBCr and RGBCMb. Note: The maximum horizontal enable area size(RGBHEN) which can be captured is 840 pixels. This is the restriction by line buffer size in a video capture module. MB86276 'LIME' GDC Specifications Rev1.1a 102 FUJITSU SEMICONDUCTOR CONFIDENTIAL 3) Input Operation At the time of a RGB input, the synchronization of data is taken by VSYNC and SYNCI, which are inputted with Data RI, GI and BI. Input rule of HSYNCI The positive or negative edge of VINHSYNC is considered as a horizontal synchronization by register setup(HP). Input the signal of 1 or more RGBCLKs -(840+)RGBCLK cycle. RGBCLK More than 1 RGBCLK HSYNCI HSYNC(internal RGB input ~840RGBCLK+(HBLANK) function) Note: The maximum horizontal enable area size(RGBHEN) which can be captured is 840 pixels. This is the restriction by line buffer size in a video capture module. Valid data input rule to HSYNC The valid image data input rule to HSYNC is shown. Input data is inputted synchronizing with HSYNC of each line. (The synchronization of data needs to make a synchronization establish by HSYNC in each line unit. Since the sampling clock of image data is generated from HSYNC, it is because a clock may have jitter per line.) RGBCLK HSYNCI RGBHST captured RI5-0 GI5-0 BI5-0 MB86276 'LIME' GDC Specifications Rev1.1a 103 FUJITSU SEMICONDUCTOR CONFIDENTIAL Input rule of VINVSYNC A VSYNCI signal is synchronizing with HSYNCI. Moreover, VSYNCI is sampled by HSYNCI , and it considers as a VSYNC signal. Width is made into at least one line or more although a VSYNCI signal does not need to synchronize with HSYNC at this time. The positive or negative of VSYNCI is set to VSYNC by register setup(VP). ~840RGBCLK+RGBCLK HSYNC(internal RGB 1RGBCLK input function) More than 1 line VSYNCI Valid line input rule to VSYNC The valid image data input rule to VSYNC is shown. HSYNCI VSYNCI RG BVST MB86276 'LIME' GDC Specifications Rev1.1a 104 s tart to c apture FUJITSU SEMICONDUCTOR CONFIDENTIAL 4) Conversion Operation RGB input data is converted to YCbCr by the following matrix operation : Y= a11*R + a12*G + a13*B + b1 Cb= a21*R + a22*G + a23*B + b2 aij : 10bit signed real ( lower 8bit is fraction ) Cr= a31*R + a32*G + a33*B + b3 bi: 8bit unsigned integer Note: - registers can define each coefficient. - Cb and Cr components are reduced to half after this operation to form in 4:2:2 format. MB86276 'LIME' GDC Specifications Rev1.1a 105 FUJITSU SEMICONDUCTOR CONFIDENTIAL 8.5 Input Video Signal Parameter Setup A parameter setup of an input video signal changes with video formats inputted. A register to be set up is shown in the following figure. RGB666 VIS 0 1 ITU R.BT656 NRGB 0 1 RGB->YUV422 VS Native-RGB RGBHC RGBHC RGBHST RGBHST RGBHEN RGBHEN RGBVST RGBVST RGBVEN RGBVEN RM RM VP VP HP HP RGBCMY RGBCMY RGBCMCb RGBCMCr RGBCMb Figure 8.2 A register required for a setup according to format MB86276 'LIME' GDC Specifications Rev1.1a 106 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9 DRAWING PROCESSING 9.1 9.1.1 Coordinate System Drawing coordinates LIME GDC draws data in the drawing frame in the graphics memory that finally uses the drawing coordinates (device coordinates). Drawing frame is treated as 2D coordinates with the origin at the top left as shown in the figure below. The maximum coordinates is 4096 x 4096. Each drawing frame is located in the Graphics Memory by setting the address of the origin and resolution of X direction (size). Although the size of Y direction does not need to be set, Y coordinates which are max. at drawing must not be overlapped with other area. In addition, at drawing, specifying the clip frame (top left and bottom right coordinates) can prevent the drawing of images outside the clip frame. X (max. 4096) Drawing frame size Y Y (max. 4096) Origin Drawing frame size X (Xmin, Ymin) Clip frame (Xmax, Ymax) MB86276 'LIME' GDC Specifications Rev1.1a 107 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.1.2 Texture coordinates Texture coordinate is a 2D coordinate system represented as S and T (S: horizontal, T: vertical). Any integer in a range of -8192 to +8191 can be used as the S and T coordinates. The texture coordinates is correlated to the 2D coordinates of a vertex. One texture pattern can be applied to up to 4096 x 4096 pixels. The pattern size is set in the register. When the S and T coordinates exceed the maximum pattern size, the repeat, Clamp or border color option is selected. max. 4096 pixels Origin Texture pattern 9.1.3 max. 4096 pixels T (max. 8192) S (max. 8192) Frame buffer For drawing, the following area must be assigned to the Graphics Memory. The frame size (count of pixels on X direction) is common for these areas. Drawing frame The results of drawing are stored in the graphical image data area. Both the direct and indirect color mode are applicable. Z buffer (Optional function) Z buffer is required for eliminating hidden surfaces. In 16 bits mode, 2 bytes and in 8 bits mode, 1 byte are required per 1 pixel. Polygon drawing flag buffer This area is used for polygon drawing. 1 bit is required per 1 pixel. MB86276 'LIME' GDC Specifications Rev1.1a 108 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.2 Figure Drawing 9.2.1 Drawing primitives LIME GDC is supported the rendering command that is compatible with the LIME. The following types of figure drawing primitives are compatible with the LIME. Point Line Triangle 2DLine with XY setup 2DTriangle with XY setup Polygon 9.2.2 Polygon drawing function An irregular polygon (including concave shape) is drawn by hardware in the following manner: 1. Execute PolygonBegin command. Initialize polygon drawing hardware. 2. Draw vertices. Draw outline of polygon and plot all vertices to polygon draw flag buffer using 2D Triangle with XY setup. 3. Execute PolygonEnd command. Copy shape in polygon draw flag buffer to drawing frame and fill shape with color or specified tiling pattern. MB86276 'LIME' GDC Specifications Rev1.1a 109 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.2.3 Drawing parameters The triangles (Right triangle and Left triangle) are distinguished according to the locations of three vertices as follows (not used for 2D Triangle with XY setup): V0 V0 Upper edge Upper edge Long edge Upper triangle Upper triangle V1 V1 Lower edge V2 Long edge Lower edge Lower triangle Lower triangle V2 Left-hand triangle Right-hand triangle The following parameters are required for drawing triangles (for 2D Triangle with XY setup, X and Y coordinates of each vertex are specified). Ys Xs,Zs,Rs,Gs,Bs,Ss,Ts,Qs XUs Upper edge start Y coordinates dXUdy dXdy dZdy dRdy dGdy dBdy dSdy dTdy dQdy USN dZdx,dRdx,dGdx,dBdx, dSdx,dTdx,dQdx Lower edge start Y coordinates XLs dXLdy Note: LSN Be careful about the positional relationship between coordinates Xs, XUs, and XLs. For example, in the above diagram, when a right-hand triangle is drawn using the parameter that shows the coordinates positional relationship Xs (upper edge start Y coordinates) > XUs or Xs (lower edge start Y coordinates) > XLs, the appropriate picture may not be drawn. MB86276 'LIME' GDC Specifications Rev1.1a 110 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.2.4 Ys Y coordinates start position of long edge in drawing triangle Xs X coordinates start position of long edge corresponding to Ys XUs X coordinates start position of upper edge XLs X coordinates start position of lower edge Zs Z coordinates start position of long edge corresponding to Ys Rs R color value of long edge corresponding to Ys Gs G color value of long edge corresponding to Ys Bs B color value of long edge corresponding to Ys Ss S coordinate of textures of long edge corresponding to Ys Ts T coordinate of textures of long edge corresponding to Ys Qs Q perspective correction value of texture of long edge corresponding to Ys dXdy X DDA value of long edge direction dXUdy X DDA value of upper edge direction dXLdy X DDA value of lower edge direction dZdy Z DDA value of long edge direction dRdy R DDA value of long edge direction dGdy G DDA value of long edge direction dBdy B DDA value of long edge direction dSdy S DDA value of long edge direction dTdy T DDA value of long edge direction dQdy Q DDA value of long edge direction USN Count of spans of upper triangle LSN Count of spans of lower triangle dZdx Z DDA value of horizontal direction dRdx R DDA value of horizontal direction dGdx G DDA value of horizontal direction dBdx B DDA value of horizontal direction dSdx S DDA value of horizontal direction dTdx T DDA value of horizontal direction dQdx Q DDA value of horizontal direction Anti-aliasing function LIME GDC performs anti-aliasing to make jaggies less noticeable and smooth on line edges. To use this function at the edges of primitives, redraw the primitive edges with anti-alias lines. (The edge of line is blended with a frame buffer color at that time. Ideally please draw sequentially from father object.) MB86276 'LIME' GDC Specifications Rev1.1a 111 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.3 Bit Map Processing 9.3.1 BLT A rectangular shape in pixel units can be transferred. There are following types of transfer: 1. Transfer from host CPU to Drawing frame memory 2. Transfer between Graphics Memories including Drawing frame Concerning 1 and 2 above, 2-term logic operation is performed between source and destination data and its result can be stored. Setting a transparent color enables a drawing of a specific pixel with transmission. If part of the source and destination of the BLT field are physically overlapped in the display frame, the start address (from which vertex the BLT field to be transferred) must be set correctly. 9.3.2 Pattern data format LIME GDC can handle three bit map data formats: indirect color mode (8 bits/pixel), direct color mode (16 bits/pixel), and binary bit map (1 bit/pixel). The binary bit map is used for character/font patterns, where foreground color is used for bitmap = 1 pixel, and background color (background color can be set to be transparent by setting) is applied for bitmap = 0 pixels. MB86276 'LIME' GDC Specifications Rev1.1a 112 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.4 9.4.1 Texture Mapping Texture size LIME GDC reads texel corresponding to the specified texture coordinates (S, T), and draws that data at the correlated pixel position of the polygon. For the S and T coordinates, the selectable texture data size is any value in the range from 4 to 4096 pixels represented as an exponent of 2. 9.4.2 Texture color Drawing of 8-/16-bit direct color is supported for the texture pattern. For drawing 8-bit direct color, only point sampling can be specified for texture interpolation; only de-curl can be specified for the blend mode. 9.4.3 Texture Wrapping If a negative or larger than the specified texture pattern size is specified as the texture coordinates (S, T), according to the setting, one of these options (repeat, Clamp or border) is selected for the `out-ofrange' texture mapping. The mapping image for each case is shown below: Repeat Cramp Border Repeat This just simply masks the upper bits of the applied (S, T) coordinates. When the texture pattern size is 64 x 64 pixels, the lower 6 bits of the integer part of (S, T) coordinates are used for S and T coordinates. Clamp When the applied (S, T) coordinates is either negative or larger than the specified texture pattern size, Clamp the (S, T) coordinate as follows instead of texture: S<0 S > Texture X size - 1 S=0 S = Texture X size - 1 Border When the applied (S, T) coordinate is either negative or larger than the specified texture pattern size, the outside of the specified texture pattern is rendered in the `border' color. MB86276 'LIME' GDC Specifications Rev1.1a 113 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.4.4 Filtering LIME GDC supports two texture filtering modes: point filtering, and bi-linear filtering. Point filtering This mode uses the texture pixel specified by the (S, T) coordinates as they are for drawing. The nearest pixel in the texture pattern is chosen according to the calculated (S, T) coordinates. 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0 Bi-linear filtering The four nearest pixels specified with (S, T) coordinate are blended according to the distance from specified point and used in drawing. 0.5 1.0 1.5 2.0 0.0 C00 C10 0.5 1.0 1.5 2.0 9.4.5 C01 C11 8.4.5 Texture blending LIME GDC supports the following three blend modes for texture mapping: Decal This mode displays the selected texture pixel color regardless of the polygon color. Modulate This mode multiplies the native polygon color (CP) and selected texture pixel color (CT) and the result is used for drawing. Rendering color is calculated as follows (CO): C0 = CT x CP Stencil This mode selects the display color from the texture color with MSB as a flag. MSB = 1: Texture color MSB = 0: Polygon color MB86276 'LIME' GDC Specifications Rev1.1a 114 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.5 9.5.1 Rendering Tiling Tiling reads the pixel color from the correlated tiling pattern and maps it onto the polygon. The tiling determines the pixel on the pattern read by pixel coordinates to be drawn, irrespective of position and size of primitive. Since the tiling pattern is stored in the texture memory, this function and texture mapping cannot be used at the same time. Also, the tiling pattern size is limited to within 64 x 64 pixels. (at 16-bit color) Example of Tiling 9.5.2 Alpha blending Alpha blending blends the drawn in frame buffer to-be-drawn pixel or pixel already according to the alpha value set in the alpha register. This function cannot be used simultaneously with logic operation drawing. It can be used only when the direct color mode (16 bits/pixel) is used. The blended color C is calculated as shown below when the color of the pixel to be drawn is CP, the color of frame buffer is CF, and the alpha value is A: C = CP x A + (1-A) x CF The alpha value is specified as 8-bit data. 00h means alpha value 0% and FFh means alpha value 100%. When the texture mapping function is enabled, the following blending modes can be selected: Normal Blends post texture mapping color with frame buffer color Stencil Uses MSB of texel color for ON/OFF control: MSB = 1: Texel color MSB = 0: Frame buffer color Stencil alpha Uses MSB of texel color for /OFF control: MSB = 1: Alpha blend texel color and current frame buffer color MSB = 0: Frame buffer color Note: MSB of frame buffer is drawn MSB of texel in both stencil and stencil alpha mode. Therefore in case MSB of texel is MSB=0, a color of frame buffer is frame buffer, but MSB of frame buffer is set to 0. MB86276 'LIME' GDC Specifications Rev1.1a 115 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.5.3 Logic operation This mode executes a logic operation between the pixel to be drawn and the one already drawn in frame buffer and its result is drawn. Alpha blending cannot be used when this function is specified. Type CLEAR COPY NOP SET COPY INVERTED INVERT AND REVERSE OR REVERSE 9.5.4 ID 0000 0011 0101 1111 1100 1010 0010 1011 Operation 0 S D 1 !S !D S & !D S | !D Type AND OR NAND NOR XOR EQUIV AND INVERTED OR INVERTED ID 0001 0111 1110 1000 0110 1001 0100 1101 Operation S&D S|D ! (S & D) ! (S | D) S xor D ! (S xor D) !S & D !S | D Hidden plane management (Optional function) LIME GDC supports the Z buffer for hidden plane management. This function compares the Z value of a new pixel to be drawn and the existing Z value in the Z buffer. Display/not display is switched according to the Z-compare mode setting. Define the Z-buffer access options in the ZWRITEMASK mode. The Z compare operation type is determined by the Z compare mode. Either 16 or 8 bits can be selected for the Z-value. ZWRITEMASK 1 0 Compare Z values, no Z value write overwrite Compare Z values, Z value write Z Compare mode NEVER ALWAYS LESS LEQUAL EQUAL GEQUAL GREATER NOTEQUAL Code 000 001 010 011 100 101 110 111 Condition Never draw Always draw Draw if pixel Z value < current Z buffer value Draw if pixel Z value current Z buffer value Draw if pixel Z value = current Z buffer value Draw if pixel Z value current Z buffer value Draw if pixel Z value > current Z buffer value Draw if pixel Z value ! = current Z buffer value MB86276 'LIME' GDC Specifications Rev1.1a 116 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.6 Drawing Attributes 9.6.1 Line drawing attributes In drawing lines, the following attributes apply: Line Drawing Attributes Drawing Attribute Description Line width Line width selectable in range of 1 to 32 pixels Broken line Specify broken line pattern in 32-bit data Anti-alias Line edge smoothed when anti-aliasing enabled 9.6.2 Triangle drawing attributes In drawing triangles, the following attributes apply (these attributes are disabled in 2DTriangle with XY setup). Texture mapping and tiling have separated texture attributes: Triangle Drawing Attributes Drawing Attribute Description Shading Gouraud shading or flat shading selectable Alpha blending Set alpha blending enable/disable per polygon Alpha blending coefficient Set color blending ratio of alpha blending MB86276 'LIME' GDC Specifications Rev1.1a 117 FUJITSU SEMICONDUCTOR CONFIDENTIAL 9.6.3 Texture attributes In texture mapping, the following attributes apply: Texture Attributes Drawing Attribute Description Texture mode Select either texture mapping or tiling Texture filter Select either point sampling or bi-linear filtering Texture coordinates correction Select either linear or perspective correction Texture wrap Select either repeat or Clamp of texture pattern Texture blend mode Select either decal or modulate 9.6.4 BLT attributes In BLT drawing, the following attributes apply: BLT Attributes Drawing Attribute Description Logic operation mode Specify two source logic operation mode Transparency mode Set transparent copy mode and transparent color Alpha map mode Blend a color according to alpha map 9.6.5 Character pattern drawing attributes Character Pattern Drawing Drawing Attribute Character pattern enlarge/shrink Description Vertical and Horizontal x 2, Horizontal x 2, Vertical and Horizontal x 1/2, Horizontal x 1/2 Character pattern color Set character color and background color Transparency/non-transparency Set background color to transparency/non-transparency MB86276 'LIME' GDC Specifications Rev1.1a 118 FUJITSU SEMICONDUCTOR CONFIDENTIAL 10 DISPLAY LIST 10.1 Overview Display list is a set of display list commands, parameters and pattern data. All display list commands stored in a display list are executed consequently. The display list is transferred to the display list FIFO by the following method: Transfer from graphics memory to display FIFO by register setting Display list Command-1 Data 1-1 Data 1-2 Data 1-3 Display list Command-2 Data 2-1 Data 2-2 Data 2-3 Display List MB86276 'LIME' GDC Specifications Rev1.1a 119 FUJITSU SEMICONDUCTOR CONFIDENTIAL 10.1.1 Header format The format of the display list header is shown below. Format List Format Format 1 Format 2 Format 3 Format 4 Format 5 Format 6 Format 7 Format 8 Format 9 Format 10 31 24 23 Type Type Type Type Type Type Type Type Type Type Type Format 11 16 15 0 Reserved Count Reserved Reserved Command Command Command Command Reserved Reserved Reserved Reserved Address Reserved Reserved Reserved Count Reserved Reserved Reserved Count Reserved Count Description of Each Field Type Command Count Address Vertex Flag Display list type Command Count of data excluding header Address value used at data transfer Vertex number Attribute flag peculiar to display list command Vertex Number Specified in Vertex Code Vertex 00 01 10 11 Vertex number (Line) V0 V1 Setting prohibited Setting prohibited MB86276 'LIME' GDC Specifications Rev1.1a 120 Vertex number (Triangle) V0 V1 V2 Setting prohibited Vertex Flag Vertex Vertex Flag Vertex Flag FUJITSU SEMICONDUCTOR CONFIDENTIAL 10.2 Rendering Command 10.2.1 Command list The following table lists LIME GDC rendering commands and their command codes. Type Command Description Nop No operation Interrupt Interrupt request to host CPU Sync Synchronization with events SetRegister Sets data to register PolygonEnd Sets data to 2D Triangle with XY setup vertex register Initializes border rectangle calculation of multiple vertices random shape Clears polygon flag after drawing polygon Flush_FB/Z Flushes drawing pipelines DrawPixel Pixel Draws point DrawPixelZ PixelZ Draws point with Z Xvector Draws line (principal axis X) Yvector Draws line (principal axis Y) AntiXvector Draws line with anti-alias option (principal axis X) AntiYvector Draws line with anti-alias option (principal axis Y) ZeroVector Draws 2D Line with XY setup (with vertex 0 as starting point) OneVector Draws 2D Line with XY setup (with vertex 1 as starting point) TrapRight Draws right triangle Normal SetVertex2i PolygonBegin Draw DrawLine DrawLine2i DrawLine2iP DrawTrap DrawVertex2i DrawVertex2iP DrawRectP DrawBitmapP DrawBitmapLargeP BltCopyP BltCopyAlternateP LoadTextureP BltTextureP BltCopyAltAlphaBlendP TrapLeft Draws left triangle TriangleFan Draws 2D Triangle with XY setup FlagTriangleFan Draws 2D Triangle with XY setup for multiple vertices random shape BltFill Draws rectangle with single color ClearPolyFlag Clears polygon flag buffer BltDraw Draws Blt (16-bit) Bitmap Draws binary bit map (character) BltDraw Draws Blt (32-bit) TopLeft Blt transfer from top left coordinates TopRight Blt transfer from top right coordinates BottomLeft Blt transfer from bottom left coordinates BottomRight Blt transfer from bottom right coordinates LoadTexture Loads texture pattern LoadTILE Loads tile pattern LoadTexture Loads texture pattern from local memory LoadTILE Loads tile pattern from local memory MB86276 'LIME' GDC Specifications Rev1.1a Alpha blending is supported (see the alpha map). BltCopyAlternateP 121 FUJITSU SEMICONDUCTOR CONFIDENTIAL Type Code Table Type Code DrawPixel 0000_0000 DrawPixelZ 0000_0001 DrawLine 0000_0010 DrawLine2i 0000_0011 DrawLine2iP 0000_0100 DrawTrap 0000_0101 DrawVertex2i 0000_0110 DrawVertex2iP 0000_0111 DrawRectP 0000_1001 DrawBitmapP 0000_1011 BitCopyP 0000_1101 BitCopyAlternateP 0000_1111 LoadTextureP 0001_0001 BltTextureP 0001_0011 BltCopyAltAlphaBlendP 0001_1111 SetVertex2i 0111_0000 SetVertex2iP 0111_0001 Draw 1111_0000 SetRegister 1111_0001 Sync 1111_1100 Interrupt 1111_1101 Nop 1111_1111 MB86276 'LIME' GDC Specifications Rev1.1a 122 FUJITSU SEMICONDUCTOR CONFIDENTIAL Command Code Table (1) Command Code Pixel 000_00000 PixelZ 000_00001 Xvector 001_00000 Yvector 001_00001 XvectorNoEnd 001_00010 YvectorNoEnd 001_00011 XvectorBlpClear 001_00100 YvectorBlpClear 001_00101 XvectorNoEndBlpClear 001_00110 YvectorNoEndBlpClear 001_00111 AntiXvector 001_01000 AntiYvector 001_01001 AntiXvectorNoEnd 001_01010 AntiYvectorNoEnd 001_01011 AntiXvectorBlpClear 001_01100 AntiYvectorBlpClear 001_01101 AntiXvectorNoEndBlpClear 001_01110 AntiYvectorNoEndBlpClear 001_01111 ZeroVector 001_10000 Onevector 001_10001 ZeroVectorNoEnd 001_10010 OnevectorNoEnd 001_10011 ZeroVectorBlpClear 001_10100 OnevectorBlpClear 001_10101 ZeroVectorNoEndBlpClear 001_10110 OnevectorNoEndBlpClear 001_10111 AntiZeroVector 001_11000 AntiOnevector 001_11001 AntiZeroVectorNoEnd 001_11010 AntiOnevectorNoEnd 001_11011 AntiZeroVectorBlpClear 001_11100 AntiOnevectorBlpClear 001_11101 AntiZeroVectorNoEndBlpClear 001_11110 AntiOnevectorNoEndBlpClear 001_11111 MB86276 'LIME' GDC Specifications Rev1.1a 123 FUJITSU SEMICONDUCTOR CONFIDENTIAL Command Code Table (2) Command Code BltFill 010_00001 BltDraw 010_00010 Bitmap 010_00011 TopLeft 010_00100 TopRight 010_00101 BottomLeft 010_00110 BottomRight 010_00111 LoadTexture 010_01000 LoadTILE 010_01001 TrapRight 011_00000 TrapLeft 011_00001 TriangleFan 011_00010 FlagTriangleFan 011_00011 Flush_FB 110_00001 Reserved 110_00010 PolygonBegin 111_00000 PolygonEnd 111_00001 ClearPolyFlag 111_00010 Normal 111_11111 MB86276 'LIME' GDC Specifications Rev1.1a 124 FUJITSU SEMICONDUCTOR CONFIDENTIAL 10.2.2 Details of rendering commands All parameters belonging to their command are stored in relevant registers. The definition of each parameter is explained in the section of each command. Nop (Format1) 31 24 23 Nop 16 15 0 Reserved Reserved No operation Interrupt (Format1) 31 24 23 Interrupt 16 15 0 Reserved Reserved The Interrupt command generates interrupt request to host CPU. Sync (Format9) 31 24 23 Sleep 16 15 Reserved 4 Reserved 0 flag The Sync command suspends all subsequent display list processing until event set in flag detected. Flag: Bit number Bit field name Bit 0 4 Reserved 3 Reserved VBLANK VBLANK Synchronization 0 No operation 1 Wait for VSYNC detection MB86276 'LIME' GDC Specifications Rev1.1a 125 2 Reserved 1 Reserved 0 VBLANK FUJITSU SEMICONDUCTOR CONFIDENTIAL SetRegister (Format2) 31 24 23 SetRegister 16 15 Count 0 Address (Val 0) (Val 1) (Val n) The SetRegister command sets data to sequential registers. Count: Data word count (in double-word unit) Address: Register address Set the value of the address for SetRegister given in the register list. When transferring two or more data, set the starting register address. SetVertex2i (Format8) 31 24 23 SetVertex2i 16 15 Command 4 3 2 1 0 Reserved flag vertex Xdc Ydc The SetVertex2i command sets vertices data for 2D Line with XY setup or 2D Triangle with XY setup to registers. Commands: Flag: Normal Sets vertex data (X, Y). PolygonBegin Starts calculation of circumscribed rectangle for random shape to be drawn. Calculate vertices of rectangle including all vertices of random shape defined between PolygonBegin and PolygonEnd. Not used SetVertex2iP (Format8) 31 24 23 SetVertex2i 16 15 Command 4 3 2 1 0 Reserved Ydc flag vertex Xdc The SetVertex2iP command sets vertices data for 2D Line with XY setup or 2D Triangle with XY setup to registers. Only the integer (packed format) can be used to specify these vertices. Commands: Flag: Normal Sets vertices data. PolygonBegin Starts calculation of circumscribed rectangle of random shape to be drawn. Calculate vertices of rectangle including all vertices of random shape defined between PolygonBegin and PolygonEnd. Not used MB86276 'LIME' GDC Specifications Rev1.1a 126 FUJITSU SEMICONDUCTOR CONFIDENTIAL Draw (Format5) 31 24 23 Draw 16 15 Command 0 Reserved The Draw command executes drawing command. All parameters required for drawing command execution must be set at their appropriate registers. Commands: PolygonEnd Draws polygon end. Fills random shape with color according to flags generated by FlagTriangleFan command and information of circumscribed rectangle generated by PolygonBegin command. Flush_FB Flushes drawing data in the drawing pipeline into the graphics memory. Place this command at the end of the display list. Flush_Z Flushes Z value data in the drawing pipeline into the graphics memory. When using the Z buffer, place this command together with the Flush_FB command at the end of the display list. DrawPixel (Format5) 31 24 23 DrawPixel 16 15 Command 0 Reserved PXs PYs The DrawPixel command draws pixel. Command: Pixel Draws pixel without Z value. DrawPixelZ (Format5) 31 24 23 DrawPixel 16 15 Command PXs PYs PZs The DrawPixelZ command draws pixel with Z value. Command: PixelZ Draws pixel with Z value. MB86276 'LIME' GDC Specifications Rev1.1a 0 Reserved 127 FUJITSU SEMICONDUCTOR CONFIDENTIAL DrawLine (Format5) 31 24 23 DrawLine 16 15 Command 0 Reserved LPN LXs LXde LYs LYde The DrawLine command draws line. registers. It starts drawing after setting all parameters at line draw Commands: Xvector Draws line (principal axis X). Yvector Draws line (principal axis Y). XvectorNoEnd Draws line (principal axis X, and without end point drawing). YvectorNoEnd Draws line (principal axis Y, and without end point drawing). XvectorBlpClear Draws line (principal axis X, and prior to drawing, broken line pattern reference position cleared). YvectorBlpClear Draws line (principal axis Y, and prior to drawing, broken line pattern reference position cleared). XvectorNoEndBlpClear Draws line (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). YvectorNoEndBlpClear Draws line (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiXvector Draws anti-alias line (principal axis X). AntiYvector Draws anti-alias line (principal axis Y). AntiXvectorNoEnd Draws anti-alias line (principal axis X, and without end point drawing). AntiYvectorNoEnd Draws anti-alias line (principal axis Y, and without end point drawing). AntiXvectorBlpClear Draws anti-alias line (principal axis X and prior to drawing, broken line pattern reference position cleared). AntiYvectorBlpClear Draws anti-alias line (principal axis Y and prior to drawing, broken line pattern reference position cleared). AntiXvectorNoEndBlpClear Draws anti-alias line (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiYvectorNoEndBlpClear Draws anti-alias line (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). MB86276 'LIME' GDC Specifications Rev1.1a 128 FUJITSU SEMICONDUCTOR CONFIDENTIAL DrawLine2i (Format7) 31 24 23 DrawLine2i 16 15 Command 0 Reserved 0 0 LFXs LFYs vertex The DrawLine2i command draws 2DLine with XY setup. It starts drawing after setting parameters at the 2DLine with XY setup drawing registers. Integer data can only be used for coordinates. Commands: ZeroVector Draws line from vertex 0 to vertex 1. OneVector Draws line from vertex 1 to vertex 0. ZeroVectorNoEnd Draws line from vertex 0 to vertex 1 (without drawing end point). OneVectorNoEnd Draws line from vertex 1 to vertex 0 (without drawing end point). ZeroVectorBlpClear Draws line from vertex 0 to vertex 1 (principal axis X, and prior to drawing, broken line pattern reference position cleared). OneVectorBlpClear Draws line from vertex 1 to vertex 0 (principal axis Y, and prior to drawing, broken line pattern reference position cleared). ZeroVectorNoEndBlpClear Draws line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). OneVectorNoEndBlpClear Draws line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiZeroVector Draws anti-alias line from vertex 0 to vertex 1. AntiOneVector Draws anti-alias line from vertex 1 to vertex 0. AntiZeroVectorNoEnd Draws anti-alias line from vertex 0 to vertex 1 (without end point). AntiOneVectorNoEnd Draws anti-alias line from vertex 1 to vertex 0 (without end point). AntiZeroVectorBlpClear Draws anti-alias line from vertex 0 to vertex 1 (principal axis X and prior to drawing, broken line pattern reference position cleared). AntiOneVectorBlpClear Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y and prior to drawing, broken line pattern reference position cleared). AntiZeroVectorNoEndBlpClear Draws anti-alias line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiOneVectorNoEndBlpClear Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). MB86276 'LIME' GDC Specifications Rev1.1a 129 FUJITSU SEMICONDUCTOR CONFIDENTIAL DrawLine2iP (Format7) 31 24 23 DrawLine2iP 16 15 Command 0 Reserved LFXs LFYs vertex The DrawLine2iP command draws high-speed 2DLine. It starts drawing after setting parameters at high-speed 2DLine drawing registers. Only packed integer data can be used for coordinates. Commands: ZeroVector Draws line from vertex 0 to vertex 1. OneVector Draws line from vertex 1 to vertex 0. ZeroVectorNoEnd Draws line from vertex 0 to vertex 1 (without drawing end point). OneVectorNoEnd Draws line from vertex 1 to vertex 0 (without drawing end point). ZeroVectorBlpClear Draws line from vertex 0 to vertex 1 (principal axis X, and prior to drawing, broken line pattern reference position cleared). OneVectorBlpClear Draws line from vertex 1 to vertex 0 (principal axis Y, and prior to drawing, broken line pattern reference position cleared). ZeroVectorNoEndBlpClear Draws line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). OneVectorNoEndBlpClear Draws line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiZeroVector Draws anti-alias line from vertex 0 to vertex 1. AntiOneVector Draws anti-alias line from vertex 1 to vertex 0. AntiZeroVectorNoEnd Draws anti-alias line from vertex 0 to vertex 1 (without end point). AntiOneVectorNoEnd Draws anti-alias line from vertex 1 to vertex 0 (without end point). AntiZeroVectorBlpClear Draws anti-alias line from vertex 0 to vertex 1 (principal axis X and prior to drawing, broken line pattern reference position cleared). AntiOneVectorBlpClear Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y and prior to drawing, broken line pattern reference position cleared). AntiZeroVectorNoEndBlpClear Draws anti-alias line from vertex 0 to vertex 1 (principal axis X, without end point drawing and prior to drawing, broken line pattern reference position cleared). AntiOneVectorNoEndBlpClear Draws anti-alias line from vertex 1 to vertex 0 (principal axis Y, without end point drawing and prior to drawing, broken line pattern reference position cleared). MB86276 'LIME' GDC Specifications Rev1.1a 130 FUJITSU SEMICONDUCTOR CONFIDENTIAL DrawTrap (Format5) 31 24 23 DrawTrap 16 15 0 Command Reserved 0 Ys Xs DXdy XUs DXUdy XLs DXLdy USN LSN 0 0 The DrawTrap command draws Triangle. It starts drawing after setting parameters at the Triangle Drawing registers (coordinates). Commands: TrapRight Draws right triangle. TrapLeft Draws left triangle. DrawVertex2i (Format7) 31 24 23 DrawVertex2i 16 15 Command 0 Reserved 0 0 Xdc Ydc vertex The DrawVertex2i command draws 2D Triangle with XY setup It starts triangle drawing after setting parameters at 2D Triangle Drawing registers. Commands: TriangleFan Draws 2D Triangle with XY setup. FlagTriangleFan Draws 2D Triangle with XY setup for polygon drawing in the flag buffer. DrawVertex2iP (Format7) 31 24 23 DrawVertex2iP 16 15 Command 0 Reserved Xdc Ydc vertex The DrawVertex2iP command draws 2D Triangle with XY setup. It starts drawing after setting parameters at 2D Triangle with XY setup Drawing registers Only the packed integer format can be used for vertex coordinates. Commands: TriangleFan Draw 2D Triangle with XY setup. FlagTriangleFan Draws 2D Triangle with XY setup for polygon drawing in the flag buffer. MB86276 'LIME' GDC Specifications Rev1.1a 131 FUJITSU SEMICONDUCTOR CONFIDENTIAL DrawRectP (Format5) 31 24 23 DrawRectP 16 15 Command 0 Reserved RXs RsizeX RYs RsizeY The DrawRectP command fills rectangle. The rectangle is filled with the current color after setting parameters at the rectangle registers. Please set XRES(X resolution) to in 8 byte units when using this command. Only the BitBlt command allows XRES to be in 8-byte units or boundary. For all other purposes, XRES has to be in 64-byte units. Therefore, unless BitBlt is the only rendering engine function being used, XRES must be set in 64-byte units. In general, it is also recommended for XRES to be in 64-byte units. Commands: BltFill Fills rectangle with current color (single). ClearPolyFlag Fills polygon drawing flag buffer area with 0. The size of drawing frame is defined in RsizeX,Y. Must set RXs[3:0] and RsizeX[3:0] as 0000. (16pixel aligned) Drawing clipping is not work for this command. DrawBitmapP (Format6) 31 24 23 DrawBitmapP 16 15 Command 0 Count RXs RsizeX RYs RsizeY (Pattern 0) (Pattern 1) (Pattern n) The DrawBitmapP command draws rectangle patterns. Please set XRES(X resolution) to in 8 byte units when using this command. Commands: BltDraw Draws rectangle of 8 bits/pixel or 16 bits/pixel. DrawBitmap Draws binary bitmap character pattern. Bit 0 is drawn in transparent or background color, and bit 1 is drawn in foreground color. DrawBitmapLargeP (Format11) 31 24 23 DrawBitmapLargeP 16 15 Command 0 Reserved Count Rys RsizeY Rxs RsizeX (Pattern 0) (Pattern 1) (Pattern n) The DrawBitmapP command draws rectangle patterns. The parameter(count field) could be used up to 32-bit(*1) unlike DrawBitmapP. (*1: The data format of counter field is signed long. Thus actually it is possible to use up to 31-bit.) Please set XRES(X resolution) to in 8 byte units when using this command. Commands: BltDraw Draws rectangle of 8 bits/pixel or 16 bits/pixel. MB86276 'LIME' GDC Specifications Rev1.1a 132 FUJITSU SEMICONDUCTOR CONFIDENTIAL BltCopyP (Format5) 31 24 23 BltCopyP 16 15 Command 0 Reserved SRXs DRXs BRsizeX SRYs DRYs BRsizeY The BltCopyP command copies rectangle pattern within drawing frame. Please set XRES(X resolution) to in 8 byte units when using this command. Only the BitBlt command allows XRES to be in 8-byte units or boundary. For all other purposes, XRES has to be in 64-byte units. Therefore, unless BitBlt is the only rendering engine function being used, XRES must be set in 64-byte units. In general, it is also recommended for XRES to be in 64-byte units. Commands: TopLeft Starts BitBlt transfer from top left coordinates. TopRight Starts BitBlt transfer from top right coordinates. BottomLeft Starts BitBlt transfer from bottom left coordinates. BottomRight Starts BitBlt transfer from bottom right coordinates. BltCopyAlternateP (Format5) 31 24 23 BltCopyAlternateP 16 15 Command 0 Reserved SADDR SStride SRYs SRXs DADDR DStride DRYs BRsizeY DRXs BRsizeX The BltCopyAlternateP command copies rectangle between two separate drawing frames. Please set XRES(X resolution) to in 8 byte units when using this command. And please set SStride and DStride to in 8 byte units. Command: TopLeft Starts BitBlt transfer from top left coordinates. Drawing clipping is not wok for this command. MB86276 'LIME' GDC Specifications Rev1.1a 133 FUJITSU SEMICONDUCTOR CONFIDENTIAL BltCopyAltAlphaBlendP (Format5) 31 24 23 BltCopyAlternateP 16 15 Command 0 Reserved SADDR SStride SRYs SRXs BlendStride BlendRYs DRYs BRsizeY BlendRXs DRXs BRsizeX The BltCopyAltAlphaBlendP command performs alpha blending for the source (specified using SADDR, SStride, SRXs, SRXy) and the alpha map (specified using ABR (alpha base address), BlendStride, BlendRXs, BlendRYs) and then copies the result of the alpha blending to the destination (specified using FBR (frame buffer base address), XRES (X resolution), DRXs, and DRYs). Please set XRES(X resolution) to in 8 byte units when using this command. And please set SStride and BlendStride to in 8 byte units. Only the BitBlt command allows XRES to be in 8-byte units or boundary. For all other purposes, XRES has to be in 64-byte units. Therefore, unless BitBlt is the only rendering engine function being used, XRES must be set in 64-byte units. In general, it is also recommended for XRES to be in 64-byte units. Command: reserved Set 0000_0000 to maintain future compatibility. MB86276 'LIME' GDC Specifications Rev1.1a 134 FUJITSU SEMICONDUCTOR CONFIDENTIAL 11 GDC Register MAP Terms appeared in this chapter are explained below: 1. Register address Indicates address of register 2. Bit number Indicates bit number 3. Bit field name Indicates name of each bit field included in register 4. R/W Indicates access attribute (read/write) of each field Each symbol shown in this section denotes the following: R0 "0" always read at read. Write access is Don't care. W0 Only "0" can be written. R Read enabled W Write enabled RX Read enabled (read values undefined) RW Read and write enabled RW0 Read and write 0 enabled 5. Initial value Indicates initial value of immediately before the reset of each bit field. 6. Handling of reserved bits Reserved bits should write "0". MB86276 'LIME' GDC Specifications Rev1.1a 135 FUJITSU SEMICONDUCTOR CONFIDENTIAL 11.1 Local memory register list 11.1.1 Host interface register list 27 26 25 24 23 22 21 20 19 18 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DTC 000 DTC DST DRM DST 004 16 DSU LTS DTS LTS 008 DW 28 DBM 29 DTS 30 DNA 31 DRM Offset DAM Base = HostBase LSTA LSTA 010 DRQ DRQ 018 IST 020 IST IMASK 024 IMASK SRST SRST 02C CCF COT 038 LSA 040 LSA LCO 044 LCO LREQ LREQ 048 RSW 500 504 508 MB86276 'LIME' GDC Specifications Rev1.1a RSW 05C DMA_ST_ADR DMA_ST_ADR DMA_ED_ADR DMA_ED_ADR ERR_ADR ERR_ADR 136 FUJITSU SEMICONDUCTOR CONFIDENTIAL Offset 31 30 29 28 27 26 25 24 23 22 50C 510 514 MB86276 'LIME' GDC Specifications Rev1.1a 21 20 19 18 17 16 15 14 13 ERR_DETECT INT_MSK XINT_ACT 137 12 11 10 9 8 7 6 5 4 3 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 11.1.2 I2C interface register list Base = I2CBase Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 000 Reserved BSR 004 Reserved BCR 008 Reserved CCR 00C Reserved ADR 010 Reserved DAR 014 Access Prohibitation 018 Access Prohibitation 01C Access Prohibitation MB86276 'LIME' GDC Specifications Rev1.1a 138 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 11.1.3 GPIO register list Base = PIOBase Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOC1 40 GPIO_is_out GPIO_inout GPIOC2 44 GPIO_force GPIO_xor PIC1 S1 RTO WTO OFE 4C GPIO_INT_enable PIC2 50 GPIO_INT_polarity PIC3 54 GPIO_INT_mode PIST S1 RTO WTO 11.1.4 OFE 80 GPIO_INT_status Graphics memory interface register list Base = HostBase Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 MB86276 'LIME' GDC Specifications Rev1.1a 139 RTS SAW ASW LOWD TRAS TRCD TRC TRP TRRD I TWR MMR FFFC CL 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 11.1.5 Display controller register list 3 2 SF ESY SYNC ESY 8 SF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 EEQ Offset EEQ Base = DisplayBase 7 6 5 4 1 0 SYNC L0E CKS L1E L23E DEN L45E DCM0 (Display Control Mode 0) 000 SC CKS L0E L1E L2E L3E L4E L5E 100 DEN DCM1 (Display Control Mode 1) SC RUF HTP (H Total Pixels) 008 HDB (H Display Boundary) 00C VSW DCKinv POM 004 DCKed DCM3 (Display Control Mode 3) 108 DCKD Reserved HDP (H Display Period) HSW HSP (H Sync pulse Position) 010 VTR (V Total Rasters) 014 VDP (V Display Period) VSP (V Sync pulse Position) 018 WY (Window Y) WX (Window X) 01C WH (Window Height) WW (Window Width) MB86276 'LIME' GDC Specifications Rev1.1a Reserved 140 RUM0 DCM2 (Display Control Mode 2) 104 FUJITSU SEMICONDUCTOR CONFIDENTIAL 020 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L0M (L0 Mode) L0C Offset L0W (L0 memory Width) 024 L0H (L0 Height) L0OA0 (L0 Origin Address 0) 028 L0DA0 (L0 Display Address 0) 02C L0DY (L0 Display Y) L0DX (L0 Display X) L0WP L0EM (L0 Extend Mode) 110 L0PB L0EC 114 L0WY (L0 Window Y) L0WX (L0 Window X) 118 L0WH (L0 Window Height) L0WW (L0 Window Width) L1IM L1CS L1C L1M (L1 Mode) L1YC 030 L1W (L1 memory Width) L1OA0(L1 Origin Address 0) / CBDA0(Capure Buffer Display Address 0) CBDA1 ( Capture Buffer Display Address 1) 034 038 L1EM (L1 Extend Mode) 120 L1EC L1DM L1PB 124 L1WY (L1 Window Y) L1WX (L1 Window X) 128 L1WH (L1 Window Height) L1WW (L1 Window Width) L2M (L2 Mode) L2C 040 L2FLP L2W(L2 memory Width) L2H (L2 Height) 044 L2OA0 (L2 Origin Address 0) 048 L2DA0 (L2 Display Address 0) 04C L2OA1 (L2 Origin Address 1) 050 L2DA1 (L2 Display Address 1) 054 L2DY (L2 Display Y) L2DX (L2 Display X) L2EC L2PB 134 L2WY (L2 Window Y) L2WX (L2 Window X) 138 L2WH (L2 Window Height) L2WW (L2 Window Width) MB86276 'LIME' GDC Specifications Rev1.1a 141 L2WP 130 L2OM L2EM (L2 Extend Mode) FUJITSU SEMICONDUCTOR CONFIDENTIAL 058 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L3M (L3 Mode) L3C Offset L3FLP L3W (L3 memory Width) L3H (L3 Height) 05C L3OA0 (L3 Origin Address 0) 060 L3DA0 (L3 Display Address 0) 064 L3OA1 (L3 Origin Address 1) 068 L3DA1 (L3 Display Address 1) 06C L3DY (L3 Display Y) L3DX (L3 Display X) L3PB 144 L3WY (L3 Window Y) L3WX (L3 Window X) 148 L3WH (L3 Window Height) L3WW (L3 Window Width) L4M (L4 Mode) L4C 070 L3WP L3EC L3OM L3EM (L3 Extend Mode) 140 L4FLP L4W (L4 memory Width) L4H (L4 Height) 074 L4OA0 (L4 Origin Address 0) 078 L4DA0 (L4 Display Address 0) 07C L4OA1 (L4 Origin Address 1) 080 L4DA1 (L4 Display Address 1) 084 L4DY (L4 Display Y) L4DX (L4 Display X) L4WX (L4 Window X) 158 L4WH (L4 Window Height) L4WW (L4 Window Width) L5M (L5 Mode) L5C 088 L4WP L4WY (L4 Window Y) L4OM 154 L5WP L4EC L5OM L4EM (L4 Extend Mode) 150 L5FLP L5W (L5 memory Width) L5H (L5 Height) 08C L5OA0 (L5 Origin Address 0) 090 L5DA0 (L5 Display Address 0) 094 L5OA1 (L5 Origin Address 1) 098 L5DA1 (L5 Display Address 1) 09C L5DY (L5 Display Y) L5X (L5 Display X) L5EM (L5 Extend Mode) 160 L5EC 164 L5WY (L5 Window Y) L5WX (L5 Window X) 168 L5WH (L5 Window Height) L5WW (L5 Window Width) MB86276 'LIME' GDC Specifications Rev1.1a 142 FUJITSU SEMICONDUCTOR CONFIDENTIAL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0A4 8 7 6 5 CUZT CUO0 CEN1 9 4 3 2 1 CUTC (Cursor Transparent Control) CUO1 CPM 0A0 CEN0 Offset CUTC CUOA0 (CUrsor0 Origin Address) 0A8 CUY0 (Cursor0 Position Y) 0AC CUX0 (Cursor0 Position X) CUOA1 (CUrsor1 Origin Address) 0B0 CUY1 (Cursor1 Position Y) CUX1 (Cursor1 Position X) MDen MDC (Multi Display Control ) 170 SC1en SC0en DLS (Display Layer Select) 180 DLS5 184 DLS4 DLS3 DLS2 DLS1 DLS0 DBGC (Display Back Ground Color) L0BP L0BI L0BE L0BS L0BLD (L0 Blend) 0B4 L0BR L1BP L1BI L1BE L1BS L1BLD (L1 Blend) 188 L1BR L2BP L2BI L2BE L2BS L2BLD (L2 Blend) 18C L2BR MB86276 'LIME' GDC Specifications Rev1.1a L3BP L3BE L3BI L4BP L4BI L4BS L4BE L4BR 143 L5BI L5BLD (L5 Blend) L5BS 198 L3BR L4BLD (L4 Blend) L5BE 194 L3BS L3BLD (L3 Blend) 190 L5BR 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 7 6 5 L0ZT L2TC (L2 Transparent Color) L3TC(L3 Transparent Color) L0ETC (L0 Extend Transparency Control) L0ETC (L0 Extend Transparent Color) L1EZT L1ETC (L1 Extend Transparent Color) L2EZT L2ETC (L2 Transparent Extend Control) 1A8 L2ETC (L2 Extend Transparent Color) L3EZT L3ETC (L3 Transparent Extend Control) 1AC L3ETC (L3 Extend Transparent Color) L4EZT L4ETC (L4 Extend Transparent Control) 1B0 L4ETC (L4 Extend Transparent Color) 1E0 1E4 1E8 1EC 1F0 1F4 L5EZT L5ETC (L5 Extend Transparent Control) 1B4 3 L0TC (L0 Transparent Color) L1ETC (L1 Transparent Extend Control) 1A4 4 L3TC (L3 Transparent Control) L3ZT L2ZT L2TC (L2 Transparent Control) L0EZT 1A0 8 L0TC (L0 Transparent Control) 0BC 0C0 9 L5ETC (L5 Extend Transparent Color) L1YCR0 (L1 YC to Red Coefficient 0) a12 a11 L1YCR1 (L1 YC to Red Coefficient 1) b1 a13 L1YCG0 (L1 YC to Green Coefficient 0) a22 a21 L1YCG1 (L1 YC to Green Coefficient 1) b2 a23 L1YCB0 (L1 YC to Blue Coefficient 0) a32 a31 L1YCB1 (L1 YC to Blue Coefficient 1) MB86276 'LIME' GDC Specifications Rev1.1a b3 a33 144 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL Offset 400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 A R L0PAL1 : : 7FC L0PAL255 A R L1PAL1 : : BFC L1PAL255 6 5 4 G B G B G B G B L2PAL0 A R 1004 L2PAL1 : : 13FC L2PAL255 1400 7 L1PAL0 804 1000 8 L0PAL0 404 800 9 L3PAL0 A R 1404 L3PAL1 : : 17FC L3PAL255 MB86276 'LIME' GDC Specifications Rev1.1a 145 3 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 11.1.6 Video capture register list 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VS Offset NRGB Base = CaptureBase 0 CM VI VIS VIE 004 VICE VCM (Video Capture Mode) 000 CSC (Capture SCale) VSCF HSCI VCS (Video Capture Status) VSCI 008 HSCF CE 014 018 SSM CBOA (Capture Buffer Origin Address) CBLA (Capture Buffer Limit Address) 01C CIVSTR CIHSTR 020 CIVEND CIHEND CVCNT 300 CVCNT CHP (Capture Horizontal Pixel) 028 CHP 02C 40 CBST SSS HRV CSW C24 CBW (stride) BED PAU CRGB OO SBUF CBM (Capture Buffer Mode) 010 CVLPF 048 04C 080 CVP (Capture Vertical Pixel) CVPP CLPF CHLPF CMSS (Capture Magnify Source Size) CMSHP CMDS (Capture Magnify Display Size) CMDHP RGBHC(RGB input HSYNC Cycle)/VIN_HSSIZE CVPN CMSVL CMDVL RGBHC RGBHEN(RGB input Horizontal Enable Area) RGBHST RGBVEN(RGB input Vertical Enable Area) 084 088 RGBVST RGBHEN RGBVEN 0C0 0C4 0C8 0CC a21 a31 b1 RGBCMY(RGB Color convert Matrix Y coefficient) a12 RGBCMCb(RGB Color convert Matrix Cb coefficient) a22 RGBCMCr(RGB Color convert Matrix Cr coefficient) a32 RGBCMb(RGB Color convert Matrix b coefficient) b2 MB86276 'LIME' GDC Specifications Rev1.1a 146 HP RM a11 a13 a23 a33 b3 VP RGBS(RGB input SYNC) 090 FUJITSU SEMICONDUCTOR CONFIDENTIAL Offset 4000 4004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 CDCN(Capture Data Count for NTSC) BDCN CDCP(Capture Data Count for PAL) BDCP MB86276 'LIME' GDC Specifications Rev1.1a 147 9 8 7 6 5 VDCN VDCP 4 3 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 11.1.7 Drawing engine register list The parenthesized value in the Offset field denotes the absolute address used by the SetRegister command. Base = DrawBase Offset 000 (000) 004 (001) 008 (002) 00C (003) 010 (004) 014 (005) 018 (006) 01C (007) 020 (008) 040 (010) 044 (011) 048 (012) 04C (013) 050 (014) 054 (015) 058 (016) 05C (017) 060 (018) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 Ys S S S Int S Frac Xs S S S Int S Frac dXdy S S S Int S Frac XUs S S S Int S Frac dXUdy S S S Int S Frac XLs S S S Int S Frac dXLdy S S S Int S Frac USN 0 0 0 Int 0 0 LSN 0 0 0 Int 0 0 Rs 0 0 0 0 0 0 0 0 Int Frac dRdx S S S S S S S S Int Frac dRdy S S S S S S S S Int Frac Gs 0 0 0 0 0 0 0 0 Int Frac dGdx S S S S S S S S Int Frac dGdy S S S S S S S S Int Frac Bs 0 0 0 0 0 0 0 0 Int Frac dBdx S S S S S S S S Int Frac dBdy S S S S S S S S MB86276 'LIME' GDC Specifications Rev1.1a Int Frac 148 6 5 4 3 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 0C4 (031) 0C8 (032) 0CC (033) 0D0 (034) 0D4 (035) 0D8 (036) 0DC (037) 0E0 (038) 140 (050) 144 (051) 148 (052) 14C (053) 150 (054) 154 (055) 158 (056) 7 dZdx Int S Frac dZdy Int S Frac Ss S S Int S Frac dSdx S S Int S Frac dSdy S S Int S Frac Ts S S Int S Frac dTdx S S Int S Frac dTdy S S Int S Frac Qs 0 0 0 0 0 0 0 Frac dQdx S S S S S S S Frac dQdy S S S S S S S Frac LPN 0 0 0 Int 0 0 LXs S S S Int S Frac LXde S S S S S S S S S S S S S S Int 0C0 (030) 8 Frac S Frac LYs S S S Int S Frac LYde S S S S S S S S S S S S S S Int 088 (022) Int 0 INT 084 (021) 9 Zs INT 080 (020) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 INT Offset S Frac LZs S Int Frac LZde S Int MB86276 'LIME' GDC Specifications Rev1.1a Frac 149 6 5 4 3 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 180 (060) S S S Int S S S S Int S Int S S S S Int S 0 RYs S S S Int S S S S Int S S S S Int S 0 0 0 0 0 0 Address 0 SStride 0 0 0 Int 0 0 0 0 Int 0 0 0 0 Int 0 0 0 0 0 0 0 Address 0 DStride 0 0 0 Int 0 0 0 0 Int 0 0 0 0 Int 0 0 0 0 Int 0 0 BRsizeY 0 0 0 Int 0 0 TColor 280 (0A0) 0 BRsizeX 264 (099) 0 DRYs 260 (098) 0 DRXs 25C (097) 0 DADDR 258 (096) 0 SRYs 254 (095) 0 SRXs 250 (094) 0 SADDR 24C (093) 0 RsizeY 248 (092) 0 RsizeX 244 (091) 2 RXs 240 (090) 3 Frac 20C (083) 4 PZdc 208 (082) 5 Frac 204 (081) 6 Frac 200 (080) 7 PYdc 188 (062) 8 PXdc 184 (061) 9 0 3E0 Color BLPO (0f8) MB86276 'LIME' GDC Specifications Rev1.1a BCR 150 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 FCNT FE NF CE FO (100) 0 SS DS PS IFSR NF FF FE 404 (-) IFCNT 408 (-) FCNT SST 40C (-) SS DST 410 (-) DST PST 414 (-) PS FO CE EST 418 (108) CF CX MDR0 ZP 420 CY (-) BSV BSH BM ZW ZCL LOG BM ZCL ZC LOG ZW LW BL (109) BP MDR1/MDR1S/MDR1B/MDR1TL 424 TWT MDR4 (10c) MB86276 'LIME' GDC Specifications Rev1.1a TWS TC TBL LOG 151 BM TE 430 TAB TF MDR3 42C (10b) ZC TT SM MDR2/MDR2S/MDR2TL 428 (10a) 1 CTR 400 FF Offset FUJITSU SEMICONDUCTOR CONFIDENTIAL Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 440 8 7 6 5 4 3 FBR (110) FBASE XRES 444 (111) XRES ZBR 448 (112) ZBASE TBR 44C (113) TBASE PFBR 450 (114) PFBASE CXMIN 454 (115) CLIPXMIN CXMAX 458 (116) CLIPXMAX CYMIN 45C (117) CLIPYMIN CYMAX 460 (118) CLIPYMAX TXS 464 (119) 9 TXSN TXSM TIS 468 (11a) 46C TISN TISM TOA (11b) XBO ABR 474 (11D) ABASE FC 480 (120) FGC8/16/24 BC 484 (121) BGC8/16/24 ALF 488 (122) A 48C BLP (123) TBC 494 (129) MB86276 'LIME' GDC Specifications Rev1.1a BC16/24 152 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0 0 0 Int 0 0 0 0 0 0 0 0 Int 0 0 0 0 Int 0 0 0 0 Int 0 0 0 0 Int 0 0 0 0 Int 0 0 0 0 Int 0 X2dc 0 0 0 0 Int 0 Y2dc 594 (165) 0 Y1dc 590 (164) 0 X1dc 58C (163) 0 Y0dc 588 (162) 0 X0dc 584 (161) 0 LY1dc 580 (160) 0 LX1dc 54C (151) 0 Int 548 (150) 7 LY0dc 544 (151) 8 LX0dc 540 (150) 9 0 0 0 0 Int 0 4A0 DFIFO (128) DFIFO MB86276 'LIME' GDC Specifications Rev1.1a 153 6 5 4 3 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12 Explanation of GDC Registers Terms appeared in this chapter are explained below: 6. Register address Indicates address of register 7. Bit number Indicates bit number 8. Bit field name Indicates name of each bit field included in register 9. R/W Indicates access attribute (read/write) of each field Each symbol shown in this section denotes the following: R0 "0" always read at read. Write access is Don't care. W0 Only "0" can be written. R Read enabled W Write enabled RX Read enabled (read values undefined) RW Read and write enabled RW0 Read and write 0 enabled 10. Initial value Indicates initial value of immediately before the reset of each bit field. 6. Handling of reserved bits "0" is recommended for the write value so that compatibility can be maintained with future products. MB86276 'LIME' GDC Specifications Rev1.1a 154 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.1 Host interface registers DTC (DMA Transfer Count) Register HostBaseAddress + 00H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved DTC R/W R0 RW Initial value 0 Don't care DTC is a readable/writable 32-bit register which sets the transfer count in either one long-word (32 bits) or 32 bytes units. When "1h" is set transfer is performed once. However, when "0h" is set, it indicates the maximum transfer count and 16M (16,777,216) data are transferred. During DMA transfer, the remaining transfer count is shown, therefore, the register value cannot be overwritten until DMA transfer is completed. Note: This register need not be set in a mode in which Dual DMA ACK is not used, or the V832 mode. DSU (DMA Set Up) Register HostBaseAddress + 04H address Bit number 7 6 5 Bit field name Reserved R/W R0 Initial value 0 Bit 0 4 3 2 DAM RW 0 1 DBM RW 0 0 DW RW 0 DW (DMA Word) Specifies DMA transfer count Bit 1 Bit 2 0: 1-double word (32 bits) per DMA transfer 1: 8-double words (32 bytes) per DMA transfer (only SH4) DBM (DMA Bus request Mode) Selects DREQ mode used in DMA transfer in dual-address mode 0: DREQ is not negated during DMA transfer irrespective of cycle steal or burst mode. 1: DREQ is negated irrespective of cycle steal or burst mode when CORAL cannot receive data (that is, when Ready cannot be returned immediately). When CORAL is ready to receive data, DREQ is reasserted (When DMA transfer is performed in the single-address mode, DREQ is controlled automatically). DAM (DMA Address Mode) Selects DMA address mode in issuing external request Bit 3 0: Dual address mode 1: Single address mode (SH4 only) DNA (Dual address No Ack mode) This bit is selected when using the dual-address-mode DMA that does not use the ACK signal. 0: Uses dual-address-mode DMA that uses ordinary ACK signal 1: Uses dual-address-mode DMA that does not use ACK signal Detection of the DREQ edge is supported; DREQ is negated per transfer. When data cannot be received irrespective of the Bit1 setting, DREQ continues being negated. MB86276 'LIME' GDC Specifications Rev1.1a 155 FUJITSU SEMICONDUCTOR CONFIDENTIAL DRM (DMA Request Mask) Register HostBaseAddress + 05H address Bit number 7 6 Bit field name R/W Initial value 5 4 Reserved R0 0 3 2 1 0 DRM RW 0 This register enables the DMA request. Setting "1" to this register to temporarily stop the DMA request from the CORAL. The external request is enabled by setting "0" to this register. DST (DMA STatus) Register HostBaseAddress + 06H address Bit number 7 6 Bit field name R/W Initial value 5 4 Reserved R0 0 3 2 1 0 DST R 0 This register indicates the DMA transfer status. DST is set to "1" during DMA transfer. This state is cleared to "0" when the DMA transfer is completed. DTS (DMA Transfer Stop) Register HostBaseAddress + 08H address Bit number 7 6 Bit field name R/W Initial value 5 4 Reserved R0 0 3 2 1 0 DTS RW 0 This register suspends DMA transfer. An ongoing DMA transfer is suspended by setting DTS to "1". In the dual-address without ACK mode, to end the DMA transfer, write "1" to this register after CPU DMA transfer. LTS (display Transfer Stop) Register HostBaseAddress + 09H address Bit number 7 6 Bit field name R/W Initial value 5 4 Reserved R0 0 3 2 1 0 LTS RW 0 2 1 0 LSTA R 0 This register suspends DisplayList transfer. Ongoing DisplayList transfer is suspended by setting LTS to "1". LSTA (displayList transfer STAtus) Register HostBaseAddress + 10H address Bit number 7 6 Bit field name R/W Initial value 5 4 Reserved R0 0 3 This register indicates the DisplayList transfer status from Graphics Memory. LSTA is set to "1" while DisplayList transfer is in progress. This status is cleared to 0 when DisplayList transfer is completed MB86276 'LIME' GDC Specifications Rev1.1a 156 FUJITSU SEMICONDUCTOR CONFIDENTIAL DRQ (DMA ReQquest) Register HostBaseAddress + 18H address Bit number 7 6 Bit field name R/W Initial value 5 4 Reserved R0 0 3 2 1 0 DRQ RW1 0 This register starts sending external DMA request. DMA transfer using the external request handshake is triggered by setting DRQ to "1". The external DREQ signal cannot be issued when DMA is masked by the DRM register. This register cannot be written "0". When DMA transfer is completed, this status is cleared to "0". IST (Interrupt STatus) Register HostBaseAddress + 20H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved Resv Reserved IST IST R/W R0 R0W0 R0 RW0 RW0 Initial value 0 0 0 0 0 This register indicates the current interrupt status. It shows that an interrupt request is issued when "1" is set to this register. The interrupt status is cleared by writing "0" to this register. Bit 0 CERR (Command Error Flag) Indicates drawing command execution error interrupt Bit 1 CEND (Command END) Indicates drawing command end interrupt Bit 2 VSYNC (Vertical Sync.) Indicates vertical interrupt synchronization Bit 3 FSYNC (Frame Sync.) Indicates frame synchronization interrupt Bit 4 SYNCERR (Sync. Error) Indicates external synchronization error interrupt Bit 5 REGUD (Register update) Indicates register update interrupt Bit 17 and 16 Reserved This field is provided for testing. Normally, the read value is "0", but note that it may be "1" when a drawing command error (Bit 0) has occurred. IMASK (Interrupt MASK) Register HostBaseAddress + 24H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved Resv Reserved IMASK IMASK R/W R0 R0W0 R0 RW RW Initial value 0 0 0 0 0 This register masks interrupt requests. Even when the interrupt request is issued for the bit to which "0" is written, interrupt signal is not asserted for CPU. Bit 0 CERRM (Command Error Interrupt Mask) Masks drawing command execution error interrupt MB86276 'LIME' GDC Specifications Rev1.1a 157 FUJITSU SEMICONDUCTOR CONFIDENTIAL Bit 1 CENDM (Command Interrupt Mask) Masks drawing command end interrupt Bit 2 VSYNCM (Vertical Sync. Interrupt Mask) Masks vertical synchronization interrupt Bit 3 FSYNCH (Frame Sync. Interrupt Mask) Masks frame synchronization interrupt Bit 4 SYNCERRM (Sync Error Mask) Masks external synchronization error interrupt Bit 5 REGUD (Register update) Masks register update interrupt SRST (Software ReSeT) Register HostBaseAddress + 2CH address Bit number 7 6 Bit field name R/W Initial value 5 4 Reserved R0 0 3 2 1 0 SRST W1 0 This register controls software reset. When "1" is set to this register, a software reset is performed. CCF (Change of Clock Frequency) Register HostBaseAddress + 0038H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved COT Reserved R/W RW0 RW RW0 Initial value 0 00 0 This register changes the operating frequency. Bit 17 and 16 COT (Clock select for GDC) Selects the clock for GDC 11 Reserved 10 Reserved 01 133 MHz 00 100 MHz Notes: 1. Write "0" to the bit field other than the above ([31:18], [15:00]). MB86276 'LIME' GDC Specifications Rev1.1a 158 FUJITSU SEMICONDUCTOR CONFIDENTIAL LSA (displayList Source Address) Register HostBaseAddress + 40H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved LSA R/W R0 RW R0 Initial value 0 Don't care 0 This register sets the DisplayList transfer source address. When DisplayList is transferred from Graphics Memory, set the transfer start address of DisplayList stored in Graphics Memory. Since the lower two bits of this register are always treated as "0", DisplayList must be 4-byte aligned. The values set at this register do not change during or after transfer. LCO (displayList Count) Register HostBaseAddress + 44H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved LCO R/W R0 RW Initial value 0 Don't care This register sets the DisplayList transfer count. Set the display list transfer count by the long word. When "1h" is set, 1-word data is transferred. When "0" is set, it is considered to be the maximum count and 16M (16,777,216) words of data are transferred. The values set at this register do not change during or after transfer. LREQ (displayList transfer REQuest) Register HostBaseAddress + 48H address Bit number 7 6 Bit field name R/W Initial value 5 4 Reserved R0 0 3 2 1 0 LREQ RW1 0 This register triggers DisplayList transfer from the Graphics Memory. Transfer is started by setting LREQ to "1". The DisplayList is transferred from the Graphics Memory to the internal display list FIFO. Access to the display list FIFO by the CPU or DMA is disabled during transfer. The reserved area in the register area in the host interface excluding the abovementioned. Please write ALL0 when you write to the Reserved area. A read will produce undefined results. RSW (Register location Switch) Register HostBaseAddress + 5CH address Bit number 7 6 Bit field name R/W Initial value 5 4 Reserved R0 0 3 2 1 0 RSW RW 0 In SH3 or SH4 mode, set this register when moving the register area from the center (1FC0000) to the end of the GDC area (3FC0000). This move can be performed when "1" is written to this register. Set this register at the first access after reset. Access GDC after about 20 bus clocks after setting the register. MB86276 'LIME' GDC Specifications Rev1.1a 159 FUJITSU SEMICONDUCTOR CONFIDENTIAL DMA_ST_ADR Register HostBaseAddress + 500H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name DMA_ST_ADR R/W RW Initial value 26'h3FFFFFF DMA start address (*address width, 16-bit CPU:[23:0], 32-bit CPU[25:0]) When DMA_ST_ADR[input address]DMA_ED_ADR, it is DMA transfer. When [input address]>DMA_ST_ADR, it is normal access. DMA_ED_ADR Register HostBaseAddress + 504H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name DMA_ED_ADR R/W RW Initial value 26'h0 DMA end address (*address width, 16-bit CPU:[23:0], 32-bit CPU[25:0]) When DMA_ST_ADR[input address]DMA_ED_ADR, it is DMA transfer. When [input address]>DMA_ED_ADR, it is normal access. ERR_ADR Register HostBaseAddress + 508H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name ERR_ADR R/W R Initial value 26'h0 This register keeps the address, when the below interrupt request occurs. It accesses the following order, upper address of 32-bit and lower address of 32-bit in 16-bit CPU mode. It accesses the randam address in 16-bit CPU mode. ERR_DETECT Register HostBaseAddress + 50CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name R/W RW RW Initial value 0 0 Bit0: 16-bit CPU interrupts status register When "1" is set on the bit0, it shows the following interrupt request. It accesses the following order, upper address of 32-bit and lower address of 32-bit in 16-bit CPU mode. It clears the status by writing "0" on the bit0. Bit1: 16-bit CPU interrupts status register When "1" is set on the bit0, it shows the following interrupt request. It accesses the randam address in 16-bit CPU mode. (It accesses the following order, lower address of 32-bit and upper address of 32-bit, but it is not a continuance address.) It clears the status by writing "0" on the bit1. MB86276 'LIME' GDC Specifications 160 Rev1.1a FUJITSU SEMICONDUCTOR CONFIDENTIAL INT_MSK Register HostBaseAddress + 510H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name R/W RW RW Initial value 0 0 Bit0: 16-bit CPU interrupts request mask register (It accesses the following order, upper address of 32bit and lower address of 32-bit in 16-bit CPU mode.) It masks 16-bit CPU interrupts. When "0" is set on the bit0, it does not assert interrupts signal even if the interrupts request occurs. Bit1: 16-bit CPU interrupts request mask register (It accesses a randam address in 16-bit CPU mode.) It masks 16-bit CPU interrupts. When "0" is set on the bit1, it does not assert interrupts signal even if the interrupts request occurs. INT_MSK Register HostBaseAddress + 514H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name R/W RW Initial value 0 XINT polarity change signal "0" is Low Active, "1" is High Active. MB86276 'LIME' GDC Specifications Rev1.1a 161 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.1.1 GPIO control registers GPIO control 1 (GPIOC1) Register address Bit number Bit field name R/W Initial value PIOBaseAddress+40h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 GPIO_is_out GPIO_inout R0W R/W 0000_0000 XXXX_XXXX (*1) 4 3 2 1 The register controls the GPIO pins. Each bit can be set correspondingly from MSB to LSB by couple 1 in each bit. (*1) The value of the GPIO pin is reflected longer than the fixed time. (*2) Changes to the GPIO pin are not immediately reflected in the register. It takes time more than constancy (system clock cycle order) to mutual reflection with the GPIO pin. Bit15-0 GPIO_inout (GPIO input/output data ) (*2) The data of the GPIO pin is read and written. At read The value of external pin GPIO15-0 can be read about the bit to which `0' is set with GPIO_is_out. However, the bit reversing value of external pin GPIO15-0 is read about the bit that GPIOC2.GPIO_xor is set to `1'. When GPIOC2.GPIO_force is set to `1', the value in which the write is compulsorily done to GPIO_inout is read as it is (*3). The value in which the write is done to GPIO_inout is read as it is (*3) about the bit to which `1' is set with GPIO_is_out. (*3 The influence of GPIO_xor is not undertaken.) inout (at read) = (is_out || force) ? inout (at write) : (xor ^ GPIO pin) At write The written value is disregarded about the bit to which `0' is set with GPIO_is_out. The write value is output to external pin GPIO15-0 about the bit to which `1' is set with GPIO_is_out. However, the bit reversing value is output about the bit that GPIOC2.GPIO_xor is set to `1'. GPIO pin = (is_out) ? (xor ^ inout (at write)) : Hi-Z Bit31-16 GPIO_is_out (GPIO direction) The direction of each bit of the terminal GPIO I/O is specified. At read : 0 is always read. At write : The corresponding bit of `1' is an output of this. MB86276 'LIME' GDC Specifications Rev1.1a 162 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL GPIO control 2 (GPIOC2) Register address Bit number Bit field name R/W Initial value PIOBaseAddress +44h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 GPIO_force R/W 0000_0000 9 8 7 6 GPIO_xor R/W 0000_0000 5 4 3 2 1 The register controls the GPIO pin. Each set bit can be set corresponding from MSB to LSB by couple 1 in each bit. Refer to the paragraph of GPIOC1 for details. Bit15-0 GPIO_xor (GPIO_inout read/write data invert) Bit of GPIO_inout=`0' `0' : An untouched value of external pin GPIO15-0 is read from GPIO_inout. `1' : A reversed value of external pin GPIO15-0 is read from GPIO_inout. Bit of GPIO_inout=`1' `0' : The value in which the write is done to GPIO_inout is reflected in external pin GPIO15-0 as it is. `1' : The reversing value in which the write is done to GPIO_inout is reflected in external pin GPIO15-0 as it is. Bit31-16 GPIO_force (GPIO_inout force enable for input port read) It is set whether to force the read value of GPIO_inout set to the input. `0' : not force `1' : The read value of a bit of GPIO_inout concerned is forced to the value in which the write is done to GPIO_inout. MB86276 'LIME' GDC Specifications Rev1.1a 163 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.1.2 Peripheral Interrupt related registers Peripheral Interrupt control1 (PIC1) Register address Bit number PIOBaseAddress +4Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R/W 0 0 S1 R/W 0000_0000 0 RTO 0000_0000 R/W 0 Initial value GPIO_INT_enable R/W R0W0 6 R/W R/W 7 OFE Reserve 8 WTO Bit field name 9 5 4 3 2 1 The register controls the interrupt which relates to peripheral logic. The one of GPIO reacts without regard to input and output in the situation of the setting. Each set bit can be set corresponding from MSB to LSB by couple 1 in each bit. Bit15-0 GPIO_INT_enable (GPIO interrupt enable) It is set whether the generation of interrupt of each bit by the value in which external pin GPIO15-0 is sampled with the internal clock. Interrupt is not generated for `0'. Interrupt is generated for `1' based on the following register setting. Bit16 S1 (Serial1 Interrupt Enable) Interrupt when data is abandoned is set because of word not read by input FIFO of serial 1CH. 0:Interrupt is not generated. 1:Interrupt is generated. Bit17 RTO (Internal bus timeout interrupt Enable for read) It is specified whether interrupt is generated when input FIFO Read Wait time of an internal bus becomes more than a set cycle. (This bit does not work if it is not TE bit = 1 of SPC2 registers.) 0:Interrupt is not generated. 1:Interrupt is generated. Bit18 WTO (Internal bus timeout interrupt Enable for write) It is specified whether interrupt is generated when input FIFO Read Wait time of an internal bus becomes more than a set cycle. (This bit does not work if it is not TE bit = 1 of SPC2 registers.) 0:Interrupt is not generated. 1:Interrupt is generated. Bit19 OFE (Output FIFO empty interrupt Enable) It is specified whether interrupt is generated when output FIFO becomes empty. 0:Interrupt is not generated. 1:Interrupt is generated. MB86276 'LIME' GDC Specifications Rev1.1a 164 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL Peripheral Interrupt control2 (PIC2) Register address Bit number Bit field name R/W Initial value PIOBaseAddress +50h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Reserve GPIO_INT_polarity R0W0 R/W 0000_0000 0000_0000 4 3 2 1 0 4 3 2 1 0 The register controls interrupt concerning GPIO. It reacts without regard to input and output in the situation of the setting. Each set bit can be set corresponding from MSB to LSB by couple 1 in each bit. Bit15-0 GPIO_INT_polarity (GPIO interrupt polarity) Interrupt is generated for the following values. 0: When you detect Level `0' or negative edge (Depend on GPIO_INT_mode) 1: When you detect Level `1' or positive edge (Depend on GPIO_INT_mode) Peripheral Interrupt control3 (PIC3) Register address Bit number Bit field name R/W Initial value PIOBaseAddress +54h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Reserve GPIO_INT_mode R0W0 R/W 0000_0000 0000_0000 The register controls interrupt concerning GPIO. It reacts without regard to input and output in the situation of the setting. Each set bit can be set corresponding from MSB to LSB by couple 1 in each bit. Bit15-0 GPIO_INT_mode (GPIO interrupt mode) 0: level sensitive (`0' or `1' depends on GPIO_INT_polarity) 1: edge sensitive (`pos' or `neg' depends on GPIO_INT_polarity) MB86276 'LIME' GDC Specifications Rev1.1a 165 FUJITSU SEMICONDUCTOR CONFIDENTIAL Peripheral Interrupt Status (PIST) Register address Bit number PIOBaseAddress +80h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 R/W0 0 0000_0000 0 S1 0000_0000 R/W0 0 0000_0000 R/W0 Initial value RTO R0W0 0 R0W0 GPIO_INT_status R/W0 R/W 6 R/W0 Reserve 7 OFE Reserve 8 WTO Bit field name 9 5 4 3 2 1 The register shows the state of the interrupt which relates to peripheral logic. It clears by 0 Write. This state is consolidated and it is reflected in bit17 of host interface register IST. Bit15-0 GPIO_INT_status (GPIO interrupt status) Shows that interrupt is generated by the bit of the correspondence of GPIO. 0: interrupt is not generated 1: interrupt is generated Bit16 S1 (Serial1 port interrupt status) In Serial1communication, It is shown that interruption which notifies that input data was thrown away occurred. 0: interrupt is not generated 1: interrupt is generated Bit17 RTO (Internal bus timeout interrupt Status for read) It is shown that interruption when the input FIFO Read Wait time of an internal bus becomes more than a setting cycle occurred. 0: interrupt is not generated 1: interrupt is generated Bit18 WTO (Internal bus timeout interrupt Status for write) It is shown that interruption when the output FIFO Read Wait time of an internal bus becomes more than a setting cycle occurred. 0: interrupt is not generated 1: interrupt is generated Bit19 OFE (Output FIFO empty interrupt Status) It is shown that interruption when Output FIFO becomes empty occurred. 0: interrupt is not generated 1: interrupt is generated MB86276 'LIME' GDC Specifications Rev1.1a 166 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL Revision Register address Bit number PIOBaseAddress +84h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name YEAR R/W Initial value 8 7 6 5 4 3 REVISION 0x01 0x00 RO 0x2005 The register shows the chip version. MB86276 'LIME' GDC Specifications Rev1.1a 9 VERSION 167 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.1.3 I2C Interface Registers BSR (Bus Status Register) Register address I2C Base Address + 000h Bit No 7 6 5 4 3 2 1 0 Bit field name BB RSC AL LRB TRX AAS GCA FBT R/W R R R R R R R R Default 0 0 0 0 0 0 0 0 All bits on this register are cleared while bit EN on CCR register is "0". Bit7 BB (Bus Busy) Indicate state of I2C-bus 0: STOP condition was detected. 1: START condition (The bus is in use.) was detected. Bit6 RSC (Repeated START Condition) Indicate repeated START condition This bit is cleared by writing "0" to INT bit, the case of not addressed in a slave mode, the detection of START condition under bus stop, and the detection of STOP condition. 0: Repeated START condition was not detected. 1: START condition was detected again while the bus was in use. AL(Arbitration Lost) Detect Arbitration lost This bit is cleared by writing "0" to INT bit. 0: Arbitration lost was not detected. 1: Arbitration occurred during master transmission, or "1" writing was performed to MSS bit while other systems were using the bus. LRB (Last Received Bit) Store Acknowledge This bit is cleared by detection of START condition or STOP condition. TRX (Transmit / Receive) Indicate data receipt and data transmission. 0: receipt 1: transmission AAS (Address As Slave) Detect addressing This bit is cleared by detection of START condition or STOP condition. 0: Addressing was not performed in a slave mode. 1: Addressing was performed in a slave mode. GCA (General Call Address) Detect general call address (00h) This bit is cleared by detection of START condition or STOP condition. 0: General call address was not received in a slave mode. 1: General call address wad received in a slave mode. FBT (First Byte Transfer) Detect the 1st byte Even if this bit is set to "1" by detection of START condition, it is cleared by writing "0" on INT bit or by not being addressed in a slave mode. 0: Received data is not the 1st byte. 1: Received data is the 1st byte (address data). Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MB86276 'LIME' GDC Specifications Rev1.1a 168 FUJITSU SEMICONDUCTOR CONFIDENTIAL BCR (Bus Control Register) Register address I2C Base Address + 0004h Bit No 7 6 5 4 3 2 1 0 Bit field name BER BEIE SCC MSS ACK GCAA INTE INT R/W R/W0 R/W R0/W1 R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Bit7 Bit4 BER (Bus Error) Flag bit for request of bus error interruption When this bit is set, EN bit on CCR register will be cleared, this module will be in a stop state and data transfer will be discontinued. write case 0: A request of buss error interruption is cleared. 1: Don't care. read case 0: A bus error was not detected. 1: Undefined START condition or STOP condition was detected while data transfer. BEIE (Bus Error Interruption Enable) Permit bus error interruption When both this bit and BER bit are "1", the interruption is generated. 0: Prohibition of bus error interruption 1: Permission of bus error interruption SCC (Start Condition Continue) Generate START condition write case 0: Don't care. 1: START condition is generated again at the time of master transmission. MSS (Master Slave Select) Bit3 Select master / slave mode When arbitration lost is generated in master transmission, this bit is cleared and this module becomes a slave mode. 0: This module becomes a slave mode after generating STOP condition and completing transfer. 1: This module becomes a master mode, generates START condition and starts transfer. ACK (ACKnowledge) Bit6 Bit5 Bit2 Bit1 Bit0 Permit generation of acknowledge at the time of data reception This bit becomes invalid at the time of address data reception in a slave mode. 0: Acknowledge is not generated. 1: Acknowledge is generated. GCAA(General Call Address Acknowledge) Permit generation of acknowledge at the time of general call address reception 0: Acknowledge is not generated. 1: Acknowledge is generated. INTE (INTerrupt Enable) Permit interruption When this bit is "1" interruption is generated if INT bit is "1". 0: Prohibition of interrupt 1: Permission of interrupt INT (INTerrupt) Flag bit for request of interruption for transfer end When this bit is "1" SCL line is maintained at "L" level. If this bit is cleared by being written "0", SCL line is released and the following byte transfer is started. Moreover, it is reset to "0" by generating of START condition or STOP condition at the time of a master. write case MB86276 'LIME' GDC Specifications Rev1.1a 169 FUJITSU SEMICONDUCTOR CONFIDENTIAL 0: The flag is cleared. 1: Don't care. read case 0: The transfer is not ended. 1: It is set when 1 byte transfer including the acknowledge bit is completed and it corresponds to the following conditions. - It is a bus master. - It is an addressed slave. - It was going to generate START condition while other systems by which arbitration lost happened used the bus. Competition of SCC, MSS and INT bit Competition of the following byte transfer, generation of START condition and generation of STOP condition happens by the simultaneous writing of SCC, MSS and INT bit. The priority at this case is as follows. 1) The following byte transfer and generation of STOP condition If "0" is written to INT bit and "0" is written to MSS bit, priority will be given to "0" writing to MSS bit and STOP condition will be generated. 2) The following byte transfer and generation of START condition If "0" is written to INT bit and "1" is written to SCC bit, priority will be given to "1" writing to SCC bit and START condition will be generated. 3) Generation of START condition and STOP condition The simultaneous writing of "1" to SCC bit and "0" to MSS bit is prohibition. MB86276 'LIME' GDC Specifications Rev1.1a 170 FUJITSU SEMICONDUCTOR CONFIDENTIAL CCR (Clock Control Register) Register address I2C Base Address + 0008h Bit No 7 6 5 4 3 2 1 Bit field name - HSM EN CS4 CS3 CS2 CS1 CS0 R/W R1 R/W R/W R/W R/W R/W R/W R/W Default 1 0 0 - - - - - Bit7 Nonuse "1" is always read at read. Bit6 HSM (High Speed Mode) Select standard-mode 0: 1: High-speed-mode Bit5 / 0 high-speed-mode Standard-mode EN (Enable) Permission of operation When this bit is "0", each bit of BSR and BCR register (except BER and BEIE bit) is cleared. This bit is cleared when BER bit is set. 0: Prohibition of operation 1: Permission of operation CS4 - 0 (Clock Period Select4 - 0) Bit4 Set up the frequency of a serial transfer clock Frequency fscl of a serial transfer clock is shown as the following formula. Please set up fscl not to exceed the value shown below at the time of master operation. standard-mode: 100KHz high-speed-mode: 400KHz standard-mode fscl = A (2 x m)+2 high-speed-mode fscl = A int(1.5 x m)+2 A: I2C system clock = 16.6MHz <Notes> +2 cycles are minimum overhead to confirm that the output level of SCL terminal changed. When the delay of the positive edge of SCL terminal is large or when the clock is extended by the slave device, it becomes larger than this value. The value of m becomes like the following page to the value of CS 4-0. MB86276 'LIME' GDC Specifications Rev1.1a 171 FUJITSU SEMICONDUCTOR CONFIDENTIAL CS4 CS3 CS2 CS1 CS0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB86276 'LIME' GDC Specifications Rev1.1a 172 m standard 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 high-speed inhibited inhibited inhibited inhibited inhibited inhibited inhibited inhibited 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 FUJITSU SEMICONDUCTOR CONFIDENTIAL Address Register(ADR) Register address I2C Base Address + 000Ch Bit No 7 6 5 4 3 2 1 0 Bit field name - A6 A5 A4 A3 A2 A1 A0 R/W R1 R/W R/W R/W R/W R/W R/W R/W Default 1 - - - - - - - Bit7 Nonuse "1" is always read at read. Bit6 - 0 A6 - 0 (Address6 - 0) Store slave address In a slave mode it is compared with DAR register after address data reception, and when in agreement, acknowledge is transmitted to a master. Data Register(DAR) Register address I2C Base Address + 0010h Bit No 7 6 5 4 3 2 1 0 Bit field name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Default - - - - - - - - Bit7 - 0 D7 - 0 (Data7 - 0) Store serial data This is a data register for serial data transfer. The data is transferred from MSB. At the time of data reception (TRX=0) the data output is set to "1". The writing side of this register is a double buffer. When the bus is in use (BB=1), the write data is loaded to the register for serial transfer for every transfer. At the time of read-out, the receiving data is effective only when INT bit is set because the register for serial transfer is read directly at this time. MB86276 'LIME' GDC Specifications Rev1.1a 173 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.2 Graphics memory interface registers MMR (Memory I/F Mode Register) Register HostBaseAddress + FFFCH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name *1 tWR Reserved *1 *1 TRRD TRC TRP TRAS TRCD LOWD RTS SAW ASW CL R/W Initial value R R1 R RW RW RW RW RW RW RW RW RW RW 0 0 Don't care 1 0 00 0000 00 000 00 00 000 000 0 000 RW RW W0 *1: Reserved This register sets the mode of the graphics memory interface. A value must be written to this register after a reset. (When default setting is performed, a value must also be written to this register.) Only write once to this register; do not change the written value during operation. This register is not initialized at a software reset. Bit 2 to 0 CL (CAS Latency) Sets the CAS latency. Write the same value as this field, to the mode register for SDRAM Bit 3 011 CL3 010 CL2 Other than the above Setting disabled ASW (Attached SDRAM bit Width) Sets the bit width of the data bus (memory bus width mode) Bit 6 to 4 1 Reserved 0 32 bit SAW (SDRAM Address Width) Sets the bit width of the SDRAM address Bit 9 to 7 001 15 bit BANK 2 bit ROW 13 bit COL 9 bit SDRAM 111 14 bit BANK 2 bit ROW 12 bit COL 9 bit SDRAM 110 14 bit BANK 2 bit ROW 12 bit COL 8 bit SDRAM 101 13 bit BANK 2 bit ROW 11 bit COL 8 bit SDRAM 100 12 bit BANK 1 bit ROW 11 bit COL 8 bit FCRAM Other than the above Setting disabled RTS (Refresh Timing Setting) Sets the refresh interval 000 Refresh is performed every 384 internal clocks. 111 Refresh is performed every 1552 internal clocks. 001 to 110 Refresh is performed every `64 x n' internal clocks in the 64 to 384 range. MB86276 'LIME' GDC Specifications Rev1.1a 174 FUJITSU SEMICONDUCTOR CONFIDENTIAL Bit 11 and 10 LOWD Sets the count of clocks secured for the period from the instant the ending data is output to the instant the write command is issued. It is able to adjust the internal timing of memory interface by the setting. Bit 13 and 12 11 3 clocks 10 2 clocks 01 1 clocks Other than the above Setting disabled TRCD Sets the wait time secured from the bank active to CAS. The clock count is used to express the wait time. Bit 16 to 14 11 3 clocks 10 2 clocks 01 1 clock 00 0 clock TRAS Sets the minimum time for 1 bank active. The clock count is used to express the minimum time. Bit 18 and 17 111 7 clocks 110 6 clocks 101 5 clocks 100 4 clocks 011 3 clocks 010 2 clocks Other than the above Setting disabled TRP Sets the wait time secured from the pre-charge to the bank active. The clock count is used to express the wait time. Bit 22 to 19 11 3 clocks 10 2 clocks 01 1 clock TRC This field sets the wait time secured from the refresh to the bank active. The clock count is used to express the wait time. 1010 10 clocks 1001 9 clocks 1000 8 clocks 0111 7 clocks 0110 6 clocks 0101 5 clocks MB86276 'LIME' GDC Specifications Rev1.1a 175 FUJITSU SEMICONDUCTOR CONFIDENTIAL Bit 24 and 23 0100 4 clocks 0011 3 clocks Other than the above Setting disabled TRRD Sets the wait time secured from the bank active to the next bank active. The clock count is used to express the wait time. Bit 26 11 3 clocks 10 2 clocks Reserved Always write "0" at write. "1" is always read at read. Bit 30 TWR Sets the write recovery time (the time from the write command to the read or to the precharge command). 1 2 clocks 0 1 clock MB86276 'LIME' GDC Specifications Rev1.1a 176 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.3 Display control registers DCM0/1 (Display Control Mode 0/1) 1 SF 0 2 ESY RW 11110 3 SYNC RW R0 RW RW 0 RW 0 0 0 0 5 4 3 2 1 ESY RW 0 Resv R0 0 4 SF 0 5 Resv 0 RW RW RW RW RW RW RW R0 0 0 0 0 0 0 0 0 9 8 7 SC EEQ Resv X CKS RW 0 L0E RW L1E R/W Initial value L2E Reserve L3E Bit field name L4E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DEN Bit number 0 6 00 SYNC DisplayBaseAddress + 100H (DCM1) L5E Register address 0 7 SC Resv RW RW RW RW RW 8 Resv X 9 EEQ RX 0 L0E RW CKS R/W Initial value L1E Reserve L23E Bit field name L45E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Resv DisplayBaseAddress + 00H ( DCM0) DEN Register address Bit number RW RW 11101 0 6 RW R0 RW RW 0 0 0 0 0 RW 00 This register controls the display count mode. It is not initialized by a software reset. This register is mapped to two addresses but it is one substance. The differences between the two registers are the format of the frequency division rate setting (SC) and layer enable. The two formats exist to maintain backword compatibility with previous products. Bit 1 to 0 SYNC (Synchronize) Set synchronization mode Bit 2 X0 Non-interlace mode 10 Interlace mode 11 Interlace video mode ESY (External Synchronize) Sets external synchronization mode Bit 3 0: External synchronization disabled 1: External synchronization enabled SF (Synchronize signal format) Sets format of synchronization (VSYNC, HSYNC) signals Bit 7 0: Negative logic 1: Positive logic EEQ (Enable Equalizing pulse) Sets CCYNC signal mode Bit 13 to 8 0: Does not insert equalizing pulse into CCYNC signal 1: Inserts equalizing pulse into CCYNC signal SC (Scaling) Divides display reference clock by the preset ratio to generate dot clock Offset = 0 x00000 Offset = 100H Frequency not divided MB86276 'LIME' GDC Specifications Rev1.1a 000000 177 Frequency not divided FUJITSU SEMICONDUCTOR CONFIDENTIAL x00001 Frequency division rate = 1/4 000001 Frequency division rate = 1/2 x00010 Frequency division rate = 1/6 000010 Frequency division rate = 1/3 X00011 Frequency division rate = 1/8 000011 Frequency division rate = 1/4 : : x11111 Frequency division rate = 1/64 111111 Frequency division rate = 1/64 When n is set, with Offset = 0, the frequency division rate is 1/(2n + 2). When m is set, with Offset = 100h, the frequency division rate is 1/(m + 1). Basically, these are setting parameters with the same function (2n + 2 = m + 1). Because of this, m = 2n + 1 is established. When n is set to the SC field with Offset = 0, 2n + 1 is reflected with Offset = 100h. Also, when PLL is selected as the reference clock, frequency division rates 1/1 to 1/5 are non-functional even when set; other frequency division rates are assigned. Bit 15 CKS (Clock Source) Selects reference clock Bit 16 0: Internal PLL output clock 1: DCLKI input L0E (L0 layer Enable) Enables display of the L0 layer. The L0 layer corresponds to the C layer for previous products. Bit 17 0: Does not display L0 layer 1: Displays L0 layer L1E (L1 layer Enable) Enables display of the L1 layer. The L1 layer corresponds to the W layer for previous products. Bit 18 0: Does not display L1 layer 1: Displays L1 layer L23E (L2 & L3 layer Enable) ------ DCM0 Enables simultaneous display of the L2 and L3 layers. These layers correspond to the M layer for previous products. 0: Does not display L2 and L3 layer 1: Displays L2 and L3 layer L2E (L2 layer Enable) ------ DCM1 Enables L2 layer display Bit 19 0: Does not display L2 layer 1: Displays L2 layer L45E (L4 & L5 layer Enable) ------ DCM0 Enables simultaneous display of the L4 and L5 layers. These layers correspond to the B layer for previous products. 0: Does not display L4 and L5 layer 1: Displays L4 and L5 layer MB86276 'LIME' GDC Specifications Rev1.1a 178 FUJITSU SEMICONDUCTOR CONFIDENTIAL L3E (L3 layer Enable)) ------ DCM1 Enables L3 layer display Bit 20 0: Does not display L3 layer 1: Displays L3 layer L4E (L4 layer Enable) Enables L4 layer display Bit 21 0: Does not display L4 layer 1: Displays L4 layer L5E (L5 layer Enable) Enables L5 layer display Bit 31 0: Does not display L5 layer 1: Displays L5 layer DEN (Display Enable) Enables display 0: Does not output display signal 1: Outputs display signal MB86276 'LIME' GDC Specifications Rev1.1a 179 FUJITSU SEMICONDUCTOR CONFIDENTIAL DCM2 (Display Control Mode 2) Register DisplayBaseAddress + 104H address 17 16 15 14 Bit number 31 30 29 28 27 28 Reserve Bit field name R0 R/W 0 Initial value Bit0 13 12 11 10 9 8 7 6 5 1 0 Reserv 4 3 Reserv 2 RUF RUM R0 R0 RW RW 0 0 0 0 RUM (Register Update Mode) The mode reflects the register value synchronizing with vertical synchronization is selected. Bit1 0: The register update is in real time reflected in the internal control circuit. The display falls into disorder when updating it for the display period. 1: It value of the register spreads to the internal control circuit synchronizing with vertical synchronization. The simultaneity is controlled with the following RUF flags. RUF (Register Update Flag) The value is directed to be updated in the following vertical synchronization in writing 1 in this flag. If the update ends, it becomes 0. 0: Initial or update end 1: Vertical synchronous waiting MB86276 'LIME' GDC Specifications Rev1.1a 180 FUJITSU SEMICONDUCTOR CONFIDENTIAL DCM3 (Display Control Mode 3) Register DisplayBaseAddress + 108H address 17 16 15 14 13 Bit number 31 30 29 reserve Bit field name R0 R/W 0 Initial value Bit5-0 12 11 10 resv POM 9 8 R0 RW RW RW RW0 R0 RW 0 0 0 0 0 0 000000 DCKed DCKinv 7 6 Reserve 5 4 3 2 1 DCKD DCKD ( Display Clock Delay) This defines additional delay time by internal PLL clock period. 000000 No additional delay 000010 +2 PLL clock 000100 +3 PLL clock 000110 +4 PLL clock : Bit8 Bit9 : 111110 +33 PLL clock xxxxx1 reserve DCKinv (Display Clock inversion ) 0: DCLKO output signal is not inverted 1: DCLKO output signal is inverted. DCKed ( Display clock edge ) This defines which edge mode is used. Bit10 0: single edge mode in which positive edge is used for digital RGB output. 1: bi-edge mode in which positive edge and negative edge are used for digital RGB output to identify two data streams. POM (Parallel output Mode) This defines a way to output two data streams for two display 0: multiplex output mode in which two data streams are multiplexed and goes to the digital RGB output. 1: parallel output mode in which one data stream go to the digital RGB output and another data stream goes to the analog RGB output. MB86276 'LIME' GDC Specifications Rev1.1a 181 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL HTP (Horizontal Total Pixels) Register DisplayBaseAddress + 06H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 HTP RW Don't care 4 3 2 1 0 This register controls the horizontal total pixel count. Setting value + 1 is the total pixel count. HDP (Horizontal Display Period) Register DisplayBaseAddress + 08H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 HDP RW Don't care 4 3 2 1 0 This register controls the total horizontal display period in unit of pixel clocks. Setting value + 1 is the pixel count for the display period. HDB (Horizontal Display Boundary) Register DisplayBaseAddress + 0AH address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 HDB RW Don't care 4 3 2 1 0 This register controls the display period of the left part of the window in unit of pixel clocks. Setting value + 1 is the pixel count for the display period of the left part of the window. When the window is not divided into right and left before display, set the same value as HDP. HSP (Horizontal Synchronize pulse Position) Register DisplayBaseAddress + 0CH address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 HSP RW Don't care 4 3 2 1 0 This register controls the pulse position of the horizontal synchronization signal in unit of pixel clocks. When the clock count since the start of the display period reaches setting value + 1, the horizontal synchronization signal is asserted. HSW (Horizontal Synchronize pulse Width) Register DisplayBaseAddress + 0EH address Bit number 7 6 5 Bit field name R/W Initial value 4 3 2 1 0 HSW RW Don't care This register controls the pulse width of the horizontal synchronization signal in unit of pixel clocks. Setting value + 1 is the pulse width clock count. MB86276 'LIME' GDC Specifications Rev1.1a 182 FUJITSU SEMICONDUCTOR CONFIDENTIAL VSW (Vertical Synchronize pulse Width) Register DisplayBaseAddress + 0FH address Bit number 7 6 5 Bit field name Reserved R/W R0 Initial value 0 4 3 2 1 0 VSW RW Don't care This register controls the pulse width of vertical synchronization signal in unit of raster. Setting value + 1 is the pulse width raster count. VTR (Vertical Total Rasters) Register DisplayBaseAddress + 12H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 VTR RW Don't care 4 3 2 1 0 This register controls the vertical total raster count. Setting value + 1 is the total raster count. For the interlace display, Setting value + 1.5 is the total raster count for 1 field; 2 x setting value + 3 is the total raster count for 1 frame (see Section 8.3.2). VSP (Vertical Synchronize pulse Position) Register DisplayBaseAddress + 14H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 VSP RW Don't care 4 3 2 1 0 This register controls the pulse position of vertical synchronization signal in unit of raster. The vertical synchronization pulse is asserted starting at the setting value + 1st raster relative to the display start raster. VDP (Vertical Display Period) Register DisplayBaseAddress + 16H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 VDP RW Don't care 4 3 2 1 0 This register controls the vertical display period in unit of raster. Setting value + 1 is the count of raster to be displayed. MB86276 'LIME' GDC Specifications Rev1.1a 183 FUJITSU SEMICONDUCTOR CONFIDENTIAL L0M (L0 layer Mode) Register DisplayBaseAddress + 20H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L0C Reserved Reserved L0W Reserved L0H R/W RW R0 R0 RW R0 RW Initial value 0 0 0 Don't care 0 Don't care Bit 11 to 0 L0H (L0 layer Height) Specifies the height of the logic frame of the L0 layer in pixel units. Setting value + 1 is the height Bit 23 to 16 L0W (L0 layer memory Width) Sets the memory width (stride) of the logic frame of the L0 layer in 64-byte units Bit 31 L0C (L0 layer Color mode) Sets the color mode for L0 layer 0 Indirect color (8 bits/pixel) mode 1 Direct color (16 bits/pixel) mode L0EM (L0-layer Extended Mode) Register DisplayBaseAddress + 110H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 ----Bit field name L0EC Reserved L0PB Reserved R/W RW R0 RW R0 Initial value 0 0 Bit 0 4 3 2 1 0 L0WP RW 0 L0 WP (L0 layer Window Position enable) Selects the display position of L0 layer Bit 23 to 20 0 Compatibility mode display (C layer supported) 1 Window display L0PB (L0 layer Palette Base) Shows the value added to the index when subtracting palette of L0 layer. 16 times of setting value is added. Bit 31 and 30 L0EC (L0 layer Extended Color mode) Sets extended color mode for L0 layer 00 Mode determined by L0C 01 Direct color (24 bits/pixel) mode 1x Reserved MB86276 'LIME' GDC Specifications Rev1.1a 184 FUJITSU SEMICONDUCTOR CONFIDENTIAL L0OA (L0 layer Origin Address) Register DisplayBaseAddress + 24H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0OA R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L0 layer. Since lower 4 bits are fixed at "0", address 16-byte-aligned. L0DA (L0-layer Display Address) Register DisplayBaseAddress + 28H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0DA R/W R0 RW0 RW Initial value 0 Don't care This register sets the display origin address of the L0 layer. For the direct color mode (16 bits/pixel), the lower 1 bit is "0", and this address is treated as being aligned in 2 bytes. L0DX (L0-layer Display position X) Register DisplayBaseAddress + 2CH address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 L0DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L0 layer on the basis of the origin of the logic frame in pixels. L0DY (L0-layer Display position Y) Register DisplayBaseAddress + 2EH address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 L0DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L0 layer on the basis of the origin of the logic frame in pixels. MB86276 'LIME' GDC Specifications Rev1.1a 185 FUJITSU SEMICONDUCTOR CONFIDENTIAL L0WX (L0 layer Window position X) Register DisplayBaseAddress + 114H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WX RW 4 3 2 1 0 2 1 0 2 1 0 This register sets the X coordinates of the display position of the L0 layer window. L0WY (L0 layer Window position Y) Register DisplayBaseAddress + 116H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WY RW 4 3 This register sets the Y coordinates of the display position of the L0 layer window. L0WW (L0 layer Window Width) Register DisplayBaseAddress + 118H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WW RW Don't care 4 3 This register controls the horizontal direction display size (width) of the L0 layer window. Do not specify "0". L0WH (L0 layer Window Height) Register DisplayBaseAddress + 11AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L0WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L0 layer window. Setting value + 1 is the height. MB86276 'LIME' GDC Specifications Rev1.1a 186 FUJITSU SEMICONDUCTOR CONFIDENTIAL L1M (L1-layer Mode) Register DisplayBaseAddress + 30H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - 5 4 3 2 1 0 Bit field name L1C L1YC L1CS L1IM Reserved L1W Reserved R/W R0 Initial value 0 Bit 23 to 16 L1W (L1 layer memory Width) Sets the memory width (stride) of the logic frame of the W layer in unit of 64 bytes Bit 28 L1IM (L1 layer Interlace Mode) Sets video capture mode when L1CS in capture mode Bit 29 0: Normal mode 1: For non-interlace display, displays captured video graphics in WEAVE mode For interlace and video display, buffers are managed in frame units (pair of odd field and even field). L1CS (L1 layer Capture Synchronize) Sets whether the layer is used as normal display layer or as video capture Bit 30 0: Normal mode 1: Capture mode L1YC (L1 layer YC mode) Sets color format of L1 layer The YC mode must be set for video capture. Bit 31 0: RGB mode 1: YC mode L1C (L1 layer Color mode) Sets color mode for L1 layer 0: Indirect color (8 bits/pixel) mode 1: Direct color (16 bits/pixel) mode MB86276 'LIME' GDC Specifications Rev1.1a 187 FUJITSU SEMICONDUCTOR CONFIDENTIAL L1EM (L1 layer Extended Mode) Register DisplayBaseAddress + 120H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 - - - Bit field name L1EC Reserved DM L1PB Reserved R/W RW R0 RW R0 Initial value 0 0 Bit 23 to 20 4 3 2 1 0 L1PB (L1 layer Palette Base) Shows the value added to the index when subtracting palette of L1 layer. 16 times of setting value is added. Bit 25 to 24 Bit 31 to 30 L1DM (L1 layer Display Magnify Mode) 00 Normal Mode (no scaling or shrink scaling) 01 Reserved 10 Magnify Scaling 11 Reserved L1EC (L1 layer Extended Color mode) Sets extended color mode for L1 layer 00 Mode determined by L1C 01 Direct color (24 bits/pixel) mode 1x Reserved L1DA (L1 layer Display Address) Register DisplayBaseAddress + 34H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L1DA R/W R0 RW Initial value 0 Don't care This register sets the display origin address of the L1 layer. For the direct color mode (16 bits/pixel), the lower 1 bit is "0", and this register is treated as being aligned in 2 bytes. Wraparound processing is not performed for the L1 layer, so the frame origin linear address and display position (X coordinates, and Y coordinates) are not specified. CBDA1 (Capture Buffer Display Address 1) Register address DisplayBaseAddress + 0x38 Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserve R/W R0 CBDA1 R Initial value 0 Undefined This register is a read-only register which is only enabled when the L1CS bit is 1 and the L1IM bit is also 1. This register indicates the starting address of an even field of the capture screen. MB86276 'LIME' GDC Specifications Rev1.1a 188 FUJITSU SEMICONDUCTOR CONFIDENTIAL L1WX (L1 layer Window position X) Register DisplayBaseAddress + 124H (DisplayBaseAddress + 18H) address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WX R/W R0 RW Initial value 0 Don't care 4 3 2 1 0 This register sets the X coordinates of the display position of the L1 layer window. This register is placed in two address spaces. The parenthesized address is the register address to maintain compatibility with previous products. The same applies to L1WY, L1WW, and L1WH. L1WY (L1 layer Window position Y) Register DisplayBaseAddress + 126H (DisplayBaseAddress + 1AH) address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WY R/W R0 RW Initial value 0 Don't care 4 3 This register sets the Y coordinates of the display position of the L1 layer window. MB86276 'LIME' GDC Specifications Rev1.1a 189 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL L1WW (L1 layer Window Width) Register DisplayBaseAddress + 128H (DisplayBaseAddress + 1CH) address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WW R/W R0 RW Initial value 0 Don't care 4 3 2 1 0 This register controls the horizontal direction display size (width) of the L1 layer window. Do not specify "0". L1WH (L1 layer Window Height) Register DisplayBaseAddress + 12AH ((DisplayBaseAddress + 1EH) address Bit number 15 14 13 12 11 10 9 8 7 6 5 Bit field name Reserved L1WH R/W R0 RW Initial value 0 Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L1 layer window. Setting value + 1 is the height. MB86276 'LIME' GDC Specifications Rev1.1a 190 FUJITSU SEMICONDUCTOR CONFIDENTIAL L2M (L2 layer Mode) Register DisplayBaseAddress + 40H address Bit number 31 30 29 28 27 - - 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L2C L2FLP Reserved L2W Reserved L2H R/W RW RW R0 RW R0 RW Initial value 0 Don't care 0 Don't care Bit 11 to 0 L2H (L2 layer Height) Specifies the height of the logic frame of the L2 layer in pixel units. Setting value + 1 is the height Bit 23 to 16 L2W (L2 layer memory Width) Sets the memory width (stride) of the logic frame of the L2 layer in 64-byte units Bit 30 and 29 L2FLP (L2 layer Flip mode) Sets flipping mode for L2 layer Bit 31 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved L2C (L2 layer Color mode) Sets the color mode for L2 layer 0 Indirect color (8 bits/pixel) mode 1 Direct color (16 bits/pixel) mode MB86276 'LIME' GDC Specifications Rev1.1a 191 FUJITSU SEMICONDUCTOR CONFIDENTIAL L2EM (L2 layer Extended Mode) Register DisplayBaseAddress + 130H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name L2EC Reserved L2PB Reserved R/W RW R0 RW R0 Initial value 00 0 0 0 Bit 0 ----- 4 3 2 1 RW RW 0 0 L2 WP (L2 layer Window Position enable) Selects the display position of L2 layer Bit 1 0 Compatibility mode display (ML layer supported) 1 Window display L2OM (L2 layer Overlay Mode) Selects the overlay mode for L2 layer Bit 23 to 20 0 Compatibility mode 1 Extended mode L2PB (L2 layer Palette Base) Shows the value added to the index when subtracting palette of L2 layer. 16 times of setting value is added. Bit 31 and 30 L2EC (L2 layer Extended Color mode) Sets extended color mode for L2 layer 00 Mode determined by L2C 01 Direct color (24 bits/pixel) mode 1x Reserved MB86276 'LIME' GDC Specifications Rev1.1a 192 0 L2OM L2WP FUJITSU SEMICONDUCTOR CONFIDENTIAL L2OA0 (L2 layer Origin Address 0) Register DisplayBaseAddress + 44H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L2 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L2DA0 (L2 layer Display Address 0) Register DisplayBaseAddress + 48H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L2 layer in frame 0. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L2OA1 (L2 layer Origin Address 1) Register DisplayBaseAddress + 4CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L2 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L2DA1 (L2 layer Display Address 1) Register DisplayBaseAddress + 50H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L2 layer in frame 1. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L2DX (L2 layer Display position X) Register DisplayBaseAddress + 54H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 L2DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L2 layer on the basis of the origin of the logic frame in pixels. MB86276 'LIME' GDC Specifications Rev1.1a 193 FUJITSU SEMICONDUCTOR CONFIDENTIAL L2DY (L2 layer Display position Y) Register DisplayBaseAddress + 56H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 L2DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L2 layer on the basis of the origin of the logic frame in pixels. L2WX (L2 layer Window position X) Register DisplayBaseAddress + 134H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WX RW Don't care 4 3 2 1 0 2 1 0 2 1 0 This register sets the X coordinates of the display position of the L2 layer window. L2WY (L2 layer Window position Y) Register DisplayBaseAddress + 136H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WY RW Don't care 4 3 This register sets the Y coordinates of the display position of the L2 layer window. L2WW (L2 layer Window Width) Register DisplayBaseAddress + 138H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WW RW Don't care 4 3 This register controls the horizontal direction display size (width) of the L2 layer window. Do not specify "0". L2WH (L2 layer Window Height) Register DisplayBaseAddress + 13AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L2WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L2 layer window. Setting value + 1 is the height. MB86276 'LIME' GDC Specifications Rev1.1a 194 FUJITSU SEMICONDUCTOR CONFIDENTIAL L3M (L3 layer Mode) Register DisplayBaseAddress + 58H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L3C L3FLP Reserved L3W Reserved L3H R/W RW R0 R0 RW R0 RW Initial value 0 0 0 Don't care 0 Don't care Bit 11 to 0 L3H (L3 layer Height) Specifies the height of the logic frame of the L3 layer in pixel units. Setting value + 1 is the height Bit 23 to 16 L3W (L3 layer memory Width) Sets the memory width (stride) of the logic frame of the L3 layer in 64-byte units Bit 30 and 29 L3FLP (L3 layer Flip mode) Sets flipping mode for L3 layer Bit 31 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved L3C (L3 layer Color mode) Sets the color mode for L3 layer 0 Indirect color (8 bits/pixel) mode 1 Direct color (16 bits/pixel) mode MB86276 'LIME' GDC Specifications Rev1.1a 195 FUJITSU SEMICONDUCTOR CONFIDENTIAL L3EM (L3 layer Extended Mode) Register DisplayBaseAddress + 140H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name L3EC Reserved L3PB Reserved R/W RW R0 RW R0 Initial value 00 0 0 0 Bit 0 --- 4 3 2 1 RW RW L3 WP (L3 layer Window Position enable) Selects the display position of L3 layer Bit 1 0 Compatibility mode display (MR layer supported) 1 Window display L3OM (L3 layer Overlay Mode) Selects the overlay mode for L3 layer Bit 23 to 20 0 Compatibility mode 1 Extended mode L3PB (L3 layer Palette Base) Shows the value added to the index when subtracting palette of L3 layer. 16 times of setting value is added. Bit 31 and 30 L3EC (L3 layer Extended Color mode) Sets extended color mode for L3 layer 00 Mode determined by L3C 01 Direct color (24 bits/pixel) mode 1x Reserved MB86276 'LIME' GDC Specifications Rev1.1a 196 0 L3OM L3WP 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL L3OA0 (L3 layer Origin Address 0) Register DisplayBaseAddress + 5CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L3 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L3DA0 (L3 layer Display Address 0) Register DisplayBaseAddress + 60H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L3 layer in frame 0. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L3OA1 (L3 layer Origin Address 1) Register DisplayBaseAddress + 64H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L3 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L3OA1 (L3 layer Display Address 1) Register DisplayBaseAddress + 68H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L3 layer in frame 1. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L3DX (L3 layer Display position X) Register DisplayBaseAddress + 6CH address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 L3DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L3 layer on the basis of the origin of the logic frame in pixels. MB86276 'LIME' GDC Specifications Rev1.1a 197 FUJITSU SEMICONDUCTOR CONFIDENTIAL L3DY (L3 layer Display position Y) Register DisplayBaseAddress + 6EH address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 L3DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L3 layer on the basis of the origin of the logic frame in pixels. L3WX (L3 layer Window position X) Register DisplayBaseAddress + 144H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WX RW Don't care 4 3 2 1 0 2 1 0 2 1 0 This register sets the X coordinates of the display position of the L3 layer window. L3WY (L3 layer Window position Y) Register DisplayBaseAddress + 146H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WY RW Don't care 4 3 This register sets the Y coordinates of the display position of the L3 layer window. L3WW (L3 layer Window Width) Register DisplayBaseAddress + 148H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WW RW Don't care 4 3 This register controls the horizontal direction display size (width) of the L3 layer window. Do not specify "0". L3WH (L3-layer Window Height) Register DisplayBaseAddress + 14AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L3WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L3 layer window. Setting value + 1 is the height. MB86276 'LIME' GDC Specifications Rev1.1a 198 FUJITSU SEMICONDUCTOR CONFIDENTIAL L4M (L4 layer Mode) Register DisplayBaseAddress + 70H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L4C L4FLP Reserved L4W Reserved L4H R/W RW RW R0 RW R0 RW Initial value 0 Don't care 0 Don't care Bit 11 to 0 L4H (L4 layer Height) Specifies the height of the logic frame of the L4 layer in pixel units. Setting value + 1 is the height Bit 23 to 16 L4W (L4 layer memory Width) Sets the memory width (stride) logic frame of the L4 layer in 64-byte units Bit 30 and 29 L4FLP (L4 layer Flip mode) Sets flipping mode for L4 layer Bit 31 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved L4C (L4 layer Color mode) Sets the color mode for L4 layer 0 Indirect color (8 bits/pixel) mode 1 Direct color (16 bits/pixel) mode MB86276 'LIME' GDC Specifications Rev1.1a 199 FUJITSU SEMICONDUCTOR CONFIDENTIAL L4EM (L4 layer Extended Mode) Register DisplayBaseAddress + 150H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name L4EC Reserved Reserved R/W RW R0 R0 Initial value 00 0 0 Bit 0 L4 WP (L4 layer Window Position enable) Selects the display position of L4 layer Bit 1 0 Compatibility mode display (BL layer supported) 1 Window display L4OM (L4 layer Overlay Mode) Selects the overlay mode for L4 layer Bit 31 and 30 0 Compatibility mode 1 Extended mode L4EC (L4 layer Extended Color mode) Sets extended color mode for L4 layer 00 Mode determined by L4C 01 Direct color (24 bits/pixel) mode 1x Reserved MB86276 'LIME' GDC Specifications Rev1.1a 200 --- 4 3 2 1 0 L4OM L4WP RW RW 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL L4OA0 (L4 layer Origin Address 0) Register DisplayBaseAddress + 74H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L4 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L4DA0 (L4 layer Display Address 0) Register DisplayBaseAddress + 78H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L4 layer in frame 0. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L4OA1 (L4 layer Origin Address 1) Register DisplayBaseAddress + 7CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L4 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L4DA1 (L4 layer Display Address 1) Register DisplayBaseAddress + 80H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L4 layer in frame 1. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L4DX (L4 layer Display position X) Register DisplayBaseAddress + 84H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 L4DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L4 layer on the basis of the origin of the logic frame in pixels. MB86276 'LIME' GDC Specifications Rev1.1a 201 FUJITSU SEMICONDUCTOR CONFIDENTIAL L4DY (L4 layer Display position Y) Register DisplayBaseAddress + 86H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 L4DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L4 layer on the basis of the origin of the logic frame in pixels. L4WX (L4 layer Window position X) Register DisplayBaseAddress + 154H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WX RW Don't care 4 3 2 1 0 2 1 0 2 1 0 This register sets the X coordinates of the display position of the L4 layer window. L4WY (L4 layer Window position Y) Register DisplayBaseAddress + 156H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WY RW Don't care 4 3 This register sets the Y coordinates of the display position of the L4 layer window. L4WW (L4 layer Window Width) Register DisplayBaseAddress + 158H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WW RW Don't care 4 3 This register controls the horizontal direction display size (width) of the L4 layer window. Do not specify "0". L4WH (L4 layer Window Height) Register DisplayBaseAddress + 15AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L4WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L4 layer window. Setting value + 1 is the height. MB86276 'LIME' GDC Specifications Rev1.1a 202 FUJITSU SEMICONDUCTOR CONFIDENTIAL L5M (L5 layer Mode) Register DisplayBaseAddress + 88H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L5C L5FLP Reserved L5W Reserved L5H R/W RW RW R0 RW R0 RW Initial value 0 Don't care 0 Don't care Bit 11 to 0 L5H (L5 layer Height) Specifies the height of the logic frame of the L5 layer in pixel units. Setting value + 1 is the height Bit 23 to 16 L5W (L5 layer memory Width) Sets the memory width (stride) logic frame of the L5 layer in 64-byte units Bit 30 and 29 L5FLP (L5 layer Flip mode) Sets flipping mode for L5 layer Bit 31 00 Displays frame 0 01 Displays frame 1 10 Switches frame 0 and 1 alternately for display 11 Reserved L5C (L5 layer Color mode) Sets the color mode for L5 layer 0 Indirect color (8 bits/pixel) mode 1 Direct color (16 bits/pixel) mode MB86276 'LIME' GDC Specifications Rev1.1a 203 FUJITSU SEMICONDUCTOR CONFIDENTIAL L5EM (L5 layer Extended Mode) Register DisplayBaseAddress + 110H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name L5EC Reserved Reserved R/W RW R0 R0 Initial value 00 0 0 Bit 0 L5 WP (L5 layer Window Position enable) Selects the display position of L5 layer Bit 1 0 Compatibility mode display (BR layer supported) 1 Window display L5OM (L5 layer Overlay Mode) Selects the overlay mode for L5 layer Bit 31 to 30 0 Compatibility mode 1 Extended mode L5EC (L5 layer Extended Color mode) Sets extended color mode for L5 layer 00 Mode determined by L5C 01 Direct color (24 bits/pixel) mode 1x Reserved MB86276 'LIME' GDC Specifications Rev1.1a 204 --- 4 3 2 1 0 L5OM L5WP RW RW 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL L5OA0 (L5 layer Origin Address 0) Register DisplayBaseAddress + 8CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5OA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L5 layer in frame 0. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. L5DA0 (L5 layer Display Address 0) Register DisplayBaseAddress + 90H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5DA0 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L5 layer in frame 0. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L5OA1 (L5 layer Origin Address 1) Register DisplayBaseAddress + 94H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5OA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the origin address of the logic frame of the L5 layer in frame 1. Since lower 4-bits are fixed to "0", this address is 16-byte aligned. L5DA1 (L5 layer Display Address 1) Register DisplayBaseAddress + 98H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5DA1 R/W R0 RW Initial value 0 Don't care This register sets the origin address of the L5 layer in frame 1. For the direct color mode (16 bits/pixel), the lower 1 bit is "0" and this address is 2-byte aligned. L5DX (L5 layer Display position X) Register DisplayBaseAddress + 9CH address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 L5DX RW Don't care 4 3 2 1 0 This register sets the display starting position (X coordinates) of the L5 layer on the basis of the origin of the logic frame in pixels. MB86276 'LIME' GDC Specifications Rev1.1a 205 FUJITSU SEMICONDUCTOR CONFIDENTIAL L5DY (L5 layer Display position Y) Register DisplayBaseAddress + 9EH address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 L5DY RW Don't care 4 3 2 1 0 This register sets the display starting position (Y coordinates) of the L5 layer on the basis of the origin of the logic frame in pixels. L5WX (L5 layer Window position X) Register DisplayBaseAddress + 164H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WX RW Don't care 4 3 2 1 0 2 1 0 2 1 0 This register sets the X coordinates of the display position of the L5 layer window. L5WY (L5 layer Window position Y) Register DisplayBaseAddress + 166H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WY RW Don't care 4 3 This register sets the Y coordinates of the display position of the L5 layer window. L5WW (L5 layer Window Width) Register DisplayBaseAddress + 168H address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WW RW Don't care 4 3 This register controls the horizontal direction display size (width) of the L5 layer window. Do not specify "0". L5WH (L5 layer Window Height) Register DisplayBaseAddress + 16AH address Bit number 15 14 13 12 11 10 Bit field name Reserved R/W R0 Initial value 0 9 8 7 6 5 L5WH RW Don't care 4 3 2 1 0 This register controls the vertical direction display size (height) of the L5 layer window. Setting value + 1 is the height. MB86276 'LIME' GDC Specifications Rev1.1a 206 FUJITSU SEMICONDUCTOR CONFIDENTIAL CUTC (Cursor Transparent Control) Register DisplayBaseAddress + A0H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value Bit 7 to 0 10 9 8 CUZT RW 7 6 5 4 3 CUTC RW Don't 0 2 1 0 Don't care care CUTC (Cursor Transparent Code) Sets color code handled as transparent code Bit 8 CUZT (Cursor Zero Transparency) Defines handling of color code 0 0 Code 0 as non-transparency color 1 Code 0 as transparency color CPM (Cursor Priority Mode) Register DisplayBaseAddress + A2H address Bit number 7 6 5 Bit field name Reserved CEN1 R/W R0 RW Initial value 0 0 4 CEN0 RW 0 3 2 Reserved R0 0 1 CUO1 RW 0 0 CUO0 RW 0 This register controls the display priority of cursors. Cursor 0 is always preferred to cursor 1. Bit 0 CUO0 (Cursor Overlap 0) Sets display priority between cursor 0 and pixels of Console layer Bit 1 0 Puts cursor 0 at lower than L0 layer. 1 Puts cursor 0 at higher than L0 layer. CUO1 (Cursor Overlap 1) Sets display priority between cursor 1 and C layer Bit 4 0 Puts cursor 1 at lower than L0 layer. 1 Puts cursor 1 at lower than L0 layer. CEN0 (Cursor Enable 0) Sets enabling display of cursor 0 Bit 5 0 Disabled 1 Enabled CEN1 (Cursor Enable 1) Sets enabling display of cursor 1 0 Disabled 1 Enabled MB86276 'LIME' GDC Specifications Rev1.1a 207 FUJITSU SEMICONDUCTOR CONFIDENTIAL CUOA0 (Cursor-0 Origin Address) Register DisplayBaseAddress + A4H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CUOA0 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the start address of the cursor 0 pattern. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. CUX0 (Cursor-0 X position) Register DisplayBaseAddress + A8H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 CUX0 RW Don't care 4 3 2 1 0 This register sets the display position (X coordinates) of the cursor 0 in pixels. The reference position of the coordinates is the top left of the cursor pattern. CUY0 (Cursor-0 Y position) Register DisplayBaseAddress + AaH address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 CUY0 RW Don't care 4 3 2 1 0 This register sets the display position (Y coordinates) of the cursor 0 in pixels. The reference position of the coordinates is the top left of the cursor pattern. MB86276 'LIME' GDC Specifications Rev1.1a 208 FUJITSU SEMICONDUCTOR CONFIDENTIAL CUOA1 (Cursor-1 Origin Address) Register DisplayBaseAddress + ACH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved CUOA1 R/W R0 RW R0 Initial value 0 Don't care 0000 This register sets the start address of the cursor 1 pattern. Since lower 4 bits are fixed to "0", this address is 16-byte aligned. CUX1 (Cursor-1 X position) Register DisplayBaseAddress + B0H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 CUX1 RW Don't care 4 3 2 1 0 This register sets the display position (X coordinates) of the cursor 1 in pixels. The reference position of the coordinates is the top left of the cursor pattern. CUY1 (Cursor-1 Y position) Register DisplayBaseAddress + B2H address Bit number 15 14 13 12 11 Bit field name Reserved R/W R0 Initial value 0 10 9 8 7 6 5 CUY1 RW Don't care 4 3 2 1 0 This register sets the display position (Y coordinates) of the cursor 1 in pixels. The reference position of the coordinates is the top left of the cursor pattern. MB86276 'LIME' GDC Specifications Rev1.1a 209 FUJITSU SEMICONDUCTOR CONFIDENTIAL MDC (Multi Display Control) Register DisplayBaseAddress + 170H address 31 30 29 28 24 23 21 Bit number reserve Bit field name MDen RW R0 R/W 0 0 Initial value 20 19 18 17 16 15 14 13 12 11 10 This register controls dual display mode. Bit 0 Bit 1 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 13 Bit 14 SC0en0 ( screen 0 enable 0) 0: L0 is not included into screen 0 1: L0 is included into screen 0 SC0en1 ( screen 0 enable 1) 0: L1 is not included into screen 0 1: L1 is included into screen 0 SC0en5 ( screen 0 enable 5) 0: L5 is not included into screen 0 1: L5 is included into screen 0 SC0en6 ( screen 0 enable 6) 0: Cursor0 is not included into screen 0 1: Cursor0 is included into screen 0 SC0en7 ( screen 0 enable 7) 0: Cursor1 is not included into screen 0 1: Cursor1 is included into screen 0 SC1en0 ( screen 1 enable 0) 0: L0 is not included into screen 1 1: L0 is included into screen 1 SC1en1 ( screen 1 enable 1) 0: L1 is not included into screen 1 1: L1 is included into screen 1 SC1en5 ( screen 1 enable 5) 0: L5 is not included into screen 1 1: L5 is included into screen 1 SC1en6 ( screen 1 enable 6) MB86276 'LIME' GDC Specifications Rev1.1a 210 9 8 7 6 5 4 3 SC1en SC0en RW RW X X 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL Bit 15 Bit 31 0: Cursor 0 is not included into screen 1 1: Cursor 0 is included into screen 1 SC1en7 ( screen 1 enable 7) 0: Cursor 1 is not included into screen 1 1: Cursor 1 is included into screen 1 MDen ( multi display enable ) This enables multi or dual display mode 0: Single display mode 1: Dual display mode MB86276 'LIME' GDC Specifications Rev1.1a 211 FUJITSU SEMICONDUCTOR CONFIDENTIAL DLS (Display Layer Select) Register DisplayBaseAddress + 180H address Bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved DLS5 DLS4 DLS3 DLS2 DLS1 DSL0 R/W R0 R0 RW R0 RW R0 RW R0 RW R0 RW R0 RW Initial value 101 100 011 010 001 000 This register defines the blending sequence. Bit 3 to 0 DSL0 (Display Layer Select 0) Selects the top layer subjected to blending. 0000 L0 layer 0001 L1 layer : : 0101 L5 layer 0110 Reserved : Bit 7 to 4 : 0110 Reserved 0111 Not selected DSL1 (Display Layer Select 1) Selects the second layer subjected to blending. The bit values are the same as DSL0. Bit 11 to 8 DSL2 (Display Layer Select 2) Selects the third layer subjected to blending. The bit values are the same as DSL0. Bit 15 to 12 DSL3 (Display Layer Select 3) Selects the fourth layer subjected to blending. The bit values are the same as DSL0. Bit 19 to 16 DSL4 (Display Layer Select 4) Selects the fifth layer subjected to blending. The bit values are the same as DSL0. Bit 23 to 20 DSL5 (Display Layer Select 5) Selects the bottom layer subjected to blending. The bit values are the same as DSL0. MB86276 'LIME' GDC Specifications Rev1.1a 212 FUJITSU SEMICONDUCTOR CONFIDENTIAL DBGC (Display Background Color) Register DisplayBaseAddress + 184H address Bit number 31 30 29 ----- 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved DBGR DBGG DBGB R/W R0 Initial value This register specifies the color to be displayed in areas outside the display area of each layer on the window. Bit 7 to 0 DBGB (Display Background Blue) Specifies the blue level of the background color. Bit 15 to 8 DBGG (Display Background Green) Specifies the green level of the background color. Bit 23 to 16 DBGR (Display Background Red) Specifies the red level of the background color. MB86276 'LIME' GDC Specifications Rev1.1a 213 FUJITSU SEMICONDUCTOR CONFIDENTIAL L0BLD (L0 Blend) Register DisplayBaseAddress + B4H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L0BE L0BS L0BI L0BP Reserved L0BR R/W Initial value This register specifies the blend parameters for the L0 layer. This register corresponds to BRATIO or BMODE for previous products. Bit 7 to 0 L0BR (L0 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 13 L0BP (L0 layer Blend Plane) Specifies that the L5 layer is the blend plane. Bit 14 0 Value of L0BR used as blend ratio 1 Pixel of L5 layer used as blend ratio L0BI (L0 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". Bit 15 0 Blend ratio calculated as is 1 1/256 added when blend ratio 0 L0BS (L0 layer Blend Select) Selects the blend calculation expression. Bit 16 0 Upper image x Blend ratio + Lower image x (1 - Blend ratio) 1 Upper image x (1 - Blend ratio) + Lower image x Blend ratio L0BE (L0 layer Blend Enable) This bit enables blending. 0 Overlay via transparent color 1 Overlay via blending Before blending, the blend mode must be specified using L0BE, and alpha must also be enabled for L0 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86276 'LIME' GDC Specifications Rev1.1a 214 FUJITSU SEMICONDUCTOR CONFIDENTIAL L1BLD (L1 Blend) Register DisplayBaseAddress + 188H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L1BE L1BS L1BI L1BP Reserved L1BR R/W Initial value This register specifies the blend parameters for the L1 layer. Bit 7 to 0 L1BR (L1 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 13 L1BP (L1 layer Blend Plane) Specifies that the L5 layer is the blend plane. Bit 14 0 Value of L1BR used as blend ratio 1 Pixel of L5 layer used as blend ratio L1BI (L1 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". Bit 15 0 Blend ratio calculated as is 1 1/256 added when blend ratio 0 L1BS (L1 layer Blend Select) Selects the blend calculation expression. Bit 16 0 Upper image x Blend ratio + Lower image x (1 - Blend ratio) 1 Upper image x (1 - Blend ratio) + Lower image x Blend ratio L1BE (L1 layer Blend Enable) This bit enables blending. 0 Overlay via transparent color 1 Overlay via blending Before blending, the blend mode must be specified using L1BE, and alpha must also be enabled for L1 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86276 'LIME' GDC Specifications Rev1.1a 215 FUJITSU SEMICONDUCTOR CONFIDENTIAL L2BLD (L2 Blend) Register DisplayBaseAddress + 18CH address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L2BE L2BS L2BI L2BP Reserved L2BR R/W Initial value This register specifies the blend parameters for the L2 layer. Bit 7 to 0 L2BR (L2 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 13 L2BP (L2 layer Blend Plane) Specifies that the L5 layer is the blend plane. Bit 14 0 Value of L2BR used as blend ratio 1 Pixel of L5 layer used as blend ratio L2BI (L2 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". Bit 15 0 Blend ratio calculated as is 1 1/256 added when blend ratio 0 L2BS (L2 layer Blend Select) Selects the blend calculation expression. Bit 16 0 Upper image x Blend ratio + Lower image x (1 - Blend ratio) 1 Upper image x (1 - Blend ratio) + Lower image x Blend ratio L2BE (L2 layer Blend Enable) This bit enables blending. 0 Overlay via transparent color 1 Overlay via blending Before blending, the blend mode must be specified using L2BE, and alpha must also be enabled for L2 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86276 'LIME' GDC Specifications Rev1.1a 216 FUJITSU SEMICONDUCTOR CONFIDENTIAL L3BLD (L3 Blend) Register DisplayBaseAddress + 190H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L3BE L3BS L3BI L3BP Reserved L3BR R/W Initial value This register specifies the blend parameters for the L3 layer. Bit 7 to 0 L3BR (L3 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 13 L3BP (L3 layer Blend Plane) Specifies that the L5 layer is the blend plane. Bit 14 0 Value of L3BR used as blend ratio 1 Pixel of L5 layer used as blend ratio L3BI (L3 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". Bit 15 0 Blend ratio calculated as is 1 1/256 added when blend ratio 0 L3BS (L3 layer Blend Select) Selects the blend calculation expression. Bit 16 0 Upper image x Blend ratio + Lower image x (1 - Blend ratio) 1 Upper image x (1 - Blend ratio) + Lower image x Blend ratio L3BE (L3 layer Blend Enable) This bit enables blending. 0 Overlay via transparent color 1 Overlay via blending Before blending, the blend mode must be specified using L3BE, and alpha must also be enabled for L3 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86276 'LIME' GDC Specifications Rev1.1a 217 FUJITSU SEMICONDUCTOR CONFIDENTIAL L4BLD (L4 Blend) Register DisplayBaseAddress + 194H address Bit number 31 30 29 28 ----- 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L4BE L4BS L4BI L4BP Reserved L4BR R/W Initial value This register specifies the blend parameters for the L4 layer. Bit 7 to 0 L4BR (L4 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 13 L4BP (L4 layer Blend Plane) Specifies that the L5 layer is the blend plane. Bit 14 0 Value of L4BR used as blend ratio 1 Pixel of L5 layer used as blend ratio L4BI (L4 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". Bit 15 0 Blend ratio calculated as is 1 1/256 added when blend ratio 0 L4BS (L4 layer Blend Select) Selects the blend calculation expression. Bit 16 0 Upper image x Blend ratio + Lower image x (1 - Blend ratio) 1 Upper image x (1 - Blend ratio) + Lower image x Blend ratio L4BE (L4 layer Blend Enable) This bit enables blending. 0 Overlay via transparent color 1 Overlay via blending Before blending, the blend mode must be specified using L4BE, and alpha must also be enabled for L4 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86276 'LIME' GDC Specifications Rev1.1a 218 FUJITSU SEMICONDUCTOR CONFIDENTIAL L5BLD (L5 Blend) Register DisplayBaseAddress + 198h address Bit number 31 30 29 28 ----- 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved L5BE L5BS L5BI Reserved L5BR R/W R0 RW RW RW R0 RW Initial value 0 0 0 This register specifies the blend parameters for the L5 layer. Bit 7 to 0 L5BR (L5 layer Blend Ratio) Sets the blend ratio. Basically, the blend ratio is setting value/256. Bit 14 L5BI (L5 layer Blend Increment) Selects whether or not 1/256 is added when the blend ratio is not "0". Bit 15 0 Blend ratio calculated as is 1 1/256 added when blend ratio 0 L5BS (L5 layer Blend Select) Selects the blend calculation expression. Bit 16 0 Upper image x Blend ratio + Lower image x (1 - Blend ratio) 1 Upper image x (1 - Blend ratio) + Lower image x Blend ratio L5BE (L5 layer Blend Enable) This bit enables blending. 0 Overlay via transparent color 1 Overlay via blending Before blending, the blend mode must be specified using L5BE, and alpha must also be enabled for L5 layer display data. For direct color, alpha is specified using the MSB of data; for indirect color, alpha is specified using the MSB of palette data. MB86276 'LIME' GDC Specifications Rev1.1a 219 FUJITSU SEMICONDUCTOR CONFIDENTIAL L0TC (L0 layer Transparency Control) Register DisplayBaseAddress + BCH address Bit number 15 14 13 12 11 10 Bit field name L0ZT R/W RW Initial value 0 9 8 7 6 L0TC RW Don't care 5 4 3 2 1 0 This register sets the transparent color for the L0 layer. Color set by this register is transparent in blend mode. When L0TC = 0 and L0ZT = 0, color 0 is displayed in black (transparent). This register corresponds to the CTC register for previous products. Bit 14 to 0 L0TC (L0 layer Transparent Color) Sets transparent color code for the L0 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 15 L0ZT (L0 layer Zero Transparency) Sets handling of color code 0 in L0 layer 0: Code 0 as transparency color 1: Code 0 as non-transparency color L2TC (L2 layer Transparency Control) Register DisplayBaseAddress + C2H address Bit number 15 14 13 12 11 Bit field name L2ZT R/W RW Initial value 0 10 9 8 7 6 L2TC RW Don't care 5 4 3 2 1 This register sets the transparent color for the L2 layer. When L2TC = 0 and L2ZT = 0, color 0 is displayed in black (transparent). This register corresponds to the MLTC register for previous products. Bit 14 to 0 L2TC (L2 layer Transparent Color) Sets transparent color code for the L2 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 15 L2ZT (L2 layer Zero Transparency) Sets handling of color code 0 in L2 layer 0 Code 0 as transparency color 1 Code 0 as non-transparency color MB86276 'LIME' GDC Specifications Rev1.1a 220 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL L3TC (L3 layer Transparency Control) Register DisplayBaseAddress + C0H address Bit number 15 14 13 12 11 Bit field name L3ZT R/W RW Initial value 0 10 9 8 7 6 L3TC RW Don't care 5 4 3 2 1 0 This register sets the transparent color for the L3 layer. When L3TC = 0 and L3ZT = 0, color 0 is displayed in black (transparent). This register corresponds to the MLTC register for previous products. Bit 14 to 0 L3TC (L3 layer Transparent Color) Sets transparent color code for the L3 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 15 L3ZT (L3 layer Zero Transparency) Sets handling of color code 0 in L3 layer 0 Code 0 as transparency color 1 Code 0 as non-transparency color L0ETC (L0 layer Extend Transparency Control) Register DisplayBaseAddress + 1A0H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L0EZT Reserved L0ETC R/W RW R0 RW Initial value 0 0 This register sets the transparent color for the L0 layer. The 24 bits/pixel transparent color is set using this register. The lower 15 bits of this register are physically the same as L0TC. Also, L0ETZ is physically the same as L0TZ. When L0ETC = 0 and L0EZT = 0, color 0 is displayed in black (transparent). Bit 23 to 0 L0ETC (L0 layer Extend Transparent Color) Sets transparent color code for the L0 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L0EZT (L0 layer Extend Zero Transparency) Sets handling of color code 0 in L0 layer 0 Code 0 as transparency color 1 Code 0 as non-transparency color MB86276 'LIME' GDC Specifications Rev1.1a 221 FUJITSU SEMICONDUCTOR CONFIDENTIAL L1ETC (L1 layer Extend Transparency Control) Register DisplayBaseAddress + 1A4H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L1EZT Reserved L1ETC R/W RW R0 RW Initial value This register sets the transparent color for the L1 layer. When L1ETC = 0 and L1EZT = 0, color 0 is displayed in black (transparent). For YCbCr display, transparent color checking is not performed; processing is always performed assuming that transparent color is not used. Bit 23 to 0 L1ETC (L1 layer Extend Transparent Color) Sets transparent color code for the L1 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L1EZT (L1 layer Extend Zero Transparency) Sets handling of color code 0 in L1 layer 0 Code 0 as transparency color 1 Code 0 as non-transparency color L2ETC (L2 layer Extend Transparency Control) Register DisplayBaseAddress + 1A8H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L2EZT Reserved L2ETC R/W RW R0 RW Initial value This register sets the transparent color for the L2 layer. The 24 bits/pixel transparent color is set using this register. The lower 15 bits of this register are physically the same as L2TC. Also, L2ETZ is physically the same as L2TZ. When L2ETC = 0 and L2EZT = 0, color 0 is displayed in black (transparent). Bit 23 to 0 L2ETC (L2 layer Extend Transparent Color) Sets transparent color code for the L2 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L2EZT (L2 layer Extend Zero Transparency) Sets handling of color code 0 in L2 layer 0 Code 0 as transparency color 1 Code 0 as non-transparency color MB86276 'LIME' GDC Specifications Rev1.1a 222 FUJITSU SEMICONDUCTOR CONFIDENTIAL L3ETC (L3 layer Extend Transparency Control) Register DisplayBaseAddress + 1ACH address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L3EZT Reserved L3ETC R/W RW R0 RW Initial value 0 0 This register sets the transparent color for the L3 layer. The 24 bits/pixel transparent color is set using this register. The lower 15 bits of this register are physically the same as L3TC. Also, L3ETZ is physically the same as L3TZ. When L3ETC = 0 and L3EZT = 0, color 0 is displayed in black (transparent). Bit 23 to 0 L3ETC (L3 layer Extend Transparent Color) Sets transparent color code for the L3 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L3EZT (L3 layer Extend Zero Transparency) Sets handling of color code 0 in L3 layer 0 Code 0 as transparency color 1 Code 0 as non-transparency color L4ETC (L4 layer Extend Transparency Control) Register DisplayBaseAddress + 1B0H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L4EZT Reserved L4ETC R/W RW R0 RW Initial value 0 0 This register sets the transparent color for the L4 layer. This register sets the transparent color for the L4 layer. When L4ETC = 0 and L4EZT = 0, color 0 is displayed in black (transparent). Bit 23 to 0 L4ETC (L4 layer Extend Transparent Color) Sets transparent color code for the L4 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L4EZT (L4 layer Extend Zero Transparency) Sets handling of color code 0 in L4 layer 0 Code 0 as transparency color 1 Code 0 as non-transparency color MB86276 'LIME' GDC Specifications Rev1.1a 223 FUJITSU SEMICONDUCTOR CONFIDENTIAL L5ETC (L5 layer Extend Transparency Control) Register DisplayBaseAddress + 1B4H address Bit number 31 30 29 28 --- 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name L5EZT Reserved L5ETC R/W RW R0 RW Initial value 0 0 This register sets the transparent color for the L5 layer. This register sets the transparent color for the L5 layer. When L5ETC = 0 and L5EZT = 0, color 0 is displayed in black (transparent). Bit 23 to 0 L5ETC (L5 layer Extend Transparent Color) Sets transparent color code for the L5 layer. In indirect color mode (8 bits/pixel) bits 7 to 0 are used. Bit 31 L5EZT (L5 layer Extend Zero Transparency) Sets handling of color code 0 in L5 layer 0 Code 0 as transparency color 1 Code 0 as non-transparency color MB86276 'LIME' GDC Specifications Rev1.1a 224 FUJITSU SEMICONDUCTOR CONFIDENTIAL L1YCR0 (L1 layer YC to Red coefficient 0) Register address Bit No. DisplayBaseAddress + 0x1E0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved a12 Reserved a11 R/W R0 RW R0 RW Initial value 0 000 0000 0000 0 001 0010 1011 This register defines the parameter for the red component at YCbCr/RGB conversion. Bit 10-0 a11 11-bit signed fixed-point value. The lower 8 bits of the value are placed after the decimal point. The value is complement representation for 2. Bit 26-16 a12 11-bit signed fixed-point value. The lower 8 bits of the value are placed after the decimal point. The value is complement representation for 2. L1YCR1 (L1 layer YC to Red coefficient 1) Register address Bit No. DisplayBaseAddress + 0x1E4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved b1 Reserved R/W Initial value a13 R0 RW R0 RW 0 1 1111 0000 0 001 1001 1000 This register defines the parameter for the red component at YCbCr/RGB conversion time. Bit 10-0 a13 11-bit signed fixed-point value. The lower 8 bits of the value are placed after the decimal point. The value is complement representation for 2. Bit 24-16 b1 9-bit signed integer. The value is complement representation for 2. MB86276 'LIME' GDC Specifications Rev1.1a 225 FUJITSU SEMICONDUCTOR CONFIDENTIAL L1YCG0 (L1 layer YC to Green coefficient 0) Register address Bit No. DisplayBaseAddress + 0x1E8 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved a22 Reserved a21 R/W R0 RW R0 RW Initial value 0 111 1001 1100 0 001 0010 1011 This register defines the parameter for the green component at YCbCr/RGB conversion time. Bit 10-0 a21 11-bit signed fixed-point value. The lower 8 bits of the value are placed after the decimal point. The value is complement representation for 2. Bit 26-16 a22 11-bit signed fixed-point value. The lower 8 bits of the value are placed after the decimal point. The value is complement representation for 2. L1YCG1 (L1 layer YC to Green coefficient 1) Register address Bit No. DisplayBaseAddress + 0x1EC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved b2 Reserved a23 R/W R0 RW R0 RW Initial value 0 1 1111 0000 0 111 0010 1111 This register defines the parameter for the green component at YCbCr/RGB conversion time. Bit 10-0 a23 11-bit signed fixed-point value. The lower 8 bits of the value are placed after the decimal point. The value is complement representation for 2. Bit 24-16 b2 9-bit signed integer. The value is complement representation for 2. MB86276 'LIME' GDC Specifications Rev1.1a 226 FUJITSU SEMICONDUCTOR CONFIDENTIAL L1YCB0 (L1 layer YC to Blue coefficient 0) Register address Bit No. DisplayBaseAddress + 0x1F0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved a32 Reserved a31 R/W R0 RW R0 RW Initial value 0 010 0000 0100 0 001 0010 1011 This register defines the parameter for the blue component at YCbCr/RGB conversion. Bit 10-0 a31 11-bit signed fixed-point value. The lower 8 bits of the value are placed after the decimal point. The value is complement representation for 2. Bit 26-16 a32 11-bit signed fixed-point value. The lower 8 bits of the value are placed after the decimal point. The value is complement representation for 2. L1YCB1 (L1 layer YC to Green coefficient 1) Register address Bit No. DisplayBaseAddress + 0x1F4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name Reserved b3 Reserved a33 R/W R0 RW R0 RW Initial value 0 1 1111 0000 0 000 0000 0000 This register defines the parameter for the blue component at YCbCr/RGB conversion. Bit 10-0 a33 11-bit signed fixed-point value. The lower 8 bits of the value are placed after the decimal point. The value is complement representation for 2. Bit 24-16 b3 The value is a 9-bit signed integer. The value is complement representation for 2. MB86276 'LIME' GDC Specifications Rev1.1a 227 FUJITSU SEMICONDUCTOR CONFIDENTIAL L0PAL0-255 (L0 layer Palette 0-255) Register DisplayBaseAddress + 400H -- DisplayBaseAddress + 7FCH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A R G B R/W RW R0 RW R0 RW R0 RW R0 Initial value Don't 0000000 Don't care 00 Don't care 00 Don't care 00 care These are color palette registers for L0 layer and cursors. In the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. This register corresponds to the CPALn register for previous products. Bit 7 to 2 B (Blue) Sets blue color component Bit 15 to 10 G (Green) Sets green color component Bit 23 to 18 R (Red) Sets red color component Bit 31 A (Alpha) Specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 Blending not performed even when blending mode enabled Overlay is performed via transparent color. 1 Blending performed MB86276 'LIME' GDC Specifications Rev1.1a 228 FUJITSU SEMICONDUCTOR CONFIDENTIAL L1PAL0-255 (L1 layer Palette 0-255) Register DisplayBaseAddress + 800H -- DisplayBaseAddress + BFCH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A R G B R/W RW R0 RW R0 RW R0 RW R0 Initial value Don't 0000000 Don't care 00 Don't care 00 Don't care 00 care These are color palette registers for L1 layer and cursors. In the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. This register corresponds to the MBPALn register for previous products. Bit 7 to 2 B (Blue) Sets blue color component Bit 15 to 10 G (Green) Sets green color component Bit 23 to 18 R (Red) Sets red color component Bit 31 A (Alpha) Specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 Blending not performed even when blending mode enabled Overlay is performed via transparent color. 1 Blending performed MB86276 'LIME' GDC Specifications Rev1.1a 229 FUJITSU SEMICONDUCTOR CONFIDENTIAL L2PAL0-255 (L2 layer Palette 0-255) Register DisplayBaseAddress + 1000H -- DisplayBaseAddress + 13FCH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A R G B R/W RW R0 RW R0 RW R0 RW R0 Initial value Don't 0000000 Don't care 00 Don't care 00 Don't care 00 care These are color palette registers for L2 layer and cursors. In the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. Bit 7 to 2 B (Blue) Sets blue color component Bit 15 to 10 G (Green) Sets green color component Bit 23 to 18 R (Red) Sets red color component Bit 31 A (Alpha) Specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 Blending not performed even when blending mode enabled Overlay is performed via transparent color. 1 Blending performed MB86276 'LIME' GDC Specifications Rev1.1a 230 FUJITSU SEMICONDUCTOR CONFIDENTIAL L3PAL0-255 (L3 layer Palette 0-255) Register DisplayBaseAddress + 1400H -- DisplayBaseAddress + 17FCH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A R G B R/W RW R0 RW R0 RW R0 RW R0 Initial value Don't 0000000 Don't care 00 Don't care 00 Don't care 00 care These are color palette registers for L3 layer and cursors. In the indirect color mode, a color code in the display frame indicates the palette register number, and the color information set in that register is applied as the display color of that pixel. Bit 7 to 2 B (Blue) Sets blue color component Bit 15 to 10 G (Green) Sets green color component Bit 23 to 18 R (Red) Sets red color component Bit 31 A (Alpha) Specifies whether or not to perform blending with lower layers when the blending mode is enabled. 0 Blending not performed even when blending mode enabled Overlay is performed via transparent color. 1 Blending performed MB86276 'LIME' GDC Specifications Rev1.1a 231 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.4 Video capture registers VCM (Video Capture Mode) Bit number Bit field name R/W Initial value CaptureBaseAddress + 00h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Re VIC Reserv VIE VIS ser E e ve R/ R/ R/ RX W W W 0 0 X 0 CM Reserve RX R/W RX X 00 X VI R/ W 0 9 8 7 6 5 4 3 Reserve 2 1 0 NRGB Register address VS Rs v RX X R/ R/ RX W W 0 0 X This register sets the video capture mode. This register is not initialized by software reset. Bit1 VS (Video Select) NTSC or PAL is selected for the code error detection (only RBT656 is input) 0 NTSC 1 PAL Bit2 NRGB (Native RGB input on) Native RGB mode is set up. 0 RGB video data is accepted via an internal RGB preprocessor which converts RGB to YUV422 1 Native RGB Bit20 VI (Vertical Interpolation) Sets whether to perform vertical interpolation 0 Performs vertical interpolation. The graphics are enlarged vertically by two times 1 Does not perform vertical interpolation Bit25-24 CM (Capture Mode) Sets video capture mode. To capture vides, set these bits to "11". 00 Initial value 01 Reserved 10 Reserved 11 Capture Bit28 VICE (Video Input Clock Enable) Capture clock enable 0 Enable 1 Disable Bit30 VIS (Video Input Select) 0 RBT656/601 1 RGB Bit31 VIE (Video Input Enable) Enables video capture function 0 Does not capture video 1 Captures video - Procedure of video capture clock Stop 1) 0 is written in bit31 (VIE) of the VCM register, and the video capture function is invalidated. 2) 1 is written in bit28 (VICE) of the VCM register, and Stop does video capture clock. - Procedure of video capture clock beginning 1) 0 is written in bit28 (VICE) of the VCM register, and video capture clock is made effective. 2) 1 is written in bit31 (VIE) of the VCM register, and the video capture function is made effective. MB86276 'LIME' GDC Specifications Rev1.1a 232 FUJITSU SEMICONDUCTOR CONFIDENTIAL CSC (Capture SCale) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 04h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 VSCI VSCF HSCI R/W R/W R/W 00001 00000000000 00001 9 8 7 6 5 4 3 HSCF R/W 00000000000 This register sets the video capture upscaling/downscaling ratio. Bit10-0 HSCF (Vertical SCale Fraction) The decimal part of a horizontal upscaling/downscaling ratio is set. Bit15-11 HSCI (Horizontal Scale Integer) The integer part of a horizontal upscaling/downscaling ratio is set. Bit26-16 VSCF (Vertical SCale Fraction) The decimal part of a vertical upscaling/downscaling ratio is set. Bit31-27 VSCI (Vertical SCale Integer) The integer part of a vertical upscaling/downscaling ratio is set. Note: It is not possible to smoothly transition from downscaling mode to upscaling mode. Picture artefacts will occur at transition time. The reason for this hardware limitation is that the downscaling and upscaling modules share the same interpolation unit. MB86276 'LIME' GDC Specifications Rev1.1a 233 2 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL CBM (video Capture Buffer Mode) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 10h 31 27 ... 24 23 22 ... 17 16 15 14 13 12 11 10 9 8 res C2 Reserve CBW BED CSW resv SSS v 4 R/ R/W R/W R/W R/W RX R/W RX R/W R/W RX R/W W 0 X X 0 X X X 0 0 0 X 000 OO 30 29 28 SCPAU BUF RGB 7 6 5 4 3 2 1 0 CBST SSM HRV reserve R/W R/W RX R/W 000 0 X 0 Bit0 CBST (Capture Burst) The burst-length at the capture Write is specified. Because long burst-length is good the access efficiency, 1 is recommended to be set. 0 Normal burst write (4word) 1 Long burst write (8word) Bit4 HRV (H-reverse) The horizontal reversing mode specification 0 Normal operation mode 1 Horizontal reversing mode Bit7-5 SSM (Single Shot Mode) Single shot mode 000 Normal operation mode 001 Single shot/odd field mode 010 Single shot/even field mode 011 Single shot/both field mode (with field distinction) 111 Single shot/both field mode2 (without field distinction) Bit10-8 SSS (Single Shot Status) The state of single shot operation is shown. 000 Initial state 001 Odd field mode / under capture 010 Even field mode / under capture 100 Both field mode / under first field capture 101 Both field mode / under second field capture Bit12 CSW (Color Swap) The byte position of a color ingredient is replaced. 0 Without exchange 1 With exchange Bit13 BED (Big EnDian) Endian is reversed 0 Little endian (enable display) 1 Big endian (disable display) Bit14 C24 ( Color 24bit/pixel ) It specifies wherther 24bit/pixel or 16bit/pixel is used in RGB capture. It is effective in native RGB capture (NRGB=1) or converted RGB capture(CRGB=1). 0 16bit/pixel 1 24bit/pixel Bit23-16 CBW (Capture Buffer memory Width) Sets memory width (stride) of capture buffer in 64 bytes Bit28 PAU (PAUse) It is shown that capture operation is Stop temporarily. 0 can be written and it can cancel. 0 Under operation 1 Stop temporarily Bit29 CRGB ( Capture RGB write) It specifies whether YCbCr to RGB conversion is applied or not before writing into the capture buffer. There are two formats of RGB or RGB=5:5:5 (16 bits/pixel) and RGB = 8:8:8 (24 bit/pixel) format, depending to C24-bit value described above. 0 YCbCr (without conversion) 1 RGB Bit30 SBUF (Single Buffer) It specifies managing a capture buffer by the single buffer system. 0 Normal mode (ring buffer) 1 Single buffer mode Bit31 OO (Odd Only mode) Specifies whether to capture odd fields only MB86276 'LIME' GDC Specifications Rev1.1a 234 FUJITSU SEMICONDUCTOR CONFIDENTIAL 0 1 Normal mode Odd only mode Note: This register is not initialized by software reset. CBOA (video Capture Buffer Origin Address) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 14h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved CBOA RX R/W Don't care Don't care 9 8 7 6 5 4 3 2 1 0 1 0 R0 0 This register specifies the starting (origin) address of the video capture buffer. CBLA (video Capture Buffer Limit Address) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 18h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved CBLA RX R/W Don't care Don't care 9 8 7 6 5 4 3 2 R0 0 This register specifies the end (limit) address of the video capture buffer. CBLA must be larger than CBOA. CIHSTR (Capture Image Horizontal STaRt) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 1Ch 15 14 13 Reserved RX Don't care 12 11 10 9 8 7 6 5 CIHSTR R/W Don't care 4 3 2 1 0 This register sets the range of the images to be written (captured) to the video capture buffer. Specify the X coordinates located in the top left of the image range as the count of pixels from the top left of the image. For downscaling, apply this setting to the post-reduction image coordinates. CIVSTR (Capture Image Vertical STaRt) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 1Eh 15 14 13 Reserved RX Don't care 12 11 10 9 8 7 6 5 CIVSTR R/W Don't care 4 3 2 1 This register sets the range of the images to be written (captured) to the video capture buffer. Specify the Y coordinates located in the top left of the image range as the count of pixels from the top left of the image. For downscaling, apply this setting to the post-reduction image coordinates. MB86276 'LIME' GDC Specifications Rev1.1a 235 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL CIHEND (Capture Image Horizontal END) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 20h 15 14 13 Reserved RX X 12 11 10 9 8 7 6 5 CIHEND R/W X 4 3 2 1 0 This register sets the range of the images to be written (captured) to the video capture buffer. Specify the X coordinates located in the bottom right of the image range as the count of pixels from the top left of the image. For downscaling, apply this setting to the post-reduction image coordinates. If the pixel at the right end of the image is not aligned on 64 bits/word boundary, extra data is written before 64 bits/word boundary. If the width of the input image is less than the range set by this command, data is written only at the size of input image. CIVEND (Capture Image Vertical END) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 22h 15 14 13 Reserved RX X 12 11 10 9 8 7 6 5 CIVEND R/W X 4 3 2 1 0 This register sets the range of the images to be written (captured) to the video capture buffer. Specify the Y coordinates located in the bottom right of the image range as the count of pixels from the top left of the original image to be input. For downscaling, apply this setting to the post-reduction image coordinates. If the count of rasters of the input image is less than the range set by this command, data is written only at the size of the input image. CVCNT (Capture Vertical Count) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 300h 15 14 13 Reserved R0 0 12 11 10 9 8 7 6 5 CVCNT R Don't care 4 3 2 Y coordinates of the raster which is carrying out the capture are shown. The register is read-only. MB86276 'LIME' GDC Specifications Rev1.1a 236 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL CHP (Capture Horizontal Pixel) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 28h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved RX X 9 8 7 6 5 4 3 CHP R/W 0x168 (360) 2 1 This register sets the count of horizontal pixels of the image output after scaling. Specify the count of horizontal pixels in 2 pixels. Maximum is 840 pixels (setting value is 0x1A4) CVP (Capture Vertical Pixel) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 2cH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CVPP Reserved CVPN RX RW RX RW X 271H (625D) X 20DH (525D) This register sets the count of vertical pixels of the image output after scaling. The fields to be used depend on the video format to be used. Bit 25 to 16 CVPP (Capture Vertical Pixel for PAL) Set count of vertical pixels of output image in PAL format used Bit 9 to 0 CVPN (Capture Vertical Pixel for NTSC) Set count of vertical pixels of output image in NTSC format used MB86276 'LIME' GDC Specifications Rev1.1a 237 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL CLPF (Capture Low Pass Filter) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 40h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved CVLPF Reserved CHLPF RX R/W RX R/W 0 0 0 0 9 8 7 6 Reserved RX X 5 4 3 2 This register sets the Low Pass Filter Coefficient. The vertical low pass filter consists of FIR filters of three taps. The horizontal low pass filter consists of FIR filters of five taps. It specifies independently in 2-bit coefficient code with a luminance signal (Y) and a chrominance signal (Cb and Cr) . A low pass filter is OFF (through) in a setup of each coefficient code "00". Bit 17 to 16 Bit 19 to 18 Bit 25 to 24 Bit 27 to 26 CHLPF_C (Capture Horizontal LPF coefficient C) CHLPF_C K0 K1 K2 K3 K4 00 0 0 1 0 0 01 0 1/4 2/4 1/4 0 10 0 3/16 10/16 3/16 0 11 3/32 8/32 10/32 10/32 3/32 CHLPF_Y (Capture Horizontal LPF coefficient Y) CHLPF_Y K0 K1 K2 K3 K4 00 0 0 1 0 0 01 0 1/4 2/4 1/4 0 10 0 3/16 10/16 3/16 0 11 3/32 8/32 10/32 10/32 3/32 CVLPF_C (Capture Vertical LPF coefficient C) CVLPF_C K0 K1 K2 00 0 1 0 01 1/4 2/4 1/4 10 3/16 10/16 3/16 11 Reserved CVLPF_Y (Capture Vertical LPF coefficient Y) CVLPF_Y K0 K1 K2 00 0 1 0 01 1/4 2/4 1/4 10 3/16 10/16 3/16 11 Reserved Note: - In the case of Native RGB mode (NRGB=1), only a setup of CVLPF_Y code becomes effective. MB86276 'LIME' GDC Specifications Rev1.1a 238 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL CMSS (Capture Magnify Source Size) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 48h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved CMSHP Reserved RX R/W RX X X X 9 8 7 6 5 4 CMSVL R/W X 3 2 1 Bit11-0 CMSVL (Capture Magnify Source Vertical Line) This register sets the number of vertical lines of the image input before Magnify scaling. Bit27-16 CMSHP (Capture Magnify Source Horizontal Pixel) This register sets the number of horizontal pixels of the image input before Magnify scaling. Specify the number of horizontal pixels in 2-pixel units. 0 CMDS (Capture Magnify Display Size) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 4Ch 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved CMDHP Reserved RX R/W RX X X X 9 8 7 6 5 4 CMDVL R/W X 3 2 1 Bit11-0 CMDVL (Capture Magnify Display Vertical Line) This register sets the number of vertical lines of the image output after Magnify scaling. Bit27-16 CMDHP (Capture Magnify Display Horizontal Pixel) This register sets the number of horizontal pixels of the image output after Magnify scaling. Specify the number of horizontal pixels in 2-pixel units. MB86276 'LIME' GDC Specifications Rev1.1a 239 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL RGBHC (RGB input Hsync Cycle) Register address Bit number Bit field name R/W Initial value Bit13-0 CaptureBaseAddress + 80h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved RX X 9 8 7 6 5 RGBHC R/W X 4 3 2 1 0 RGBHC This register sets number of HSYNC cycles of the RGB input. . It is used when it is made a setup which samples VSYNC. The setting value +1 is a level cycle. RGBHEN (RGB input Horizontal Enable area) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 84h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved RGBHST Reserved RX R/W RX X X X 9 8 7 6 5 RGBHEN R/W X 4 3 2 1 0 1 0 It is a parameter for determining effective pixel data. Bit12-0 RGBHEN(RGB input Horizontal Enable area Size) Effective pixel data size is set up per pixel. Specify the number of horizontal pixels in 2-pixel units Bit25-16 RGBHST(RGB input Horizontal Enable area Start position) The start position of effective pixel data is set up. The setting value -4 is a start position. Note: - The maximum horizontal enable area size (RGBHEN) which can be captured is 840 pixels. This restriction is due to the line buffer size in the video capture module. RGBVEN (RGB input Vertical Enable area) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 88h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserv Reserved RGBVST Reserved ed RX R/W R/W RX X X X X 9 8 7 This parameter determines the effective pixel data. Bit12-0 RGBVEN(RGB input Vertical Enable area Size) Set effective line size Bit25-16 RGBVST(RGB input Vertical Enable area Start position) The start position of effective line is set up. The setting value -1 is a start position. MB86276 'LIME' GDC Specifications Rev1.1a 240 6 5 RGBVEN R/W X 4 3 2 FUJITSU SEMICONDUCTOR CONFIDENTIAL RGBS (RGB input Sync) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 90h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved RM Reserved R/ RX RX W X 1 X 9 8 7 6 5 4 Edge detection of a synchronized signal is set up. It is used at the time of RGB input format. Bit0 VP (VSYNCI Polarity) 0 Negative edge of VINVSYNC is set to VSYNC. 1 Positive edge of VINVSYNC is set to VSYNC. Bit1 HP (HSYNCI Polarity) 0 Negative edge of VINHSYNC is set to HSYNC. 1 Positive edge of VINHSYNC is set to HSYNC. Bit16 RM (RGB Input Mode select) Sets Direct RGB input mode 0 reserved 1 RGB666 Direct input Mode MB86276 'LIME' GDC Specifications Rev1.1a 241 3 2 1 HP R/ W 0 0 VP R/ W 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL Conversion Operation RGB data is converted to YUV by the following matrix expression : Y = a11*R + a12*G + a13*B + b1 Cb= a21*R + a22*G + a23*B + b2 Cr= a31*R + a32*G + a33*B + b3 aij 10bit signed real ( lower 8bit is fraction ) bi 8bit unsigned integer Each coefficients can be defined by following registers. Cb and Cr components are reduced half after this operation to form the 4:2:2 format. RGBCMY (RGB Color convert Matrix Y coefficient) Register CaptureBaseAddress + C0H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name a11 RW 0001000010 b R/W Initial value Re R 0 a12 RW 0010000000 b Re R 0 a13 RW 0000011001 b This register sets the RGB color convert matrix coefficient. Bit 31 to 22 a11 10bit signed real (the lower 8bit are the fraction part) Bit 20 to 11 a12 10bit signed real (the lower 8bit are the fraction part) Bit 9 to 0 a13 10bit signed real (the lower 8bit are the fraction part) RGBCMCb (RGB Color convert Matrix Cb coefficient) Register CaptureBaseAddress + C4H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name a21 RW 1111011010 b R/W Initial value Re R 0 a22 RW 1110110110 b This register sets the RGB color convert matrix coefficient. Bit 31 to 22 A21 10bit signed real (the lower 8bit are the fraction part) Bit 20 to 11 A22 10bit signed real (the lower 8bit are the fraction part) Bit 9 to 0 A23 10bit signed real (the lower 8bit are the fraction part) RGBCMCr (RGB Color convert Matrix Cr coefficient) Register address CaptureBaseAddress + C8H MB86276 'LIME' GDC Specifications Rev1.1a 242 Re R 0 a23 RW 0001110000 b FUJITSU SEMICONDUCTOR CONFIDENTIAL Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A31 RW 0001110000 b R/W Initial value Re R 0 A32 RW 1110100010 b Re R 0 A33 RW 1111101110 b This register sets the RGB color convert matrix coefficient. Bit 31 to 22 A31 10bit signed real (the lower 8bit are the fraction part) Bit 20 to 11 A32 10bit signed real (the lower 8bit are the fraction part) Bit 9 to 0 A33 10bit signed real (the lower 8bit are the fraction part) RGBCMb (RGB Color convert Matrix b coefficient) Register CaptureBaseAddress + CCH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name R R/W R Initial value 0 B1 RW 000010000 b Res R 0 b2 RW 010000000 b Res R 0 b3 RW 010000000 b This register sets the RGB color convert matrix coefficient. Bit 30 to 22 B1 9bit unsigned integer Bit 19 to 11 B2 9bit unsigned integer Bit 8 to 0 B3 9bit unsigned integer CINT (Capture Interrupt) Register address Bit No. CaputureBaseAddress + 178H 31 30 29 28 27 26 .. .. .. 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit field name Reserved VS R/W R RW0 Initial value 0 0 0 This register is the video synchronization signal interrupt status register. This register is cleared by writing "0" to it. Bit 1 VS (VSYNC) 1: VSYNC 0: No VSYNC CINTMASK (Capture Interrupt Mask) Register address Bit No. CaputureBaseAddress + 17CH 31 30 29 28 27 26 MB86276 'LIME' GDC Specifications Rev1.1a 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 243 1 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL Bit field name Reserved VS R/W R RW Initial value 0 0 This register masks the video synchronization signal interrupt Bit 1 VS (VSYNC) 1: Does not mask interrupt. MB86276 'LIME' GDC Specifications Rev1.1a 0: Masks interrupt. 244 FUJITSU SEMICONDUCTOR CONFIDENTIAL 656 Code error detect < RBT656 format input only> CDCN (Capture Data Count for NTSC) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 4000h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved BDCN Reserved RX RW RX X 0x10f(271) X 9 8 7 6 5 4 VDCN RW 0x5A3(1443) 3 2 1 This register sets the count of data of the input video stream in NTSC format. Bit12-0 VDCN (Valid Data Count for NTSC) Sets count of data processed during valid period in NTSC format. The setting value +1 is a data number Bit28-16 BDCN (Blanking Data Count for NTSC) Sets count of data processed during blanking period in NTSC format. The setting value +1 is a data number 4T VI[7:0] EAV 4T Blanking data SAV 80,10,80,10,80,. H-BLANK 276T 525 288T 625 4T Multiplexed video data Cb,Y,Cr,Y,Cb,Y,Cr,Y,... .. ACTIVE-VIDEO 1440T [525] 1440T [625] 272T(BDCN:271T) 284T(BDCP:283T) 1444T(VDCN:1443T) 1444T(VDCP:1443T) The range of VDCN and BDCN is shown in the following figure. SAV: start of active video timing reference code EAV: end of active video timing reference code T: clock period 37 ns nom. MB86276 'LIME' GDC Specifications Rev1.1a 245 EAV 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL CDCP (Capture Data Count for PAL) Register address Bit number Bit field name R/W Initial value CaptureBaseAddress + 4004h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserved BDCP Reserved RX RW RX X 0x11B(283) X 9 8 7 6 5 4 VDCP RW 0x5A3(1443) 3 2 1 This register sets the count of data of the input video stream in PAL format. Bit12-0 VDCP (Valid Data Count for PAL) Sets count of data processed during valid period in PAL format. The setting value +1 is a data number Bit28-16 BDCP (Blanking Data Count for PAL) Sets count of data processed during blanking period in PAL format. The setting value +1 is a data number MB86276 'LIME' GDC Specifications Rev1.1a 246 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL VCS (Video Capture Status) Register address CaptureBaseAddress + 08h Bit number Bit field name R/W Initial value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Reserve RX X 9 8 7 6 5 4 3 2 1 CE RW0 00000 This register indicates the ITU-RBT656 SAV and EAV status. To detect error codes, set NTSC/PAL in the VS bit of VCM. If NTSC is set, reference the number of data in the capture data count register (CDCN). If PAL is set, reference the number of data in the capture data counter register (CDCP). If the reference data does not match the stream data , or undefined Fourth word of SAV/EAV codes are detected, bits 4 to 0 of the video capture status register (VCS) will be values as follows. Bits 6-0 CE0 (Capture Error 0) Bit0 Bit1 Bit2 Bit3 Bit4 1: 1: 1: 1: 1: RBT.656 RBT.656 RBT.656 RBT.656 RBT.656 undefined error (Code Bit7) undefined error (Code Bit7-4) undefined error (Code Bit7-0) long term H code error (SAV) long term H code error (EAV) MB86276 'LIME' GDC Specifications Rev1.1a 247 0 : true 0 : true 0 : true 0 : true 0 : true 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.5 Drawing registers 12.5.1 Drawing control registers CTR (Control Register) Register DrawBaseAddress + 400H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FO CE FCNT NF FF FE SS DS PS R/W RW RW R R R R R R R Initial value 0 0 011101 0 0 1 00 00 00 This register indicates drawing flags and status information. Bits 24 to 22 are not cleared until 0 is set. Bit 1 and 0 PS (Pixel engine Status) Indicate status of pixel engine unit Bit 5 and 4 00 Idle 01 Busy 10 Reserved 11 Reserved DS (DDA Status) Indicate status of DDA Bit 9 and 8 00 Idle 01 Busy 10 Busy 11 Reserved SS (Setup Status) Indicate status of Setup unit Bit 12 00 Idle 01 Busy 10 Reserved 11 Reserved FE (FIFO Empty) Indicates whether data contained or not in display list FIFO Bit 13 0 Valid data 1 No valid data FF (FIFO Full) Indicates whether display list FIFO is full or not Bit 14 0 Not full 1 Full NF (FIFO Near Full) Indicates how empty the display list FIFO is 0 Empty entries equal to or more than half MB86276 'LIME' GDC Specifications Rev1.1a 248 FUJITSU SEMICONDUCTOR CONFIDENTIAL 1 Bit 20 to 15 Empty entries less than half FCNT (FIFO Counter) Indicates count of empty entries of display list FIFO (0 to 100000b) 32 entries deep Bit 22-23 CE (Display List Command Error) Indicates command error occurrence (Not all error can detect. Need software reset or hardware reset for recovery) Bit 24 00 Normal 11 Command error detected FO (FIFO Overflow) Indicates FIFO overflow occurrence 0 Normal 1 FIFO overflow detected MB86276 'LIME' GDC Specifications Rev1.1a 249 FUJITSU SEMICONDUCTOR CONFIDENTIAL IFSR (Input FIFO Status Register) Register DrawBaseAddress + 404H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name NF FF FE R/W R R R Initial value 0 0 1 This is a mirror register for bits 14 to 12 of the CTR register. IFCNT (Input FIFO Counter) Register DrawBaseAddress + 408H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FCNT R/W R Initial value 011101 This is a mirror register for bits 20 to 15 of the CTR register. SST (Setup engine Status) Register DrawBaseAddress + 40CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name SS R/W R Initial value 00 This is a mirror register for bits 9 to 8 of the CTR register. DST (DDA Status) Register DrawBaseAddress + 410H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name DS R/W RW Initial value 00 This is a mirror register for bits 5 to 4 of the CTR register. PST (Pixel engine Status) Register DrawBaseAddress + 414H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name PS R/W R Initial value 00 This is a mirror register for bits 1 to 0 of the CTR register. EST (Error Status) Register DrawBaseAddress + 418H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FO CE R/W RW RW Initial value 0 0 This is a mirror register for bits 24 to 22 of the CTR register. MB86276 'LIME' GDC Specifications Rev1.1a 250 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.5.2 Drawing mode registers When write to the registers, use the SetRegister command. The registers cannot be accessed from the CPU. MDR0 (Mode Register for miscellaneous) Register DrawBaseAddress + 420H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name ZP CF CY CX BSV BSH R/W W0 RW W0 RW W0 RW RW W0 RW RW Initial value 0 00 0 0 00 00 Bit 1 to 0 BSH (Bitmap Scale Horizontal) Sets horizontal zoom ratio of bitmap draw Bit 3 to 2 00 x1 01 x2 10 x1/2 01 Reserved BSV (Bitmap Scale Vertical) Sets vertical zoom ratio of bitmap draw Bit 8 00 x1 01 x2 10 x1/2 01 Reserved CX (Clip X enable) Sets X coordinates clipping mode Bit 9 0 Disabled 1 Enabled CY (Clip Y enable) Sets Y coordinates clipping mode Bit 16 and 15 0 Disabled 1 Enabled CF (Color Format) Sets drawing color format Bit 20 00 Indirect color mode (8 bits/pixel) 01 Direct color mode (16 bits/pixel) ZP (Z Precision) Sets the precision of the Z value used for erasing hidden planes 16 bits/pixel 8 bits/pixel MB86276 'LIME' GDC Specifications Rev1.1a 251 FUJITSU SEMICONDUCTOR CONFIDENTIAL MDR1 (Mode Register for LINE) Register DrawBaseAddress + 424H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name LW BP BL LOG BM ZW ZCL ZC R/W RW RW RW RW RW RW RW RW Initial value 00000 0 0 0011 0 0 0000 0 This register sets the mode of line and pixel drawing. Please set ZC bit ( bit 2 ) to 0 when draw BltCopyAltAlphaBlendP command. Bit 2 ZC (Z Compare mode) Sets Z comparison mode Bit 5 to 3 0 Disabled 1 Enabled ZCL (Z Compare Logic) Selects type of Z comparison Bit 6 000 NEVER 001 ALWAYS 010 LESS 011 LEQUAL 100 EQUAL 101 GEQUAL 110 GREATER 111 NOTEQUAL ZW (Z Write mode) Sets Z write mode Bit 8 to 7 0 Writes Z values. 1 Not write Z values. BM (Blend Mode) Sets blend mode Bit 12 to 9 00 Normal (source copy) 01 Alpha blending 10 Drawing with logic operation 11 Reserved LOG (Logical operation) Sets type of logic operation 0000 CLEAR 0001 AND 0010 AND REVERSE 0011 COPY 0100 AND INVERTED MB86276 'LIME' GDC Specifications Rev1.1a 252 FUJITSU SEMICONDUCTOR CONFIDENTIAL Bit 19 0101 NOP 0110 XOR 0111 OR 1000 NOR 1001 EQUIV 1010 INVERT 1011 OR REVERSE 1100 COPY INVERTED 1101 OR INVERTED 1110 NAND 1111 SET BL (Broken Line) Selects line type Bit 20 0 Solid line 1 Broken line BP (Broken line Period) Selects broken line cycle Bit 28 to 24 0: 32 bits 1: 24 bits LW (Line Width) Sets line width for drawing line 00000 1 pixel 00001 2 pixels : : 11111 32 pixels MB86276 'LIME' GDC Specifications Rev1.1a 253 FUJITSU SEMICONDUCTOR CONFIDENTIAL MDR2 (Mode Register for Polygon) Register DrawBaseAddress + 428H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name TT LOG BM ZW ZCL ZC SM R/W W0 RW RW RW RW RW RW RW Initial value 00 0011 0 0 0000 0 0 This register sets the polygon drawing mode. Bit 0 SM (Shading Mode) Sets shading mode Bit 2 0 Flat shading 1 Gouraud shading ZC (Z Compare mode) Sets Z comparison mode Bit 5 to 3 0 Disabled 1 Enabled ZCL (Z Compare Logic) Selects type of Z comparison Bit 6 000 NEVER 001 ALWAYS 010 LESS 011 LEQUAL 100 EQUAL 101 GEQUAL 110 GREATER 111 NOTEQUAL ZW (Z Write mask) Sets Z write mode Bit 8 to 7 0 Writes Z values 1 Not write Z values BM (Blend Mode) Sets blend mode Bit 12 to 9 00 Normal (source copy) 01 Alpha blending 10 Drawing with logic operation 11 Reserved LOG (Logical operation) Sets type of logic operation MB86276 'LIME' GDC Specifications Rev1.1a 254 FUJITSU SEMICONDUCTOR CONFIDENTIAL Bit 29 to 28 0000 CLEAR 0001 AND 0010 AND REVERSE 0011 COPY 0100 AND INVERTED 0101 NOP 0110 XOR 0111 OR 1000 NOR 1001 EQUIV 1010 INVERT 1011 OR REVERSE 1100 COPY INVERTED 1101 OR INVERTED 1110 NAND 1111 SET TT (Texture-Tile Select) Selects texture or tile pattern 00 Neither used 01 Enabled tiling 10 Enabled texture 11 Reserved MB86276 'LIME' GDC Specifications Rev1.1a 255 FUJITSU SEMICONDUCTOR CONFIDENTIAL MDR3 (Mode Register for Texture) Register DrawBaseAddress + 42CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 Bit field name TAB TBL TWS R/W RW RW RW Initial value 00 00 00 9 8 7 6 5 4 3 2 1 0 TWT TF TC RW RW RW 00 0 0 This register sets the texture mapping mode. Bit 3 TC (Texture coordinates Correct) Sets texture coordinates correction mode Bit 5 0 Disabled 1 Reserved TF (Texture Filtering) Sets type of texture interpolation (filtering) Bit 9 and 8 0 Point sampling 1 Bi-linear filtering TWT (Texture Wrap T) Sets type of texture coordinates T direction wrapping Bit 11 and 10 00 Clamp 01 Repeat 10 Border 11 Reserved TWS (Texture Wrap S) Sets type of texture coordinates S direction wrapping Bit 17 and 16 00 Clamp 01 Repeat 10 Border 11 Reserved TBL (Texture Blend mode) Sets texture blending mode Bit 21 and 20 00 De-curl 01 Modulate 10 Stencil 11 Reserved TAB (Texture Alpha Blend mode) Sets texture blending mode The stencil mode and the stencil alpha mode are enabled only when the MDR2 register blend mode (BM) is set to the alpha blending mode. If it is not set to the alpha blending mode, the stencil mode and stencil alpha mode perform the same function as the normal mode. MB86276 'LIME' GDC Specifications Rev1.1a 256 FUJITSU SEMICONDUCTOR CONFIDENTIAL 00 Normal 01 Stencil 10 Stencil alpha 11 Reserved MB86276 'LIME' GDC Specifications Rev1.1a 257 FUJITSU SEMICONDUCTOR CONFIDENTIAL MDR4 (Mode Register for BLT) Register DrawBaseAddress + 430H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name LOG BM TE R/W RW RW RW Initial value 0011 00 0 This register controls the BLT mode. Bit 1 TE (Transparent Enable) Sets transparent mode Bit 8 to 7 0: Not perform transparent processing 1: Not draw pixels that corresponds to set transparent color in BLT (transparancy copy) Note: Set the blend mode (BM) to normal. BM (Blend Mode) Sets blend mode Bit 12 to 9 00 Normal (source copy) 01 Reserved 10 Drawing with logic operation 11 Reserved LOG (Logical operation) Sets logic operation 0000 CLEAR 0001 AND 0010 AND REVERSE 0011 COPY 0100 AND INVERTED 0101 NOP 0110 XOR 0111 OR 1000 NOR 1001 EQUIV 1010 INVERT 1011 OR REVERSE 1100 COPY INVERTED 1101 OR INVERTED 1110 NAND 1111 SET MB86276 'LIME' GDC Specifications Rev1.1a 258 FUJITSU SEMICONDUCTOR CONFIDENTIAL FBR (Frame buffer Base) Register DrawBaseAddress + 440H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FBASE R/W RW R0 Initial value Don't care 0 This register stores the base address of the drawing frame. XRES (X Resolution) Register DrawBaseAddress + 444H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name XRES R/W RW Initial value Don't care This register sets the drawing frame horizontal resolution. ZBR (Z buffer Base) Register DrawBaseAddress + 448H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name ZBASE R/W RW R0 Initial value Don't care 0 This register sets the Z buffer base address. TBR (Texture memory Base) Register DrawBaseAddress + 44CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name TBASE R/W RW R0 Initial value Don't care 0 This register sets the texture memory base address. PFBR (2D Polygon Flag-Buffer Base) Register address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name R/W Initial value RW Don't care DrawBaseAddress + 450H PFBASE This register sets the polygon flag buffer base address. MB86276 'LIME' GDC Specifications Rev1.1a 259 R0 0 FUJITSU SEMICONDUCTOR CONFIDENTIAL CXMIN (Clip X minimum) Register DrawBaseAddress + 454H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CLIPXMIN R/W RW Initial value Don't care This register sets the clip frame minimum X position. CXMAX (Clip X maximum) Register DrawBaseAddress + 458H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CLIPXMAX R/W RW Initial value Don't care This register sets the clip frame maximum X position. CYMIN (Clip Y minimum) Register DrawBaseAddress + 45CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CLIPYMIN R/W RW Initial value Don't care This register sets the clip frame minimum Y position. CYMAX (Clip Y maximum) Register DrawBaseAddress + 460H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name CLIPYMAX R/W RW Initial value Don't care This register sets the clip frame maximum Y position. MB86276 'LIME' GDC Specifications Rev1.1a 260 FUJITSU SEMICONDUCTOR CONFIDENTIAL TXS (Texture Size) Register DrawBaseAddress + 464H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name TXSN TXSM R/W RW RW Initial value 000010000000 000010000000 This register specifies the texture size (m, n). Bit 12 to 0 TXSM (Texture Size M) Sets horizontal texture size. Any power of 2 between 4 and 4096 can be used. Values that are not a power of 2 cannot be used. Bit 28 to 16 0_0000_0000_0100 M=4 0_0010_0000_0000 M=512 0_0000_0000_1000 M=8 0_0100_0000_0000 M=1024 0_0000_0001_0000 M=16 0_1000_0000_0000 M=2048 0_0000_0010_0000 M=32 1_0000_0000_0000 M=4096 0_0000_0100_0000 M=64 0_0000_1000_0000 M=128 0_0001_0000_0000 M=256 Other than the above Setting disabled TXSN (Texture Size N) Sets vertical texture size. Any power of 2 between 4 and 4096 can be used. Values that are not a power of 2 cannot be used. 0_0000_0000_0100 N=4 0_0010_0000_0000 N=512 0_0000_0000_1000 N=8 0_0100_0000_0000 N=1024 0_0000_0001_0000 N=16 0_1000_0000_0000 N=2048 0_0000_0010_0000 N=32 1_0000_0000_0000 N=4096 0_0000_0100_0000 N=64 0_0000_1000_0000 N=128 0_0001_0000_0000 N=256 Other than the above Setting disabled MB86276 'LIME' GDC Specifications Rev1.1a 261 FUJITSU SEMICONDUCTOR CONFIDENTIAL TIS (Tile Size) Register DrawBaseAddress + 468H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name TISN TISM R/W RW RW Initial value 1000000 1000000 This register specifies the tile size (m, n). Bit 6 to 0 TISM (Title Size M) Sets horizontal tile size. Any power of 2 between 4 and 64 can be used. Values that are not a power of 2 cannot be used. Bit 22 to 16 0.000100 M=4 0001000 M=8 0010000 M=16 0100000 M=32 1000000 M=64 Other than the above Setting disabled TISN (Title Size N) Sets vertical tile size. Any power of 2 between 4 and 64 can be used. Values that are not a power of 2 cannot be used. 0000100 N=4 0001000 N=8 0010000 N=16 0100000 N=32 1000000 N=64 Other than the above Setting disabled TOA (Texture Buffer Offset address) Register DrawBaseAddress + 46CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name XBO R/W RW Initial value Don't care This register sets the texture buffer offset address. Using this offset value, texture patterns can be referred to the texture buffer memory. Specify the word-aligned byte address (16 bits). (Bit 0 is always "0".) MB86276 'LIME' GDC Specifications Rev1.1a 262 FUJITSU SEMICONDUCTOR CONFIDENTIAL ABR (Alpha map Base) Register DrawBaseAddress + 474H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name ABASE R/W RW R0 Initial value Don't care 0 This register sets the base address of the alpha map. FC (Foreground Color) Register DrawBaseAddress + 480H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name FGC R/W RW Initial value 0 This register sets the drawing foreground color. This color is for the object color for flat shading and foreground color for bitmap drawing and broken line drawing. All bits set to "1" are drawn in the color set at this register. 8 bit color mode: Bit 7 to 0 FGC8 (Foreground 8 bit Color) Sets the indirect color for the foreground (color index code). Bit 31 to 8 These bits are not used. 16 bit color mode: Bit 15 to 0 FGC16 (Foreground 16 bit Color) This field sets the 16-bit direct color for the foreground. Note that the handling of bit 15 is different from that in ORCHID. Up to ORCHID, bit 15 is "0" for other than bit map and rectangular drawing, but starting with LIME GDC, the setting value is reflected in memory as is. This bit is also reflected in bit 15 of the 16-bit color at Gouraud shading. Bit 31 to 16 These bits are not used. MB86276 'LIME' GDC Specifications Rev1.1a 263 FUJITSU SEMICONDUCTOR CONFIDENTIAL BC (Background Color) Register DrawBaseAddress + 484H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BGC8/16 R/W RW Initial value 0 This register sets the drawing frame background color. This color is used for the background color of bitmap drawing and broken line drawing. At bitmap drawing, all bits set to "0" are drawn in the color set at this register. BT bit of this register allows the background color of be transparent (no drawing). 8 bit color mode: Bit 7 to 0 BGC8 (Background 8 bit Color) Sets the indirect color for the background (color index code) Bit 14 to 8 Not used Bit 15 BT (Background Transparency) Sets the transparent mode for the background color Bit 31 to 16 0 Background drawn using color set for BGC field 1 Background not drawn (transparent) Not used 16 bit color mode: Bit 14 to 0 BGC16 (Background 16 bit Color) Sets 16-bit direct color (RGB) for the background Bit 15 BT (Background Transparency) Sets the transparent mode for the background color Bit 31 to 16 0 Background drawn using color set for BGC field 1 Background not drawn (transparent) Not used MB86276 'LIME' GDC Specifications Rev1.1a 264 FUJITSU SEMICONDUCTOR CONFIDENTIAL ALF (Alpha Factor) Register DrawBaseAddress + 488H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name A R/W RW Initial value 0 This register sets the alpha blending coefficient. BLP (Broken Line Pattern) Register DrawBaseAddress + 48CH address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BLP R/W RW Initial value 0 This register sets the broken-line pattern. The bit 1 set in the broken-line pattern is drawn in the foreground color and bit 0 is drawn in the background color. The line pattern for 1 pixel line is laid out in the direction of MSB to LSB and when it reaches LSB, it goes back to MSB. The BLPO register manages the bit numbers of the broken-line pattern. 32 or 24 bits can be selected as the repetition of the broken-line pattern by the BP bit of the MDR1 register. When 24 bits are selected, bits 23 to 0 of the BLP register are used. TBC (Texture Border Color) Register DrawBaseAddress + 494H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BC8/16 R/W RW Initial value 0 This register sets the border color for texture mapping. 8 bit color mode: Bit 7 to 0 BC8 (Border Color) Sets the 8-bit direct color for the texture border color 16 bit color mode: Bit 15 to 0 BC16 (Border Color) Sets the 16-bit direct color for the texture border color Bit15 is used for controlling a stencil and stencil alpha BLPO (Broken Line Pattern Offset) Register DrawBaseAddress + 3E0H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name BCR R/W RW Initial value 11111 This register stores the bit number of the broken-line pattern set to BLP registers, for broken line drawing. This value is decremented at each pixel drawing. Broken line can be drawn starting from any starting position of the specified broken-line pattern by setting any value at this register. When no write is performed, the position of broken-line pattern is sustained. MB86276 'LIME' GDC Specifications Rev1.1a 265 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.5.3 Triangle drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. (XY coordinates register) Register Address Ys Xs dXdy XUs dXUdy XLs dXLdy USN LSN Address S 0 Int Frac 0000H 0004H 0008H 000cH 0010H 0014H 0018H 001bH 0020H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S S S S Int Frac S S S S Int Frac S S S S Int Frac S S S S Int Frac S S S S Int Frac S S S S Int Frac S S S S Int Frac 0 0 0 0 Int 0 0 0 0 0 Int 0 Offset value from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets (X, Y) coordinates for triangle drawing Ys Xs dXdy XUs dXUdy XLs dXLdy USN LSN Y coordinates start position of long edge X coordinates start position of long edge corresponding to Ys X DDA value of long edge direction X coordinates start position of upper edge X DDA value of upper edge direction X coordinates start position of lower edge X DDA value of lower edge direction Count of spans of upper triangle. If this value is "0", the upper triangle is not drawn. Count of spans of lower triangle. If this value is "0", the lower triangle is not drawn. MB86276 'LIME' GDC Specifications Rev1.1a 266 FUJITSU SEMICONDUCTOR CONFIDENTIAL (Color setting register) Register Address Rs dRdx dRdy Gs dGdx dGdy Bs dBdx dBdy As dAdx dAdy Address S 0 Int Frac 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005cH 0060H 0064H 0068H 006cH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Int Frac S S S S S S S S Int Frac S S S S S S S S Int Frac 0 0 0 0 0 0 0 0 Int Frac S S S S S S S S Int Frac S S S S S S S S Int Frac 0 0 0 0 0 0 0 0 Int Frac S S S S S S S S Int Frac S S S S S S S S Int Frac 0 0 0 0 0 0 0 0 Int Frac S S S S S S S S Int Frac S S S S S S S S Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets color parameters for triangle drawing. These parameters are enabled in the Gouraud shading mode. Rs dRdx dRdy Gs dGdx dGdy Bs dBdx dBdy As dAdx dAdy R value at (Xs, Ys, Zs) of long edge corresponding to Ys R DDA value of horizontal direction R DDA value of long edge G value at (Xs, Ys, Zs) of long edge corresponding to Ys G DDA value of horizontal direction G DDA value of long edge B value at (Xs, Ys, Zs) of long edge corresponding to Ys B DDA value of horizontal direction B DDA value of long edge Alpha value at (Xs, Ys, Zs) of long edge corresponding to Ys Alpha DDA value of horizontal direction Alpha DDA value of long edge (Z coordinates register) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Zs 0080h 0 Int Frac dZdx 0084h S Int Frac dZdy 008ch S Int Frac Register Address Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets Z coordinates for 3D triangle drawing Zs dZdx dZdy Z coordinate start position of long edge Z DDA value of horizontal direction Z DDA value of long edge (Texture coordinates-setting register) MB86276 'LIME' GDC Specifications Rev1.1a 267 FUJITSU SEMICONDUCTOR CONFIDENTIAL Register Address Ss dSdx dSdy Ts dTdx dTdy Qs dQdx dQdy Address S 0 Int Frac 00c0H 00c4H 00c8H 00ccH 00d0H 00d4H 00d8H 00dcH 00e0H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S S S Int Frac S S S Int Frac S S S Int Frac S S S Int Frac S S S Int Frac S S S Int Frac 0 0 0 0 0 0 0 Int Frac S S S S S S S Int Frac S S S S S S S Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets texture coordinates parameters for triangle drawing Ss dSdx dSdy Ts dTdx dTdy Qs dQdx dQdy S texture coordinates (Xs, Ys, Zs) of long edge corresponding to Ys S DDA value of horizontal direction S DDA value of long edge direction T texture coordinates (Xs, Ys, Zs) of long edge corresponding to Ys T DDA value of horizontal direction T DDA value of long edge direction Q (Perspective correction value) of texture at (Xs, Ys, Zs) of long edge corresponding to Ys Q DDA value of horizontal direction Q DDA value of long edge direction MB86276 'LIME' GDC Specifications Rev1.1a 268 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.5.4 Line drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or by using the SetRegister command. (Coordinates setting register) Register Address LPN LXs LXde LYs LYde LZs LZde Address S 0 Int Frac 0140H 0144H 0148H 014cH 0150H 0154H 0158H 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 Int 0 S S S S Int Frac S S S S S S S S S S S S S S S Int Frac S S S S Int Frac S S S S S S S S S S S S S S S Int Frac S Int Frac S Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets coordinates parameters for line drawing LPN Pixel count of principal axis direction LXs X coordinates start position of draw line (In principal axis X) Integer value of X coordinates rounded off (In principal axis Y) X coordinates in form of fixed point data LXde Inclination data for X coordinates (In principal axis X) Increment or decrement according to drawing direction (In principal axis Y) Fraction part of DX/DY LYs Y coordinates start position of draw line (In principal axis X) Y coordinates in form of fixed point data (In principal axis Y) Integer value of Y coordinates rounded off LYde Inclination data for Y coordinates (In principal axis X) Fraction part of DY/DX (In principal axis Y) Increment or decrement according to drawing direction LZs Z coordinates start position of line drawing line LZde Z Inclination MB86276 'LIME' GDC Specifications Rev1.1a 269 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.5.5 Pixel drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PXdc 0180H 0 0 0 0 Int 0 PYdc 0184H 0 0 0 0 Int 0 PZdc 0188H 0 0 0 0 Int 0 Register Address Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets coordinates parameter for drawing pixel. The foreground color is used. PXdc PYdc PZdc 12.5.6 Sets X coordinates position Sets Y coordinates position Sets Z coordinates position Rectangle drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. Register Address RXs Rys RsizeX RsizeY Address S 0 Int Frac 0200H 0204H 0208H 020cH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets coordinates parameters for rectangle drawing. The foreground color is used. RXs Rys RsizeX RsizeY Sets the X coordinates of top left vertex Sets the Y coordinates of top left vertex Sets horizontal size Sets vertical size MB86276 'LIME' GDC Specifications Rev1.1a 270 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.5.7 Blt registers Sets the parameters of each register as described below: Set the Tcolor register with the SetRegister command. Note that the Tcolor register cannot be set at access from the CPU and by drawing commands. Each register except the Tcolor register is set by executing a drawing command. Note that access from the CPU and the SetRegister command cannot be used. Register Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 0 0 0 Address 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 Color SADDR 0240H 0 0 0 0 0 0 0 SStride 0244H SRXs 0248H SRYs 024cH DADDR 0250H DStride 0254H DRXs 0258H DRYs 025cH BRsizeX 0260H BRsizeY 0264H TColor 0280H Address S 0 Int Frac Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets parameters for Blt operations SADDR Sets start address of source rectangle area in byte address SStride Sets stride of source SRXs Sets X coordinates start position of source rectangle area SRYs Sets Y coordinates start position of source rectangle area DADDR Sets start address of destination rectangle area in byte address DStride Sets stride of destination DRXs Sets X coordinates start position of destination rectangle area DRYs Sets Y coordinates start position of destination rectangle area BRsizeX Sets horizontal size of rectangle BRsizeY Sets vertical size of rectangle Tcolor Sets transparent color For indirect color, set a palette code in the lower 8 bits. MB86276 'LIME' GDC Specifications Rev1.1a 271 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.5.8 2D line with XY setup drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU. Register Address LX0dc LY0dc LX1dc LY1dc Address S 0 Int Frac 0540H 0544H 0548H 054cH 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets coordinates of line end points for 2D Line with XY setup drawing LX0dc Sets X coordinates of vertex V0 LY0dc Sets Y coordinates of vertex V0 LX1dc Sets X coordinates of vertex V1 LY1dc Sets Y coordinates of vertex V1 MB86276 'LIME' GDC Specifications Rev1.1a 272 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.5.9 2D triangle with XY setup drawing registers Each register is used by the drawing commands. The registers cannot be accessed from the CPU or using the SetRegister command. Register Address X0dc Y0dc X1dc Y1dc X2dc Y2dc Address S 0 Int Frac 0580h 0584h 0588h 058ch 0590h 0594h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 0 0 0 0 Int 0 Offset from DrawBaseAddress Sign bit or sign extension Not used or 0 extension Integer or integer part of fixed point data Fraction part of fixed point data Sets coordinates of three vertices for 2D Triangle with XY setup drawing X0dc Sets X coordinates of vertex V0 Y0dc Sets Y coordinates of vertex V0 X1dc Sets X coordinates of vertex V1 Y1dc Sets Y coordinates of vertex V1 X2dc Sets X coordinates of vertex V2 Y2dc Sets Y coordinates of vertex V2 MB86276 'LIME' GDC Specifications Rev1.1a 273 FUJITSU SEMICONDUCTOR CONFIDENTIAL 12.5.10 Display list FIFO registers DFIFO (Displaylist FIFO) Register DrawBaseAddress+ 4A0H address Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit field name DFIFO R/W W Initial value Don't care FIFO registers for Display List transfer. The Display List FIFO is 32 entries deep. MB86276 'LIME' GDC Specifications Rev1.1a 274 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13 TIMING DIAGRAM 13.1 Graphics Memory Interface The LIME GDC access timing and graphics memory access timing are explained here. 13.1.1 Timing of read access to same row address MCLKO MRAS TRCD MCAS MWE MA ROW COL COL COL COL DATA DATA CL MD DATA DATA DQM ROW: Row Address COL: Column Address DATA: READ DATA TRCD: RAS to CAS Delay Time CL: CAS Latency *Timing when CL2 operating Timing of Read Access to Same Row Address The above timing diagram shows that read access is made four times from LIME to the same row address of SDRAM. The ACTV command is issued and then the READ command is issued after TRCD elapses. Then data that is output after the elapse of CL after the READ command is issued is captured into LIME. MB86276 'LIME' GDC Specifications Rev1.1a 275 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.1.2 Timing of read access to different row addresses MCLKO TRAS TRP MRAS TRCD TRCD MCAS MWE MA ROW COL ROW CL MD COL CL DATA DATA DQM ROW: Row Address COL: Column Address DATA: READ DATA TRAS: RAS Active Time TRCD: RAS to CAS Delay Time CL: CAS Latency TRP: RAS Precharge Time *Timing when CL2 operating Timing of Read Access to Different Row Addresses The above timing diagram shows that read access is made from LIME to different row addresses of SDRAM. The first and next address to be read fall across an SDRAM page boundary, so the Precharge command is issued at the timing satisfying TRAS, and then after the elapse of TRP, the ACTV command is reissued, and then the READ command is issued. MB86276 'LIME' GDC Specifications Rev1.1a 276 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.1.3 Timing of write access to same row address MCLKO MRAS TRCD MCAS MWE MA ROW MD COL COL COL COL DATA DATA DATA DATA DQM ROW: Row Address COL: Column Address DATA: READ DATA TRCD: RAS to CAS Delay Time Timing of Write Access to Same Row Address The above timing diagram shows that write access is made form times form LIME to the same row address of SDRAM. The ACTV command is issued, and then after the elapse of TRCD, the WRITE command is issued to write to SDRAM. MB86276 'LIME' GDC Specifications Rev1.1a 277 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.1.4 Timing of write access to different row addresses MCLKO TRAS TRP MRAS TRCD TRCD MCAS MWE MA ROW MD COL ROW DATA COL DATA DQM ROW: Row Address COL: Column Address DATA: READ DATA TRAS: RAS Active Time TRCD: RAS to CAS Delay Time TRP: RAS Precharge Time Timing of Write Access to Different Row Addresses The above timing diagram shows that write access is made from LIME to different row addresses of SDRAM. The first and next address to be write fall across an SDRAM page boundary, so the Precharge command is issued at the timing satisfying TRAS, and then after the elapse of TRP, the ACTV command is reissued, and then the WRITE command is issued. MB86276 'LIME' GDC Specifications Rev1.1a 278 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.1.5 Timing of read/write access to same row address MCLKO MRAS TRCD MCAS MWE MA ROW COL COL CL MD LOWD DATA DATA DQM ROW: Row Address COL: Column Address DATA: READ DATA TRAS: RAS Active Time TRCD: RAS to CAS Delay Time CL: CAS Latency TRP: RAS Precharge Time LOWD: Last Output to Write Command Delay Timing when CL2 operating Timing of Read/Write Access to Same Row Address The above timing diagram shows that write access is made immediately after read access is made from LIME to the same row address of SDRAM. Read data is output from SDRAM, LOWD elapses, and then the WRITE command is issued. MB86276 'LIME' GDC Specifications Rev1.1a 279 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.1.6 Delay between ACTV commands MCLKO TRRD MRAS MCAS MWE MA ROW ROW ROW: Row Address TRRD: RAS to RAS Bank Active Delay Time Delay between ACTV Commands The ACTV command is issued from LIME GDC to the row address of SDRAM after the elapse of TRRD after issuance of the previous ACTV command. 13.1.7 Delay between Refresh command and next ACTV command MCLKO TRC MRAS MCAS MWE MA ROW ROW: Row Address TRC: RAS Cycle Time Delay between Refresh Command and Next ACTV Command The ACTV command is issued after the elapse of TRC after issuance of the Refresh command. MB86276 'LIME' GDC Specifications Rev1.1a 280 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.2 Display Timing 13.2.1 Non-interlace mode VTR+1 rasters VSP+1 rasters VSW+1 rasters VDP+1 rasters Ri/Gi/Bi HSYNC VSYNC Assert Frame Interrupt Assert Vsync Interrupt Ri/Gi/Bi DISPE HSYNC Latency 13 clocks HDP+1 clocks HSP+1 clocks HSW+1 clocks HTP+1 clocks DCLKO Ri/Gi/Bi 0 1 2 n-2 n-1 n=HDP+1 DISPE Non-interlace Timing In the above diagram, VTR, HDP, etc., are the setting values of their associated registers. The VSYNC/frame interrupt is asserted when display of the last raster ends. When updating display parameters, synchronize with the frame interrupt so no display disturbance occurs. Calculation for the next frame is started immediately after the vertical synchronization pulse is asserted, so the parameters must be updated by the time that calculation is started. VSYNC is output 1 dot clock faster than HSYNC. MB86276 'LIME' GDC Specifications Rev1.1a 281 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.2.2 Interlace video mode VTR+1 rasters (odd field) VSP+1 rasters VSW+1 rasters VDP+1 rasters Ri/Gi/Bi HSYNC VSYNC Assert Vsync Interrupt Ri/Gi/Bi HSYNC VSYNC VDP+1 rasters VSP+1 rasters VSW+1 rasters VTR+1 rasters (even field) Assert Frame Interrupt Assert Vsync Interrupt Interlace Video Timing In the above diagram, VTR, HDP, etc., are the setting values of their associated registers. The interlace mode also operates at the same timing as the interlace video mode. The only difference between the two modes is the output image data. MB86276 'LIME' GDC Specifications Rev1.1a 282 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.2.3 Composite synchronous signal When the EEQ bit of the DCM register is "0", the CSYNC signal output waveform is as shown below. even field odd field odd field even field CSYNC VSYNC CSYNC VSYNC Composite Synchronous Signal without Equalizing Pulse When the EEQ bit of the DCM register is "1", the equalizing pulse is inserted into the CSYNC signal, producing the waveform shown below. even field odd field odd field even field CSYNC VSYNC CSYNC VSYNC Composite Synchronous Signal with Equalizing Pulse The equalizing pulse is inserted when the vertical blanking time period starts. It is also inserted three times after the vertical synchronization time period has elapsed. MB86276 'LIME' GDC Specifications Rev1.1a 283 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3 Host interface Timing 13.3.1 CPU read/write timing diagram in SH3 mode (Normally Not Ready Mode) ( MODE[2:0]=000, RDY_MODE=0, BS_MODE=0) T1 Tsw1 Thw1 T2 T1 Tsw1 Thw1 Thw2 Thw3 T2 BCLKI A[24:2] XCS At Write At Read XBS XRD D[31:0] Hi-Z Valid Data Valid Data Hi-Z XWE[3:0] D[31:0] XWAIT Valid Data IN Valid Data IN Hi-Z Hi-Z Hi-Z SoftWait HardWait NotWait SoftWait HardWait HardWait HardWait Not Wait {: XWAIT sampling in SH3 mode x : Soft Wait (1 cycle) in SH3 mode T1: Read/write start cycle (XRDY in wait state) Tsw*: Thw*: Software wait insertion cycle (1 cycle setting) Hardware wait insertion cycle (XRDY cancels the wait state after the preparations) T2: Read/write end cycle (XRDY ends in wait state) Fig. Read/Write Timing Diagram for SH3 (Normally Not Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 284 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.2 CPU read/write timing diagram in SH3 mode (Normally Ready Mode) ( MODE[2:0]=000, RDY_MODE=1, BS_MODE=0) T1 Tsw1 Tsw2 T2 T1 Tsw1 Tsw2 Thw1 Thw2 T2 BCLKI A[24:2] XCS At Write At Read XBS XRD D[31:0] Hi-Z Valid Data Valid Data Hi-Z XWE[3:0] D[31:0] XWAIT Valid Data IN Valid Data IN Hi-Z Hi-Z SoftWait SoftWait NotWait Hi-Z SoftWait SoftWait HardWait HardWait NotWait {: XWAIT sampling in SH3 mode x : Soft Wait (2 cycles) in SH3 mode T1: Read/write start cycle (XRDY in not wait state) Tsw*: Software wait insertion cycle (2-cycle setting required) Thw*: Hardware wait insertion cycle (In hardware state when the immediate accessing is disabled) T2: Read/write end cycle (XRDY ends in not wait state) Fig. Read/Write Timing Diagram for SH3 (Normally Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 285 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.3 CPU read/write timing diagram in SH4 mode (Normally Not Ready Mode) ( MODE[2:0]=001, RDY_MODE=0, BS_MODE=0) T1 Tsw1 Thw1 T2 T1 Tsw1 Thw1 Thw2 Thw3 T2 BCLKI A[24:2] XCS At Write At Read XBS XRD Hi-Z D[31:0] Valid Data OUT Valid Data OUT XWE[3:0] D[31:0] XRDY Valid Data IN Valid Data IN Hi-Z Hi-Z SoftWaiit HardWait Ready SoftWait HardWait HardWait HardWait Ready {: XRDY sampling in SH4 mode x: Soft Wait (1 cycle) in SH4 mode T1: Read/write start cycle (XRDY in the not ready state) Tsw*: Software wait insertion cycle (1 cycle) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T2: Read/write end cycle (XRDY ends in not ready state) Fig. Read/Write Timing Diagram for SH4 Mode (Normally Not Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 286 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.4 CPU read/write timing diagram in SH4 mode (Normally Ready Mode) ( MODE[2:0]=001, RDY_MODE=1, BS_MODE=0) T1 Tsw1 Tsw2 T2 T1 Tsw1 Tsw2 Thw1 Thw2 T2 BCLKI A[24:2] XCS At Write At Read XBS XRD Hi-Z D[31:0] Valid Data OUT Valid Data OUT XWE[3:0] D[31:0] XRDY Valid Data IN Valid Data IN Hi-Z Hi-Z SoftWaiit SoftWait Ready SoftWait SoftWait HardWait HardWait Ready {: XRDY sampling in SH4 mode x : Soft Wait (2 cycles) in SH4 mode T1: Read/write start cycle (XRDY in ready state) Tsw*: Software wait insertion cycle (2-cycle setting required) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T2: Read/write end cycle (XRDY ends in ready state.) Fig. CPU Read/Write Timing Diagram for SH4 Mode (Normally Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 287 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.5 CPU read/write timing diagram in V832 mode (Normally Not Ready Mode) ( MODE[2:0]=010, RDY_MODE=0, BS_MODE=0) T1 Tsw1 Thw1 T2 T1 Tsw1 Thw1 Thw2 Thw3 T2 BCLKI A[23:2] XCS At Write At Read XB1CYST XMRD(XIORD) D[31:0] Hi-Z Valid Data Hi-Z Valid Data XMWR(XIOWR) XXXBEN[3:0] D[31:0] XREADY Valid Data IN Valid Data IN Hi-Z Hi-Z SoftWaiit HardWait Ready SoftWait HardWait HardWait HardWait Ready {: XREADY sampling in V832 mode x: Soft Wait (1 cycle) in V832 mode T1: Read/write start cycle (XREADY in not ready state) Tsw*: Software wait insertion cycle Twh*: Hardware wait insertion cycle (XREADY asserts Ready after the preparations) T2: Read/write end cycle (XREADY ends in not ready state) Notes: 1.The XxxBEN signal is used only for a write from the CPU; it is not used for a read from the CPU. 2.The CPU always inserts one cycle wait after read access. Fig. Read/Write Timing Diagram in V832 Mode (Normally Not Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 288 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.6 CPU read/write timing diagram in V832 mode (Normally Ready Mode) ( MODE[2:0]=010, RDY_MODE=1, BS_MODE=0) T1 Tsw1 Tsw2 T2 T1 Tsw1 Tsw2 Thw1 Thw2 T2 BCLKI A[23:2] XCS At Write At Read XBCYST XMRD(XIORD) D[31:0] Hi-Z Valid Data Valid Data Hi-Z XMWR(XIOWR) XXXBEN[3:0]) D[31:0] XREADY Valid Data IN Valid Data IN Hi-Z Hi-Z SoftWaiit SoftWait Ready SoftWait SoftWait HardWait HardWait Ready {: XREADY sampling in V832 mode x : Soft Wait (2 cycles) in V832 mode T1: Read/write start cycle (XREADY in ready state) Tsw*: Software wait insertion cycle (2-cycle setting required) Twh*: Hardware wait insertion cycle (XREADY asserts Ready after the preparations) T2: Read/write end cycle (XREADY ends in ready state) Notes: 1.The XxxBEN signal is used only for a write from the CPU; it is not used for a read from the CPU. 2.The CPU always inserts one cycle wait after read access. Fig. Read/Write Timing Diagram in V832 Mode (Normally Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 289 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.7 CPU read/write timing diagram in SPARClite (Normally Not Ready Mode) ( MODE[2:0]=011, RDY_MODE=0, BS_MODE=0) T1 Tsw1 Thw1 T2 T1 Tsw1 Thw1 Thw2 Thw3 T2 CLKINI ADR[23:2] CS# At Write At Read AS# RDWR# D[31:0] Hi-Z Valid Data Hi-Z Valid Data RDWR# BE[3:0]# D[31:0] READY# Valid Data IN Valid Data IN Hi-Z Hi-Z SoftWaiit HardWait Ready Hi-Z SoftWait HardWait HardWait HardWait Ready { : READY# sampling in SPARClite x: Soft Wait (1 cycle) in SPARClite T1: Read/write start cycle (READY# in not ready state) Tsw*: Software wait insertion cycle Twh*: Hardware wait insertion cycle (READY# asserts Ready after the preparations) T2: Read/write end cycle (READY# ends in not ready state) Note: BE# signal is used only for a write from the CPU; it is not used for a read from the CPU. Fig. Read/Write Timing Diagram in SPARClite (Normally Not Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 290 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.8 CPU read/write timing diagram in SPARClite (Normally Ready Mode) ( MODE[2:0]=011, RDY_MODE=1, BS_MODE=0) T1 Tsw1 Tsw1 T2 T1 Tsw1 Tsw1 Thw1 Thw2 T2 CLKINI ADR[23:2] CS# At Read AS# RDWR# D[31:0] Hi-Z Valid Data Hi-Z Valid Data At Write RDWR# BE#[3:0] D[31:0] READY# Valid Data IN Valid Data IN Hi-Z Hi-Z SoftWaiit SoftWait Ready Hi-Z SoftWait HardWait HardWait HardWait Ready { : READY# sampling in SPARClite x : Soft Wait (1 cycle) in SPARClite T1: Read/write start cycle (READY# in ready state) Tsw*: Software wait insertion cycle (2-cycle setting required) Twh*: Hardware wait insertion cycle (READY# asserts Ready after the preparations) T2: Read/write end cycle (READY# ends in ready state) Note: BE# signal is used only for a write from the CPU; it is not used for a read from the CPU. Fig. Read/Write Timing Diagram in SPARClite (Normally Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 291 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.9 SH4 single-address DMA write (transfer of 1 long word) BCLKIN D[31:0] DREQ DRACK Acceptance Acceptance Acceptance DTACK Bus cycle CPU DMAC *1 DMAC CPU *1 {: DREQ sampling and channel priority determination for SH mode (DREQ = level detection) *1: In the cycle steal mode, even when DREQ is already asserted at the 2nd DREQ sampling, the right to use the bus is returned to the CPU temporarily. In the burst mode, DMAC secures the right to use the bus unless DREQ is negated. Fig. SH4 Single-address DMA Write (Transfer of 1 Long Word) CORAL writes data according to the DTACK assert timing. When data cannot be received, the DREQ signal is automatically negated. And then the DREQ signal is reasserted as soon as data reception is ready. MB86276 'LIME' GDC Specifications Rev1.1a 292 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.10 SH4 single-address DMA write (transfer of 8 long words) BCLKIN D[31:0] DREQ DRACK Acceptance Acceptance DTACK Bus cycle {: CPU DMAC CPU DREQ sampling and channel priority determination for SH mode (DREQ = level detection) Fig. SH4 Single-address DMA Write (Transfer of 8 Long Words) After the CPU has asserted DRACK, CORAL negates DREQ and receives 32-byte data in line with the DTACK assertion timing. As soon as the next data is ready to be received, CORAL reasserts DREQ but the reassertion timing depends on the internal status. MB86276 'LIME' GDC Specifications Rev1.1a 293 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.11 SH3/4 dual-address DMA (transfer of 1 long word) BCLKIN DREQ Source address Destination address Source address Destination address A[24:2] Read Write Read Write D[31:0] For the CORAL, the read/write operation is performed according to the SRAM protocol. Fig. SH3/4 Dual-address DMA (Transfer of 1 Long Word) In the dual-address mode, the DREQ signal is kept asserted until the transfer ends by default. Consequently, when CORAL cannot return the ready signal immediately, in order to negate the DREQ signal set the DBM register. 13.3.12 SH3/4 dual-address DMA (transfer of 8 long words) BCLKIN DREQ Source address A[24:2] Read 1 D[31:0] Destination address ......... Read 2 ......... ......... ......... Read 8 Write 1 Write 2 ......... ......... Write 8 For the CORAL, the read/write operation is performed according to the SRAM protocol. Fig. SH3/4 Dual-address DMA (Transfer of 8 Long Words) In the dual-address mode, the DREQ signal is kept asserted until the transfer ends by default. Consequently, when CORAL cannot return the ready signal immediately, in order to negate the DREQ signal set the DBM register. MB86276 'LIME' GDC Specifications Rev1.1a 294 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.13 V832 DMA transfer BCLKIN DMARQ DMAAK Source address Destination address Source address Destination address A[23:2] Read Write Read Write D[31:0] For the CORAL, the read/write operation is performed according to the SRAM protocol. Fig. V832 DMA Transfer In the dual-address mode, the DREQ signal is kept asserted until the transfer ends by default. Consequently, when CORAL cannot return the ready signal immediately, in order to negate the DREQ signal set the DBM register. MB86276 'LIME' GDC Specifications Rev1.1a 295 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.14 SH4 single-address DMA transfer end timing BCLKIN D[31:0] DREQ DRACK Acceptance Acceptance DTACK Last data {: DREQ sampling and channel priority determination for SH mode (DREQ = level detection) Fig. SH4 Single-address DMA Transfer End Timing DREQ is negated three cycles after DRACK is written as the last data. 13.3.15 SH3/4 dual-address DMA transfer end timing BCLKIN DREQ DRACK Source address Destination address A[24:2] Read Write D[31:0] DTACK For the CORAL, the read/write operation is performed according to the SRAM protocol. Fig. SH3/4 Dual-address DMA Transfer End Timing DREQ is negated three cycles after DRACK is written as the last data. Note: When the dual address mode (DMA) is used, the DTACK signal is not used. MB86276 'LIME' GDC Specifications Rev1.1a 296 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.16 V832 DMA transfer end timing BCLKIN DMARQ A[24:2] D[31:0] Destination address Source address Write Read DMAAK XTC For the CORAL, the read/write operation is performed according to the SRAM protocol. Fig. V832 DMA Transfer End Timing DMMAK and XTC are logic ANDed inside CORAL to end DMA. MB86276 'LIME' GDC Specifications Rev1.1a 297 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.17 SH4 dual DMA write without ACK 1 2 3 4 CLK /DREQ When CORAL can not receive data immediately, DREQ negation continues. /BS While DREQ is issued at each write access to CORAL, DREQ is negated at every four cycles.. /RD /WE[3:0] ADDRESS SAR DAR /CS(CORAL) Right to use bus CPU DMAC Fig. DREQ Negate Timing for Each Transfer At each DMA transfer, DREQ is negated and then reasserted at the next cycle. Only the FIFO address can be used as the destination address. When CORAL cannot receive data immediately, DREQ negation continues. At that time, the negate timing is not only above diagram. MB86276 'LIME' GDC Specifications Rev1.1a 298 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.18 Dual-address DMA (without ACK) end timing /DREQ Right to use bus CPU DMAC CPU DMAC CPU Fig. Dual-address DMA (without ACK) End Timing Example: DMA operation when DMA transfer performed twice (1) The CPU accesses the DREQ issue register (DRQ) of Coral to issue DREQ. (2) The right to use bus is transferred from the CPU to the DMAC. (3) In the first DMAC cycle, write is performed to CORAL and DREQ is negated; DREQ is reasserted in the next cycle. (4) The right to use bus is returned to the CPU and the DREQ edge is detected, so the right to use bus is transferred to the DMAC. (5) The second write operation is performed and DREQ is negated, but DREQ is reasserted because CORAL does not recognize that the transfer has ended. (6) The right to use bus is transferred to the CPU, so the CPU writes to the DTS register of CORAL to negate DREQ. MB86276 'LIME' GDC Specifications Rev1.1a 299 MB86276 'LIME' GDC Specifications Rev1.1a 300 XRDY D[15:0] XWE[1:0] XBS XCS A[24:1] BCLKI Tsw1 Tsw2 Thw1 Thw2 Thw3 Thw4 T3 T1: Read/write start cycle (XRDY in the not ready state) Tsw*: Software wait insertion cycle (2 cycle) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T3: Write end cycle Upper 16bit data SoftWait SoftWait HardWai HardWai HardWai HardWai Ready Valid Data-2 IN T2 T1: Read/write start cycle (XRDY in the not ready state) Tsw*: Software wait insertion cycle (2 cycle) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T2: Write end cycle T1 XRDY sampling in 16bit CPU mode ( MODE[2:0]=100 ) Lower 16bit data SoftWaiit SoftWaiit HardWai Ready Valid Data-1 IN Tsw1 Tsw2 Thw1 T2 XRDY sampling in 16bit CPU mode ( MODE[2:0]=100 ) T1 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.19 CPU write timing diagram in 16bit CPU mode (Normally Not Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 301 XRDY D[15:0] XRD XBS XCS A[24:1] BCLKI T1 T1: Read/write start cycle (XRDY in the not ready state) Tsw*: Software wait insertion cycle (2 cycle) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T2: Read end cycle XRDY sampling in 16bit CPU mode ( MODE[2:0]=100 ) SoftWait SoftWait HardWai HardWai HardWai HardWai Ready Valid Data Tsw1 Tsw2 Thw1 Thw2 Thw3 Thw4 T2 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.20 CPU read timing diagram in 16bit CPU mode (Normally Not Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a XRDY AD[15:0] XWE[1:0] XBS(ALE) XCS BCLKI T2 302 T2 T1: Read/write start cycle (XRDY in the not ready state) Tsw*: Software wait insertion cycle (2 cycle) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T3: Write end cycle Upper 16bit data SoftWait SoftWait HardWai HardWai HardWai HardWai Ready Write Data2 Tsw1 Tsw2 Thw1 Thw2 Thw3 Thw4 T3 T1: Read/write start cycle (XRDY in the not ready state) Tsw*: Software wait insertion cycle (2 cycle) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T2: Write end cycle Address2 T1 XRDY sampling in 16bit CPU mode ( MODE[2:0]=101 ) Lower 16bit data SoftWaiit SoftWaiit HardWai Ready Write Data1 Tsw1 Tsw2 Thw1 T3 XRDY sampling in 16bit CPU mode ( MODE[2:0]=101 ) Address1 T1 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.21 CPU write timing diagram in 16bit AD-MUX CPU mode (Normally Not Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 303 XRDY AD[15:0] XWE[1:0] XBS(ALE) XCS BCLKI Address T1 T2 T1: Read/write start cycle (XRDY in the not ready state) Tsw*: Software wait insertion cycle (2 cycle) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T2: Read end cycle XRDY sampling in 16bit CPU mode ( MODE[2:0]=101 ) XWE[1:0]='H' means "Read" cycle. SoftWait SoftWait HardWai HardWai HardWai HardWai Ready Valid Data Tsw1 Tsw2 Thw1 Thw2 Thw3 Thw4 T3 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.22 CPU read timing diagram in 16bit AD-MUX CPU mode (Normally Not Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 304 XRDY AD[31:0] XWE[1:0] XBS(ALE) XCS BCLKI T2 Address T1 T1: Read/write start cycle (XRDY in the not ready state) Tsw*: Software wait insertion cycle (2 cycle) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T3: Write end cycle XRDY sampling in 16bit CPU mode ( MODE[2:0]=110 ) SoftWait SoftWait HardWai HardWai HardWai HardWai Ready Write Data Tsw1 Tsw2 Thw1 Thw2 Thw3 Thw4 T3 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.23 CPU write timing diagram in 32bit AD-MUX CPU mode (Normally Not Ready Mode) MB86276 'LIME' GDC Specifications Rev1.1a 305 XRDY AD[31:0] XWE[1:0] XBS(ALE) XCS BCLKI Address T1 T2 T1: Read/write start cycle (XRDY in the not ready state) Tsw*: Software wait insertion cycle (2 cycle) Twh*: Hardware wait insertion cycle (XRDY asserts Ready after the preparations) T3: Read end cycle XRDY sampling in 16bit CPU mode ( MODE[2:0]=110 ) XWE[1:0]='H' means "Read" cycle. SoftWait SoftWait HardWai HardWai HardWai HardWai Ready Valid Data Tsw1 Tsw2 Thw1 Thw2 Thw3 Thw4 T3 FUJITSU SEMICONDUCTOR CONFIDENTIAL 13.3.24 CPU read timing diagram in 32bit AD-MUX CPU mode (Normally Not Ready Mode) FUJITSU SEMICONDUCTOR CONFIDENTIAL 14 ELECTRICAL CHARACTERISTICS 14.1 Introduction The values in this chapter are the final specification for LIME. 14.2 Maximum Rating Maximum Rating Parameter *1 Symbol Power supply voltage VDDL VDDH Input voltage *1 Maximum rating Unit -0.5 < VDDL < 2.5 -0.5 < VDDH < 4.0 V VI -0.5 < VI < VDDH+0.5 (<4.0) V Output current IO 13 mA Ambient for storage temperature TST -55 < TST < +125 C Includes PLL power supply <Notes> z Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc) in excess of absolute maximum ratings. Do not exceed these ratings. z Do not directly connect output pins or bidirectional pins of IC products to each other or VDD or VSS to avoid the breakdown of the device. However direct connection of the output pins or bidirectional pins to each other is possible, if the output pins are designed to avoid a conflict in a timing. z Because semiconductor devices are particularly susceptible to damaged by static electricity, you must take the measure like ground all fixtures and instruments. z In CMOS ICs, a latch-up phenomenon is caused when an voltage exceeding Vcc or an voltage below Vss is applied to input or output pins or a voltage exceeding the rating is applied across Vcc and Vss. When a latch-up is caused, the power supply current may be dramatically increased causing resultant thermal break-down of devices. To avoid the latch-up, make sure that the voltage does not exceed the maximum rating. MB86276 'LIME' GDC Specifications Rev1.1a 306 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.3 Recommended Operating Conditions 14.3.1 Recommended operating conditions Recommended Operating Conditions Parameter Rating Symbol *1 Min. Typ. Max. 1.65 1.8 1.95 3.0 3.3 3.6 Unit Supply voltage VDDL VDDH Input voltage (High level) VIH 2.0 VDDH+0.3 V Input voltage (low level) VIL -0.3 0.8 V Ambient temperature for operation TA -40 85 C *1 V Includes PLL power supply <Note> z Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the manual. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. MB86276 'LIME' GDC Specifications Rev1.1a 307 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.3.2 Note at power-on * There is no restriction on the sequence of power-on/power-off between VDDL and VDDH. However, do not apply only VDDH for more than a few seconds. * Do not input HSYNC and VSYNC signals when the power supply voltage is not applied. (See the input voltage item in Maximum rating.) * Immediately after power-on, please reset immediately because CMOS IC is in an unstable state. 1) Immediately after power-on, input the "Low" level to the S and XRST pins. 2) Immediately after power-on, input clock to the BCLKI pin. It is necessary to input 10 clk or more in order that "Low" level signal reach to the whole internal circuit completely. 3) Immediately after power-on, input clock to the CLK pin. It is necessary to supply the stable clock before S pin is changed "Low" level to "High" level in order that PLL is oscillated stably. * There is a reset sequences as described below. VDDL There is no restriction on the sequence of power on. The recommendation is the order of VDDL and VDDH. Note: Clock shows the image and is not an actual cycle. VDDH System reset starts in 10 cycles. BCLKI Immediately after power-on, please input clock. CLK Immediately after power-on, please input clock. S Please input L level signal in the case of a power on. XRST Please input L level signal in the case of a power on. More than 500ns More than 300us Immediately after power-on, input the "Low" level to the S and XRST pins. After 500ns or more, input the "High" level to S pin. After the S pin is set to "High" level, input the "Low" level to the XRST pin for 300us or more. Immediately after power-on, input clock to the BCLKI and CLK pins. MB86276 'LIME' GDC Specifications Rev1.1a 308 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.4 DC Characteristics 14.4.1 DC Characteristics Measuring condition: VDDL = 1.8 1.5 V, VDDH = 3.3 0.3 V, VSS = 0.0 V, Ta = -40 to +85C Parameter Output voltage ("High" level) Output voltage ("Low" level) Output current ("High" level) Output current ("Low" level) Rating Unit Symbol Condition VOH IOH=-100uA VDDH-0.2 VDDH V VOL IOL=100uA 0.0 0.2 V -- VDDH=3.3V0.3V (*1) mA -- VDDH=3.3V0.3V (*1) mA Min. Typ. Max. Input leakage current IL 5 A Pin capacitance C 16 pF *1: Please refer "V-I characteristics diagram". L Type: Output characteristics of MD0-31 and MDQM0-3 pins M Type: Output characteristics of pins other than signals indicated by L type and H type H Type: Output characteristics of XINT, DREQ, XRDY pins MB86276 'LIME' GDC Specifications Rev1.1a 309 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.4.2 V-I characteristics diagram Condition MIN: Process=Slow, Ta=85C, VDD=3.0V TYP: Process=Typical, Ta=25C, VDD=3.3V MAX: Process=Fast, Ta=-40C, VDD=3.6V Fig. V-I characteristics L, M type Condition MIN: Process=Slow, Ta=85C, VDD=3.0V TYP: Process=Typical, Ta=25C, VDD=3.3V MAX: Process=Fast, Ta=-40C, VDD=3.6V Fig. V-I characteristics H type MB86276 'LIME' GDC Specifications Rev1.1a 310 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.5 AC Characteristics 14.5.1 Host interface Clock Parameter Symbol Condition Min. Rating Typ. Max. 66 Unit BCLKI frequency fBCLKI MHz BCLKI H-width tHBCLKI 1 ns BCLKI L-width tLBCLKI 1 ns Host interface signals based on BCLK (Operating condition: external load = 20 pF) Parameter Symbol Condition Rating Min. Typ. Max. Unit Address set up time tADS 3.0 ns Address hold time tADH 0.0 ns XBS Set up time tBSS 3.0 ns XBS Hold time tBSH 0.0 ns XCS Set up time tCSS 3.0 ns XCS Hold time tCSH 0.0 ns XRD Set up time tRDS 3.0 ns XRD Hold time tRDH 0.0 ns XWE Set up time tWES 5.0 ns XWE Hold time tWEH 0.0 ns Write data set up time tWDS 3.5 ns Write data hold time tWDH 0.0 ns DTACK Set up time tDAKS 3.0 ns DTACK Hold time tDAKH 0.0 ns DRACK Set up time tDRKS 3.0 ns DRACK Hold time tDRKH 0.0 ns Read data delay time (for XRD) tRDDZ 4.5 10.5 ns Read data delay time tRDD 4.5 9.5 ns XRDY Delay time (for XCS) tRDYDZ 3.5 7.0 ns XRDY Delay time tRDYD 2.5 6.0 ns XINT Delay time tINTD 3.0 7.0 ns DREQ Delay time tDQRD 3.5 7.0 ns MODE Hold time tMODH 20.0 ns *2 *1 *1 Hold time required for canceling reset *2 Valid data is output at assertion of XRDY and is retained until XRD is negated. MB86276 'LIME' GDC Specifications Rev1.1a 311 FUJITSU SEMICONDUCTOR CONFIDENTIAL Serial Control interface signals TBD MB86276 'LIME' GDC Specifications Rev1.1a 312 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.5.2 I2C Interface I2C bus timing symbol TS2SDAI SDA(I) setup time standard MIN 250 100 0 TH2SDAI SCL(I) hold time high-speed standard TCSCLI SCL(I) cycle time high-speed standard 0 10.0 TWHSCLI SCL(I) H period high-speed standard 4.0 SCL(I) L period high-speed standard 0.6 4.7 TCSCLO SCL(O) cycle time high-speed standard 1.3 2*m+2(*2) TWHSCLO SCL(O) H period high-speed standard int(1.5*m)+2(*2) m+2(*2) TWLSCLO SCL(O) L period TW2SCLI SCL(I) setup time TH2SCLI SCL(I) hold time TWBFI bus free time TS2SCLO SCL(O) set up time TH2SCLO SCL(O) hold time high-speed standard high-speed standard high-speed standard high-speed standard hirh-speed standard high-speed standard high-speed TH2SDAO SDA(O) hold time int(0.5*m)+2(*2) m(*2) m(*2) 4.0 0.6 4.7 1.3 4.7 1.3 m+2(*2) int(0.5*m)+2(*2) m-2(*2) int(0.5*m)-2(*2) 5 TWLSCLI 2.5 *1 PCLK is an internal clock of I2C module. (16.6MHz) *2 Refer to the clock control register (CCR) for the value of m. MB86276 'LIME' GDC Specifications Rev1.1a 313 MAX unit ns ns ns ns us us us us us us PCLK*1 PCLK*1 PCLK*1 PCLK*1 PCLK*1 PCLK*1 us us us us us us PCLK*1 PCLK*1 PCLK*1 PCLK*1 PCLK*1 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.5.3 Video interface (1) Clock Parameter Symbol Condition Rating Min. Typ. Max. 14.318 Unit CLK Frequency fCLK MHz CLK H-width tHCLK 25 ns CLK L-width tLCLK 25 ns DCLKI Frequency fDCLKI DCLKI H-width tHDCLKI 5 ns DCLKI L-width tLDCLKI 5 ns DCLKO frequency fDCLKO 80 80 MHz MHz (2) Input signals Parameter Rating Min. Typ. Max. Unit *1 3 clock tWHSYNC1 *2 3 clock HSYNC Input setup time tSHSYNC *2 6 ns HSYNC Input hold time tHHSYNC *2 1 ns 1 HSYNC 1 cycle VSYNC Input pulse width *2 Condition tWHSYNC0 HSYNC Input pulse width *1 Symbol tWHSYNC1 Applied only in PLL synchronization mode (CKS=0), reference clock output from internal PLL (cycle = 1/14*fCLK) Applied only in DCLKI synchronization mode (CKS=1), reference clock = DCLKI (3) Output signals (standard) This definition is applied for followig mode operations 1) single display & non-inverting DCLKO (MDen=0) & (DCKinv=0) 2) dual display & single-edge & non-inverting DCLKO (MDen=1) & (DCKed=0) & (DCKinv=0) (Operating condition: external load = 20 pF) Parameter Symbol Condition Rating Min. Typ. Max. Unit RGB Output delay time 1 TRGB1 2 9 ns DISPE Output delay time 1 tDEO1 2 9 ns HSYNC Output delay time 1 tDHSYNC1 2 9 ns VSYNC Output delay time 1 tDVSYNC1 2 9 ns CSYNC Output delay time 1 tDCSYNC1 2 10 ns GV Output delay time 1 tDGV1 1.5 9 ns MB86276 'LIME' GDC Specifications Rev1.1a 314 FUJITSU SEMICONDUCTOR CONFIDENTIAL (4) Output signals (inverting) This definition is applied for followig mode operations 1) single display & inverting DCLKO (MDen=0) & (DCKinv=1) 2) dual display & single-edge & inverting DCLKO (MDen=1) & (DCKed=0) & (DCKinv=1) (Operating condition: external load = 20 pF) Parameter Symbol Condition Rating Min. Typ. Max. Unit RGB Output delay time 2 TRGB2 2 9 ns DISPE Output delay time 2 tDEO2 2 9 ns HSYNC Output delay time 2 tDHSYNC2 2 9 ns VSYNC Output delay time 2 tDVSYNC2 2 9 ns CSYNC Output delay time 2 tDCSYNC2 2 10 ns GV Output delay time 2 tDGV2 1.5 9 ns (5) Output signals (bi-edge) This definition is applied for followig mode operations dual display & bi-edge (MDen=1) & (DCKed=1) (Operating condition: external load = 20 pF) Parameter Symbol Condition Rating Min. Typ. Max. Unit RGB Output delay time 3 TRGB3 1.5 9 ns DISPE Output delay time 3 tDEO3 1.5 9 ns HSYNC Output delay time 3 tDHSYNC3 1.5 9 ns VSYNC Output delay time 3 tDVSYNC3 1.5 9 ns CSYNC Output delay time 3 tDCSYNC3 1.5 10 ns GV Output delay time 3 tDGV3 1.5 9 ns RGB Output delay time 4 TRGB4 1.5 9 ns DISPE Output delay time 4 tDEO4 1.5 9 ns HSYNC Output delay time 4 tDHSYNC4 1.5 9 ns VSYNC Output delay time 4 tDVSYNC4 1.5 9 ns CSYNC Output delay time 4 tDCSYNC4 1.5 10 ns GV Output delay time 4 tDGV4 1.5 9 ns MB86276 'LIME' GDC Specifications Rev1.1a 315 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.5.4 Video capture interface clock parameter Symbol Rating Condition Min. Typ. Unit Max. *1 CCLK (RGBCLK) frequency fCCLK 27 CCLK (RGBCLK) H-width tHCCLKI 5 MHz ns CCLK (RGBCLK) L-width tLCCLKI 5 ns *1: Max buffer size of horizontal direction is 840. Input signals parameter Symbol Rating Condition Min. VI setup time VI hold time HSYNCI setup time HSYNCI hold time VSYNCI setup time VSYNCI hold time RI setup time RI hold time GI setup time GI hold time BI setup time BI hold time 14.5.5 tSVI tHVI tSHSI tHHSI tSVSI tHVSI tSRI tHRI tSGI tHGI tSBI tHBI Typ. Unit Max. 6 0 6 0 6 0 6 0 6 0 6 0 ns ns ns ns ns ns ns ns ns ns ns ns Graphics memory interface An assumed external capacitance Parameter An assumed external capacitance Min Typ Unit Max Board pattern 5.0 15.0 pF SDRAM (CLK) 2.5 4.0 pF SDRAM (D) 4.0 6.5 pF SDRAM (A, DQM) 2.5 5.0 pF MB86276 'LIME' GDC Specifications Rev1.1a 316 FUJITSU SEMICONDUCTOR CONFIDENTIAL Clock Parameter Symbol Condition Rating Min. Typ. Max. Unit MCLKO Frequency fMCLKO MCLKO H-width tHMCLKO 1.0 ns MCLKO L-width tLMCLKO 1.0 ns MCLKI Frequency fMCLKI MCLKI H-width tHMCLKI 1.0 ns MCLKI L-width tLMCLKI 1.0 ns *1 *1 *1 MHz MHz For the bus-asynchronous mode, the frequency is 1/3 of the oscillation frequency of the internal PLL. For the bus-synchronous mode, the frequency is the same as the frequency of BCLKI. Input signals Parameter Symbol Condition Rating Min. Typ. Max. Unit MD Input data setup time tMDIDS *2 2.0 ns MD Input data hold time tMDIDH *2 0.7 ns *2 It means against MCLKI. MB86276 'LIME' GDC Specifications Rev1.1a 317 FUJITSU SEMICONDUCTOR CONFIDENTIAL There are some cases regarding AC specifications of output signals. The following tables shows typical twelve cases of external SDFAM capacitance. (1) External SDRAM capacitance case 1 External SDRAM capacitance SDRAM x1 Total capacitance Unit MCLKO 9.8pF (DRAM CLK 2.5pF, Board pattern 5pF) pF MA,MRAS,MCAS,MWE 7.5pF (DRAM A.DQM 2.5pF, Board pattern 5pF) pF MD,DQM 9.0pF (DRAM D 4pF, Board pattern 5pF) pF Output signals Parameter Symbol MCLKI signal delay time against MCLKO MA, MRAS, MCAS, MWE Access time Condition Rating *1 Min. Typ. Unit Max. tDID 0 4.2 ns tMAD 1.0 5.0 ns MDQM Access time tMDQMD 1.1 5.4 ns MD Output access time tMDOD 1.1 5.4 ns (2) External SDRAM capacitance case 2 External SDRAM capacitance SDRAM x1 Total capacitance Unit MCLKO 24.8pF (DRAM CLK 4.0pF, Board pattern 15pF) pF MA,MRAS,MCAS,MWE 20.0pF (DRAM A.DQM 5pF, Board pattern 15pF) pF MD,DQM 21.5pF (DRAM D 6.5pF, Board pattern 15pF) pF Output signals Parameter MCLKI signal delay time against MCLKO MA, MRAS, MCAS, MWE Access time Symbol Condition Rating *1 Min. Typ. Max. Unit tDID 0 3.5 ns tMAD 1.0 5.2 ns MDQM Access time tMDQMD 1.2 5.5 ns MD Output access time tMDOD 1.2 5.5 ns MB86276 'LIME' GDC Specifications Rev1.1a 318 FUJITSU SEMICONDUCTOR CONFIDENTIAL (3) External SDRAM capacitance case 3 External SDRAM capacitance SDRAM x2 Total capacitance Unit MCLKO 12.3pF (DRAM CLK 2.5pF x2, Board pattern 5pF) pF MA,MRAS,MCAS,MWE 10.0pF (DRAM A.DQM 2.5pF x2, Board pattern 5pF) pF MD,DQM 9.0pF (DRAM D 4pF, Board pattern 5pF) pF Output signals Parameter Symbol MCLKI signal delay time against MCLKO MA, MRAS, MCAS, MWE Access time Condition Rating *1 Min. Typ. Unit Max. tDID 0 4.1 ns tMAD 1.0 5.0 ns MDQM Access time tMDQMD 1.1 5.2 ns MD Output access time tMDOD 1.1 5.2 ns (4) External SDRAM capacitance case 4 External SDRAM capacitance SDRAM x2 Total capacitance Unit MCLKO 28.8pF (DRAM CLK 4.0pF x2, Board pattern 15pF) pF MA,MRAS,MCAS,MWE 25.0pF (DRAM A.DQM 5pF x2, Board pattern 15pF) pF MD,DQM 21.5pF (DRAM D 6.5pF, Board pattern 15pF) pF Output signals Parameter MCLKI signal delay time against MCLKO MA, MRAS, MCAS, MWE Access time Symbol Condition Rating *1 Min. Typ. Max. Unit tDID 0 3.4 ns tMAD 1.1 5.4 ns MDQM Access time tMDQMD 1.1 5.5 ns MD Output access time tMDOD 1.1 5.5 ns MB86276 'LIME' GDC Specifications Rev1.1a 319 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.5.6 PLL specifications Parameter Description Input frequency (typ.) 14.31818 MHz Output frequency 400.9090 MHz x 28 Duty ratio 101.6 to 93.0% H/L Pulse width ratio of PLL output Jitter 60 to -60 ps Frequency tolerant of two consecutive clock cycles CLKSEL1 *1 Rating CLKSEL0 Input frequency Assured operation range (*1) L L 13.5 MHz 13.365 to 13.5 MHz L H 14.32 MHz 14.177 to 14.32 MHz H L 17.73 Hz 17.553 to 17.73 MHz H H 33.33 Hz 32.997 to 33.33 MHz Assured operation input frequency range: Standard value -1% MB86276 'LIME' GDC Specifications Rev1.1a 320 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.6 AC Characteristics Measuring Conditions tf tr 80 % 80 % VIH +VIL /2 Input 20 % 20 % tpHL tpLH Output VDD /2 VDD /2 tpZL Output disabled ( pull up ) tpLZ VDD /2 Output enabled (L) tpZH tpHZ Output enabled (H) VDD /2 Output disabled ( pull down ) tr, tf 5 ns :All input signals have to change within V =2.0 V, V5ns. = 0.8V (3.3-V CMOS interface input) IH IL MB86276 'LIME' GDC Specifications Rev1.1a 0.5 V 321 0.5 V FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.7 Timing Diagram 14.7.1 Host interface Host interface based on BCLKI (1)Clock 1/fBCLKI tHBCLKI tLBCLKI BCLKI (2)MODE hold time XRESET MODE tMODH (3)XINT output delay times BCLK XINT tINT MB86276 'LIME' GDC Specifications Rev1.1a 322 FUJITSU SEMICONDUCTOR CONFIDENTIAL (4)Host bus AC timing (Normally Not Ready) T1 Tsw1 Thw1 T2 BCLKI tADH tADS tBSH tBSS tCSH tCSS A tBSH tBSS XBS XCS tRDS tRDH XRD (RDXWR) tRDDZ tRDD Hi-Z D(output) tRDDZ Hi-Z Output data tWES tWEH XWE (XMWE) tWDS tWDH D(Input) tRDYDZ XRDY tRDYD tRDYDZ Hi-Z Hi-Z tRDYDZ XWAIT tRDYD tRDYD tRDYDZ Hi-Z MB86276 'LIME' GDC Specifications Rev1.1a tRDYD 323 Hi-Z FUJITSU SEMICONDUCTOR CONFIDENTIAL (5)Host bus AC timing (Normally Ready) T1 Tsw1 Tsw2 Thw1 T2 BCLKI tADH tADS tBSH tBSS tCSH tCSS A tBSH tBSS XBS XCS tRDS tRDH XRD (RDXWR) tRDDZ D(output) tRDD tRDDZ Hi-Z Hi-Z Output data tWES tWEH tWDS tWDH XWE (XMWE) D(Input) tRDYDZ XRDY tRDYD Hi-Z tRDYDZ tRDYD tRDYDZ XWAIT Hi-Z Hi-Z tRDYD tRDYD MB86276 'LIME' GDC Specifications Rev1.1a Hi-Z tRDYDZ 324 FUJITSU SEMICONDUCTOR CONFIDENTIAL (6)DMA AC timing BCLKI tWDH tWDS tWDH tDAKH tDAKS tDAKH tDAKS tRRKH tDRKS tRRKH tDRKS D(Input) DTACK (XTC) DRACK (DMAAK ) tDRQD tDRQD DREQ *: The above timing diagram for the D pin is that of when a single DMA is used. When a dual DMA is used, see the host bus-timing diagram. MB86276 'LIME' GDC Specifications Rev1.1a 325 FUJITSU SEMICONDUCTOR CONFIDENTIAL Serial Control interface TBD MB86276 'LIME' GDC Specifications Rev1.1a 326 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.7.2 Video interface (1) Clock 1/fCLK tHCLK CLK tLCLK VIH VIL (2) HSYNC signal setup/hold 1/fDCLKI tHDCLKI tLDCLKI DCLKI HSYNC (input) tSHSYN tHHSYN (3) Output signal delay ( standard ) DCLKO DR7-2, DG7-2 DB7-2 HSYNC (output) VSYNC (output) CSYNC, DE GV tRGB , tDEO, tDHSYNC, tDVSYNC, tDCSYNC, tDGV MB86276 'LIME' GDC Specifications Rev1.1a 327 FUJITSU SEMICONDUCTOR CONFIDENTIAL (4) Output signal delay ( inverted ) DCLKO DR7-2, DG7-2 DB7-2 HSYNC (output) VSYNC (output) CSYNC, DE GV tRGB2 , tDEO2, tDHSYNC2, tDVSYNC2, tDCSYNC2, tDGV2 (5) Output signal delay ( bi-edge ) DCLKO DR7-2, DG7-2 DB7-2 HSYNC (output) VSYNC (output) CSYNC, DE GV tRGB3 , tDEO3, tDHSYNC3, tDVSYNC3, tDCSYNC3, tDGV3 MB86276 'LIME' GDC Specifications Rev1.1a 328 tRGB4, tDEO4, tDHSYNC4, tDVSYNC4, tDCSYNC4, tDGV4 FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.7.3 Video capture interface clock Video input CCLK RGBCLK VI RI,GI,BI VSYNCI HSYNCI tSVI tSRI tSVSI MB86276 'LIME' GDC Specifications Rev1.1a tSGI tSHSI tSBI 329 tHVI tHRI tHVSI tHGI tHHSI tHBI FUJITSU SEMICONDUCTOR CONFIDENTIAL 14.7.4 Graphics memory interface Clock 1/fMCLKO, 1/fMCLKI tHMCLKO, tHMCLKI tLMCLKO, tLMCLKI MCLKO, MCLKI Input signal setup/hold time MCLKI MD Input data tMDIDS tMDIDH MCLKI signal delay MCLKO MCLKI tOID MB86276 'LIME' GDC Specifications Rev1.1a 330 FUJITSU SEMICONDUCTOR CONFIDENTIAL Output signal delay MCLKO MA, MRAS, MCAS, MWE, MD, MDQM tMAD, tMDOD, tMDQMD MB86276 'LIME' GDC Specifications Rev1.1a 331