TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 - APRIL 1994 - REVISED JULY 1995 D D D D D D D Low rDS(on) . . . 5 Typical Avalanche Energy . . . 30 mJ Eight Power DMOS-Transistor Outputs of 150-mA Continuous Current 500-mA Typical Current-Limiting Capability Output Clamp Voltage . . . 50 V Four Distinct Function Modes Low Power Consumption DW OR N PACKAGE (TOP VIEW) NC VCC S0 DRAIN0 DRAIN1 DRAIN2 DRAIN3 S1 GND GND description This power logic 8-bit addressable latch controls open-drain DMOS-transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multifunctional device capable of storing single-line data in eight addressable latches and 3-to-8 decoder or demultiplexer with active-low DMOS outputs. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 NC CLR D DRAIN7 DRAIN6 DRAIN5 DRAIN4 G S2 GND NC - No internal connection FUNCTION TABLE EACH OTHER DRAIN Qio Qio H H L L H L OUTPUT OF ADDRESSED DRAIN L H H H X Qio Qio L L H L H INPUTS CLR G D FUNCTION Addressable Latch Memory 8-Line Four distinct modes of operation are selectable by L L L Demultiplexer H H controlling the clear (CLR) and enable (G) inputs L H X H H Clear as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) LATCH SELECTION TABLE terminal is written into the addressed latch. The SELECT INPUTS DRAIN addressed DMOS-transistor output inverts the ADDRESSED S2 S1 S0 data input with all unaddressed DMOS-transistor L L L 0 outputs remaining in their previous states. In the L L H 1 memory mode, all DMOS-transistor outputs L H L 2 L H H remain in their previous states and are unaffected 3 H L L 4 by the data or address inputs. To eliminate the H L H 5 possibility of entering erroneous data in the latch, H H L 6 enable G should be held high (inactive) while the H H H 7 address lines are changing. In the 3-to-8 decoding H = high level, L = low level or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are off. In the clear mode, all outputs are off and unaffected by the address and data inputs. When data is low for a given output, the DMOS-transistor output is off. When data is high, the DMOS-transistor output has sink-current capability. Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and 150-mA continuous sink-current capability. Each output provides a 500-mA typical current limit at TC = 25C. The current limit decreases as the junction temperature increases for additional device protection. The TPIC6B259 is characterized for operation over the operating case temperature range of - 40C to 125C. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 - APRIL 1994 - REVISED JULY 1995 logic symbol S0 S1 S2 G D CLR 3 0 8 12 13 18 19 8M 0/7 2 G8 Z9 Z10 9,0D 4 DRAIN0 10,0R 9,1D 5 DRAIN1 10,1R 9,2D 6 DRAIN2 10,2R 9,3D 7 DRAIN3 10,3R 9,4D 14 DRAIN4 10,4R 9,5D 15 DRAIN5 10,5R 9,6D 16 DRAIN6 10,6R 9,7D 17 10,7R This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 DRAIN7 TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 - APRIL 1994 - REVISED JULY 1995 logic diagram (positive logic) 4 DRAIN0 S0 3 D C1 CLR 5 DRAIN1 D C1 CLR 6 DRAIN2 D S1 C1 CLR 8 7 DRAIN3 D C1 CLR S2 14 12 DRAIN4 D C1 CLR 15 DRAIN5 D C1 CLR 16 DRAIN6 D C1 CLR 18 17 D DRAIN7 D G CLR C1 CLR 13 9,10,11 19 GND POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 - APRIL 1994 - REVISED JULY 1995 schematic of inputs and outputs EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS VCC DRAIN 50 V Input 25 V 20 V 12 V GND GND absolute maximum ratings over the recommended operating case temperature range (unless otherwise noted) Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to 7 V Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 V Continuous source-to-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Pulsed source-to-drain diode anode current (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A Pulsed drain current, each output, all outputs on, ID, TC = 25C (see Note 3) . . . . . . . . . . . . . . . . . . . 500 mA Continuous drain current, each output, all outputs on, ID, TC = 25C . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA Peak drain current single output, IDM, TC = 25C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mJ Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipating Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 150C Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values are with respect to GND. 2. Each power DMOS source is internally connected to GND. 3. Pulse duration 100 s and duty cycle 2%. 4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25C, L = 200 mH, IAS = 0.5 A (see Figure 4). DISSIPATION RATING TABLE 4 PACKAGE TC 25C POWER RATING DERATING FACTOR ABOVE TC = 25C TC = 125C POWER RATING DW 1389 mW 11.1 mW/C 278 mW N 1050 mW 10.5 mW/C 263 mW POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 - APRIL 1994 - REVISED JULY 1995 recommended operating conditions Logic supply voltage, VCC High-level input voltage, VIH MIN MAX 4.5 5.5 UNIT V 0.85 VCC Low-level input voltage, VIL Pulsed drain output current, TC = 25C, VCC = 5 V (see Notes 3 and 5) V 0.15 VCC V 500 mA - 500 Setup time, D high before G, tsu (see Figure 2) 20 ns Hold time, D high after G, th (see Figure 2) 20 ns Pulse duration, tw (see Figure 2) 40 Operating case temperature, TC - 40 ns C 125 electrical characteristics, VCC = 5 V, TC = 25C (unless otherwise noted) PARAMETER TEST CONDITIONS V(BR)DSX Drain-to-source breakdown voltage ID = 1 mA VSD Source-to-drain diode forward voltage IF = 100 mA MIN TYP MAX 50 V 0.85 IIH IIL High-level input current Low-level input current VCC = 5.5 V, VCC = 5.5 V, ICC Logic supply current 5V VCC = 5 5.5 IN Nominal current VDS(on) = 0.5 V, IN = ID, See Notes 5, 6, and 7 VI = VCC VI = 0 IDSX Off state drain current Off-state VDS = 40 V, VDS = 40 V, VCC = 5.5 V VCC = 5.5 V, rDS(on) Static drain-to-source on-state resistance ID = 100 mA, ID = 100 mA, TC = 125C ID = 350 mA, VCC = 4.5 V VCC = 4.5 V, 1 V 1 A -1 A All outputs off 20 100 All outputs on 150 300 TC = 85C, 90 TC = 125C See Notes 5 and 6 and Figures 6 and 7 VCC = 4.5 V UNIT A mA 0.1 5 0.15 8 4.2 5.7 6.8 9.5 5.5 8 TYP MAX A switching characteristics, VCC = 5 V, TC = 25C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low-to-high-level output from D tr tf Rise time, drain output ta trr Reverse-recovery-current rise time Propagation delay time, high-to-low-level output from D CL = 30 pF,, ID = 100 mA,, See Figures 1, 2, and 8 Fall time, drain output Reverse-recovery time NOTES: 3. 5. 6. 7. IF = 100 mA, di/dt = 20 A/s, See Notes 5 and 6 and Figure 3 MIN UNIT 150 ns 90 ns 200 ns 200 ns 100 300 ns Pulse duration 100 s and duty cycle 2%. Technique should limit TJ - TC to 10C maximum. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a voltage drop of 0.5 V at TC = 85C. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 - APRIL 1994 - REVISED JULY 1995 thermal resistance PARAMETER RJA TEST CONDITIONS DW package junction to ambient Thermal resistance junction-to-ambient All 8 outputs with equal power N package MIN MAX 90 95 UNIT C/W PARAMETER MEASUREMENT INFORMATION 5V CLR 5V 0V 5V 24 V S0 2 3 8 Word Generator (see Note A) 12 13 19 18 S0 VCC 0V 5V ID S2 DUT G 4 -7, 14 -17 0V 5V Output S2 0V DRAIN CLR D S1 RL = 235 S1 GND CL = 30 pF (see Note B) 5V G 0V 9, 10, 11 5V D 0V 24 V TEST CIRCUIT DRAIN5 0.5 V 24 V DRAIN3 0.5 V VOLTAGE WAVEFORMS NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 . B. CL includes probe and jig capacitance. Figure 1. Resistive-Load Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 - APRIL 1994 - REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 5V G 5V 2 Word Generator (see Note A) 18 24 V 19 VCC D 50% tPLH ID D G DRAIN 4 -7, 14 -17 24 V 90% 10% 10% tr Output 0.5 V tf SWITCHING TIMES GND CL = 30 pF (see Note B) 9, 10,11 tPHL 90% Output 235 13 50% 0V CLR DUT Word Generator (see Note A) 0V 5V 5V G 50% 0V tsu th TEST CIRCUIT 5V D 50% 50% 0V tw INPUT SETUP AND HOLD WAVEFORMS NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz, ZO = 50 . B. CL includes probe and jig capacitance. Figure 2. Test Circuit, Switching Times, and Voltage Waveforms TP K DRAIN 0.1 A 2500 F 250 V Circuit Under Test + L = 1 mH IF (see Note A) 25 V di/dt = 20 A/s IF - TP A 0 25% of IRM t2 t1 t3 Driver IRM RG VGG (see Note B) ta 50 trr CURRENT WAVEFORM TEST CIRCUIT NOTES: A. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the TP A test point. B. The VGG amplitude and RG are adjusted for di/dt = 20 A/s. A VGG double-pulse train is used to set IF = 0.1 A, where t1 = 10 s, t2 = 7 s, and t3 = 3 s. Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-to-Drain Diode POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 - APRIL 1994 - REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 5V 15 V tw 2 12 S2 8 Word Generator (see Note A) VCC S0 13 Input See Note B ID DUT G 18 5V 10.5 S1 3 D DRAIN 19 4 -7, 14 -17 tav 0V IAS = 0.5 A 200 mH ID VDS CLR V(BR)DSX = 50 V MIN VDS GND 9, 10, 11 VOLTAGE AND CURRENT WAVEFORMS TEST CIRCUIT NOTES: A. The word generator has the following characteristics: tr 10 ns, tf 10 ns, ZO = 50 . B. Input pulse duration, tw, is increased until peak current IAS = 0.5 A. Energy test level is defined as EAS = IAS x V(BR)DSX x tav/2 = 30 mJ. Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms TYPICAL CHARACTERISTICS PEAK AVALANCHE CURRENT vs TIME DURATION OF AVALANCHE DRAIN-TO-SOURCE ON-STATE RESISTANCE vs DRAIN CURRENT rDS(on) - Drain-to-Source On-State Resistance - 10 IAS - Peak Avalanche Current - A TC = 25C 4 2 1 0.4 0.2 0.1 0.1 0.2 0.4 1 2 4 10 18 VCC = 5 V See Note A 16 14 TC = 125C 12 10 8 6 TC = 25C 4 TC = - 40C 2 0 0 100 tav - Time Duration of Avalanche - ms 200 300 400 500 ID - Drain Current - mA 700 NOTE C: Technique should limit TJ - TC to 10C maximum. Figure 5 Figure 6 8 600 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 - APRIL 1994 - REVISED JULY 1995 TYPICAL CHARACTERISTICS 8 SWITCHING TIME vs CASE TEMPERATURE 300 ID = 100 mA See Note A 7 ID = 100 mA See Note A tf TC = 125C 250 6 Switching Time - ns r DS(on) - Static Drain-to-Source On-State Resistance - STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE vs LOGIC SUPPLY VOLTAGE 5 TC = 25C 4 3 TC = - 40C 2 tr 200 tPLH 150 tPHL 100 1 0 4 4.5 5 5.5 6 6.5 7 50 - 50 - 25 VCC - Logic Supply Voltage - V Figure 7 0 25 50 75 100 TC - Case Temperature - C 125 Figure 8 NOTE D: Technique should limit TJ - TC to 10C maximum. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TPIC6B259 POWER LOGIC 8-BIT ADDRESSABLE LATCH SLIS030 - APRIL 1994 - REVISED JULY 1995 MAXIMUM CONTINUOUS DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY I D - Maximum Continuous Drain Current of Each Output - A 0.45 VCC = 5 V 0.4 0.35 0.3 0.25 TC = 25C 0.2 0.15 TC = 100C 0.1 TC = 125C 0.05 0 1 2 3 4 5 6 7 8 N - Number of Outputs Conducting Simultaneously I D - Maximum Peak Drain Current of Each Output - A THERMAL INFORMATION MAXIMUM PEAK DRAIN CURRENT OF EACH OUTPUT vs NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 0.5 d = 10% 0.45 d = 20% 0.4 0.35 d = 50% 0.3 0.25 d = 80% 0.2 0.15 VCC = 5 V TC = 25C d = tw/tperiod = 1 ms/tperiod 0.1 0.05 0 1 3 4 Figure 10 POST OFFICE BOX 655303 5 6 7 8 N - Number of Outputs Conducting Simultaneously Figure 9 10 2 * DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 29-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) TPIC6B259DW ACTIVE SOIC DW 20 25 TBD CU NIPDAU Level-1-220C-UNLIM TPIC6B259DWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD CU NIPDAU Level-1-220C-UNLIM CU NIPDAU Level-1-260C-UNLIM CU NIPDAU N / A for Pkg Type TPIC6B259DWR ACTIVE SOIC DW 20 2000 TPIC6B259DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) TPIC6B259N ACTIVE PDIP N 20 20 Pb-Free (RoHS) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Dec-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPIC6B259DWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.1 2.65 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 9-Dec-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPIC6B259DWR SOIC DW 20 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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