1
JUNE 1999
DSC-2720/9
IDT7134SA/LA
HIGH-SPEED
4K x 8 DUAL-PORT
STATIC SRAM
Features
◆◆
◆◆
◆High-speed access
Military: 25/35/45/55/70ns (max.)
Industrial: 55ns (max.)
Commercial: 20/25/35/45/55/70ns (max.)
◆◆
◆◆
◆Low-power operation
IDT7134SA
Active: 700mW (typ.)
Standby: 5mW (typ.)
IDT7134LA
Active: 700mW (typ.)
Standby: 1mW (typ.)
◆◆
◆◆
◆Fully asynchronous operation from either port
◆◆
◆◆
◆Battery backup operation2V data retention
◆◆
◆◆
◆TTL-compatible; single 5V (±10%) power supply
◆◆
◆◆
◆Available in 48-pin DIP, LCC, Flatpack and 52-pin PLCC
◆◆
◆◆
◆Military product compliant to MIL-PRF-38535 QML
◆◆
◆◆
◆Industrial temperature range (40°C to +85°C) is available for
selected speeds
Functional Block Diagram
COLUMN
I/O COLUMN
I/O
MEMORY
ARRAY
LEFT SIDE
ADDRESS
DECODE
LOGIC
RIGHT SIDE
ADDRESS
DECODE
LOGIC
R/WL
OEL
A0L-A
11L
I/O0L-I/O
7L
2720 drw 01
CEL
A0R-A
11R
I/O0R-I/O
7R
OER
CER
R/WR
Description
The IDT7134 is a high-speed 4K x 8 Dual-Port Static RAM
designed to be used in systems where on-chip hardware port arbitration
is not needed. This part lends itself to those systems which cannot
tolerate wait states or are designed to be able to externally arbitrate or
withstand contention when both sides simultaneously access the
same Dual-Port RAM location.
The IDT7134 provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. It is the users responsibility
to ensure data integrity when simultaneously accessing the same
memory location from both ports. An automatic power down feature,
controlled by CE, permits the on-chip circuitry of each port to enter a
very low standby power mode.
Fabricated using IDTs CMOS high-performance technology, these
Dual-Port typically operate on only 700mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port
typically consuming 200µW from a 2V battery.
The IDT7134 is packaged on either a sidebraze or plastic 48-pin
DIP, 48-pin LCC, 52-pin PLCC and 48-pin Flatpack. Military grade
product is manufactured in compliance with the latest revision of MIL-
PRF-38535 QML, making it ideally suited to military temperature
applications demanding the highest level of performance and reliability.
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
2
Pin Configurations(1,2,3)
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. P48-1 package body is approximately .55 in x .61 in x .19 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
J52-1 package body is approximately .75 in x .75 in x .17 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approxiamtely .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of actual part-marking.
A10R
2720 drw 02
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
A9R
A8R
A7R
A6R
A4R
A3R
A2R
A1R
A0R
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
148
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
IDT7134P or C
P48-1(4)
&
C48-2(4)
48-Pin
Top
View(5)
CEL
R/WL
OEL
VCC
A5R
R
OE
A11R
R/WR
CER
A11L
A10L
GND ,2720 drw 03
IDT7134J
J52-1(4)
52-Pin PLCC
Top View(5)
INDEX
N/C
GND
I/O
4L
I/O
5L
I/O
6L
I/O
7L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
N/C
I/O7R
46
45
44
43
42
41
40
39
38
37
36
35
34
I/O3L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
8
9
10
11
12
13
14
15
16
17
18
19
20
474849505152
1
234567
33323130292827262524232221
A
0L
V
CC
OE
L
R/W
L
CE
R
R/W
R
CE
L
A
10L
A
11L
A
11R
A
10R
N/C
N/C
2720 drw 04
IDT7134L48 or F
L48-1(4)
&
F48-1(4)
48-Pin LCC/Flatpack
Top View(5)
INDEX
65432148 47 46 45 44 43
19 20 21 22 23 25 26 27 28 29 3024
GND
I/O
3L
I/O
4L
I/O
5
L
I/O
6L
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
7L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O0L
I/O1L
I/O2L
A0R
A1R
A2R
A3R
A4R
A5R
A6R
A7R
A8R
A9R
I/O6R
I/O7R
42
41
40
39
38
37
36
35
34
33
32
31
7
8
9
10
11
12
13
14
15
16
17
18
A
0L
V
CC
OE
L
R/W
L
CE
R
R/W
R
CE
L
OE
R
A
10L
A
11L
A
11R
A
10R
,
3
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Capacitance(1) (TA = +25°C, f = 1.0MHz)
Absolute Maximum Ratings(1) Recommended Operating
Temperature and Supply Voltage(1,2)
Recommended DC Operating
Conditions
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5V ± 10%)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 10% for more than 25%of the cycle time or 10 ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc +10%.
3. VTERM = 5.5V.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V and from 3V to 0V.
NOTES:
1. This is the parameter TA.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
NOTES:
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
NOTES:
1. At Vcc < 2.0V input leakages are undefined.
Symbol Rating Commercial
& Industrial
Military Unit
VTERM(2 ) Terminal Voltage
with Respect
to GND
-0.5 to +7.0 -0.5 to +7.0 V
TBIAS Temperature
Under Bias
-55 to +125 -65 to +135 oC
TSTG Storage
Temperature
-55 to +125 -65 to +150 oC
PT(3 ) Power
Dissipation
1.5 1.5 W
IOUT DC Output
Current
50 50 mA
2720 tbl 01
Grade Ambient
Temperature
GND Vcc
Military -55OC to +125OC0V 5.0V
+ 10%
Commercial 0OC to +70OC0V5.0V
+ 10%
Industrial -40OC to +85OC0V 5.0V
+ 10%
2720 tbl 03
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
VIH Inp ut Hig h Vo ltage 2.2 ____ 6.0(2 ) V
VIL Input Low Voltage -0.5(1 ) ____ 0.8 V
2720 tbl 04
Symbol Parameter Conditions(2) Max. Unit
CIN Input Capacitance VIN = 3dV 11 pF
COUT Output Capacitance VOUT
= 3dV 11 pF
2720 tbl 02
Symbol Parameter Test Conditions
7134SA 7134LA
UnitMin. Max. Min. Max.
|ILI| Input Leakage Current(1 ) VCC = 5.5V, VIN = 0V to VCC ___ 10 ___ 5µA
|ILO| Output Leakage Current CE - VIH, VOUT
= 0V to VCC ___ 10 ___ 5µA
VOL Output Low Voltage IOL = 6mA ___ 0.4 ___ 0.4 V
IOL = 8mA ___ 0.5 ___ 0.5 V
VOH Output High Vo ltage IOH = -4mA 2.4 ___ 2.4 ___ V
2720 tbl 05
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,2,4) (VCC = 5.0V ± 10%)
NOTES:
1. 'X' in part number indicates power rating (SA or LA).
2. VCC = 5V, TA = +25°C for typical, and parameters are not production tested.
3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable). f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.
4. Industrial temperature: for other speeds, packages and powers contact your sales office.
7134X20
Com'l Only
7134X25
Com'l &
Military
7134X35
Com'l &
Military
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CE = VIL
Outputs Open
f = fMAX(3)
COM'L SA
LA
170
170
280
240
160
160
280
220
150
150
260
210
mA
MIL &
IND
SA
LA
____
____
____
____
160
160
310
260
150
150
300
250
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(3)
COM'L SA
LA
25
25
100
80
25
25
80
50
25
25
75
45
mA
MIL &
IND
SA
LA
____
____
____
____
25
25
100
80
25
25
75
55
ISB2 Standb y Current
(One Port - TTL
Level Inputs)
CE"A" = VIL
and CE"B"
= VIH
Active Port Outputs Open,
f=fMAX(3)
COM'L SA
LA
105
105
180
150
95
95
180
140
85
85
170
130
mA
MIL &
IND
SA
LA
____
____
____
____
95
95
210
170
85
85
200
160
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
COM'L SA
LA
1.0
0.2
15
4.5
1.0
0.2
15
4.0
1.0
0.2
15
4.0
mA
MIL &
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
1.0
0.2
30
10
ISB4 Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CE"A" or
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open,
f = fMAX(3)
COM'L SA
LA
105
105
170
130
95
95
170
120
85
85
160
110
mA
MIL &
IND
SA
LA
____
____
____
____
95
95
210
150
85
85
190
130
2720 tb l 06a
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
Symbol Parameter Test Condition Version Typ. Max. Typ. Max. Typ. Max. Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CE = VIL
Outputs Open
f = fMAX(3)
COM'L SA
LA
140
140
240
200
140
140
240
200
140
140
240
200
mA
MIL &
IND
SA
LA
140
140
280
240
140
140
270
220
140
140
270
220
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CE
R = VIH
f = fMAX(3)
COM'L SA
LA
25
25
70
40
25
25
70
40
25
25
70
40
mA
MIL &
IND
SA
LA
25
25
70
50
25
25
70
50
25
25
70
50
ISB2 Standby Current
(One Po rt - TTL
Level Inputs)
CE"A" = VIL
and CE
"B" = VIH
Active Port Outputs Open,
f=fMAX(3)
COM'L SA
LA
75
75
160
130
75
75
160
130
75
75
160
130
mA
MIL &
IND
SA
LA
75
75
190
150
75
75
180
150
75
75
180
150
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(3)
COM'L SA
LA
1.0
0.2
15
4.0
1.0
0.2
15
4.0
1.0
0.2
15
4.0
mA
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
ISB4 Full Standby Current
(One Po rt -
CMOS Level Inputs)
One Port CE
"A" or
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Open,
f = fMAX(3)
COM'L SA
LA
75
75
150
100
75
75
150
100
75
75
150
100
mA
MIL &
IND
SA
LA
75
75
180
120
75
75
170
120
75
75
170
120
2720 tb l 06b
5
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
VCC
CE
DATA RETENTION MODE
4.5V4.5V VDR ≥2V
VDR VIH
VIH
tCDR tR
2720 drw 05
Data Retention Characteristics Over All Temperature Ranges
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
Data Retention Waveform
AC Test Conditions
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
*Including scope and jig
+5V
1250Ω
30pF
775Ω
DATAOUT
2720 drw 06 ,
+5V
1250Ω
5pF *
775Ω
DATAOUT
2720 drw 07 ,
NOTES:
1. VCC = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but not production tested.
Input Pulse Levels
Input Rise /Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1 and 2
2720 tbl 08
Symbol Parameter Test Condition Min. Typ.(1) Max. Unit
VDR VCC fo r Da ta Re te ntio n VCC = 2V 2.0 ___ ___ V
ICCDR Data Rete ntion Current CE > VHC
VIN > VHC or < VLC
MIL. & IND. ___ 100 4000 µA
COM'L. ___ 100 1500
tCDR (3 ) Chip Dese lec t to Data Retention Time 0 ___ ___ ns
tR(3 ) Operation Recovery Time tRC(2) ___ ___ ns
2720 tbl 07
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
6
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (SA or LA).
4. Industrial temperature: for other speeds, packages and powers contact your sales office.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(3,4)
7134X20
Com'l Only
7134X25
Com'l &
Military
7134X35
Com'l &
Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
tRC Read Cyc le Time 20 ____ 25 ____ 35 ____ ns
tAA Address Access Time ____ 20 ____ 25 ____ 35 ns
tACE Chip Enable Access Time ____ 20 ____ 25 ____ 35 ns
tAOE Output Enable Access Time ____ 15 ____ 15 ____ 20 ns
tOH Output Hold from Address Change 0 ____ 0____ 0____ ns
tLZ Output Low-Z Time (1,2) 0____ 0____ 0____ ns
tHZ Output Hig h-Z Time (1,2) ____ 15 ____ 15 ____ 20 ns
tPU Chip Enable to Power Up Time (2 ) 0____ 0____ 0____ ns
tPD Chi p Dis able to Power Do wn Time (2 ) ____ 20 ____ 25 ____ 35 ns
2720 tbl 09a
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
READ CYCLE
tRC Read Cycle Time 45 ____ 55 ____ 70 ____ ns
tAA Address Access Time ____ 45 ____ 55 ____ 70 ns
tACE Chip Enable Access Time ____ 45 ____ 55 ____ 70 ns
tAOE Output Enable Access Time ____ 25 ____ 30 ____ 40 ns
tOH Output Hold from Address Change 0 ____ 0____ 0____ ns
tLZ Output Low-Z Time (1,2) 5____ 5____ 5____ ns
tHZ Output Hig h-Z Time (1,2) ____ 20 ____ 25 ____ 30 ns
tPU Chip Enable to Power Up Time (2) 0____ 0____ 0____ ns
tPD Chi p Disable to Po wer Do wn Time (2) ____ 45 ____ 50 ____ 50 ns
2720 tbl 09b
7
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1,2,4)
Timing Waveform of Read Cycle No. 2, Either Side(1,3)
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH.
4. Start of valid data depends on which timing becomes effective, tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
ADDRESS
DATAOUT PREVIOUS DATA VALID DATA VALID
tOH
tOH tAA(5)
tRC
2720 drw 08
2720 drw 09
CE
DATAOUT VALID DATA(4)
tPD
tAOE(4)
tACE
OE
tHZ(2)
tLZ(1)
tLZ(1)
tPU
50%50%
ICC
ISB
CURRENT
tHZ(2)
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
8
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5,7)
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to Timing Waveform of Write with Port-to-Port Read.
5. 'X' in part number indicates power rating (SA or LA).
6. tDDD = 35ns for military temperature range.
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
Symbol Parameter
7134X20
Com'l Only
7134X25
Com'l &
Military
7134X35
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max.
WRI TE CYCLE
tWC Write Cycle Time 20 ____ 25 ____ 35 ____ ns
tEW Chip Enable to End-of-Write 15 ____ 20 ____ 30 ____ ns
tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ ns
tAS Address Set-up Time 0 ____ 0____ 0____ ns
tWP Write Pulse Width 15 ____ 20 ____ 25 ____ ns
tWR Write Recovery Time 0 ____ 0____ 0____ ns
tDW Data Valid to End-of-Write 15 ____ 15 ____ 20 ____ ns
tHZ Output High-Z Time(1,2) ____ 15 ____ 15 ____ 20 ns
tDH Data Hold Time(3 ) 0____ 0____ 3____ ns
tWZ Write Enable to Output in High-Z(1,2) ____ 15 ____ 15 ____ 20 ns
tOW Output Active from End-of-Write(1 , 2 ,3 ) 3____ 3____ 3____ ns
tWDD Write Pulse to Data Delay(4) ____ 40 ____ 50 ____ 60 ns
tDDD Write Data Valid to Re ad Data De lay (4,6) ____ 30 ____ 30 ____ 35 ns
2720 tbl 10a
Symbol Parameter
7134X45
Com'l &
Military
7134X55
Com'l, Ind
& Military
7134X70
Com'l &
Military
UnitMin. Max. Min. Max. Min. Max.
WRI TE CYCLE
tWC Write Cycle Time 45 ____ 55 ____ 70 ____ ns
tEW Chip Enable to End-of-Write 40 ____ 50 ____ 60 ____ ns
tAW Address Valid to End-of-Write 40 ____ 50 ____ 60 ____ ns
tAS Address Set-up Time 0 ____ 0____ 0____ ns
tWP Write Pulse Width 40 ____ 50 ____ 60 ____ ns
tWR Write Recovery Time 0 ____ 0____ 0____ ns
tDW Data Valid to End-of-Write 20 ____ 25 ____ 30 ____ ns
tHZ Output High-Z Time(1,2) ____ 20 ____ 25 ____ 30 ns
tDH Data Hold Time(3 ) 3____ 3____ 3____ ns
tWZ Write Enable to Output in High-Z(1,2) ____ 20 ____ 25 ____ 30 ns
tOW Output Active from End-of-Write(1 , 2 ,3 ) 3____ 3____ 3____ ns
tWDD Write Pulse to Data Delay(4) ____ 70 ____ 80 ____ 90 ns
tDDD Write Data Valid to Read Data Delay(4,6) ____ 45 ____ 55 ____ 70 ns
2720 tbl 1 0b
9
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
2720 drw 10
R/W"A"(1)
VALID
tWC
MATCH
VALID
MATCH
tWP
tDW
tWDD
tDDD
ADDR "A"
DATAIN "A"
DATAOUT "B"
ADDR "B"
tAW
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
Timing Waveform of Write with Port-to-Port Read(1,2,3)
NOTES:
1. Write cycle parameters should be adhered to, in order to ensure proper writing.
2. CEL = CER = VIL. OE"B" = VIL.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going to VIH to the end-of-write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +500mV from steady state with the Output Test Load
(Figure 2).
8. If OE = VIL during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus
for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
CE
2720 drw 11
tAW
tAS(6)
tDW
DATAIN
ADDRESS
tWC
R/W
tWP
DATAOUT
tWZ(7)
(4) (4)
(2)
OE
tHZ(7)
tLZ
(7)
tHZ
tWR(3)
(7)
tDH
tOW
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
10
Truth Table I Read/Write Control
Functional Description
The IDT7134 provides two ports with separate control, address,
and I/O pins that permit independent access for reads or writes to any
location in memory. These devices have an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Each port has its own Output Enable
control (OE). In the read mode, the ports OE turns on the output drivers
when set LOW. Non-contention READ/WRITE conditions are illustrated
in the table below.
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,4)
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end-of-write cycle.
4. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
5. Timing depends on which enable signal (CE or R/W) is asserted last.
NOTE:
1. A0L - A11L ≠ A0R - A11R
"H" = VIH, "L" = VIL, "X" = Dont Care, and "Z" = High Impedance
Left or Right Port(1)
R/WCE OE D0-7 Function
X H X Z Port Deselected and in Power-Down
Mode, ISB2 or ISB4
XHX Z CE
R = CE
L = H, Power Down
Mode ISB1 or ISB3
LLX DATA
IN Data o n po rt written into memory
HLLDATA
OUT Data in memory output on port
X X H Z High impedance outputs
2720 tbl 11
2720 drw 12
R/W
tWC
ADDRESS
DATAIN
CE
tDW
tWR(3)
tDH
tEW(2)
tAW
tAS(5)
11
IDT7134SA/LA
High-Speed 4K x 8 Dual-Port Static SRAM Military, Industrial and Commercial Temperature Ranges
Ordering Information
2720 drw 13
IDT XXXX A 999 A A
Device Type Power Speed Package Process/
Temperature
Range
Blank
I(1)
B
P
C
J
L48
F
20
25
35
45
55
70
LA
SA
7134
Commercial (0°Cto+70
°C)
Industrial (-40°Cto+85
°C)
Military (-55°Cto+125
°C)
Compliant to MIL-PRF-38535 QML
48-pin Plastic DIP (P48-1)
48-pin Ceramic DIP (C48-2)
52-pin PLCC (J52-1)
48-pin LCC (L48-1)
48-pin Ceramic Flatpack (F48-1)
Speed in nanoseconds
Low Power
Standard Power
32K (4K x 8-Bit) Dual-Port RAM
Commercial Only
Commercial & Military
Commercial & Military
Commercial & Military
Commercial, Industrial & Military
Commercial & Military
NOTE:
1. Industrial temperature is available for PLCC packages in standard power.
For other speeds, packages and powers contact your sales office.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
2975 Stender Way 800-345-7015 or 408-727-5166 831-754-4613
Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
3/25/99 Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Pages 2 Added additional notes to pin configurations
6/9/99: Changed drawing format
