Vishay Siliconix
DG417, DG418, DG419
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
www.vishay.com
1
Precision CMOS Analog Switches
FEATURES
• ± 15 V analog signal range
• On-resistance - RDS(on): 20
• Fast switching action - tON: 100 ns
• Ultra low power requirements - PD: 35 nW
• TTL and CMOS compatible
• MiniDIP and SOIC packaging
• 44 V supply max. rating
• 44 V supply max. rating
• Compliant to RoHS directive 2002/95/EC
BENEFITS
• Wide dynamic range
• Low signal errors and distortion
• Break-before-make switching action
• Simple interfacing
• Reduced board space
• Improved reliability
APPLICATIONS
• Precision test equipment
• Precision instrumentation
• Battery powered systems
• Sample-and-hold circuits
• Military radios
• Guidance and control systems
• Hard disk drives
DESCRIPTION
The DG417, DG418, DG419 monolithic CMOS analog
switches were designed to provide high performance
switching of analog signals. Combining low power, low
leakages, high speed, low on-resistance and small physical
size, the DG417 series is ideally suited for portable and
battery powered industrial and military applications requiring
high performance and efficient use of board space.
To achieve high-voltage ratings and superior switching
performance, the DG417 series is built on Vishay Siliconix’s
high voltage silicon gate (HVSG) process. Break-before-
make is guaranteed for the DG419, which is an SPDT
configuration. An epitaxial layer prevents latchup.
Each switch conducts equally well in both directions when
on, and blocks up to the power supply level when off.
The DG417 and DG418 respond to opposite control logic
levels as shown in the Truth Table.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Logic "0" 0.8 V
Logic "1" 2.4 V
Logic "0" 0.8 V
Logic "1" 2.4 V
* Pb containing terminations are not RoHS compliant, exemptions may apply
1
Dual-In-Line and SOIC
S D
NC V-
GND IN
V+ VL
2
3
4
8
7
6
5
Top View
DG417
TRUTH TABLE
Logic DG417 DG418
0 ON OFF
1OFFON
1
Dual-In-Line and SOIC
D S2
S1V-
GND IN
V+ VL
2
3
4
8
7
6
5
Top View
DG419
TRUTH TABLE DG419
Logic SW1SW2
0 ON OFF
1OFFON
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2
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
Vishay Siliconix
DG417, DG418, DG419
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 6 mW/°C above 75 °C.
d. Derate 6.5 mW/°C above 75 °C.
e. Derate 12 mW/°C above 75 °C.
ORDERING INFORMATION
Temp. Range Package Part Number
DG417, DG418
- 40 °C to 85 °C
8-Pin Plastic MiniDIP
DG417DJ
DG417DJ-E3
DG418DJ
DG418DJ-E3
8-Pin Narrow SOIC
DG417DY
DG417DY-E3
DG417DY-T1
DG417DY-T1-E3
DG418DY
DG418DY-E3
DG418DY-T1
DG418DY-T1-E3
DG419
- 40 °C to 85 °C
8-Pin Plastic MiniDIP DG419DJ
DG419DJ-E3
8-Pin Narrow SOIC
DG419DY
DG419DY-E3
DG419DY-T1
DG419DY-T1-E3
ABSOLUTE MAXIMUM RATINGS
Parameter (Voltages referenced to V-) Limit Unit
V+ 44
V
GND 25
VL(GND - 0.3) to (V+) + 0.3
Digital Inputsa, VS, VD
(V-) - 2 to (V+) + 2
or 30 mA, whichever occurs first
Current , (Any Terminal) Continuous 30 mA
Current, S or D (Pulsed at 1 ms, 10 % Duty Cycle) 100
Storage Temperature (AK Suffix) - 65 to 150 °C
(DJ, DY Suffix) - 65 to 125
Power Dissipation (Package)b
8-Pin Plastic MiniDIPc400
mW
8-Pin Narrow SOICd400
8-Pin CerDIPe600
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
www.vishay.com
3
Vishay Siliconix
DG417, DG418, DG419
SCHEMATIC DIAGRAM Typical Channel
Figure 1.
SPECIFICATIONSa
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V
VL = 5 V, VIN = 2.4 V, 0.8 VfTemp.b Typ.c
A Suffix
- 55 °C to 125 °C
D Suffix
- 40 °C to 85 °C
Unit Min.d Max.dMin.d Max.d
Analog Switch
Analog Signal RangeeVANALOG Full - 15 15 - 15 15 V
Drain-Source
On-Resistance RDS(on)
IS = - 10 mA, VD = ± 12.5 V
V+ = 13.5 V, V- = - 13.5 V
Room
Full
20 35
45
35
45
Switch Off Leakage
Current
IS(off)
V+ = 16.5, V- = - 16.5 V
VD = ± 15.5 V
VS = ± 15.5 V
Room
Full
- 0.1 - 0.25
- 20
0.25
20
- 0.25
- 5
0.25
5
nA
ID(off)
DG417
DG418
Room
Full
- 0.1 - 0.25
- 20
0.25
20
- 0.25
- 5
0.25
5
DG419 Room
Full
- 0.1 - 0.75
- 60
0.75
60
- 0.75
- 12
0.75
12
Channel Off Leakage
Current ID(on)
V+ = 16.5 V, V- = - 16.5 V
VS = VD = ± 15.5 V
DG417
DG418
Room
Full
- 0.4 - 0.4
- 40
0.4
40
- 0.4
- 10
0.4
10
DG419 Room
Full
- 0.4 - 0.75
- 60
0.75
60
- 0.75
- 12
0.75
12
Digital Control
Input Current VIN Low IIL Full 0.005 - 0.5 0.5 - 0.5 0.5 µA
Input Current VIN High IIH Full 0.005 - 0.5 0.5 - 0.5 0.5
Dynamic Characteristics
Tu r n - O n T ime tON RL = 300 , CL = 35 pF
VS = ± 10 V
See Switching Time
Test Ci r c u it
DG417
DG418
Room
Full
100 175
250
175
250
ns
Turn-Off Time tOFF DG417
DG418
Room
Full
60 145
210
145
210
Transition Time tTRANS
RL = 300 , CL = 35 pF
VS1 = ± 10 V, VS2 = ± 10 V DG419 Room
Full
175
250
175
250
Break-Before-Make
Time Delay (DG403) tD
RL = 300 , CL = 35 pF
VS1 = VS2 = ± 10 V DG419 Room 13 5 5
Charge Injection Q CL = 10 nF, Vgen = 0 V, Rgen = 0 Room 60 pC
Level
Shift/
Drive
VIN
VL
S
V+
GND
V-
D
V-
V+
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Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
Vishay Siliconix
DG417, DG418, DG419
Notes:
a. Refer to Process Option Flowchart.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V
VL = 5 V, VIN = 2.4 V, 0.8 VfTemp.b Typ.c
A Suffix
- 55 °C to 125 °C
D Suffix
- 40 °C to 85 °C
Unit Min.d Max.dMin.d Max.d
Dynamic Characteristics
Source Off
Capacitance CS(off)
f = 1 MHz, VS = 0 V
Room 8
pF
Drain Off Capacitance CD(off) DG417
DG418 Room 8
Channel On
Capacitance CD(on) f = 1 MHz, VS = 0 V
DG417
DG418 Room 30
DG419 Room 35
Power Supplies
Positive Supply Current I+
V+ = 16.5 V, V- = - 16.5 V
VIN = 0 or 5 V
Room
Full
0.001 1
5
1
5
µA
Negative Supply
Current I- Room
Full
- 0.001 - 1
- 5
- 1
- 5
Logic Supply Current ILRoom
Full
0.001 1
5
1
5
Ground Current IGND Room
Full
- 0.0001 - 1
- 5
- 1
- 5
SPECIFICATIONSa for Unipolar Supplies
Parameter Symbol
Test Conditions
Unless Otherwise Specified
V+ = 12 V, V- = 0 V
VL = 5 V, VIN = 2.4 V, 0.8 VfTemp.b Typ.c
A Suffix
- 55 °C to 125 °C
D Suffix
- 40 °C to 85 °C
Unit Min.d Max.dMin.d Max.d
Analog Switch
Analog Signal RangeeVANALOG Full 012012V
Drain-Source
On-Resistance RDS(on)
IS = - 10 mA, VD = 3.8 V
V+ = 10.8 V Room 40
Dynamic Characteristics
Tur n -On Ti m e tON RL = 300 , CL = 35 pF, VS = 8 V
See Switching Time Test Circuit
Room 110
ns
Tur n -Off Ti m e tOFF Room 40
Break-Before-Make
Time Delay tD
DG419 Only
RL = 300 , CL = 35 pF Room 60
Charge Injection Q CL = 10 nF, Vgen = 0 V, Rgen = 0 Room 5 pC
Power Supplies
Positive Supply
Current I+
V+ = 13.2 V, VL = 5.25 V
VIN = 0 or 5 V
Room 0.001
µA
Negative Supply
Current I- Room - 0.001
Logic Supply
Current ILRoom 0.001
Ground
Current IGND Room - 0.001
SPECIFICATIONSa
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
www.vishay.com
5
Vishay Siliconix
DG417, DG418, DG419
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
RDS(on) vs. VD and Supply Voltage
Leakage Currents vs. Analog Voltage
RDS(on) ()
5
0
40
30
0
- 20 - 15 20
20
10
- 10 - 5 5 1 5
10 0
I
D
= - 10 mA
± 10 V
± 15 V
± 20 V
± 12 V
± 8 V
± 5 V
V
D
- Drain Voltage (V)
I (pA)
30
20
- 30
- 15 - 10 15
10
0
- 5 0 5 10
- 10
- 20
V+ = 15 V
V- = - 15 V
V
L
= 5 V
DG417/418: I
D(of f)
, I
S( of f)
DG419: IS(off)
DG417/418: I
D(on)
DG419: ID(off), ID(on)
VD or VS - Drain or Source Voltage (V)
RDS(on) vs. Temperature
Drain Charge Injection
RDS(on) ()
40
30
0
- 15 - 10 15
20
- 5 0 5 10
10
25 °C
- 55 °C
T
A
= 125 °C
VD - Drain Voltage (V)
Q (pC)
200
150
100
- 50
- 15 - 10 15
50
0
- 5 0 5 10
100 pF
500 pF
1 nF
V+ = 16.5 V
V- = - 16.5 V
V
L
= 5 V
V
IN
= 0 V
CL = 10 nF
VS - Source Voltage (V)
Input Switching Threshold vs. Supply Voltages
(V)
TH
V
3.5
3.0
2.5
0
510 40
2.0
1.5
1.0
0.5
15 20 25 30 35
(V+)
VL = 5 V
VL = 7 V
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Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
Vishay Siliconix
DG417, DG418, DG419
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Switching Time vs. Temperature
Switching Time vs. Supply Voltages
Power Supply Currents vs. Switching Frequency
Temperature (°C)
tON (ns) , t OFF
120
100
80
20
0
- 55 - 40 - 20 0 2 0 4 0 6 0 8 0 100 120
40
60
V+ = 15 V , V- = - 15 V
V
L
= 5 V , V
IN
= 3 V Pulse
t
OFF
t
ON
± 10 ± 11 ± 12 ± 13 ± 14 ± 15 ± 16
80
70
60
50
40
V- = 0 V
V
L
= 5 V
V
IN
= 3 V
t
OFF
t
ON
Supply V oltage (V)
tON (ns) , t OFF
f - Frequency (Hz)
100 10 k 1M 10M
V+ = 15 V, V- = - 15 V
V
L
= 5 V , V
IN
= 5 V , 50 % D-Cycle
I+, I-
I
L
10 m
1 mA
100 µA
10 µA
1 µA
100 nA
ISUPPLY
1 k 100 k
Crosstalk and Off Isolation vs. Frequency
Switching Time vs. V+
Supply Current vs. Temperature
f - Frequency (Hz)
(dB)
100
140
120
100
0
80
60
40
20
DG417/418/419
Source 2
DG419
Source 1
10 k 1 M 100M
V+ = 15 V
V- = - 15 V
V
L
= 5 V
1 k 100 k 10M
tON (ns), t OFF
130
120
100
50
30
10 1 1 12 13 14 15 16
11 0
90
40
60
80
70
V- = 0 V
V
L
= 5 V
V
IN
= 3 V
tOFF
tON
V+ Supply V oltage (V)
ISUPPLY
Temperature (°C)
- 55 - 40 120
100 nA
10 nA
1 nA
0.1 pA
100 pA
10 pA
1 pA
- 20 0 2 0 4 0 6 0 8 0 100
I+, I-
1 µA
V+ = 16.5 V, V- = - 16.5 V
V
L
= 5 V , V
IN
= 0 V
I
GND
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
www.vishay.com
7
Vishay Siliconix
DG417, DG418, DG419
TEST CIRCUITS
VO is the steady state output with the switch on.
Figure 2. Switching Time (DG417, DG418)
C
L
(includes fixture and stray capacitance)
R
L
R
L
+ r
DS(on)
V
O
= V
S
V-
IN
S D
C
L
35 pF
- 15 V
V
L
GND
V
O
± 10 V
V+
R
L
300
+ 15 V + 5 V
0 V
Logic
Input
Switch
Input
Switch
Output
3 V
50 %
0 V
V
O
V
S
t
r
< 20 ns
t
f
< 20 ns
t
OFF
t
ON
90 %
Note: Logic input waveform is inverted for switches that have the
opposite logic sense.
Figure 3. Break-Before-Make (DG419)
IN
VL
VS1
D
V-
VS2
S2
V+
S1
- 15 V
GND
+ 15 V+ 5 V
CL
35 pF
VO
RL
300
CL (includes fixture and stray capacitance)
0 V
3 V
0 V
Logic
Input
Switch
Output
VO
VS1 = VS2
tr < 20 ns
tf < 20 ns
90 %
tDtD
Figure 4. Transition Time (DG419)
CL (includes fixture and stray capacitance)
VL
RL
RL + rDS(on)
VO = VS
V-
V+
IN
CL
35 pF
RL
300
DVO
S2
S1
VS2
VS1
- 15 V
GND
+ 15 V+ 5 V
0 V
3 V
50 %
Logic
Input
Switch
Output
VS1
tr < 20 ns
tf < 20 ns
10 %
tTRANS
90 %
V01
VS2
V02
tTRANS
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Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
Vishay Siliconix
DG417, DG418, DG419
TEST CIRCUITS
Figure 5. Charge Injection
CL
10 nF
D
Rg
VO
V+
S
V-
3 V
IN
VL
- 15 V
GND
- 15 V+ 5 V
OFFONOFF
VO
VO
INX
Q = VO x CL
Figure 6. Crosstalk (DG419)
Rg = 50
IN
0.8 V
VLV+
V-
XTA L K Isolation = 20 log
VS
VO
GND
S2
VS
VO
S1
RL
D
C = RF bypass
50
+ 15 V
- 15 V
C
C
+ 5 V
C
Figure 7. Off Isolation
V+
S
VL
Rg = 50
D
- 15 V
VS
GND V- C
RL
IN
VO
0 V, 2.4 V
Off Isolation = 20 log
VS
VO
+ 5 V
C
+ 15 V
C
Figure 8. Insertion Loss
S
V
S
V
O
0 V, 2.4 V
IN R
L
V
L
D
R
g
= 50
+ 5 V
- 15 V
GND V- C
C
+ 15 V
V+
C
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
www.vishay.com
9
Vishay Siliconix
DG417, DG418, DG419
TEST CIRCUITS
APPLICATIONS
Switched Signal Powers Analog Switch
The analog switch in Figure 10 derives power from its input
signal, provided the input signal amplitude exceeds 4 V and
its frequency exceeds 1 kHz.
This circuit is useful when signals have to be routed to either
of two remote loads. Only three conductors are required: one
for the signal to be switched, one for the control signal and a
common return.
A positive input pulse turns on the clamping diode D1 and
charges C1. The charge stored on C1 is used to power the
chip; operation is satisfactory because the switch requires
less than 1 µA of stand-by supply current. Loading of the
signal source is imperceptible. The DG419’s on-resistance is
a low 100 for a 5 V input signal.
Figure 9. Source/Drain Capacitances
VL
IN
S
V+
D
f = 1 MHz
- 15 V
GND V- C
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
+ 5 V
C
+ 15 V
C
D2D1
S1
f = 1 MHz
+ 15 V
IN
S2
NC
GND
V+
C
C
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
DG417/418 DG419
VL
IN
S
D
f = 1 MHz
GND C
0 V, 2.4 V
CC
D2D1
S1
f = 1 MHz
IN
S2
NC
- 15 V
GND
V+
V-
C
C
0 V, 2.4 V
Meter
HP4192A
Impedance
Analyzer
or Equivalent
Figure 10. Switched Signal Powers Remote SPDT Analog Switch
Input
Control
GND
DG419
V-
C
1
0.01 µF
D
1
S
1
S
2
V
OUT
R
L1
10 k
R
L2
10 k
V
L
D
IN
V+
www.vishay.com
10
Document Number: 70051
S10-1528-Rev. G, 19-Jul-10
Vishay Siliconix
DG417, DG418, DG419
APPLICATIONS
Micropower UPS Transfer Switch
When VCC drops to 3.3 V, the DG417 changes states,
closing SW1 and connecting the backup cell, as shown in
Figure 10. D1 prevents current from leaking back towards the
rest of the circuit. Current consumption by the CMOS analog
switch is around 100 pA; this ensures that most of the power
available is applied to the memory, where it is really needed.
In the stand-by mode, hundreds of A are sufficient to retain
memory data.
When the 5 V supply comes back up, the resistor divider
senses the presence of at least 3.5 V, and causes a new
change of state in the analog switch, restoring normal
operation.
Programmable Gain Amplifier
The DG419, as shown in figure 11, allows accurate gain
selection in a small package. Switching into virtual ground
reduces distortion caused by RDS(on) variation as a function
of analog signal amplitude.
GaAs FET Driver
The DG419, as shown in figure 12 may be used as a GaAs
FET driver. It translates a TTL control signal into - 8 V, 0 V
level outputs to drive the gate.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70051.
Figure 11. Micropower UPS Circuit
GND
IN
D
V-
3 V Li Cell
Memory DG417
(5 V)
V+
S
+
–
SW1
VL
VSENSE
R1
453 k
D1
VCC
R2
383 k
Figure 12. Programmable Gain Amplifier
DG419
+
-
IN
R1
R2
VIN
VOUT
D
S1
S2
Figure 13. GaAs FET Driver
DG419
5 V
VOUT
D
V-GND
S2
S1
VLV+
+ 5 V
- 8 V
GaAs FET
Vishay Siliconix
Package Information
Document Number: 71192
11-Sep-06
www.vishay.com
1
DIM
MILLIMETERS INCHES
Min Max Min Max
A 1.35 1.75 0.053 0.069
A10.10 0.20 0.004 0.008
B 0.35 0.51 0.014 0.020
C 0.19 0.25 0.0075 0.010
D 4.80 5.00 0.189 0.196
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.50 0.93 0.020 0.037
q0°8°0°8°
S 0.44 0.64 0.018 0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
4
3
12
5
6
87
HE
h x 45
C
All Leads
q0.101 mm
0.004"
L
BA
1
A
e
D
0.25 mm (Gage Plane)
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
S
Q1
A
L
A1
B
E1E
e1
B1
S
CeA
D
15°
MAX
1234
8765
NOTE: End leads may be half leads.
Package Information
Vishay Siliconix
Document Number: 71259
05-Jul-01 www.vishay.com
1
PDIP: 8ĆLEAD
MILLIMETERS INCHES
Dim Min Max Min Max
A3.81 5.08 0.150 0.200
A10.38 1.27 0.015 0.050
B0.38 0.51 0.015 0.020
B10.89 1.65 0.035 0.065
C0.20 0.30 0.008 0.012
D9.02 10.92 0.355 0.430
E7.62 8.26 0.300 0.325
E15.59 7.11 0.220 0.280
e12.29 2.79 0.090 0.110
eA7.37 7.87 0.290 0.310
L2.79 3.81 0.110 0.150
Q11.27 2.03 0.050 0.080
S0.76 1.65 0.030 0.065
ECN: S-03946—Rev. E, 09-Jul-01
DWG: 5478
E1E
Q1
A
L
A1
e1
BB1
L1
S
C
eA∝
D
1234
8765
Package Information
Vishay Siliconix
Document Number: 71280
03-Jul-01 www.vishay.com
1
CERDIP: 8ĆLEAD
MILLIMETERS INCHES
Dim Min Max Min Max
A4.06 5.08 0.160 0.200
A10.51 1.14 0.020 0.045
B0.38 0.51 0.015 0.020
B11.14 1.65 0.045 0.065
C0.20 0.30 0.008 0.012
D9.40 10.16 0.370 0.400
E7.62 8.26 0.300 0.325
E16.60 7.62 0.260 0.300
e12.54 BS C 0.100 BSC
eA7.62 BSC 0.300 BSC
L3.18 3.81 0.125 0.150
L13.18 5.08 0.150 0.200
Q11.27 2.16 0.050 0.085
S0.64 1.52 0.025 0.060
∝0°15°0°15°
ECN: S-03946—Rev. C, 09-Jul-01
DWG: 5348
VISHAY SILICONIX
TrenchFET® Power MOSFETs Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
APPLICATION NOTE
Document Number: 70740 www.vishay.com
Revision: 18-Jun-07 1
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a s ingle MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providin g the thermal connect ion
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
Figure 1. Single M O SFET SO-8 Pad
Pattern With Copper Spreading
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footpri nt with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
0.027
0.69
0.078
1.98
0.2
5.07
0.196
5.0
0.288
7.3
0.050
1.27
0.027
0.69
0.078
1.98
0.2
5.07
0.088
2.25
0.288
7.3
0.050
1.27
0.088
2.25
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72606
22 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SO-8
0.246
(6.248)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.172
(4.369)
0.152
(3.861)
0.047
(1.194)
0.028
(0.711)
0.050
(1.270)
0.022
(0.559)
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