ANALOG DEVICES LCM0S 8-Bit Sampling ADC AD7821 REV. B 1.1 Scope. This specification covers the detail requirement for a monolithic CMOS 8-bit sampling analog-to-digital converter. It features a conversion time of 660 ns and accepts unipolar or bipolar inputs. 1.2 Part Number. The complete part number per Table 1 of this specification is as follows: Device Part Number -1 AD7821T(X)/883B 1.2.3 Case Outline. See Appendix | of General Specification ADI-M-1000: package outline: (X) Package Description Q Q20 20-Pin Cerdip E E-20A 20-Contact LCC 1.3 Absolute Maximum Ratings. (T, = +25C) Vpp GND 2... cc ce enter e enn eee Vsg tOGND 22 tenet n eee Vin toGND 2.0... ce eee nce ete n en eee teee Veet) tOGND 2.0... eee ee een eta Veer(-) tOGND 2.00 eee eee Vin tOGND 2200 eee eee eee nee Digital Inputs to DGND ........00.0 0.2.0 eee eee eee Digital Outputs to DGND ... 0... eee eee Power Dissipation (to +75C) 2.0.0.0... 2 eee eee eee Derates above +75 0... ee ee eee eee Operating Temperature Range ...........-- 0.00. ee eee ene ene Storage Temperature . 0.0.2... cece eee eee eee Lead Temperature (Soldering 10 sec)... 2.6... 2.0... c eee ee ee 1.5 Thermal Characteristics. Thermal Resistance 6,_. = 35C/W for Q-20 and E-20A 8j, = 120C/W for Q-20 and E-20A Lecce seeees -0.3V,47V beeen eeees +0.3V,-7V .. Vg -0.3 V, Vpp +0.3 V .. Vgg -0.3 V, Vpp +0.3 V ... Vgg 0.3 V, Vpp +0.3 V _.. Veg 0.3 Vy Vpp +0.3 V be ceee -0.3 V, Vpp +03 V beeeee -0.3 V, Vpp +0.3 V Lice cence encase 450 mW boven ee eeeeceas 6 mW/C see eens +300C ANALOG-TO-DIGITAL CONVERTERS 6-139 ANALOG-TO-DIGITAL CONVERTERS aAD7821SPECIFICATIONS Table 1. Design Sub Sub Limit Group Group Test Symbol | Device | Tam-Tmax | 1 2,3 Test Condition ? Units Resolution RES -1 8 This Is the Minimum Resolu- Bits tion for Which No Missing Codes Are Guaranteed, Total Unadjusted Error? TUE -1 1 1 1 +LSB max Signal to Noise Ratio SNR -1 45 45 45 dB Total Harmonic Distortion THD -1 -50 50 -50 dB Peak Harmonic or Spurious Noise -1 30 30 30 dB Intermodulation Distortion Second Order IMD ~1 30 -30 30 dB Third Order ~1 50 -50 -50 dB Analog Input Leakage Current lin -1 3 3 3 +pA max Analog Input Capacitance Cc, -1 $5 pF typ Reference Input Resistance R, -1 1 1 1 kQ min 4 4 4 kO. max Digital Input High Level Vin -1 2.4 2.4 2.4 CS, WR, RD V min 3.5 3.5 3.5 Mode (Pin 7) Digital Input Low Level Vin -1 0.8 0.8 0.8 CS, WR, RD V max 1.5 1S 1.5 Mode (Pin 7) Digital Input High Current Ing -1 1.0 1.0 1.0 cs, RD pA max 3.0 3.0 3.0 WR 200.0 200.0 200.0 Mode (Pin 7) Digital Input Low Current Ii -1 1.0 1.0 1.0 CS, WR, RD, Mode (Pin 7) pA max Digital Input Capacitance Cc -1 8.0 CS, WR, RD, Mode (Pin 7) pF max Digital Ourput High Level Von -1 4.0 4.0 4.0 DBO-DB7, OFL, INT V min Tsource = 360 pA Digital Output Low Level Vor -1 0.4 0.4 0.4 DBO-DB7, OFL, INT Vv max Tgnk = 1.6 mA 0.4 RDY: Isink = 2.6 mA Floating State Leakage Current lout -1 3.0 3.0 3.0 DBO-DB7 pA max Digital Output Capacitance Cour ~-1 8.0 (Typically 5 pF) pF max Slew Rate Tracking -1 1.6 Typically 2.36 Vins Supply Current from Vpp Ipp -1 25 25 25 cS =RD=0V mA max Supply Current from Vg5 Iss -1 100 100 100 CS = RD=0V pA max Power Supply Sensitivity -1 1/4 1/4 1/4 Vpn = 5 V + 5% +LSB max CS to RD/WR Setup Time tes -1 0 ns min CS to RDAWR Hold Time ton -1 0 ns min CS to RDY Delay. Pull-Up Resistor 2 k* tapy ~1 100 70 ns max at +25C ns max Conversion Time (RD Mode) terp -1 975 700 ns max at +25C ns max Data Access Time (RD Mode)* tacco -1 terp +75 (torp +50) ns max at +25C ns max 6-140 ANALOG-TO-DIGITAL CONVERTERS REV. BAD7821 Design Sub Sub Limit Group Group Test Symbol | Device | Tain-Tmax | 1 2,3 Test Condition: ? Units RDB to INT Delay (RD Mode)* tera -1 90 80 ns max at +25C ns max Data Hold Time low -1 80 60 ns max at +25C ns max 15 15 ns min at +25C ns min Delay Time Between Conversions tp -1 500 350 ns min at + 25C ns min Write Pulse Width twr -1 400 ns min 10 250 ns min at +25C us max Delay Time Between WR and RD Pulses tap -1 450 250 ns min at +25C ns min Data Access Time* (WR/RD Mode, See Figure 4) acer -1 275 185 ns min at + 25C ns max RD to INT Delay tet -1 220 150 ns max at +25C ns max WR to INT Delay* Unt -1 700 500 ns max at +25C ns max Access Time (WR/RD Mode, See Figure 3) tacc2 -1 130 90 ns max at + 25C ns max WR to INT Delay (Stand- Alone Operation)* tuiwr -1 120 80 ns max at +25C ns max Data Access Time after INT (Stand-Alone Operation) up -1 70 45 ns max at +25C ms max NOTES Vop = +5 V3 Vres(+) = +5 V3 Vace() = GND = 0 V unless otherwise specified. Specifications apply for RD mode (Pin 7 = 0 V). 7All input control signals are specified with t, = t; = 20 ns (10% to 90% of +5 V) and timed from a voltage level of + 1.6 V. 3Includes gain error, offset error and linearity error. *C, = 50 pF. Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V. Defined as the time required for the data lines to changed 0.5 V when loaded with the circuits of Figure 2. 3k? DGND L a. High-Z to Vo, b. High-Z to Vo, 5Vv 3k 100pF See 100pF Figure 1. Load Circuits for Data Access Time Test REV. B OBN aka . L &@. Von to High-Z 5V wn 10pF See b. Vo, to High-Z Figure 2. Load Circuits for Data Hold Time Test ANALOG-TO-DIGITAL CONVERTERS 6-141AD7821 3.2.1 Functional Block Diagram and Terminal Assignments. Voo Vaerl +) Veeel-) (11 Vw (4 4-BIT FLASH ADC (4MsB) 4-BIT FLASH ADC (4LS8) TIMING AND CONTROL CIRCUITRY 7 6 OFL THREE DB0-DB7 STATE DATAOUT DRIVERS PINS 2-5, 14-17 AD7821 19) Vs5 GNO MODE WRRDY CS Q Package E Package (DIP) (LCC) M a8 2243 vw [ e 201 Voo a0 >>> 3 2 1 20 19 DBO | 2 3] Vss bei | 3 18] OF DB2 4 18 GFL OB2 | 4 7] DB7 (MSB) DB3 5 17 DB7(MSB} AD7821 DB3 | 5 AD7821 6] OB6 WRIRDY 6 TOP VIEW 16 DBE TOP VIEW (Not to Scale} wry [6] (Not to Scale) 15] pes MODE 7 1s DBs RD 8 14 OB4 MODE | 7 14] DB4 RD [ 8 13) cs _ 9 10 11 12 13 int [o 12] Vance +) gE 3 T z iB ots GND [7 | Vaer(-1 = 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (81). 6-142 ANALOG-TO-DIGITAL CONVERTERSAD7821 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). rhfftcc cc ct ccc rc ccc ccc ccd 7 | tie | etttrr rrr ccc rrr 1 ' VV T 250mA | iv tk 1 T I \ ww io eh {o-0}}+ ; I 1k oa I dy = I EI 19 rf | | ; ' ' ' Gl Fa] I : JL JL 2] [3] ' t ! ce 7] I 7] z ! i 1! El pore, | {E] motto seas fis] ; fe] topwew ff rm ' {Not to Scale) 1 | Lo ed Tek fe ! ' ~~ Ly Os 1 | We o) uw CI fe} a 1 ola fro] i amt [| TTL Lam - 1 | | ed I oy - 1 \ 5K1 ' n 1 AM LLL ee we +. th] LLL Ld 4 2x 100k 2x 100 1W 2x 120k Tt 2x We AIN C> ts-AD C> ov GND C+ e | $ $ -5V Vss CD. 5V Vpp > Ain (> Cs-RD > ov GND C>9 TEST POINTS TEST POINTS AD7821 Edge Connections ANALOG-TO-DIGITAL CONVERTERS a cs-RD | 1.ms MIN AIN = OV Static Burn-in Initialization em STLILILIULUL 50kHz, MAX AIN = +4.7V SINE @ 100Hz Dynamic Burn-in Signals REV. B ANALOG-TO-DIGITAL CONVERTERS 6-143AD7821 6-144 ANALOG-TO-DIGITAL CONVERTERS 6.0 Digital Interface. The AD7821 has two basic interface modes which are determined by the status of the MODE pin. When this pin is low, the converter is in the RD mode; with this pin high, the AD7821 is set up for the WR- RD mode. The RD mode is designed for microprocessors which can be driven into a WAIT state. A READ opera- tion (i.e., CS and RD are taken low) starts a conversion and data is read when the conversion is com- plete. The WR-RD mode does not require microprocessor WAIT states. A WRITE operation (i.e., CS and WR are taken low) initiates a conversion, and a READ operation reads the result when the conver- sion is complete. 6.1 RD Mode (MODE = 0). The timing diagram for the RD mode is shown in Figure 3. This mode is intended for use with micro- processors which have a WAIT state facility, whereby a READ instruction cycle can be extended to accommodate slow memory devices. A conversion is started by taking CS and RD low (READ opera- tion). Both CS and RD are then kept low until output data appears. In this mode, Pin 6 of the AD7821 is configured as a status output, RDY. This RDY output can be used to drive the processor READY or WAIT input. It is an open drain output (no internal pull-up device) which goes low after the falling edge of CS and goes high impedance at the end of conversion. An INT line is also provided which goes low when a conversion is complete. INT returns high on the rising edge of CS or RD. Figure 3. RD Mode 6.2 WR-RD Mode (MODE = 1). In the WR-RD mode, Pin 6 is configured as a WRITE (WR) input for the AD7821. With CS low, con- version is initiated on the falling edge of WR. Two options exist for reading data from the converter. In the first of these options the processor waits for the INT status line to go low before reading the data (see Figure 4). INT typically goes low within 380 ns after the rising edge of WR. It indicates that con- version is complete and that the data result is in the output latch. With CS low, the data outputs (DBO-DB7) are activated when RD goes low. INT is reset by the rising edge of RD or CS. REV. BREV. B AD7821_ | | we ee ee eee VALID 060-087 | DATA | tacc2 * fe ->| ton le Figure 4. WR-RD Mode (tap>tinri) The alternative option can be used to shorten the conversion time. This is a method for bypassing the internal time-out circuit. The INT line is ignored and RD can be brought low 250 ns after the rising edge of WR. In this case RD going low transfers the data result into the output latch and activates the data output (DBO-DB7). INT is driven low on the falling edge of RD and is reset on the rising edge of RD or CS. The timing for this interface is shown in Figure 5. s I Figure 5. WR-RD Mode (tan<tiwre! ANALOG-TO-DIGITAL CONVERTERS 6-145 ANALOG-TO-DIGITAL CONVERTERS aAD7821 . r tewe r - tan a Ke Figure 6. WR-RD Stand-Alone Operation, CS = RD = 0 The AD7821 can also be used in stand-alone operation in the WR-RD mode. CS and RD are tied low, and a conversion is initiated by bringing WR low. Output data is valid 530 ns (tpyr_ + typ) after the rising edge of WR. The timing diagram for this mode is shown in Figure 6. 6-146 ANALOG-TO-DIGITAL CONVERTERS REV. B