SL811HSTAXC - CYPRESS SEMICONDUCTOR

May, 2011 − Rev. 6

1Publication Order Number:

MC74VHC374/D

MC74VHC374

Octal D-Type Flip-Flop

with 3-State Output

The MC74VHC374 is an advanced high speed CMOS octal

flip−flip with 3−state output fabricated with silicon gate CMOS

technology. It achieves high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining CMOS low power

dissipation.

This 8−bit D−type flip−flop is controlled by a clock input and an

output enable input. When the output enable input is high, the eight

outputs are in a high impedance state.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output. The

inputs tolerate voltages up to 7V, allowing the interface of 5V systems

to 3V systems.

Features

•High Speed: fmax = 185 MHz (Typ) at VCC = 5 V

•Low Power Dissipation: ICC = 4 μA (Max) at TA = 25°C

•High Noise Immunity: VNIH = VNIL = 28% VCC

•Power Down Protection Provided on Inputs

•Balanced Propagation Delays

•Designed for 2 V to 5.5 V Operating Range

•Low Noise: VOLP = 0.9 V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300 mA

•ESD Performance: HBM > 2000 V; Machine Model > 200 V

•Chip Complexity: 266 FETs or 66.5 Equivalent Gates

•These Devices are Pb−Free and are RoHS Compliant

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20

1

20

MARKING DIAGRAMS

SOIC−20

DW SUFFIX

CASE 751D

VHC374

AWLYYWWG

TSSOP−20

DT SUFFIX

CASE 948E

SOEIAJ−20

M SUFFIX

CASE 967

VHC374

AWLYWWG

1

20

1

20

VHC374 = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

Y = Year

WW, W = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

VHC

374

ALYWG

G

ORDERING INFORMATION

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specification

Brochure, BRD8011/D.

Device Package Shipping†

MC74VHC374DWR2G SOIC−20 1000 Units/Reel

MC74VHC374DTR2G TSSOP−20 2500 Units/T&R

MC74VHC374MELG SOEIAJ−20 2000 Units/Reel

MC74VHC374

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Figure 1. LOGIC DIAGRAM

DATA

INPUTS

D0

D1

D2

D3

D4

D5

D6

D7 18

17

14

13

8

7

4

3

1

OE

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2

NONINVERTING

OUTPUTS

11

CP

OE CP Q

L

H

L, H,

X

H

L

No Change

Z

INPUTS OUTPUT

FUNCTION TABLE

D

H

L

X

Figure 2. PIN ASSIGNMENT

Q2

D1

D0

Q0

OE

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

VCC

CP

Q4

D4

D5

Q5

MC74VHC374

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

IIK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Diode Current

ÎÎÎÎÎ

− 20

ÎÎÎ

mA

ÎÎÎÎ

IOK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Diode Current

ÎÎÎÎÎ

±20

ÎÎÎ

mA

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±75

ÎÎÎ

mA

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, SOIC Packages†

TSSOP Package†

ÎÎÎÎÎ

500

450

ÎÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_C

* Absolute maximum continuous ratings are those values beyond which damage to the device

may occur. Exposure to these conditions or conditions beyond those indicated may

adversely affect device reliability. Functional operation under absolute−maximum−rated

conditions is not implied.

†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎ

2.0

ÎÎ

5.5

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎ

0

ÎÎ

5.5

ÎÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage

ÎÎÎ

0

ÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature

ÎÎÎ

− 40

ÎÎ

+ 85

ÎÎÎ

_C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 3.3V

VCC = 5.0V

ÎÎÎ

0

ÎÎ

100

20

ÎÎÎ

ns/V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎ

Unit

ÎÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎ

Minimum High−Level

Input Voltage

ÎÎÎÎÎÎÎ

ÎÎÎ

2.0

3.0 to

5.5

ÎÎÎÎ

1.50

VCC x 0.7

ÎÎÎ

ÎÎÎÎ

1.50

VCC x 0.7

ÎÎÎÎ

ÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎ

Maximum Low−Level

Input Voltage

ÎÎÎÎÎÎÎ

ÎÎÎ

2.0

3.0 to

5.5

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

0.50

VCC x 0.3

ÎÎÎÎ

0.50

VCC x 0.3

ÎÎ

V

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎ

Minimum High−Level

Output Voltage

ÎÎÎÎÎÎÎ

Vin = VIH or VIL

IOH = − 50μA

ÎÎÎ

2.0

3.0

4.5

ÎÎÎÎ

1.9

2.9

4.4

ÎÎÎ

2.0

3.0

4.5

ÎÎÎÎ

1.9

2.9

4.4

ÎÎÎÎ

ÎÎ

V

ÎÎÎÎÎÎÎ

Vin = VIH or VIL

IOH = − 4mA

IOH = − 8mA

ÎÎÎ

3.0

4.5

ÎÎÎÎ

2.58

3.94

ÎÎÎ

ÎÎÎÎ

2.48

3.80

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎ

Maximum Low−Level

Output Voltage

ÎÎÎÎÎÎÎ

Vin = VIH or VIL

IOL = 50μA

ÎÎÎ

2.0

3.0

4.5

ÎÎÎÎ

ÎÎÎ

0.0

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎ

V

ÎÎÎÎÎÎÎ

Vin = VIH or VIL

IOL = 4mA

IOL = 8mA

ÎÎÎ

3.0

4.5

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

0.36

ÎÎÎÎ

0.44

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74VHC374

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎ

Unit

ÎÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎ

Unit

ÎÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎ

Typ

ÎÎÎÎ

Min

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎ

Maximum Input

Leakage Current

ÎÎÎÎÎÎÎ

Vin = 5.5V or GND

ÎÎÎ

0 to 5.5

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

±0.1

ÎÎÎÎ

±1.0

ÎÎ

μA

ÎÎÎÎ

IOZ

ÎÎÎÎÎÎÎ

Maximum

Three−State Leakage

Current

ÎÎÎÎÎÎÎ

Vin = VIL or VIH

Vout = VCC or GND

ÎÎÎ

5.5

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

±0.25

ÎÎÎÎ

±2.5

ÎÎ

μA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎ

Maximum Quiescent

Supply Current

ÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

5.5

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

4.0

ÎÎÎÎ

40.0

ÎÎ

μA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎ

Unit

ÎÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency

(50% Duty Cycle)

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3V CL = 15pF

CL = 50pF

ÎÎÎÎ

80

55

ÎÎÎ

130

85

ÎÎÎÎ

ÎÎÎ

70

50

ÎÎÎÎ

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎÎÎ

130

85

ÎÎÎ

185

120

ÎÎÎÎ

ÎÎÎ

110

75

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay,

CP to Q

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3V CL = 15pF

CL = 50pF

ÎÎÎÎ

ÎÎÎ

8.1

10.6

ÎÎÎÎ

12.7

16.2

ÎÎÎ

1.0

ÎÎÎÎ

15.0

18.5

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎÎÎ

ÎÎÎ

5.4

6.9

ÎÎÎÎ

8.1

10.1

ÎÎÎ

1.0

ÎÎÎÎ

9.5

11.5

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎ

Output Enable Time,

OE to Q

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3V CL = 15pF

RL = 1kΩCL = 50pF

ÎÎÎÎ

ÎÎÎ

7.1

9.6

ÎÎÎÎ

11.0

14.5

ÎÎÎ

1.0

ÎÎÎÎ

13.0

16.5

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

RL = 1kΩCL = 50pF

ÎÎÎÎ

ÎÎÎ

5.1

6.6

ÎÎÎÎ

7.6

9.6

ÎÎÎ

1.0

ÎÎÎÎ

9.0

11.0

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎ

Output Disable Time,

OE to Q

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3V CL = 50pF

RL = 1kΩ

ÎÎÎÎ

ÎÎÎ

10.2

ÎÎÎÎ

14.0

ÎÎÎ

1.0

ÎÎÎÎ

16.0

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 50pF

RL = 1kΩ

ÎÎÎÎ

ÎÎÎ

6.1

ÎÎÎÎ

8.8

ÎÎÎ

1.0

ÎÎÎÎ

10.0

ÎÎÎÎ

tOSLH,

tOSHL

ÎÎÎÎÎÎÎÎÎ

Output to Output Skew

ÎÎÎÎÎÎÎÎ

VCC = 3.3 ± 0.3V CL = 50pF

(Note 1)

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

1.5

ÎÎÎ

ÎÎÎÎ

1.5

ÎÎ

ns

ÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 50pF

(Note 1)

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

1.0

ÎÎÎ

ÎÎÎÎ

1.0

ÎÎ

ns

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

ÎÎÎ

4

ÎÎÎÎ

10

ÎÎÎ

ÎÎÎÎ

10

ÎÎ

pF

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎÎÎ

Maximum Three−State Output

Capacitance (Output in

High−Impedance State)

ÎÎÎÎÎÎÎÎ

ÎÎÎÎ

ÎÎÎ

6

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎ

pF

CPD Power Dissipation Capacitance (Note 2)

Typical @ 25°C, VCC = 5.0V

pF

32

1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC /8 (per flip−flop). CPD is used to determine the

no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

MC74VHC374

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NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)

Symbol Parameter

TA = 25°C

Unit

Typ Max

VOLP Quiet Output Maximum Dynamic VOL 0.6 0.9 V

VOLV Quiet Output Minimum Dynamic VOL − 0.6 − 0.9 V

VIHD Minimum High Level Dynamic Input Voltage 3.5 V

VILD Maximum Low Level Dynamic Input Voltage 1.5 V

TIMING REQUIREMENTS (Input tr = tf = 3.0ns)

Symbol Parameter Test Conditions

TA = 25°C

TA = − 40

to 85°C

Unit

Typ Limit Limit

twMinimum Pulse Width, CP VCC = 3.3 ± 0.3 V

VCC = 5.0 ± 0.5 V

5.0

5.5

5.0

ns

tsu Minimum Setup Time, D to CP VCC = 3.3 ± 0.3 V

VCC = 5.0 ± 0.5 V

4.5

3.0

4.5

3.0

ns

thMinimum Hold Time, D to CP VCC = 3.3 ± 0.3 V

VCC = 5.0 ± 0.5 V

2.0

ns

tr, tfMaximum Input Rise and Fall Times VCC = 3.3 ± 0.3 V

VCC = 5.0 ± 0.5 V

ns

SWITCHING WAVEFORMS

Figure 3.

VCC

GND

50% VCC

50%

CP

tPLH tPHL

Q

tW

1/fmax

50%

50% VCC

OE

Q

tPZL tPLZ

tPZH tPHZ

VCC

GND

HIGH

IMPEDANCE

VOL +0.3V

VOH -0.3V

HIGH

IMPEDANCE

50%

D

CP

VCC

GND

VALID

th

tsu

50%

Q

Figure 4.

Figure 5.

MC74VHC374

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6

TEST CIRCUITS

Figure 6.

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 kΩ

Figure 7.

Figure 8. EXPANDED LOGIC DIAGRAM

D0

3

DQ

C

Q0

2

D1

4

DQ

C

Q1

5

D2

7

DQ

C

Q2

6

D3

8

DQ

C

Q3

9

D4

13

DQ

C

Q4

12

D5

14

DQ

C

Q5

15

D6

17

DQ

C

Q6

16

D7

18

DQ

C

Q7

19

CP

OE

11

1

Figure 9. INPUT EQUIVALENT CIRCUIT

INPUT

MC74VHC374

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7

PACKAGE DIMENSIONS

SOIC−20

DW SUFFIX

CASE 751D−05

ISSUE G

20

1

11

10

B20X

H10X

C

L

18X A1

A

SEATING

PLANE

q

hX 45_

E

D

M

0.25 M

B

M

0.25 S

AS

B

T

eT

B

A

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

__

MC74VHC374

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PACKAGE DIMENSIONS

TSSOP−20

CASE 948E−02

ISSUE C

DIM

A

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

A

B

−T−

0.100 (0.004)

C

DGH

SECTION N−N

K

K1

JJ1

N

M

F

−W−

SEATING

PLANE

−V−

−U−

S

U

M

0.10 (0.004) V S

T

20X REFK

L

L/2

2X

S

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

--- ---

S

U0.15 (0.006) T

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

MC74VHC374

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9

PACKAGE DIMENSIONS

SOEIAJ−20

CASE 967−01

ISSUE A

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.15 0.25 0.006 0.010

12.35 12.80 0.486 0.504

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.81 --- 0.032

A1

HE

Q1

LE

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

HE

A1

LE

Q1

_

c

A

Z

D

E

20

110

11

b

M

0.13 (0.005)

e

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