MCP6031/2/3/4 0.9 A, High Precision Op Amps Features Description * * * * * * * * The Microchip Technology Inc. MCP6031/2/3/4 family of operational amplifiers (op amps) operate with a single supply voltage as low as 1.8V, while drawing ultra low quiescent current per amplifier (0.9 A, typical). This family also has low input offset voltage (150 V, maximum) and rail-to-rail input and output operation. This combination of features supports battery-powered and portable applications. Rail-to-Rail Input and Output Low Offset Voltage: 150 V (maximum) Ultra Low Quiescent Current: 0.9 A (typical) Wide Power Supply Voltage: 1.8V to 5.5V Gain Bandwidth Product: 10 kHz (typical) Unity Gain Stable Chip Select (CS) capability: MCP6033 Extended Temperature Range: - -40C to +125C * No Phase Reversal Applications * * * * * The MCP6031/2/3/4 family is offered in single (MCP6031), single with power saving Chip Select (CS) input (MCP6033), dual (MCP6032), and quad (MCP6034) configurations. Toll Booth Tags Wearable Products Battery Current Monitoring Sensor Conditioning Battery Powered The MCP6031/2/3/4 family is designed with Microchip's advanced CMOS process. All devices are available in the extended temperature range, with a power supply range of 1.8V to 5.5V. Design Aids * * * * * * The MCP6031/2/3/4 family is unity gain stable and has a gain bandwidth product of 10 kHz (typical). These specs make these op amps appropriate for low frequency applications, such as battery current monitoring and sensor conditioning. SPICE Macro Models FilterLab(R) Software MindiTM Circuit Designer & Simulator MAPS (Microchip Advanced Part Selector) Analog Demonstration and Evaluation Boards Application Notes Typical Application IDD Package Types MCP6031 DFN, SOIC, MSOP NC 1 8 NC NC 1 8 CS VIN- 2 7 VDD VIN- 2 7 VDD VIN+ 3 VSS 4 6 VOUT 5 NC VIN+ 3 VSS 4 6 VOUT 5 NC MCP6031 SOT-23-5 VDD 1.4V to 5.5V 10 100 k VOUT MCP6031 1 M I DD V DD - V OUT = ----------------------------------------( 10 V/V ) ( 10 ) High Side Battery Current Sensor (c) 2008 Microchip Technology Inc. MCP6033 DFN, SOIC, MSOP VOUT 1 MCP6034 SOIC, TSSOP 5 VDD VOUTA 1 14 VOUTD VINA- 2 13 VIND- 4 VIN- VINA+ 3 VDD 4 12 VIND+ 11 VSS VINB+ 5 10 VINC+ VINB- 6 9 VINC- VOUTB 7 8 VOUTC VSS 2 VIN+ 3 MCP6032 SOIC, MSOP VOUTA 1 8 VDD VINA- 2 7 VOUTB VINA+ 3 6 VINB- 5 VINB+ VSS 4 DS22041B-page 1 MCP6031/2/3/4 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings VDD - VSS ........................................................................7.0V Current at Input Pins .....................................................2 mA Analog Inputs (VIN+, VIN-) .......... VSS - 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS - 0.3V to VDD + 0.3V Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. See 4.1.2 "Input Voltage And Current Limits" Difference Input Voltage ...................................... |VDD - VSS| Output Short-Circuit Current .................................continuous Current at Output and Supply Pins ............................30 mA Storage Temperature.....................................-65C to +150C Maximum Junction Temperature (TJ) .......................... +150C ESD protection on all pins (HBM; MM) ................ 4 kV; 400V DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS=GND, TA= +25C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3). Parameters Sym Min VOS Typ Max Units Conditions Input Offset Input Offset Voltage -150 -- +150 Input Offset Drift with Temperature VOS/TA -- 3.0 -- V VDD = 3.0V, VCM = VDD/3 Power Supply Rejection Ratio PSRR 70 88 -- dB IB -- 1.0 100 pA IB -- 60 -- pA TA = +85C TA = +125C V/C TA= -40C to +125C, VDD = 3.0V, VCM = VDD/3 VCM = VSS Input Bias Current and Impedance Input Bias Current IB -- 2000 5000 pA Input Offset Current IOS -- 1.0 -- pA Common Mode Input Impedance ZCM -- 1013||6 -- ||pF ZDIFF -- 1013||6 -- ||pF Common Mode Input Voltage Range VCMR VSS - 0.3 -- VDD + 0.3 V Common Mode Rejection Ratio CMRR 70 95 -- dB VCM = -0.3V to 2.1V, VDD = 1.8V 72 93 -- dB VCM = -0.3V to 5.8V, VDD = 5.5V 70 89 -- dB VCM = 2.75V to 5.8V, VDD = 5.5V 72 93 -- dB VCM = -0.3V to 2.75V, VDD = 5.5V 95 115 -- dB 0.2V < VOUT < (VDD - 0.2V) RL = 50 k to VL Differential Input Impedance Common Mode Open-Loop Gain DC Open-Loop Gain (Large Signal) DS22041B-page 2 AOL (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS=GND, TA= +25C, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units Conditions -- VDD - 10 mV RL = 50 k to VL, 0.5V input overdrive -- 5 -- mA VDD = 1.8V -- 23 -- mA VDD = 5.5V Output Maximum Output Voltage Swing Output Short-Circuit Current VOL, VOH VSS + 10 ISC Power Supply Supply Voltage Quiescent Current per Amplifier VDD 1.8 -- 5.5 V IQ 0.4 0.9 1.35 A IO = 0, VCM = VDD, VDD = 5.5V AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25C, VDD = +1.8 to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, CL = 60 pF, RL = 1 M to VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3). Parameters Sym Min Typ Max Units kHz Conditions AC Response Gain Bandwidth Product GBWP -- 10 -- Phase Margin PM -- 65 -- Slew Rate SR -- 4.0 -- V/ms Input Noise Voltage Eni -- 3.9 -- Vp-p f = 0.1 Hz to 10 Hz Input Noise Voltage Density eni -- 165 -- nV/Hz f = 1 kHz Input Noise Current Density ini -- 0.6 -- fA/Hz f = 1 kHz G = +1 V/V Noise (c) 2008 Microchip Technology Inc. DS22041B-page 3 MCP6031/2/3/4 MCP6033 CHIP SELECT ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS =GND, TA = +25C, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, CL = 60 pF, RL = 1 M to VL and CS is tied low (Refer to Figure 1-1). Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low VIL VSS -- 0.2VDD V CS Input Current, Low ICSL -- -10 -- pA CS Logic Threshold, High VIH 0.8VDD VDD V CS Input Current, High ICSH -- 10 -- pA CS = VDD ISS -- -400 -- pA CS = VDD IO(LEAK) -- 10 -- pA CS = VDD CS Low to Amplifier Output Turn-on Time tON -- 4 100 ms CS 0.2VDD to VOUT = 0.9VDD/2, G = +1 V/V, VIN = VDD/2, RL = 50 k to VL = VSS. CS High to Amplifier Output High-Z tOFF -- 10 -- s CS 0.8VDD to VOUT = 0.1VDD/2, G = +1 V/V, VIN = VDD/2, RL = 50 k to VL = VSS. VHYST -- 0.3VDD -- V CS Low Specifications CS = VSS CS High Specifications GND Current Amplifier Output Leakage CS Dynamic Specifications CS Hysteresis CS VIL VIH tON VOUT High-Z High-Z ISS -400 pA (typical) ICS tOFF -0.9 A (typical) -400 pA (typical) 10 pA (typical) FIGURE 1-1: Timing Diagram for the CS Pin on the MCP6033. DS22041B-page 4 (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Operating Temperature Range TA -40 -- +125 C Storage Temperature Range TA -65 -- +150 C Thermal Resistance, 5L-SOT-23 JA -- 256 -- C/W Thermal Resistance, 8L-DFN (2x3) JA -- 84 -- C/W Thermal Resistance, 8L-SOIC JA -- 163 -- C/W Thermal Resistance, 8L-MSOP JA -- 206 -- C/W Thermal Resistance, 14L-SOIC JA -- 120 -- C/W Thermal Resistance, 14L-TSSOP JA -- 100 -- C/W Conditions Temperature Ranges Note Thermal Package Resistances Note: 1.1 The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150C. Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-3. The bypass capacitors are laid out according to the rules discussed in Section 4.6 "Supply Bypass". VDD 2.2 F VIN 0.1 F RN VOUT MCP603X CL RL VDD/2 VL RG RF FIGURE 1-2: AC and DC Test Circuit for Most Non-Inverting Gain Conditions. VDD 2.2 F VDD/2 0.1 F RN VOUT MCP603X CL RL VIN VL RG RF FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. (c) 2008 Microchip Technology Inc. DS22041B-page 5 MCP6031/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL , CL = 60 pF and CS is tied low. 400 -300 200 100 -300 8% 6% 4% 2% 0% 0 6 12 18 24 30 250 200 150 100 50 0 -50 -100 -150 -200 -250 VDD = 3.0V DS22041B-page 6 2.2 2.0 1.8 1.4 1.2 1.0 0.8 0.6 0.4 VDD = 5.5V VDD = 1.8V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Offset Drift with Temperature (V/C) FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA +85C. 0.2 VDD = 1.8V -0.4 Input Offset Voltage (V) 640 Samples VDD = 3.0V VCM = VDD/3 TA = +85C to +125C -6 6.0 -200 FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 1.8V. 14% -30 -24 -18 -12 5.5 0 -100 Common Mode Input Voltage (V) FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA +85C. 10% 5.0 TA = -40C TA = +25C TA = +85C TA = +125C 300 -400 12% 4.5 4.0 3.5 400 640 Samples VDD = 3.0V VCM = VDD/3 TA = -40C to +85C -20 -16 -12 -8 -4 0 4 8 12 16 20 Input Offset Drift with Temperature (V/C) Percentage of Occurences 3.0 -0.5 FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage with VDD = 5.5V. Input Offset Voltage (V) 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Input Offset Voltage with Common Mode Input Voltage (V) 1.6 FIGURE 2-1: VDD = 3.0V. 2.5 VDD = 5.5V -400 0% -150 -120 -90 -60 -30 0 30 60 90 120 150 Input Offset Voltage (V) Percentage of Occurences -200 2.0 2% 1.5 4% 0 -100 1.0 6% 100 0.5 8% 200 0.0 10% TA = -40C TA = +25C TA = +85C TA = +125C 300 -0.2 12% 0.0 640 Samples VDD = 3.0V VCM = VDD/3 Input Offset Voltage (V) Percentage of Occurences 14% Output Voltage (V) FIGURE 2-6: Output Voltage. Input Offset Voltage vs. (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF and CS is tied low. PSRR, CMRR (dB) Input Noise Voltage Density (nV/Hz) 1,000 100 0.1 1E-1 1 1E+0 10 1E+1 100 1E+2 1k 1E+3 10k 1E+4 100k 1E+5 110 105 100 95 90 85 80 75 70 65 60 10000 Input Bias and Offset Currents (pA) 175 150 125 100 75 50 f = 1 kHz VDD = 5.5V 25 10 CMRR, PSRR (dB) Input Bias Current (pA) VDD = 5.5V Input Offset Current 45 65 85 105 Ambient Temperature (C) 125 FIGURE 2-11: Input Bias, Offset Currents vs. Ambient Temperature. 10000 CMRR 125 Input Bias Current 100 25 PSRR- PSRR+ 100 VDD = 5.5V VCM = VDD 1 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 FIGURE 2-8: Input Noise Voltage Density vs. Common Mode Input Voltage. 0 25 50 75 Ambient Temperature (C) 1000 Common Mode Input Voltage (V) 100 90 80 70 60 50 40 30 20 10 0 -25 FIGURE 2-10: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Ambient Temperature. 200 -0.5 Input Noise Voltage Density (nV/Hz) Input Noise Voltage Density CMRR (VDD = 5.5V, VCM = -0.3V to 5.8V) PSRR (VDD = 1.8V to 5.5V, VCM = VSS) -50 Frequency (Hz) FIGURE 2-7: vs. Frequency. CMRR (VDD = 1.8V, VCM = -0.3V to 2.1V) 1000 VDD = 5.5V TA = +125C 100 TA = +85C 10 0.1 1 10 Frequency (Hz) 100 1000 FIGURE 2-9: Common Mode Rejection Ratio, Power Supply Rejection Ratio vs. Frequency. (c) 2008 Microchip Technology Inc. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-12: Input Bias Current vs. Common Mode Input Voltage. DS22041B-page 7 MCP6031/2/3/4 VDD = 5.5V @ VCM = VDD VDD = 1.8V @ VCM = VDD VDD = 5.5V @ VCM = VSS VDD = 1.8V @ VCM = VSS -50 -25 0 25 50 75 100 Ambient Temperature (C) DC Open-Loop Gain (dB) 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 TA = +125C TA = +85C TA = +25C TA = -40C DC Open-Loop Gain (dB) 7.0 5.5 6.0 6.5 5.0 3.5 4.0 4.5 2.0 2.5 3.0 0.5 1.0 1.5 0.0 Quiescent Current (A/Amplifier) TA = +125C TA = +85C TA = +25C TA = -40C DS22041B-page 8 -90 40 -120 20 -150 0 -180 VDD = 5.5V 130 125 120 115 110 105 100 95 90 85 80 -210 1k 10k 100 100 100 100k 1E+ 00 05 Frequency (Hz) 0 1 10 Open-Loop Gain, Phase vs. RL = 50 k VSS + 0.2V < VOUT < VDD - 0.2V 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. VCM = VSS FIGURE 2-15: Quiescent Current vs. Power Supply Voltage with VCM = VSS. -60 Power Supply Voltage VDD (V) FIGURE 2-14: Quiescent Current vs. Power Supply Voltage with VCM = VDD. Power Supply Voltage (V) Open-Loop Phase 1.5 Power Supply Voltage (V) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -30 60 FIGURE 2-16: Frequency. VCM = VDD 0.0 Quiescent Current (A/Amplifier) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 80 -20 0.001 0.01 0.1 0 0.01 125 FIGURE 2-13: Quiescent Current vs Ambient Temperature. 0 Open-Loop Gain 100 Open-Loop Phase () 120 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Open-Loop Gain (V/V) Quiescent Current (A/Amplifier) Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF and CS is tied low. 130 125 VDD = 5.5V 120 115 110 105 VDD = 1.8V 100 95 90 Large Signal AOL 85 RL = 50 k 80 0.00 0.05 0.10 0.15 0.20 0.25 Output Voltage Headroom VDD - VOUT or VOUT - VSS (V) FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom. (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 Gain Bandwidth Product (kHz) 120 110 100 90 80 70 Input Referred 60 100 1,000 Frequency (Hz) Gain Bandwidth Product Phase Margin VDD = 5.5V G = +1 V/V 60 Gain Bandwidth Product 50 40 30 VDD = 5.5V G = +1 V/V -50 20 10 0 -25 0 25 50 75 100 125 Ambient Temperature (C) FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. (c) 2008 Microchip Technology Inc. -25 0 25 50 75 100 Ambient Temperature (C) 30 TA = -40C TA = +25C TA = +85C TA = +125C 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-23: Ouput Short Circuit Current vs. Power Supply Voltage. Output Voltage Swing (V Phase Margin VDD = 1.8V G = +1 V/V FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. P-P ) 90 Phase Margin () Gain Bandwidth Product (kHz) FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Common Mode Input Voltage. 80 70 Gain Bandwidth Product -50 Common Mode Input Voltage (V) 20 18 16 14 12 10 8 6 4 2 0 Phase Margin 90 80 70 60 50 40 30 20 10 0 125 35 Phase Margin () 180 160 140 120 100 80 60 40 20 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Gain Bandwidth Product (kHz) FIGURE 2-19: Channel-to-Channel Separation vs. Frequency ( MCP6032/4 only). 20 18 16 14 12 10 8 6 4 2 0 20 18 16 14 12 10 8 6 4 2 0 10,000 Output Short Circuit Current (mA) Channel-to-Channel Seperation (dB) 130 Phase Margin () Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF and CS is tied low. 10 VDD = 5.5V VDD = 3.0V VDD = 1.8V 1 0.1 10 FIGURE 2-24: Frequency. 1K 100 1000 Frequency (Hz) 10K 10000 Output Voltage Swing vs. DS22041B-page 9 MCP6031/2/3/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF and CS is tied low. VDD - VOH @ VDD = 1.8V VOL - VSS @ VDD = 1.8V 100 10 VDD - VOH @ VDD = 5.5V VOL - VSS @ VDD = 5.5V 1 10 1m 100 Output Current (A) Time (100 s/Div) VDD - VOH VSS - VOL -25 FIGURE 2-28: Pulse Response. Output Voltage (20 mV/div) Output Voltage Headroom VDD - V OH or V SS - V OL (mV) VDD = 5.5V RL = 50 k -50 0 25 50 75 100 Ambient Temperature (C) FIGURE 2-29: Response. Output Voltage (V) Slew Rate (V/ms) Falling Edge, VDD = 5.5V Falling Edge, VDD = 1.8V 5.0 4.0 3.0 Rising Edge, VDD = 5.5V Rising Edge, VDD = 1.8V 1.0 -50 -25 FIGURE 2-27: Temperature. DS22041B-page 10 0 25 50 75 Ambient Temperature (C) 100 VDD = 5.5V G = -1 V/V Time (100 s/Div) 7.0 2.0 Small Signal Non-Inverting 125 FIGURE 2-26: Output Voltage Headroom vs. Ambient Temperature. 6.0 VDD = 5.5V G = +1 V/V 10m FIGURE 2-25: Output Voltage Headroom vs. Output Current. 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Output Voltage (20 mV/div) Output Voltage Headroom VDD - V OH, V OL - V SS (mV) 1000 125 Slew Rate vs. Ambient 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Small Signal Inverting Pulse VDD = 5.5V G = +1 V/V Time (0.5 ms/div) FIGURE 2-30: Pulse Response. Large Signal Non-Inverting (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Internal CS Switch Ouptut (V) Output Voltage (V) Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF and CS is tied low. VDD = 5.5V G = -1 V/V 4.0 2.5 1.5 0.5 VDD = 3.0V 1.8 Ouptut Voltage (V) Output Voltage (V) Output High-Z 0.0 3.0 2.0 1.0 VDD = 5.0V G = +2 V/V Output On 1.5 Hysteresis 1.2 0.9 CS Input High to Low 0.6 CS Input Low to High 0.3 Output High-Z 0.0 -1.0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 Chip Select Voltage (V) Time (2 ms/div) FIGURE 2-32: The MCP6031/2/3/4 family shows no phase reversal . 6.0 1.2 VDD = 5.5V G = +1 V/V RL = 50 k to VSS 4.0 Output On Output High-Z 3.0 2.0 Output High-Z 1.0 0.0 Time (1 ms/div) FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time (MCP6033 only). (c) 2008 Microchip Technology Inc. Ouptut Voltage (V) 1.5 5.0 Chip Select FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 3.0V. 7.0 Output Voltage (V) Chip Select Voltage (V) CS Input Low to High 2.1 VOUT 4.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 CS Input High to Low 1.0 FIGURE 2-34: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 5.5V. VIN 5.0 0.0 Hysteresis 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) Large Signal Inverting Pulse 6.0 Output On 3.0 Time (0.5 ms/div) FIGURE 2-31: Response. VDD = 5.5V 3.5 VDD = 1.8V Output On 0.9 Hysteresis 0.6 CS Input High to Low CS Input Low to High 0.3 Output High-Z 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Chip Select Voltage (V) 1.6 1.8 FIGURE 2-36: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 1.8V. DS22041B-page 11 MCP6031/2/3/4 Note: Unless otherwise indicated, TA = +25C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 1 M to VL, CL = 60 pF and CS is tied low. 10k 10000 1k 1000 GN: 101 V/V 11 V/V 1 V/V 100 100 10 10 11 1 10 100 1k 1000 10k 10000 Frequency (Hz) FIGURE 2-37: Closed Loop Output Impedance vs. Frequency. DS22041B-page 12 10m 1.00E-02 1m 1.00E-03 100 1.00E-04 10 1.00E-05 1 1.00E-06 100n 1.00E-07 10n 1.00E-08 1n 1.00E-09 100p 1.00E-10 10p 1.00E-11 1p 1.00E-12 -IIN (A) Closed Loop Output Impedance () 100000 100k 100k 100000 +125C +85C +25C -40C -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 VIN (V) FIGURE 2-38: Measured Input Current vs. Input Voltage (below VSS). (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6031 MCP6032 MCP6033 MCP6034 SOT-23-5 DFN, MSOP, SOIC MSOP, SOIC DFN, MSOP, SOIC SOIC, TSSOP Symbol 1 6 1 6 1 VOUT, VOUTA Analog Output (op amp A) 4 2 2 2 2 VIN-, VINA- Inverting Input (op amp A) 3 3 3 3 3 VIN+, VINA+ Non-inverting Input (op amp A) 5 7 8 7 4 VDD -- -- 5 -- 5 VINB+ Non-inverting Input (op amp B) -- -- 6 -- 6 VINB- Inverting Input (op amp B) -- -- 7 -- 7 VOUTB Analog Output (op amp B) -- -- -- -- 8 VOUTC Analog Output (op amp C) -- -- -- -- 9 VINC- Inverting Input (op amp C) -- -- -- -- 10 VINC+ Non-inverting Input (op amp C) 2 4 4 4 11 VSS -- -- -- -- 12 VIND+ Non-inverting Input (op amp D) -- -- -- -- 13 VIND- Inverting Input (op amp D) Analog Output (op amp D) 3.1 Negative Power Supply -- -- -- -- 14 VOUTD -- -- 8 -- CS Chip Select -- 1, 5, 8 -- 1, 5 -- NC No Internal Connection Analog Outputs Analog Inputs The non-inverting and inverting inputs are highimpedance CMOS inputs with low bias currents. 3.3 Positive Power Supply -- The output pins are low-impedance voltage sources. 3.2 Description Chip Select Digital Input 3.4 Power Supply Pins The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. This is a CMOS, Schmitt-trigerred input that places the device into a low power mode of operation. (c) 2008 Microchip Technology Inc. DS22041B-page 13 MCP6031/2/3/4 4.0 APPLICATION INFORMATION VDD The MCP6031/2/3/4 family of op amps is manufactured using Microchip's state-of-the-art CMOS process and is specifically designed for low-power, high precision applications. 4.1 D1 R1 Rail-to-Rail Input 4.1.1 PHASE REVERASAL R2 R3 VSS - (minimum expected V1) 2 mA VSS - (minimum expected V2) R2 > 2 mA R1 > INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltage that go too far above VDD; their breakdown voltage is high enough to allow normal operation and low enough to bypass ESD events within the specified limits. VDD Bond Pad VIN+ Bond Pad Bond V - IN Pad VSS Bond Pad FIGURE 4-1: Structures. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the voltages and currents at the VIN+ and VIN- pins (see Absolute Maximum Ratings at the beginning of Section 1.0 "Electrical Characteristics"). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN-) from going too far above VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. DS22041B-page 14 FIGURE 4-2: Inputs. Protecting the Analog It is also possible to connect the diodes to the left of the resistors R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC currents into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs when the common mode voltage (VCM) is below ground (VSS). 4.1.3 Input Stage MCP603X V2 The MCP6031/2/3/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-32 shows the input voltage exceeding the supply voltage without any phase reversal. 4.1.2 D2 V1 NORMAL OPERATION The input stage of the MCP6031/2/3/4 op amps uses two differential input stages in parallel. One operates at a low common mode input voltage (VCM), while the other operates at a high VCM. With this topology, the device operates with a VCM up to 300 mV above VDD and 300 mV below VSS. The input offset voltage is measured at VCM = VSS - 0.3V and VDD + 0.3V to ensure proper operation. There are two transitions in input behavior as VCM is changed. The first occurs, when VCM is near VSS + 0.4V, and the second occurs when VCM is near VDD - 0.5V. For the best distortion performance with non-inverting gains, avoid these regions of operation. (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 Rail-to-Rail Output The output voltage range of the MCP6031/2/3/4 op amps is VSS + 10 mV (minimum) and VDD - 10 mV (maximum) when RL = 50 k is connected to VDD/2 and VDD = 5.5V. Refer to Figures 2-25 and 2-26 for more information. 4.3 - VOUT CL Output Loads and Battery Life The MCP6031/2/3/4 op amp family has outstanding quiescent current, which supports battery-powered applications. There is minimal quiescent current glitching when Chip Select (CS) is raised or lowered. This prevents excessive current draw, and reduced battery life, when the part is turned off or on. Heavy resistive loads at the output can cause excessive battery drain. Driving a DC voltage of 2.5V across a 100 k load resistor will cause the supply current to increase by 25 A, depleting the battery 28 times as fast as IQ (0.9 A, typical) alone. High frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current. For instance, a 0.1 F capacitor at the output presents an AC impedance of 15.9 k (1/2fC) to a 100 Hz sinewave. It can be shown that the average power drawn from the battery by a 5.0 Vp-p sinewave (1.77 Vrms), under these conditions, is FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit's noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 1000000 1M PSupply = (VDD - VSS) (IQ + VL(p-p) f CL ) = (5V)(0.9 A + 5.0Vp-p * 100Hz * 0.1F) = 4.5 W + 50 W This will drain the battery about 12 times as fast as IQ alone. Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop's phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. While a unity-gain buffer (G = +1) is the most sensitive to capacitive loads, all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 100 pF when G = +1), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop's phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitance load. (c) 2008 Microchip Technology Inc. 100k 100000 10k 10000 GN: 1 V/V 2 V/V 5 V/V 1k 1000 10p 100p 1.E-09 1n 10n 100n 1 1.E-11 1.E-10 1.E-08 1.E-07 1.E-06 Normalized Load Capacitance; CL/GN (F) EQUATION 4-1: 4.4 RISO MCP603X + VIN Recommended R ISO () 4.2 FIGURE 4-4: Recommended RISO values for Capacitive Loads. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO's value until the response is reasonable. Bench evaluation and simulations with the MCP6031/2/3/4 SPICE macro model are very helpful. 4.5 MCP6033 Chip Select The MCP6033 is a single op amp with Chip Select (CS). When CS is pulled high, the supply current drops to 0.4 nA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier will not operate properly. Figure 1-1 shows the output voltage and supply current response to a CS pulse. DS22041B-page 15 MCP6031/2/3/4 4.6 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 F to 0.1 F) within 2 mm for good high frequency performance. It can use a bulk capacitor (i.e., 1 F or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. 4.7 Unused Op Amps An unused op amp in a quad package (MCP6034) should be configured as shown in Figure 4-5. These circuits prevent the output from toggling and causing crosstalk. Circuits A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. 1/4 MCP6034 (A) 1/4 MCP6034 (B) VDD R1 VDD VDD VREF R2 Guard Ring FIGURE 4-6: for Inverting Gain. 1. 2. VIN- VIN+ VSS Example Guard Ring Layout Non-inverting Gain and Unity-Gain Buffer: a. Connect the non-inverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b. Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the common mode input voltage. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a. Connect the guard ring to the non-inverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b. Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. R2 V REF = V DD -----------------R1 + R2 FIGURE 4-5: 4.8 Unused Op Amps. PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow; which is greater than the MCP6031/2/3/4 family's bias current at +25C (1.0 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-6. DS22041B-page 16 (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 4.9 4.9.1 Application Circuits 4.9.2 BATTERY CURRENT SENSING The MCP6031/2/3/4 op amps' Common Mode Input Range, which goes 0.3V beyond both supply rails, supports their use in high side and low side battery current sensing applications. The ultra low quiescent current (0.9 A, typical) helps prolong battery life, and the rail-to-rail output supports detection of low currents. Figure 4-7 shows a high side battery current sensor circuit. The 10 resistor is sized to minimize power losses. The battery current (IDD) through the 10 resistor causes its top terminal to be more negative than the bottom terminal. This keeps the common mode input voltage of the op amp below VDD, which is within its allowed range. The output of the op amp will also be below VDD, which is within its Maximum Output Voltage Swing specification. Use high gain before a comparator to improve the latter's input offset performance. Figure 4-8 shows a gain of 11 V/V placed before a comparator. The reference voltage VREF can be any value between the supply rails. VIN MCP6031 1 M 100 k FIGURE 4-8: Comparator. 4.9.3 IDD 1.4V to 5.5V VDD 10 100 k VOUT MCP6031 1 M V DD - V OUT I DD = ----------------------------------------( 10 V/V ) ( 10 ) FIGURE 4-7: Sensor. High Side Battery Current PRECISION COMPARATOR MCP6541 Precision, Non-inverting DRIVING MCP3421 A/D CONVERTER A RSH and CSH snubber reduces the output impedance of MCP6031 op amp, which reduces the gain error caused by switching transients, which occur at the MCP3421 ADC's sampling rate. The snubber also maintains feedback stability and avoids AC response peaking and step response overshoot and ringing (caused by the op amp's inductive output impedance resonating with the ADC's input capacitance). The cost for this improvement is low. Best of all, using an op amp with higher supply current is avoided. See Figure 4-9. This figure also includes a resistor to balance the impedance at the ADC's inputs (RBAL) at the sampling frequency; it may not be needed in all designs. MCP6031 VIN 1.00 k RSH 1.00 k CSH 2.2 F FIGURE 4-9: an R-C Snubber. (c) 2008 Microchip Technology Inc. VOUT VREF ZIND 2.25 M MCP3421 RBAL 1.00 k Driving the MCP3421 using DS22041B-page 17 MCP6031/2/3/4 5.0 DESIGN AIDS Microchip provides the basic design tools needed for the MCP6031/2/3/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6031/2/3/4 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp's linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab(R) Software Microchip's FilterLab(R) software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 MindiTM Circuit Designer & Simulator Microchip's MindiTM Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power-management applications. It is a free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation. 5.4 5.5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user's guides and technical information, visit the Microchip web site at www.microchip.com/ analogtools. Two of our boards that are especially useful are: * P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board * P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board 5.6 Application Notes The following Microchip Analog Design Note and Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. ADN003: "Select the Right Operational Amplifier for your Filtering Circuits", DS21821 AN722: "Operational Amplifier Topologies and DC Specifications", DS00722 AN723: "Operational Amplifier AC Specifications and Applications", DS00723 AN884: "Driving Capacitive Loads With Op Amps", DS00884 AN990: "Analog Sensor Conditioning Circuits - An Overview", DS00990 These application notes and others are listed in the design guide: "Signal Chain Design Guide", DS21825 MAPS (Microchip Advanced Part Selector) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip's product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparasion reports. Helpful links are also provided for Datasheets, Purchase, and Sampling of Microchip parts. DS22041B-page 18 (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 5-Lead SOT-23 (MCP6031) Device XXNN MCP6031T-E/OT 8-Lead 2x3 DFN (MCP6031 & MCP6033) XXX YWW NN EANN EA25 Example: ABV 809 25 Example: 8-Lead MSOP XXXXXX 6031E YWWNNN 809256 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: E-Temp Code Example: MCP6033E e3 SN^^0809 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2008 Microchip Technology Inc. DS22041B-page 19 MCP6031/2/3/4 Package Marking Information (Continued) 14-Lead SOIC (150 mil) (MCP6034) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6034) XXXXXX YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS22041B-page 20 MCP6034 e3 E/SL^^ 0711256 Example: 6034EST 0711 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. 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DS22041B-page 25 MCP6031/2/3/4 /HDG3ODVWLF6PDOO2XWOLQH 61 1DUURZPP%RG\>62,&@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS22041B-page 26 (c) 2008 Microchip Technology Inc. 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DS22041B-page 27 MCP6031/2/3/4 /HDG3ODVWLF7KLQ6KULQN6PDOO2XWOLQH 67 PP%RG\>76623@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 e b A2 A c A1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI3LQV L L1 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ 2YHUDOO:LGWK ( 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH /HDG7KLFNQHVV F /HDG:LGWK E 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS22041B-page 28 (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 APPENDIX A: REVISION HISTORY Revision B (March 2008) The following is the list of modifications: 1. 2. 3. 4. 5. 6. 7. 8. Added SOT-23-5 and 2x3 DFN packages. Added test circuits. Corrected VOS temperature drift information. Added Section 4.9.3. Updated Package Marking Information. Updated all package outline drawings and added package outline drawings for SOT-23-5 and 2x3 DFN packages. Added Landing Pattern drawings for 2x3 DFN and 8-lead SOIC packages. Updated information in Product Identification System for SOT-23-5 and 2x3 DFN packages. Revision A (March 2007) * Original Release of this Document. (c) 2008 Microchip Technology Inc. DS22041B-page 29 MCP6031/2/3/4 NOTES: DS22041B-page 30 (c) 2008 Microchip Technology Inc. MCP6031/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device: MCP6031: MCP6031T: MCP6032: MCP6032T: MCP6033: MCP6033T: MCP6034: MCP6034T: Single Op Amp Single Op Amp (Tape and Reel) Dual Op Amp Dual Op Amp (Tape and Reel) Single Op Amp with Chip Select Single Op Amp with Chip Select (Tape and Reel) Quad Op Amp Quad Op Amp (Tape and Reel) Temperature Range: E = -40C to +125C Package: MC MS OT SL SN ST = = = = = = Plastic Dual Flat, No Lead, (2x3 DFN ) 8-lead ** Plastic MSOP, 8-lead Plastic Small Outline Transistor, 5-lead * Plastic SOIC (150 mil Body), 14-lead Plastic SOIC, (150 mil Body), 8-lead Plastic TSSOP (4.4mm Body), 14-lead * This package is only available on the MCP6031 device. ** These packages are only available on the MCP6031 and MCP6033 devices. Examples: a) b) c) d) e) f) g) a) b) c) d) a) b) c) d) e) f) a) b) c) d) (c) 2008 Microchip Technology Inc. MCP6031-E/SN: 8LD SOIC package. MCP6031T-E/SN: Tape and Reel, 8LD SOIC package. MCP6031-E/MS: 8LD MSOP package. MCP6031T-E/MS: Tape and Reel, 8LD MSOP package. MCP6031-E/MC: 8LD DFN package. MCP6031T-E/MC: Tape and Reel, 8LD DFN package. MCP6031T-E/OT: Tape and Reel, 5-LD SOT-23 package. MCP6032-E/SN: 8LD SOIC package. MCP6032T-E/SN: Tape and Reel, 8LD SOIC package. MCP6032-E/MS: 8LD MSOP package MCP6032T-E/MS: Tape and Reel 8LD MSOP package. MCP6033-E/SN: 8LD SOIC package. MCP6033T-E/SN: Tape and Reel, 8LD SOIC package. MCP6033-E/MS: 8LD MSOP package. MCP6033T-E/MS: Tape and Reel, 8LD MSOP package. MCP6033-E/MC: 8LD DFN package. MCP6033T-E/MC: Tape and Reel, 8LD DFN package. MCP6034-E/SL: 14LD SOIC package. MCP6034T-E/SL: Tape and Reel, 14LD SOIC package. MCP6034-E/ST: 14LD TSSOP package. MCP6034T-E/ST: Tape and Reel, 14LD TSSOP package. DS22041B-page 31 MCP6031/2/3/4 NOTES: DS22041B-page 32 (c) 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2008 Microchip Technology Inc. DS22041B-page 33 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 01/02/08 DS22041B-page 34 (c) 2008 Microchip Technology Inc.