© 2008 Microchip Technology Inc. DS22041B-page 1
MCP6031/2/3/4
Features
• Rail-to-Rail Input and Output
• Low Offset Voltage: ±150 µV (maximum)
• Ultra Low Quiescent Current: 0.9 µA (typical)
• Wide Power Supply Voltage: 1.8V to 5.5V
• Gain Bandwidth Product: 10 kHz (typical)
• Unity Gain Stable
• Chip Select (CS) capability: MCP6033
• Extended Temperature Range:
- -40°C to +125°C
• No Phase Reversal
Applications
• Toll Booth Tags
• Wearable Products
• Battery Current Monitoring
• Sensor Conditioning
•Battery Powered
Design Aids
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Circuit Designer & Simulator
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes
Typical Application
Description
The Microchip Technology Inc. MCP6031/2/3/4 family
of operational amplifiers (op amps) operate with a
single supply voltage as low as 1.8V, while drawing
ultra low quiescent current per amplifier (0.9 µA,
typical). This family also has low input offset voltage
(±150 µV, maximum) and rail-to-rail input and output
operation. This combination of features supports
battery-powered and portable applications.
The MCP6031/2/3/4 family is unity gain stable and has
a gain bandwidth product of 10 kHz (typical). These
specs make these op amps appropriate for low fre-
quency applications, such as battery current
monitoring and sensor conditioning.
The MCP6031/2/3/4 family is offered in single
(MCP6031), single with power saving Chip Select (CS)
input (MCP6033), dual (MCP6032), and quad
(MCP6034) configurations.
The MCP6031/2/3/4 family is designed with Micro-
chip’s advanced CMOS process. All devices are
available in the extended temperature range, with a
power supply range of 1.8V to 5.5V.
Package Types
VDD
IDD
MCP6031
100 kΩ
1MΩ
1.4V VOUT
High Side Battery Current Sensor
10Ω
to
5.5V
IDD VDD VOUT
–
10 V/V()10
Ω
()
⋅
------------------------------------------=
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
NCNC
VINA+
VINA–
VSS
1
2
3
4
8
7
6
5
VOUTA VDD
VOUTB
VINB–
VINB+
MCP6031
DFN, SOIC, MSOP
MCP6032
SOIC, MSOP
VIN+
VIN–
VSS
VDD
VOUT
1
2
3
4
8
7
6
5NC
CS
NC
MCP6033
DFN, SOIC, MSOP
VINA+
VINA–
VDD
1
2
3
4
14
13
12
11
VOUTA VOUTD
VIND–
VIND+
VSS
MCP6034
SOIC, TSSOP
VINB+510 VINC+
VINB–69
VOUTB 7 8 VOUTC
VINC–
VIN+
VSS VIN–
1
2
3
5
4
VDD
VOUT
MCP6031
SOT-23-5
0.9 µA, High Precision Op Amps
MCP6031/2/3/4
DS22041B-page 2 © 2008 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Input Pins.....................................................±2 mA
Analog Inputs (VIN+, VIN-)†† .......... VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ...................................... |VDD – VSS|
Output Short-Circuit Current .................................continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature.....................................-65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 400V
† Notice: Stresses above those listed under “Abso lute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other conditions
above those indicated in th e operation al listin gs of this
specification is not implied . Exposure to maximum rat-
ing conditions for extended periods may affect device
reliability.
†† See 4.1.2 “Input Voltage And Current Limits”
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS=GND, TA= +25°C, VCM = VDD/2,
VOUT ≈VDD/2, VL = VDD/2, RL = 1 MΩ to VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -150 — +150 µV VDD = 3.0V, VCM = VDD/3
Input Offset Drift with Temperature ΔVOS/ΔTA— ±3.0 — µV/°C TA= -40°C to +125°C,
VDD = 3.0V, VCM = VDD/3
Power Supply Rejection Ratio PSRR 70 88 — dB VCM = VSS
Input Bias Current and Impedance
Input Bias Current IB— ±1.0 100 pA
IB—60—pAT
A = +85°C
IB— 2000 5000 pA TA = +125°C
Input Offset Current IOS — ±1.0 — pA
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF
Differential Input Impedance ZDIFF —10
13||6 — Ω||pF
Common Mode
Common Mode Input Voltage
Range VCMR VSS − 0.3 — VDD + 0.3 V
Common Mode Rejection Ratio CMRR 70 95 — dB VCM = -0. 3V to 2.1V,
VDD = 1.8V
72 93 — dB VCM = -0.3V to 5.8V,
VDD = 5.5V
70 89 — dB VCM = 2.75V to 5.8V,
VDD = 5.5V
72 93 — dB VCM = -0.3V to 2.75V,
VDD = 5.5V
Open-Loop Gain
DC Open-Loop Gain
(Large Signal) AOL 95 115 — dB 0.2V < VOUT < (VDD – 0.2V)
RL = 50 kΩ to VL
© 2008 Microchip Technology Inc. DS22041B-page 3
MCP6031/2/3/4
AC ELECTRICAL SPECIFICATIONS
Output
Maximum Output Voltage Swing VOL, VOH VSS + 10 — VDD – 10 mV RL = 50 kΩ to VL,
0.5V input overdrive
Output Short-Circuit Current ISC —±5—mAV
DD = 1.8V
—±23—mAV
DD = 5.5V
Power Supply
Supply Voltage VDD 1.8 — 5.5 V
Quiescent Current per Amplifier IQ0.4 0.9 1.35 µA IO = 0, VCM = VDD,
VDD = 5.5V
Electrical Characteristics: Unless otherwise indicated, T A = +25°C, VDD = +1.8 to +5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈VDD/2, VL = VDD/2, CL = 60 p F, RL = 1 M Ω to VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 10 — kHz
Phase Margin PM — 65 — ° G = +1 V/V
Slew Rate SR — 4.0 — V/ms
Noise
Input Noise Voltage Eni — 3.9 — µVp-p f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —165—nV/√Hz f = 1 kHz
Input Noise Current Density ini —0.6—fA/√Hz f = 1 kHz
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS=GND, TA= +25°C, VCM = VDD/2,
VOUT ≈VDD/2, VL = VDD/2, RL = 1 MΩ to VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
MCP6031/2/3/4
DS22041B-page 4 © 2008 Microchip Technology Inc.
MCP6033 CHIP SELECT ELECTRICAL CHARACTERISTICS
FIGURE 1-1: Timing Diagram for the CS
Pin on the MCP6033.
Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS =GND, T A= +25°C, VCM =V
DD/2,
VOUT =V
DD/2, VL = VDD/2, CL = 60 pF, RL = 1 MΩ to VL and CS is tied low (Refer to Figure 1-1).
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL —-10—pACS = VSS
CS High Specifications
CS Logic Threshold, High VIH 0.8VDD VDD V
CS Input Current, High ICSH —10—pACS = VDD
GND Current ISS — -400 — pA CS = VDD
Amplifier Output Leakage IO(LEAK) —10—pACS = VDD
CS Dynamic Specifications
CS Low to Amplifier Output
Turn-on Time tON — 4 100 ms CS ≤ 0.2VDD to VOUT = 0.9VDD/2,
G = +1 V/V, VIN = VDD/2,
RL = 50 kΩ to VL = VSS.
CS High to Amplifier Output
High-Z tOFF —10—µsCS ≥ 0.8VDD to VOUT = 0.1VDD/2,
G = +1 V/V, VIN = VDD/2,
RL = 50 kΩ to VL = VSS.
CS Hysteresis VHYST —0.3V
DD —V
VIL
High-Z
tON
VIH
CS
tOFF
VOUT
-400 pA
High-Z
ISS
ICS 10 pA
-400 pA
-0.9 µA
(typical)
(typical) (typical)
(typical)
© 2008 Microchip Technology Inc. DS22041B-page 5
MCP6031/2/3/4
TEMPERATURE SPECIFICATIONS
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.6 “Supply Bypass”.
FIGURE 1-2: AC and DC Te st Circ uit for
Most Non-Inverting Gain Conditions.
FIGURE 1-3: AC and DC Te st Circ uit for
Most Inverting Gain Conditions.
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperature Range TA-40 — +125 °C Note
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA —256—°C/W
Thermal Resistance, 8L-DFN (2x3) θJA —84—°C/W
Thermal Resistance, 8L-SOIC θJA —163—°C/W
Thermal Resistance, 8L-MSOP θJA —206—°C/W
Thermal Resistance, 14L-SOIC θJA —120 —°C/W
Thermal Resistance, 14L-TSSOP θJA —100 —°C/W
Note: The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
VDD
MCP603X
RGRF
RNVOUT
VIN
VDD/2
2.2 µF
CLRL
VL
0.1 µF
VDD
MCP603X
RGRF
RNVOUT
VIN
VDD/2 2.2 µF
CLRL
VL
0.1 µF
MCP6031/2/3/4
DS22041B-page 6 © 2008 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 1 MΩ to VL , CL = 60 pF and CS is tied low.
FIGURE 2-1: Input Offset Voltage with
VDD = 3.0V.
FIGURE 2-2: Input Offset V oltage Drift
with VDD = 3.0V and TA
≤
+85°C.
FIGURE 2-3: Input Offset V oltage Drift
with VDD = 3.0V and TA
≥
+85°C.
FIGURE 2-4: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 5.5V.
FIGURE 2-5: Input Offset Voltage vs.
Common Mode Input Voltage with VDD = 1.8V.
FIGURE 2-6: Input Offset Voltage vs.
Output Voltage.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provide d for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In so me graphs or tables, the data presented may be outside the specifie d
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
-150 -120 -90 -60 -30 0 30 60 90 120 150
Input Offset Voltage (μV)
Percentage of Occurences
640 Samples
VDD = 3.0V
VCM = VDD/3
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
-20 -16 -12 -8 -4 0 4 8 12 16 20
Input Offset Drift with Temperature (μV/°C)
Percentage of Occurences
640 Samples
VDD = 3.0V
VCM = VDD/3
TA = -40°C to +85°C
0%
2%
4%
6%
8%
10%
12%
14%
-30 -24 -18 -12 -6 0 6 12 18 24 30
Input Offset Drift with Temperature (μV/°C)
Percentage of Occurences
640 Samples
VDD = 3.0V
VCM = VDD/3
TA = +85°C to +125°C
-400
-300
-200
-100
0
100
200
300
400
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (μV)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
VDD = 5.5V
-400
-300
-200
-100
0
100
200
300
400
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
Common Mode Input Voltage (V)
Input Offset Voltage (μV)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
VDD = 1.8V
-250
-200
-150
-100
-50
0
50
100
150
200
250
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
Input Offset Voltage (μV)
VDD = 1.8V
VDD = 5.5V
VDD = 3.0V
© 2008 Microchip Technology Inc. DS22041B-page 7
MCP6031/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-7: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-8: Input Noise Voltage Density
vs. Common Mode Input Voltage.
FIGURE 2-9: Common Mode Rejection
Ratio, Power Supply Rejection Ratio vs.
Frequency.
FIGURE 2-10: Common Mode Rejection
Ratio, Power Supply Rejection Ratio vs. Ambien t
Temperature.
FIGURE 2-11: Input Bias, Offset Currents
vs. Ambient Temperature.
FIGURE 2-12: Input Bias Current vs.
Common Mode Input Voltage.
100
1,000
1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 1E+5
Frequency (Hz)
Input Noise Voltage Density
(nV/√Hz)
0.1 1 10 100 1k 10k 100k
0
25
50
75
100
125
150
175
200
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/√Hz)
f = 1 kHz
VDD = 5.5V
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
Frequency (Hz)
CMRR, PSRR (dB)
PSRR-
PSRR+
CMRR
VDD = 5.5V
60
65
70
75
80
85
90
95
100
105
110
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR (VDD = 1.8V to 5.5V, VCM = VSS)
CMRR (VDD = 1.8V,
VCM = -0.3V to 2.1V)
CMRR (VDD = 5.5V,
VCM = -0.3V to 5.8V)
1
10
100
1000
10000
25 45 65 85 105 125
Ambient Temperature (°C)
Input Bias and Offset
Currents (pA)
VDD = 5.5V
VCM = VDD
Input Bias Current
In
p
ut Offset Current
10
100
1000
10000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias Current (pA)
TA = +125°C
TA = +85°C
VDD = 5.5V
MCP6031/2/3/4
DS22041B-page 8 © 2008 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-13: Quiescent Current vs
Ambient Temperature.
FIGURE 2-14: Quiescent Current vs.
Power Supply Voltage with VCM = VDD.
FIGURE 2-15: Quiescent Current vs.
Power Supply Voltage with VCM = VSS.
FIGURE 2-16: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-17: DC Open-Loop Gain vs.
Power Supply Voltage.
FIGURE 2-18: DC Open-Loop Gain vs.
Output Voltage Headroom.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
-50-250 255075100125
Ambient Temperature (°C)
Quiescent Current
(μA/Amplifier)
VDD = 5.5V @ VCM = VDD
VDD = 1.8V @ VCM = VDD
VDD = 5.5V @ VCM = VSS
VDD = 1.8V @ VCM = VSS
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
Power Supply Voltage (V)
Quiescent Current
(μA/Amplifier)
VCM = V
DD
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
Power Supply Voltage (V)
Quiescent Current
(μA/Amplifier)
VCM = V
SS
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-20
0
20
40
60
80
100
120
0 0.01 0.1 1 10 100 100
0
100
00
1E+
05
Frequency (Hz)
Open-Loop Gain (V/V)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
Open-Loop Gain
Open-Loop Phase
VDD = 5.5V
0.001 0.01 1k 10k 100k
80
85
90
95
100
105
110
115
120
125
130
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Power Supply Voltage VDD (V)
DC Open-Loop Gain (dB)
RL = 50 kΩ
VSS + 0.2V < VOUT < VDD - 0.2V
80
85
90
95
100
105
110
115
120
125
130
0.00 0.05 0.10 0.15 0.20 0.25
Output Voltage Headroom
VDD - VOUT or VOUT - VSS (V)
DC Open-Loop Gain (dB)
RL
= 50 kΩ
VDD
= 5.5V
VDD
= 1.8V
Large Signal AOL
© 2008 Microchip Technology Inc. DS22041B-page 9
MCP6031/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-19: Channel-to-Channel
Separatio n vs. Fre quency ( MCP6032/4 only).
FIGURE 2-20: Gain Bandwidth Product,
Phase Margin vs. Common Mode Input Voltage.
FIGURE 2-21: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
FIGURE 2-22: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
FIGURE 2-23: Ouput Short Circuit Current
vs. Power Supply Voltage.
FIGURE 2-24: Output Voltage Swing vs.
Frequency.
60
70
80
90
100
110
120
130
100 1,000 10,000
Frequency (Hz)
Channel-to-Channel
Seperation (dB)
Input Referred
0
2
4
6
8
10
12
14
16
18
20
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Gain Bandwidth Product
(kHz)
0
20
40
60
80
100
120
140
160
180
Phase Margin (°)
Gain Bandwidth Product
Phase Mar
g
in
VDD = 5.5V
G = +1 V/V
0
2
4
6
8
10
12
14
16
18
20
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Gain Bandwidth Product
(kHz)
0
10
20
30
40
50
60
70
80
90
Phase Margin (°)
Gain Bandwidth Product
Phase Margin
VDD = 5.5V
G = +1 V/V
0
2
4
6
8
10
12
14
16
18
20
-50-25 0 255075100125
Ambient Temperature (°C)
Gain Bandwidth Product
(kHz)
0
10
20
30
40
50
60
70
80
90
Phase Margin (°)
Gain Bandwidth Product
Phase Margin
VDD = 1.8V
G = +1 V/V
0
5
10
15
20
25
30
35
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Output Short Circuit Current
(mA)
TA = -40°C
TA = +25°C
TA = +85°C
TA = +125°C
0.1
1
10
10 100 1000 10000
Frequency (Hz)
Output Voltage Swing (V P-P)
V
DD
= 1.8V
V
DD
= 3.0V
VDD = 5.5V
1K 10K
MCP6031/2/3/4
DS22041B-page 10 © 2008 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-25: Output Voltage Headroom
vs. Output Current.
FIGURE 2-26: Output Voltage Headroom
vs. Ambient Temperature.
FIGURE 2-27: Slew Rate vs. Ambient
Temperature.
FIGURE 2-28: Small Signal Non-Inverting
Pulse Response.
FIGURE 2-29: Small Signal Inverting Pulse
Response.
FIGURE 2-30: Large Signal Non-Inverting
Pulse Response.
1
10
100
1000
Output Current (A)
Output Voltage Headroom
VDD - VOH, VOL - VSS (mV)
VDD - VOH @ VDD = 1.8V
VOL - VSS @ VDD = 1.8V
VDD - VOH @ VDD = 5.5V
VOL - VSS @ VDD = 5.5V
10
μ
1m 10m
100
µ
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Output Voltage Headroom
VDD - VOH or VSS - VOL (mV)
VDD = 5.5V
RL = 50 kΩ
VSS - VOL
VDD - VOH
1.0
2.0
3.0
4.0
5.0
6.0
7.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/ms)
Falling Edge, VDD = 5.5V
Falling Edge, V
DD
= 1.8V
Rising Edge, VDD = 5.5V
Rising Edge, V
DD
= 1.8V
Time (100 μs/Div)
Output Voltage (20 mV/div)
VDD = 5.5V
G = +1 V/V
Output Voltage (20 mV/div)
VDD = 5.5V
G = -1 V/V
Time (100 μs/Div)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Time (0.5 ms/div)
Output Voltage (V)
VDD = 5.5V
G = +1 V/V
© 2008 Microchip Technology Inc. DS22041B-page 11
MCP6031/2/3/4
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-31: Large Signal Inverting Pulse
Response.
FIGURE 2-32: The MCP6031/2/3/4 family
shows no phase reversal .
FIGURE 2-33: Chip Select (CS) to
Amplifier Output Response Time (MCP6033
only).
FIGURE 2-34: Chip Select (CS) Hysteresis
(MCP6033 only) with VDD = 5.5V.
FIGURE 2-35: Chip Select (CS) Hysteresis
(MCP6033 only) with VDD = 3.0V.
FIGURE 2-36: Chip Select (CS) Hysteresis
(MCP6033 only) with VDD = 1.8V.
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Time (0.5 ms/div)
Output Voltage (V)
VDD = 5.5V
G = -1 V/V
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Time (2 ms/div)
Output Voltage (V)
VIN
VDD = 5.0V
G = +2 V/V
VOUT
-8.0
-7.0
-6.0
-5.0
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
5.0
6.0
Time (1 ms/div)
Chip Select Voltage (V)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Output Voltage (V)
Chip Select
Output On
Output
High-Z
Output
High-Z
VDD = 5.5V
G = +1 V/V
RL = 50 kΩ to V
SS
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select Voltage (V)
Internal CS Switch Ouptut (V)
Output On
Output High-Z
Hysteresis
CS Input
Low to High
VDD = 5.5V
CS Input
High to Low
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
0.00.30.60.91.21.51.82.12.42.73.0
Chip Select Voltage (V)
Ouptut Voltage (V)
Output On
Output High-Z
Hysteresis
CS Input
Low to High
CS Input
High to Low
VDD = 3.0V
0.0
0.3
0.6
0.9
1.2
1.5
0.00.20.40.60.81.01.21.41.61.8
Chip Select Voltage (V)
Ouptut Voltage (V)
Output On
Output High-Z
Hysteresis
CS Input
Low to High
CS Input
High to Low
VDD = 1.8V
MCP6031/2/3/4
DS22041B-page 12 © 2008 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 1 MΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-37: Closed Loop Output
Impedance vs. Frequency. FIGURE 2-38: Measured Input Current vs.
Input Voltage (below VSS).
1
10
100
1000
10000
100000
1 10 100 1000 10000 100000
Frequency (Hz)
Closed Loop Output
Impedance (Ω)
GN:
101 V/V
11 V/V
1 V/V
100k
10k
1k
100
10
1
100k10k1k100101
1.00E-12
1.00E-11
1.00E-10
1.00E-09
1.00E-08
1.00E-07
1.00E-06
1.00E-05
1.00E-04
1.00E-03
1.00E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
VIN (V)
-IIN (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
© 2008 Microchip Technology Inc. DS22041B-page 13
MCP6031/2/3/4
3.0 PIN DESCRIPTIONS
Description s of the pi ns are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3 Chip Select Digital Input
This is a CMOS, Schmitt-trigerred input that places the
device into a low power mode of operation.
3.4 Power Supply Pins
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are at voltages between VSS
and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
MCP6031 MCP6032 MCP6033 MCP6034
Symbol Description
SOT-23-5 DFN,
MSOP,
SOIC
MSOP,
SOIC
DFN,
MSOP,
SOIC
SOIC,
TSSOP
16 1 6 1V
OUT, VOUTA Analog Output (o p amp A)
42 2 2 2V
IN–, VINA– Inverting Input (op amp A)
33 3 3 3V
IN+, VINA+ Non-inverting Input (op amp A)
57 8 7 4 V
DD Positive Power Supply
—— 5 — 5 V
INB+ Non-inverting Input (op amp B)
—— 6 — 6 VINB–Inverting Input (op amp B)
—— 7 — 7 V
OUTB Analog Output (op amp B)
—— — — 8 V
OUTC Analog Output (o p amp C)
—— — — 9 V
INC– Inverting Input (op amp C)
—— — — 10 V
INC+ Non-inverting Input (op amp C)
24 4 4 11 V
SS Negative Power Supply
—— — — 12 V
IND+ Non-inverting Input (op amp D)
—— — — 13 V
IND– Inverting Input (op amp D)
—— — — 14 V
OUTD Analog Output (o p amp D)
—— — 8 — CS
Chip Select
— 1, 5, 8 — 1, 5 — NC No Internal Connection
MCP6031/2/3/4
DS22041B-page 14 © 2008 Microchip Technology Inc.
4.0 APPLICATION INFORMATION
The MCP6031/2/3/4 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-power, high precision
applications.
4.1 Rail-to-Rail Input
4.1.1 PHASE REVERASAL
The MCP6031/2/3/4 op amps are desig ned to prevent
phase reversal when the inpu t pins exceed the supp ly
voltages. Figure 2-32 shows the input voltage exceed-
ing the supply voltage without any phase reversal.
4.1.2 INP UT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltage that go too far above
VDD; their breakdown voltage is high enough to allow
normal operation and low enough to bypass ESD
events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must li mit the
voltages and currents at the VIN+ and VIN- pins (see
Absolute Maximum Ratings at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN-) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN-) from going too far above VDD.
When implemented as shown, resistors R1 and R2 also
limit the current through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC currents into the input pins (VIN+ and
VIN-) should be very small. A significant amount of
current can flow out of the inputs when the common
mode voltage (VCM) is below ground (VSS).
4.1.3 NORMAL OPERATION
The input stage of the MCP6031/2/3/4 op amps uses
two differential input stages in parallel. One operates at
a low common mode input voltage (VCM), while the
other operates at a high VCM. With this topology, the
device operates with a V CM up to 300 mV above VDD
and 300 mV below VSS. The input offset voltage is
measured at VCM = VSS – 0.3V and VDD + 0.3V to
ensure proper operation.
There are two transitions in input behavior as VCM is
changed. The first occurs, when VCM is near
VSS + 0.4V, a nd the second occurs when VCM is near
VDD – 0.5V. For the best distortion performance with
non-inverting gains, avoid these regions of operation.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN–
V1
MCP603X
R1
VDD
D1
R1>VSS – (minimum expected V1)
2mA
R2>VSS – (minimum expected V2)
2mA
V2R2
D2
R3
© 2008 Microchip Technology Inc. DS22041B-page 15
MCP6031/2/3/4
4.2 Rail-to-Rail Output
The output voltage range of the MCP6031/2/3/4 op
amps is VSS + 10 mV (minimum) and VDD – 10 mV
(maximum) when RL=50kΩ is connected to VDD/2
and VDD = 5.5V. Refer to Figures 2-25 and 2-26 for
more information.
4.3 Output Loads and Battery Life
The MCP6031/2/3/4 op amp family has outstanding
quiescent current, which supports battery-powered
applications. There is minimal quiescent current glitch-
ing when Chip Select (CS) is raised or lowered. This
prevents excessive current draw, and reduced battery
life, when the part is turned off or on.
Heavy resistive loads at the output can cause exces-
sive battery drain. Driving a D C voltage of 2.5V across
a 100 kΩ load resistor will cause the sup ply current to
increase by 25 µA, depleting the battery 28 times as
fast as IQ (0.9 µA, typical) alone.
High frequency signals (fast edge rate ) across capaci-
tive loads will also significantly increase supply current.
For instance, a 0.1 µF capacitor at the output presents
an AC impedance of 15.9 kΩ (1/2πfC) to a 100 Hz
sinewave. It can be shown that the average power
drawn from the battery by a 5.0 Vp-p sinewave
(1.77 Vrms), under these conditions, is
EQUATION 4-1:
This will drain the battery abou t 12 times as fast as IQ
alone.
4.4 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produce s gain peaking in the frequency
response, with overshoot and ringing in the step
response. While a unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, all gains show the same
general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitance load.
FIGURE 4-3: Output resistor, RISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g ., -1 V/V gives GN = +2 V/V).
FIGURE 4-4: Recommended RISO values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable . Bench evaluation and simula-
tions with the MCP6031/2/3/4 SPICE macro model are
very helpful.
4.5 MCP6033 Chip Select
The MCP6033 is a single op amp with Chip Select
(CS). When CS is pulled high, the supply current drops
to 0.4 nA (typical) and flows through the CS pin to VSS.
When this happens, the amplifier output is put into a
high impedance state. By pulling CS low, the amplifier
is enabled. If the CS pin is left floating, the amplifier will
not operate properly. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
PSupply = (VDD - VSS) (IQ + VL(p-p) f CL )
= (5V)(0.9 µA + 5.0Vp-p · 100Hz · 0.1µF)
= 4.5 µW + 50 µW
VIN
RISO VOUT
MCP603X
CL
–
+
1000
10000
100000
1000000
1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
Normalized Load Capacitance; CL/GN (F)
Recommended R ISO (Ω)
GN:
1 V/V
2 V/V
≥ 5 V/V
10p 100p 1n 10n 100n 1µ
1M
100k
10k
1k
MCP6031/2/3/4
DS22041B-page 16 © 2008 Microchip Technology Inc.
4.6 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) shou ld have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high frequency performance. It can use a bulk
capacitor (i.e., 1 µF or larger) within 100 mm to provide
large, slow currents. This bulk capacitor can be shared
with other analog parts.
4.7 Unused Op Amps
An unused op amp in a quad package (MCP6034)
should be configured as shown in Figure 4-5. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-5: Unused Op Amps.
4.8 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow; which is greater than the
MCP6031/2/3/4 family’s bias current at +25°C
(±1.0 pA, typical).
The easiest way to reduce surface leaka ge is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-6.
FIGURE 4-6: Example Guard Ring Layout
for Inverting Gain.
1. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (V IN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
2. Inverting Gain and T ransimpedance Gain Ampli-
fiers (convert current to voltage, such as photo
detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases th e guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
VDD
VDD
¼ MCP6034 (A) ¼ MCP6034 (B)
R1
R2
VDD
VREF
VREF VDD R2
R1R2
+
------------------
⋅=
Guard Ring VIN–V
IN+ VSS
© 2008 Microchip Technology Inc. DS22041B-page 17
MCP6031/2/3/4
4.9 Application Circuits
4.9.1 BATTERY CURRENT SENSING
The MCP6031/2/3/4 op amps’ Common Mode Input
Range, which goes 0.3V beyond both supply rails,
supports their use in high side and low side battery
current sensing applications. The ultra low quiescent
current (0.9 µA, typical) helps prolong battery life, an d
the rail-to-rail output supports detection of low currents.
Figure 4-7 shows a high side battery current sensor
circuit. The 10Ω resistor is sized to minimize power
losses. The battery current (IDD) through the 10Ω
resistor causes its top terminal to be more negative
than the bottom terminal. This keeps the common
mode input voltage of the op amp below VDD, which is
within its allowed range. The outpu t of the o p amp will
also be below VDD, which is within its Maximum Output
Voltage Swing specification.
FIGURE 4-7: High Side Battery Current
Sensor.
4.9.2 PRECISION COMPARATOR
Use high gain before a co mparator to improve the lat-
ter’s input of fset performance. Figure 4-8 shows a gain
of 11 V/V placed before a comparator. The reference
voltage VREF can be any value between the supply
rails.
FIGURE 4-8: Precision, Non-inverting
Comparator.
4.9.3 DRIVING MCP3421 ΔΣ A/D
CONVERTER
A RSH and CSH snubber reduces the output impedance
of MCP6031 op amp, which reduces the gain error
caused by switching transients, which occur at the
MCP3421 ADC's sampling rate. The snubber also
maintains feedback stability and avoids AC response
peaking and step response overshoot and ringing
(caused by the op amp’s inductive output impedance
resonating with the ADC’s input capacitance). The cost
for this improvement is low . Best of all, using an op amp
with higher supply current is avoided. See Figure 4-9.
This figure also includes a resistor to balance the
impedance at the ADC's inputs (RBAL) at the sampling
frequency; it may not be needed in all designs.
FIGURE 4-9: Driving the MCP3421 using
an R-C Snubber.
VDD
IDD
MCP6031
100 kΩ
1MΩ
1.4V VOUT
10Ω
to
5.5V
IDD VDD VOUT
–
10 V/V()10
Ω
()
⋅
------------------------------------------=
VIN
1MΩVOUT
MCP6031
100 kΩMCP6541
VREF
VIN
MCP6031
RSH
CSH
1.00 kΩ
2.2 µF
RBAL
1.00 kΩ
MCP3421
ΔΣ
1.00 kΩZIND
2.25 MΩ
MCP6031/2/3/4
DS22041B-page 18 © 2008 Microchip Technology Inc.
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6031/2/3/4 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the MCP6031/2/3/4
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.micro chip.com/filterlab, th e
FilterLab d esign tool provides fu ll schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can b e
used with the macro model to simulate actual filter
performance.
5.3 Mindi™ Circuit Designer &
Simulator
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
5.4 MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparasion
reports. Helpful links are also provided for Datasheets,
Purchase, and Sampling of Microchip parts.
5.5 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Two of our boards that are especially us eful are:
•P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
•P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evalu-
ation Board
5.6 Application Notes
The following Microchip Analog Design Note and
Application Notes are available on the Microchip web
site at www.microchip. com/appnotes and are recom-
mended as supplemental reference resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
© 2008 Microchip Technology Inc. DS22041B-page 19
MCP6031/2/3/4
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
8-Lead MSOP Example:
XXXXXX
YWWNNN
6031E
809256
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6033E
SN^^0809
256
Legend: XX...X Customer-specific information
Y Year code (last dig it of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
5-Lead SOT-23 (MCP6031)Example:
XXNN EA25
Device E-Temp
Code
MCP6031T-E/OT EANN
Example:
ABV
809
25
8-Lead 2x3 DFN (MCP6031 & MCP6033)
XXX
YWW
NN
MCP6031/2/3/4
DS22041B-page 20 © 2008 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead TSSOP (MCP6034)Example:
14-Lead SOIC (150 mil) (MCP6034)Example:
XXXXXXXXXX
YYWWNNN
XXXXXX
YYWW
NNN
6034EST
0711
256
XXXXXXXXXX MCP6034
0711256
Legend: XX...X Customer-specific information
Y Year code (last dig it of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
E/SL^^
3
e
© 2008 Microchip Technology Inc. DS22041B-page 21
MCP6031/2/3/4
/HDG3ODVWLF6PDOO2XWOLQH7UDQVLVWRU27>627@
1RWHV
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MCP6031/2/3/4
APPENDIX A: REVISION HISTORY
Revision B (March 2008)
The following is the list of modificatio ns:
1. Added SOT-23-5 and 2x3 DFN packages.
2. Added test circuits.
3. Corrected VOS temperature drift information.
4. Added Section 4.9.3.
5. Updated Package Marking Information.
6. Updated all package outline drawings and
added package outline drawings for SOT-23-5
and 2x3 DFN packages.
7. Added Landing Pattern drawings for 2x3 DFN
and 8-lead SOIC packages.
8. Updated information in Product Identification
System for SOT-23-5 and 2x3 DFN packages.
Revision A (March 2007)
• Original Release of this Document.
MCP6031/2/3/4
DS22041B-page 30 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS22041B-page 31
MCP6031/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6031: Single Op Amp
MCP6031T: Single Op Amp (Tape and Reel)
MCP6032: Dual Op Amp
MCP6032T: Dual Op Amp (Tape and Reel)
MCP6033: Single Op Amp with Chip Select
MCP6033T: Single Op Amp with Chip Select
(Tape and Reel)
MCP6034: Quad Op Amp
MCP6034T: Quad Op Amp (Tape and Reel)
Temperature Range: E = -40°C to +125°C
Package: MC = Plastic Dual Flat, No Lead, (2x3 DFN ) 8-lead **
MS = Plastic MSOP, 8-lead
OT = Plastic Small Outline Transistor, 5-lead *
SL = Plastic SOIC (150 mil Body), 14-lead
SN = Plastic SOIC, (150 mil Body), 8-lead
ST = Plastic TSSOP (4.4mm Body), 14-lead
* This package is only available on the MCP6031 device.
** These packages are on ly available on the MCP6031 and
MCP6033 devices.
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP603 1-E/SN: 8LD SOI C package.
b) MCP6031T-E /SN: Tape and Reel,
8LD SOIC package.
c) MCP6031-E/MS: 8LD MSOP package.
d) MCP603 1T-E/MS: Tape and Reel,
8LD MSOP package.
e) MCP6031-E/MC: 8LD DFN package.
f) MCP6031T-E/MC: Tape and Reel,
8LD DFN package.
g) MCP6031T-E /OT: Tape and Reel,
5-LD SOT-23 package.
a) MCP603 2-E/SN: 8LD SOI C package.
b) MCP6032T-E/SN: Tape and Reel,
8LD SOIC package.
c) MCP6032-E/MS: 8LD MSOP package
d) MCP603 2T-E/MS: Tape and Reel
8LD MSOP package.
a) MCP603 3-E/SN: 8LD SOI C package.
b) MCP6033T-E /SN: Tape and Reel,
8LD SOIC package.
c) MCP6033-E/MS: 8LD MSOP package.
d) MCP603 3T-E/MS: Tape and Reel,
8LD MSOP package.
e) MCP6033-E/MC: 8LD DFN package.
f) MCP6033T-E/MC: Tape and Reel,
8LD DFN package.
a) MCP6034-E/SL: 14LD SOIC package.
b) MCP6034T-E/SL: Tape and Reel,
14LD SOIC package.
c) MCP6034-E/ST: 14LD TSSOP package.
d) MCP6034T-E /ST: Tape and Reel,
14LD TSSOP package.
MCP6031/2/3/4
DS22041B-page 32 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS22041B-page 33
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defen d, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICST ART, PRO MA TE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts
allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:200 2 certif ication for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and
analog product s. In addition, Microchip ’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS22041B-page 34 © 2008 Microchip Technology Inc.
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