CY7C64713
EZ-USB FX1™ USB Microcontroller
Full Speed USB Peripheral Controller
Cypress Semiconductor Corporation 198 Champion Court San Jose,CA 95134-1709 408-943-2600
Document #: 38-08039 Rev. *I Revised March 4, 2011
Features
Single chip integrated USB transceiver, SIE, and enhanced
8051 microprocessor
Fit, form, and function upgradable to the FX2LP (CY7C68013A)
Pin compatible
Object code compatible
Functionally compatible (FX1 functionality is a subset of the
FX2LP)
Draws no more than 65 mA in any mode, maki ng the FX1
suitable for bus powered applications
Software: 8051 runs from internal RAM, which is:
Downloaded using USB
Loaded from EEPROM
External memory device (128 pin configuration only)
16 KB of on-chip code/data RAM
Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
Buffering options: double, triple, and quad
Additional programmable (BULK/INTERRUPT) 64-byte
endpoint
8- or 16-bit external data interface
Smart media standard ECC generation
GPIF
Allows direct connection to most parallel interfaces; 8- and
16-bit
Programmable waveform descriptors and configuration
registers to define waveforms
Supports multiple ready (RDY) inputs and Control (CTL)
outputs
Integrated, industry standard 8051 with enhanced features:
Up to 48 MHz clock rate
Four clocks for each instruction cycle
Tw o USARTS
Three counters or timers
Expanded interrupt system
Two dat a po inters
3.3 V operation with 5 V tolerant inputs
Smart SIE
Vectored USB interrupts
Separate data buffers for the setup and DATA portions of a
CONTROL transfer
Integrated I2C controller, running at 100 or 400 KHz
48 MHz, 24 MHz, or 12 MHz 8051 operation
Four integrated FIFOs
Brings glue and FIFOs inside for lower system cost
Automatic conversion to and from 16-bit buses
Master or slave operation
FIFOs can use externally supplied clock or asynchronous
strobes
Easy interface to ASIC and DSP ICs
Vectored for FIFO and GPIF Interrupts
Up to 40 general purpose IOs (GPIO)
Four package options:
128-pin TQFP
100-pin TQFP
56-pin SSOP
56-pin QFN Pb-free
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CY7C64713
Document #: 38-08039 Rev. *I Page 2 of 58
Address (16)
x20
PLL
/0.5
/1.0
/2.0
8051 Core
12/24/48 MHz,
four clocks/cycle
I
2
C
VCC
1.5k
D+
D–
Address (16) / Dat a Bus (8)
FX1
GPIF
CY
Smart
USB
Engine
USB
XCVR
16 KB
RAM
4 kB
FIFO
Integrated
full speed XCVR
Additional IOs (24)
ADDR (9)
CTL (6)
RDY (6)
8/16
Data (8)
24 MHz
Ext. XTAL
Enhanced USB core
Simplifies 8051 code ‘Soft Configuration’
Easy firmware changes FIFO and endpoint memory
(master or slave operation)
Up to 96 MBytes
burst rate
General
programmable I/F
to ASIC/DSP or bus
standards such as
ATAPI, EPP, et c.
Abundant I/O
including two USARTS
High performance micro
using st andard tools
with lower-power options
Master
connected for
enumeration
ECC
Logic Block Diagram
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CY7C64713
Document #: 38-08039 Rev. *I Page 3 of 58
Contents
Functional Description ................... ... .............. ... .. ............4
Applications ...................................................................... 4
Functional Overview .............. ............................ .. ... .........4
USB Signaling Speed ..................................................4
8051 Microprocessor ...................................................4
I2C Bus .......... ... ..................................................... ......5
Buses ..........................................................................5
USB Boot Methods ......................................................5
ReNumeration™ ..........................................................5
Bus-powered Applications ...........................................6
Interrupt System ..........................................................6
Reset and Wakeup ......... ... ..........................................7
Program/Data RAM ........... .. ............................ ... ... ......8
Endpoint RAM ............. ............................ ... ...............11
External FIFO Interface ............. ... ... ..........................11
GPIF .......................................................................... 12
ECC Generation .......... ... ............................ ... ............12
0.0.0.2 USB Uploads and Downloads .......................13
0.0.0.2 Autopointer Access .......................................1 3
0.0.0.2 I2C Controller .................................................13
Compatible with Previous Generation EZ-USB FX2 .13
Pin Assignments ............................................................13
CY7C64713 Pin Definitions ............................................19
Register Summary ....................... ............................ ... ... .26
Absolute Maximum Ratings ..........................................33
Operating Conditi ons ................................... ... ...............33
DC Characteristics ................................ ... ... ..................33
USB Transceiver .......................................................33
AC Electrical Characteristics ....................... ... ..............34
USB Transceiver .......................................................34
PORTC Strobe Feature Timings .............. ... ... ... ........37
GPIF Synchronous Signals .......................................38
Slave FIFO Synchronous Read .................................39
Slave FIFO Asynchronous Read ...............................40
Slave FIFO Synchronous Write .................................41
Slave FIFO Asynchronous Write ...............................42
Slave FIFO Synchronous Packet End Strobe ...........42
Slave FIFO Asynchronous Packet End Strobe .........44
Slave FIFO Output Enable ........................................44
Slave FIFO Address to Flags/Data ............................44
Slave FIFO Synchronous Address ............................45
Slave FIFO Asynchronous Address ..........................45
Sequence Diagram ....................................................46
Ordering Information ......................................................50
Ordering Code Definitions .........................................50
Package Diagrams ..........................................................51
Quad Flat Package No Leads (QFN)
Package Design Notes ...................................................54
Acronyms ........................................................................56
Document Conventions .................. ... ............................56
Units of Measure ............. ... ............................ ... ... .....56
Document History Page .............................. .. ... ..............57
Sales, Solutions, and Legal Information ......................58
Worldwide Sales and Design Support .......................58
Products .................................................................... 58
PSoC Solutions ............ .......................................... ...58
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CY7C64713
Document #: 38-08039 Rev. *I Page 4 of 58
Functional Description
EZ-USB FX1 (CY7C64713) is a full speed, highly integrated,
USB microcontroller. By in tegrating the USB transceiver, Serial
Interface Engine (SIE), enhanced 8051 microcontroller, and a
programmable peripheral interface in a single chip, Cypress has
created a very cost effective solution that provides superior
time-to-market advantages.
The EZ-USB FX1 is more economical, because it incorporates
the USB transceiver and provides a smaller footprint solution
than the USB SIE or external transceiver implementations. With
EZ-USB FX1, the Cypress Smart SIE handles most of the USB
protocol in hardware, freeing the embedded microcontroller for
application specific functions and decreasing the development
time to ensure USB compatibility.
The General Programmable Interface (GPIF) and Master/Slave
Endpoint FIFO (8 or 16-bit data bus) provide an easy and
glueless interface to popular interfaces such as ATA , U T O P IA ,
EPP, PCMCIA, and most DSP/processors.
Four Pb-free packages are defined for the family: 56 SSOP, 56
QFN, 100 TQFP, and 128 TQFP.
Applications
DSL modems
ATA interface
Memory card readers
Legacy conversion devices
Home PNA
Wireless LAN
MP3 play ers
Networking
The Reference Designs section of the cypress website provides
additional tools for typical USB applications. Each reference
design comes complete with firmware source and object code,
schematics, and documentation. Please visit
http://www.cypress.com for more information.
Functional Overview
USB Signaling Speed
FX1 operates at one of the three rates defined in the USB S peci-
fication Revi si on 2.0, dated April 27, 2000:
Full speed, with a signaling bit rate of 12 Mbps.
FX1 does not support the low speed signaling mode of 1.5 Mbps
or the high speed mode of 480 Mbps.
8051 Microprocessor
The 8051 microprocessor e mbedded in the FX1 family has 256
bytes of register RAM, an expanded interrupt system, three
timer/counters, and two USARTs.
8051 Clock Frequency
FX1 has an on-chip oscillator circuit that uses an external 24
MHz (±100 ppm) crystal with the following characteristics:
Parallel resonant
Fundamental mode
500 μW drive level
12 pF (5% tolerance) load capacitors.
An on-chip PLL multiplies the 24 MHz oscill ato r up to 480 MHz,
as required by the transceiver/PHY, and the internal counters
divide it down for use as the 8051 clock. The default 8051 clock
frequency is 12 MHz. The clock frequency of the 8051 is dynam-
ically changed by the 8051 th rough the CPUCS register.
The CLKOUT pin, which is three-stated and inverted using the
internal control bits, outputs the 50% duty cycle 8051 clock at the
selected 8051 clock frequency whi ch is 48, 24, or 12 MHz.
USARTS
FX1 contains two standard 8051 USARTs, addressed by S pecial
Function Register (SFR) bits. The USART interface pins are
available on separate I/O pins, and are not multiplexed with port
pins.
UART0 and UART1 can operate using an internal clock at 230
KBaud with no more than 1% baud rate error. 230 KBaud
operation is achieved by an inte rnally derived clock source that
generates overflow pulses at the appropriate time. T he internal
clock adjusts for the 8051 cl ock rate (4 8, 24, 12 MHz) su ch that
it always presents the correct frequency for 230-KBaud
operation.[1]
Special Function Registers
Certain 8051 SFR addresses are populated to provide fast
access to critical FX1 functions. These SFR additions are shown
in Table 1 on page 5. Bold type indicates non-standard,
enhanced 8051 registers. The two SFR rows that end with ‘0’ and
‘8’ contain bit addressable registers. The four I/O ports A–D use
the SFR addresses used in the standard 8051 for ports 0–3,
which are not implemented in the FX1. Because of the faster and
more efficient SFR addressing, the FX1 I/O ports are not addres-
sable in the external RAM space (using the MOVX instruction).
Notes
1. 115-KBaud operation is also possible by programming the 8051 SMOD0 or SMOD1 bits to a ‘1’ for UART0 and UART1, respectively.
2. The I2C bus SCL and SDA pins must be pulled up, even if an EEPROM is not connected. Otherwise this detection method does not work properly.
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Document #: 38-08039 Rev. *I Page 5 of 58
Figure 1. Crystal Configuration
I2C Bus
FX1 supports the I2C bus as a master only at 100/400 KHz. SCL
and SDA pins have open drain outputs and hysteresis inputs.
These signals must be pulled up to 3.3 V, even if no I2C device
is connected.
Buses
All packages: 8 or 16-bit ‘FIFO’ bidirectional data bus, multi-
plexed on I/O ports B and D. 128 pin package: adds 16-bit output
only 8051 address bus, 8-bit bidirectional data bus.
USB Boot Methods
During the power up sequence, internal logic checks the I2C port
for the connection of an EEPROM whose first byte is either 0xC0
or 0xC2. If found, it uses the VID/PID/DID values in the EEPROM
in place of the internally stored values (0xC0). Alternatively, it
boot-loads the EEPROM contents into an internal RAM (0xC 2).
If no EEPROM is detected, FX1 enumerates using internally
stored descriptors. The default ID values for FX1 are
VID/PID/DID (0x04B4, 0x6473, 0xAxxx where xxx=Chip
revision).[2]
ReNumeration™
Because the FX1’s configuration is soft, one chip can take on the
identities of multiple distinct USB devices.
When first plugged into the USB, the FX1 enumerates automat-
ically and downloads firmware and the USB descriptor tables
over the USB cable. Next, the FX1 enumerates a gain, this time
as a device defined by the downloaded information. This
patented two step process, called ReNumeration, happens
instantly when the device is plugged in, with no indication that
the initial download step has occurred.
Table 1. Special Function Registers
x8x 9x Ax Bx Cx Dx Ex Fx
0IOA IOB IOC IOD SCON1 PSW ACC B
1SP EXIF INT2CLR IOE SBUF1
2DPL0 MPAGE INT4CLR OEA
3DPH0 OEB
4DPL1 OEC
5DPH1 OED
6DPS OEE
7PCON
8 TCON SCON0 IE IP T2CON EICON EIE EIP
9 TMOD SBUF0
ATL0AUTOPTRH1 EP2468STAT EP01STAT RCAP2L
BTL1AUTOPTRL1 EP24FIFOFLGS GPIFTRIG RCAP2H
CTH0reserved EP68FIFOFLGS TL2
DTH1AUTOPTRH2 GPIFSGLDATH TH2
ECKCON AUTOPTRL2 GPIFSGLDATLX
Freserved AUTOPTRSETUP GPIFSGLDATLNOX
12 pF
12 pF
24 MHz
20 × PLL
C1 C2
12-pF capacitor values assumes
a trace capacitance of 3 pF per
side on a four layer FR4 PCA
Table 2. Default ID Values for FX1
Default VID/PID/DID
Vendor ID 0x04B4 Cypress Semiconductor
Product ID 0x6473 EZ-USB FX1
Device
release 0xAnnn Depends on chip revision (nnn = chip
revision where first silicon = 001)
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T wo control bits in the USBCS (USB Control and S tatus) register
control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To
reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit
to indicate if the firmware or the Default USB Device handles
device requests over endpoint zero:
RENUM = 0, the Default USB Device handles device requests
RENUM = 1, the firmware handles device requests
Bus-powered Applications
The FX1 fully supports bus powered designs by enumerating
with less than 100 mA as required by the USB specification.
Interrupt System
INT2 Interrupt Request and Enable Registers
FX1 implements an autovector feature for INT2 and INT4. There
are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors.
See EZ-USB Technical Reference Manual (TRM) for more
details.
USB-Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. The
FX1 provides a second level of interrupt vectoring, called
Autovectoring, to save code and processing time that is normally
required to identi fy the indivi dual USB i nterrupt source. When a
USB interrupt is asserted, the FX1 push es the pro gram counte r
on to its stack and then jumps to address 0x0043, where it
expects to find a “jump” instruction to the USB Interrupt service
routine.
The FX1 jump instruction is encoded as shown in Table 3.
If Autovectoring is enabled (AV2EN = 1 in the INTSETUP
register), the FX1 substitutes its INT2VEC byte. Therefore, if the
high byte (“page”) of a jump table address is preloaded at
location 0x0044, the automatically inserted INT2VEC byte at
0x0045 directs the jump to the correct address out of the 27
addresses within the page.
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual
USB-interrupt sources, the FIFO/GPIF interrupt is shared among
14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, such
as the USB Interrupt, can employ autovectoring. Table 4 on page
7 shows the priority and INT4VEC values for the 14 FIFO/GPIF
interrupt sources.
Table 3. INT2 USB Interrupts
USB INTERRUPT TABLE FOR INT2
Priority INT2VEC Value Source Notes
1 00 SUDAV Setup Data Available
2 04 SOF Start of Frame
3 08 SUTOK Setup Token Received
4 0C SUSPEND USB Suspend request
5 10 USB RESET Bus reset
6 14 Reserved
7 18 EP0ACK FX1 ACK’d the CONTROL Handshake
8 1C Reserved
9 20 EP0-IN EP0-IN ready to be loaded with data
10 24 EP0-OUT EP0-OUT has USB data
11 28 EP1-IN EP1-IN ready to be loaded with data
12 2C EP1-OUT EP1-OUT has USB data
13 30 EP2 IN: buffer available. OUT: buffer has data
14 34 EP4 IN: buffer available. OUT: buffer has data
15 38 EP6 IN: buffer available. OUT: buffer has data
16 3C EP8 IN: buffer available. OUT: buffer has data
17 40 IBN IN-Bulk-NAK (any IN endpoint)
18 44 Reserved
19 48 EP0PING EP0 OUT was Pinged and it NAK’d
20 4C EP1PING EP1 OUT was Pinged and it NAK’d
21 50 EP2PING EP2 OUT was Pinged and it NAK’d
22 54 EP4PING EP4 OUT was Pinged and it NAK’d
23 58 EP6PING EP6 OUT was Pinged and it NAK’d
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Document #: 38-08039 Rev. *I Page 7 of 58
If Autovectoring is enabled (AV4EN = 1 in the INTSETUP
register), the FX1 substitutes its INT4VEC byte. Therefore, if the
high byte (“page”) of a jump-table address is preloaded at
location 0x0054, the automatically inserted INT4VEC byte at
0x0055 directs the jump to the correct address out of the 14
addresses within the page. When the ISR occurs, the FX1
pushes the program counter onto its stack and then jumps to
address 0x0053, where it expects to find a “jump” instructio n to
the ISR Interrupt service routine.
Reset and Wakeup
Reset Pin
The input pin, RESET#, resets the FX1 when asserted. This pin
has hysteresis and is active LOW. When a crystal is used with
the CY7C64713, the reset period must allow for the stabilization
of the crystal and the PLL. This reset period must be approxi-
mately 5 ms after VCC has reached 3.0 V olts. If the crystal input
pin is driven by a clock signal the internal PLL stabilizes in 200
μs after VCC has reached 3.0 V[3]. Figure 2 shows a power on
reset condition and a reset applied during operation. A power on
reset is defined as the time a reset is asserted when power is
being applied to the circuit. A powered reset is defined to be
when the FX1 has been previously powered on and operating
and the RESET# pin is asserted.
Cypress provides an application note which describes and
recommends power on reset implementation and is found on the
Cypress web site. While the application note discusses the FX2,
the information provided applies also to the FX1. For more infor-
mation on reset implementation for the FX2 family of products
visit http://www.cypress.com.
24 5C EP8PING EP8 OUT was Pinged and it NAK’d
25 60 ERRLIMIT Bus errors exceeded the programmed limit
26 64
27 68 Reserved
28 6C Reserved
29 70 EP2ISOERR ISO EP2 OUT PID sequence error
30 74 EP4ISOERR ISO EP4 OUT PID sequence error
31 78 EP6ISOERR ISO EP6 OUT PID sequence error
32 7C EP8ISOERR ISO EP8 OUT PID sequence error
Table 4. Individual FIFO/GPIF Interrupt Sources
Priority INT4VEC Value Source Notes
1 80 EP2PF Endpoint 2 Programmable Flag
2 84 EP4PF Endpoint 4 Programmable Flag
3 88 EP6PF Endpoint 6 Programmable Flag
4 8C EP8PF Endpoint 8 Programmable Flag
5 90 EP2EF Endpoint 2 Empty Flag
6 94 EP4EF Endpoint 4 Empty Flag
7 98 EP6EF Endpoint 6 Empty Flag
8 9C EP8EF Endpoint 8 Empty Flag
9 A0 EP2FF Endpoint 2 Full Flag
10 A4 EP4FF Endpoint 4 Full Flag
11 A8 EP6FF Endpoint 6 Full Flag
12 AC EP8FF Endpoint 8 Full Flag
13 B0 GPIFDONE GPIF Operation Complete
14 B4 GPIFWF GPIF Waveform
Table 3. INT2 USB Interrupts (continued)
USB INTERRUPT TABLE FOR INT2
Priority INT2VEC Value Source Notes
Note
3. If the external clock is powered at the same time as the CY7C64713 and has a stabilization wait period. It must be added to the 200 μs.
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Figure 2. Reset Timing Plots
Wakeup Pins
The 8051 puts itself and the rest of the chip into a power down
mode by setting PCON.0 = 1. This stops the oscillator and
PLL. When WAKEUP is asserted by external log ic, the oscil-
lator restarts, after the PLL stabilizes, and then the 8051
receives a wakeup interrupt. This applies irrespective of
whether the FX1 is connected to the USB or not.
The FX1 exits the power down (USB suspend) state using one
of the following methods:
USB bus activity (if D+/D– lines are left floating, noise on
these lines may indicate activity to the FX1 and initiate a
wakeup).
External logic asserts the WAKEUP pin.
External logic asserts the PA3/WU2 pin.
The second wakeup pin, WU2, can also be configured as a
general purpose I/O pin. This allows a simple external R-C
network to be used as a periodic wakeup source. Note that
WAKEUP is by default active LOW.
Program/Data RAM
Size
The FX1 has 16 KBytes of internal program/data RAM, where
PSEN#/RD# signals are internally ORed to allow the 8051 to
access it as both program and data memory. No USB control
registers appear in this space.
Two memory maps are shown in the following diagrams:
Figure 3 Internal Code Memory, EA = 0
Figure 4 External Code Memory, EA = 1.
Internal Code Memory, EA = 0
This mode implements the internal 16 KByte block of RAM
(starting at 0) as combined code and data memory. When the
external RAM or ROM is added, the external read and write
strobes are suppressed for memory spaces that exist inside
the chip. This allows the use r to connect a 6 4 KByte memory
without requiring the address decodes to keep clear of internal
memory spaces.
Only the internal 16 KBytes and scratch pad 0.5 KBytes RAM
spaces have the following access:
USB download
USB upload
Setup data pointer
I2C interface boot load
VIL
0 V
3.3 V
3.0 V
TRESET
VCC
RESET#
Power on Reset
TRESET
VCC
RESET# VIL
Powered Reset
3.3 V
0 V
Table 5. Reset Timing Values
Condition TRESET
Power On Reset with crystal 5 ms
Power On Reset with external
clock 200 μs + Clock stability time
Powered Reset 200 μs
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Figure 3. Internal Code Memory, EA = 0.
Inside FX1 Outside FX1
7.5 KBytes
USB regs and
4K FIFO buffers
(RD#,WR#)
0.5 KBytes RAM
Data (RD#,WR#)*
(OK to populate
data memory
here—RD#/WR#
strobes are not
active)
40 KBytes
External
Data
Memory
(RD#,WR#)
(Ok to populate
data memory
here—RD#/WR#
strobes are not
active)
16 KBytes RAM
Code and Data
(PSEN#,RD#,WR#)*
48 KBytes
External
Code
Memory
(PSEN#)
(OK to populate
program
memory here—
PSEN# strobe
is not active)
FFFF
E200
E1FF
E000
3FFF
0000 Data Code
*SUDPTR, USB upload/download, I2C interface boot access
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External Code Memory, EA = 1
The bottom 16 KBytes of program memory is external, and therefore the bottom 16 KBytes of internal RAM is accessible only as
data memory.
Figure 4. External Code Memory, EA = 1
Figure 5. Register Addresses
FFFF
E800
E7BF
E740
E73F
E700
E6FF
E500
E4FF
E480
E47F
E400
E200
E1FF
E000
E3FF
EFFF 2 KBytes RESERVED
64 Bytes EP0 IN/OUT
64 Bytes RESERVED
8051 Addressable Registers
Reserved (128)
128 bytes GPIF Waveforms
512 bytes
8051 xdata RAM
F000
(512)
Reserved (512)
E780 64 Bytes EP1OUT
E77F
64 Bytes EP1IN
E7FF
E7C0
4 KBytes EP2-EP8
buffers
(8 x 512)
Not all Space is available
for all transfer types
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Endpoint RAM
Size
3 × 64 bytes (Endpoints 0 and 1)
8 × 512 bytes (Endpoints 2, 4, 6, 8)
Organization
EP0—Bidirectional endpoint zero, 64 byte buffer
EP1IN, EP1OUT—64 byte buffers, bulk or interrupt
EP2, 4, 6, 8—Eight 512-byte buffers, bulk, interrupt, or
isochronous, of which only the transfer size is available.
EP4 and EP8 are double buffered, while EP2 and 6 are either
double, triple, or quad buffered. Regardless of the physical size
of the buffer , each endpoint buffer accommodates only one full
speed packet. For bulk endpoints, the maximum number of
bytes it can accommodate is 64, even though the physical
buffer size is 512 or 1024. For an ISOCHRONOUS endpoint
the maximum number of bytes it can accommodate is 1023.
For endpoint configuration options, see Figure 6.
Setup Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup
data from a CONTROL transfer.
Default Alternate Settings
In the following table, ‘0’ means “not implemented”, and ‘2×’
means “double buffered”.
External FIFO Interface
Architecture
The FX1 slave FIFO architecture has eight 512-byte blocks in the
endpoint RAM that directly serve as FIFO memories, and are
controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of
these buffers depend on the USB transfer mode as described in
the section Organization on page 11.
In operation, some of the eight RAM blocks fill or empty from the
SIE, while the others are connected to the I/O transfer logic. The
transfer logic takes two forms: the GPIF for internally generated
control signals or the slave FIFO interface for externally
controlled transfers.
Figure 6. Endpoint Configuration
Table 6. Default Alternate Settings
Alternate
Setting 0 1 2 3
ep0 64 64 64 64
ep1out 0 64 bulk 64 int 64 int
ep1in 0 64 bulk 64 int 64 int
ep2 0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
ep4 0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
ep6 0 64 bulk in (2×) 64 int in (2×) 64 iso in (2×)
ep8 0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
64
64
64
64
64
1023
1023
1023
1023
1023
1023
1023
64
64
64
64
64
64
64
64
64
64
EP2 EP2 EP2
EP6
EP6
EP8 EP8
EP0 IN&OUT
EP1 IN
EP1 OUT
1023
1023
EP6 1023
64
64
EP8
64
64
EP6
64
64
64
64
EP2
64
64
EP4
64
64
EP2
64
64
EP4
64
64
EP2
64
64
EP4
64
64
EP2
64
64
64
64
EP2
64
64
64
64
EP2
64
64
1023
EP2
1023
1023
EP2
1023
1023
EP2
1023
64
64
EP6
1023
1023
EP6
64
64
EP8
64
64
EP6
64
64
64
64
EP6
1023
1023
EP6
64
64
EP8
64
64
EP6
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
12345678910 11 12
Notes
4. After the data is downloaded from the host, a ‘loader’ executes from the internal RAM to transfer downloaded dat a to the external memory.
5. This EEPROM has no ad d r ess pins.
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Document #: 38-08039 Rev. *I Page 12 of 58
Master/Slave Control Signals
The FX1 endpoint FIFOS are implemented as eight physically
distinct 256x16 RAM blocks. The 8051/SIE can switch any of the
RAM blocks between two domain s: the USB (SIE) domain and
the 8051-I/O Unit domain. This switching is done
instantaneously, giving essentially zero transfer time between
“USB FIFOS” and “Slave FIFOS.” While they are physicall y the
same memory, no bytes are actually transferred between
buffers.
At any time, some RAM blocks fill or empty with USB data under
SIE control, while other RAM blocks are available to the 8051
and the I/O control unit. The RAM blocks operate as a single-port
in the USB domain, an d dual port in the 8051-I/O do main. The
blocks are configured as single, double, triple, or quad buffered.
The I/O control unit implements either an internal master (M for
master) or external master (S for Slave) interface.
In Master (M) mode, the GPIF internally controls FIFOADR[1..0]
to select a FIFO. The RDY pins (two in the 56 pin package, six
in the 100 pin and 128 pin packages) are used as flag inputs from
an external FIFO or other logic if desire d. The GPIF is run from
either an internally deri ved cloc k or an e xtern ally su pplied clo ck
(IFCLK), at a rate that transfers data up to 96 Megabytes/s (48
MHz IFCLK with 16-bit interface).
In Slave (S) mode, the FX1 accepts eith er an internally derived
clock or an externally supplied clock (IFCLK with a maximum
frequency of 48 MHz) and SLCS#, SLRD, SLWR, SLOE,
PKTEND signals from external logic. When using an external
IFCLK, the external clock must be present before switching to
the external clock with the IFCLKSRC bit. Each endpoint can
individually be selected for byte or word operation by an internal
configuration bit, and a Slave FI FO Output En able signa l SLOE
enables data of the selected width. External logic must ensure
that the output enable signal is inactive when writing data to a
slave FIFO. The slave interface can also operate asynchro-
nously, where the SLRD and SLWR signals act directly as
strobes, rather than a clock qualifier as in the synchronous
mode. The signals SLRD, SL WR, SLOE, and PKTEND are gated
by the signal SLCS#.
GPIF and FIFO Clock Rates
An 8051 register bit selects one of two frequencies for the inter-
nally supplied interface clock: 30 MHz and 48 MHz. Alternatively ,
an externally supplied clock of 5 to 48 MHz feeding the IFCLK
pin is used as the interface clock. IFCLK is configured to function
as an output clock when the GPIF and FIFOs are internally
clocked. An output enable bit in the IFCONFIG register turns this
clock output off, if desired. Another bit within the IFCONFIG
register inverts the IFCLK signal whether internally or externally
sourced.
GPIF
The GPIF is a flexible 8 or 16-bit parallel interface driven by a
user programmable finite state machine. It allows the
CY7C6471 3 to perf orm lo cal bus ma sterin g, and can imp lem ent
a wide variety of protocols such as A TA interface, printer parallel
port, and Utopia.
The GPIF has six programmable control outputs (CTL), nine
address outputs (GPIFADRx), and six general purpose Ready
inputs (RDY). The data bus width is 8 or 16 bits. Each GPIF
vector defines the state of the control outputs, and determines
what state a Ready input (or multiple inputs) must be before
proceeding. The GPIF vector is programmed to advance a FIFO
to the next data value, advance an address, and so on. A
sequence of the GPIF vectors create a single waveform that
executes to perform the data move between the FX1 and the
external device.
Six Control OUT Signals
The 100 and 128 pin packages bring out all six Control Outp ut
pins (CTL0-CTL5). The 805 1 programs the GPIF unit to define
the CTL waveforms. The 56 pin package brings out three of
these signals: CTL0 - CTL2. CTLx waveform edges are
programmed to make transitions as fast as once per clock (20.8
ns using a 48 MHz clock).
Six Ready IN Signals
The 100 and 128 pin packages bring out all six Ready inputs
(RDY0–RDY5). The 8051 programs the GPIF unit to test the
RDY pins for GPIF branching. The 56 pin package brings out two
of these signals, RDY0–1.
Nine GPIF Address OUT Signals
Nine GPIF address lines are available in the 100 and 128 pin
packages: GPIFADR[8..0]. The GPIF address lines allow
indexing through up to a 512 byte block of RAM. If more address
lines are needed, I/O port pins are used.
Long Transfer Mode
In Master mode, the 8051 appropriately sets the GPIF trans-
action count registers (GPIFTCB3, GPIFTCB2, GPIFTCB1, or
GPIFTCB0) for unattended transfers of up to 232 transactions.
The GPIF automatically throttles data flow to prevent under or
overflow until the full number of requested transactions are
complete. The GPIF decrements the value in these registers to
represent the current status of the transaction.
ECC Generation
The EZ-USB FX1 can calculate ECCs (Error Correcting Codes)
on data that pass across its GPIF or Slave FIFO interfaces.
There are two ECC configu rations: Tw o ECCs, each calculated
over 256 bytes (SmartMedia™ Standard); and one ECC calcu-
lated over 512 bytes.
The ECC can correct any one-bit error or detect any two-bit error.
Note To use the ECC logic, the GPIF or Slave FIFO interface
must be configured for byte-wide operation .
ECC Implementation
The two ECC configurations are selected by the ECCM bit:
0.0.0. 1 ECCM = 0
T wo 3-byte ECCs, each calculated over a 256-byte block of data.
This configuration conforms to the SmartMedia Standard.
Write any value to ECCRESET, then pass dat a across the GPIF
or Slave FIFO interface . The ECC for th e fi rst 256 byte s of d ata
is calculated and stored in ECC1. The ECC for the next 256 bytes
is stored in ECC2. After the second ECC is calculated, the values
in the ECCx registers do not change until the ECCRESET is
written again, even if more data is subsequently passed across
the interf ace .
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 13 of 58
0.0.0.2 ECC M = 1
One 3-byte ECC calculated over a 512-byte block of data.
Write any value to ECCRESET, then pass data across the GPIF
or Slave FIFO interface. The ECC for the first 512 byte s o f data
is calculated and stored in ECC1; ECC2 is not used. After the
ECC is calculated, the value in ECC1 do es not chang e until the
ECCRESET is written again, even if more da ta is subsequently
passed across the interface
USB Uploads and Downloads
The core has the ability to directly edit the data contents of the
internal 16 KByte RAM a nd of t he inte rn al 51 2 byte scratch pad
RAM via a vendor specific command. This capability is normally
used when ‘soft’ downloading user code and is available only to
and from the internal RAM, only w hen the 8 051 is held in reset.
The available RAM spaces are 16 KBytes from 0x0000–0x3FFF
(code/data) and 512 bytes from 0xE000–0xE1FF (scratch pad
data RAM).[4]
Autopointer Access
FX1 provides two identical autopointers. T hey are similar to the
internal 8051 data pointers, but with an additional fe ature: they
can optionally increment after every memory access. This
capability is available to and from both internal and external
RAM. The autopointers are available in external F X1 registers,
under the control of a mode bit (AUTOPTRSETUP.0). Using the
external FX1 autopointer access (at 0xE67B – 0xE67C) allows
the autopointer to access all RAM, internal and external, to the
part. Also, the autopointers can point to any FX1 register or
endpoint buffer space. When autopointer access to external
memory is enabled, the location 0xE67B and 0xE67C in XDATA
and the code space cannot be used.
I2C Controller
FX1 has one I2C port that is driven by two internal controllers:
one that automatically operates at boot time to load VID/PID/DID
and configuration informati on; and another that the 8051, once
running, uses to control external I2C devices. The I2C port
operates in master mode only.
I2C Port Pins
The I2C pins SCL and SDA must have external 2.2 kΩ pull up
resistors even if no EEPROM is connected to the FX1. External
EEPROM device address pins must be configured properly . See
Table 7 for configuring th e device address pins.
I2C Interface Boot Load Access
At power on reset the I2C interface boot loader loads the
VID/PID/DID configuration bytes and up to 16 KBytes of
program/data. The available RAM spaces are 16 KBytes from
0x0000–0x3FFF and 512 bytes from 0xE000–0xE1FF. The 8051
is in reset. I2C interface boot loads only occur after power on
reset.
I2C Interface General Purpose Access
The 8051 can control peripherals connected to the I2C bus using
the I2CTL and I2DAT registers. FX1 pro vides I2C master control
only, because it is never an I2C slave.
Compatible with Previous Generation EZ-USB FX2
The EZ-USB FX1 is fit, form, and function upgradable to the
EZ-USB FX2LP. This makes for an easy transition for designers
wanting to upgrade thei r systems from fu ll speed to hi gh speed
designs. The pinout and package selection are identical, and all
firmware developed for the FX1 function in the FX2LP with
proper addition of high speed descriptors and speed switching
code.
Pin Assi gnment s
Figure 7 on page 14 identifies al l signals for the three package
types. The following pages illustrate the individual pin diagrams,
plus a combination diagram showing which of the full set of
signals are available in the 128, 100, and 56 pin packages.
The signals on the left edge of the 56 pin package in Figure 7 on
page 14 are common to all versions in the FX1 family. Three
modes are available in all package versions: Port, GPIF master,
and Slave FIFO. These modes define the signals on the right
edge of the diagram. The 8051 selects the interface mode using
the IFCONFIG[1:0] register bits. Port mode is the power on
default configuration.
The 100-pin package adds functionality to the 56 pin package by
adding these pins :
PORTC or alternate GPIFADR[7:0] address signals
PORTE or alternate GPIFADR[8] address signal and seven
additional 8051 signals
Three GPIF Control signal s
Four GPIF Ready signals
Nine 8051 signals (two USARTs, three timer inputs, INT4,and
INT5#)
BKPT, RD#, WR#.
The 128 pin package adds the 8051 address and data buses
plus control signals. Note that two of the required signals, RD#
and WR#, are present in the 100 pin version. In the 100 pin and
128 pin versions, an 8051 control bit is set to pulse the RD# and
WR# pins when the 8051 reads from and writes to the PORTC.
T able 7. Strap Boot EEPROM Address Lines to These Values
Bytes Example EEPROM A2 A1 A0
16 24LC00[5] N/A N/A N/A
128 24LC01 0 0 0
256 24LC02 0 0 0
4K 24LC32 0 0 1
8K 24LC64 0 0 1
16K 24LC128 0 0 1
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 14 of 58
Figure 7. Signals
RDY0
RDY1
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
56
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
RxD0
TxD0
RxD1
TxD1
INT4
INT5#
T2
T1
T0
100
D7
D6
D5
D4
D3
D2
D1
D0
EA
128
RD#
WR#
CS#
OE#
PSEN#
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
IFCLK
CLKOUT
DPLUS
DMINUS
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
Port GPIF Master Slave FIFO
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 15 of 58
Figure 8. CY7C64713 128 pin TQFP Pin Assignment
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
A11
A12
A13
A14
A15
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
EA
SCL
SDA
OE#
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
A3
A2
A1
A0
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
D7
D6
D5
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
GND
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
A4
A5
A6
A7
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
A8
A9
A10
CY7C64713
128 pin TQFP
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
D4
D3
D2
D1
D0
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
CS#
WR#
RD#
PSEN#
* indicates programmable polarity
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 16 of 58
Figure 9. CY7C64713 100 pin TQFP Pin Assignment
PD0/FD8
*WAKEUP
VCC
RESET#
CTL5
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
GND
PC7/GPIFADR7
PC6/GPIFADR6
PC5/GPIFADR5
PC4/GPIFADR4
PC3/GPIFADR3
PC2/GPIFADR2
PC1/GPIFADR1
PC0/GPIFADR0
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
VCC
CTL4
CTL3
PD1/FD9
PD2/FD10
PD3/FD11
INT5#
VCC
PE0/T0OUT
PE1/T1OUT
PE2/T2OUT
PE3/RXD0OUT
PE4/RXD1OUT
PE5/INT6
PE6/T2EX
PE7/GPIFADR8
GND
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
CY7C64713
100 pin TQFP
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
RXD1
TXD1
RXD0
TXD0
GND
VCC
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
WR#
RD#
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
RDY2
RDY3
RDY4
RDY5
AVCC
XTALOUT
XTALIN
AGND
NC
NC
NC
AVCC
DPLUS
DMINUS
AGND
VCC
GND
INT4
T0
T1
T2
*IFCLK
RESERVED
BKPT
SCL
SDA
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
* indicates programmable polarity
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 17 of 58
Figure 10. CY7C64713 56 pin SSOP Pin Assignment
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
VCC
GND
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK
RESERVED
SCL
SDA
VCC
PB0/FD0
PB1/FD1
PB2/FD2
PB3/FD3
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PD4/FD12
PD3/FD11
PD2/FD10
PD1/FD9
PD0/FD8
*WAKEUP
VCC
RESET#
GND
PA7/*FLAGD/SLCS#
PA6/PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
CY7C64713
56 pin SSOP
* indicates programmable polarity
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 18 of 58
Figure 11. CY7C64713 56 pin QFN Pin Assignment
28
27
26
25
24
23
22
21
20
19
18
17
16
15
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RESET#
GND
PA7/*FLAGD/SLCS#
PA6/*PKTEND
PA5/FIFOADR1
PA4/FIFOADR0
PA3/*WU2
PA2/*SLOE
PA1/INT1#
PA0/INT0#
VCC
CTL2/*FLAGC
CTL1/*FLAGB
CTL0/*FLAGA
RDY0/*SLRD
RDY1/*SLWR
AVCC
XTALOUT
XTALIN
AGND
AVCC
DPLUS
DMINUS
AGND
VCC
GND
*IFCLK
RESERVED
VCC
*WAKEUP
PD0/FD8
PD1/FD9
PD2/FD10
PD3/FD11
PD4/FD12
PD5/FD13
PD6/FD14
PD7/FD15
GND
CLKOUT
VCC
GND
GND
VCC
GND
PB7/FD7
PB6/FD6
PB5/FD5
PB4/FD4
PB3/FD3
PB2/FD2
PB1/FD1
PB0/FD0
VCC
SDA
SCL
CY7C64713
56 pin QFN
* indicates programmable polarity
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 19 of 58
CY7C64713 Pin Definitions
The FX1 Pin Definitions for CY7C64713 follow.[6]
Table 8. FX1 Pin Definitions
128
TQFP 100
TQFP 56
SSOP 56
QFN Name Type Default Description
10 9 10 3 AVCC Power N/A Analog VCC. Connect this pin to 3.3 V power source. This signal
provides power to the analog section of the chip.
17 16 14 7 AVCC Power N/A Analog VCC. Connect this pin to 3.3 V power source. This signal
provides power to the analog section of the chip.
13 12 13 6 AGND Ground N/A Analog Ground. Connect to ground with as short a path as possible.
20 19 17 10 AGND Ground N/A Analog Grou nd. Connect to ground with as short a path as possible.
19 18 16 9 DMINUS I/O/Z Z USB D– Signal. Connect to the USB D– signal.
18 17 15 8 DPLUS I/O/Z Z USB D+ Signal. Connect to the USB D+ signal.
94 A0 Output L 8051 Address Bus. This bus is driven at all times. When the 8051 is
addressing the internal RAM it reflects the internal address.
95 A1 Output L
96 A2 Output L
97 A3 Output L
117 A4 Output L
118 A5 Output L
119 A6 Output L
120 A7 Output L
126 A8 Output L
127 A9 Output L
128 A10 Output L
21 A11 Output L
22 A12 Output L
23 A13 Output L
24 A14 Output L
25 A15 Output L
59 D0 I/O/Z Z 8051 Data Bus. This bidirectional bus is high impedance whe n
inactive, input for bus reads, and output for bus writes. The data bus is
used for external 8051 program and data memory. The data bus is
active only for external bus accesses, and is driven LOW in suspend.
60 D1 I/O/Z Z
61 D2 I/O/Z Z
62 D3 I/O/Z Z
63 D4 I/O/Z Z
86 D5 I/O/Z Z
87 D6 I/O/Z Z
88 D7 I/O/Z Z
39 PSEN# Output H Program Store Enable. This active LOW signal indicates an 8051
code fetch from external memory. It is active for program memory
fetches from 0x4000–0xFFFF when the EA pin is LOW, or from
0x0000–0xFFFF when the EA pin is HIGH.
Note
6. Do not leave unused inputs flo ating. Tie either HIGH or LOW as appropriate. Pull output s up or down to ensure signals at power up and in standby. Note that no pins
must be driven when the device is powered down.
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 20 of 58
34 28 BKPT Output L Breakpoint. This pin goes active (HIGH) when the 8051 address bus
matches the BP ADDRH/L registers and breakpoints are enabled in the
BREAKPT register (BPEN = 1). If the BPPULSE bit in the BREAKPT
register is HIGH, this signal pulses HIGH for eight 12-/24-/48 MHz
clocks. If the BPPULSE bit is LOW, the signal remains HIGH until the
8051 clears the BREAK bit (by writing ‘1’ to it) in the BREAKPT register .
99 77 49 42 RESET# Input N/A Active LOW Reset. Resets the entire chip. See the section “Reset and
Wakeup” on page 7 for more details.
35 EA Input N/A External Access. This pin dete rmines where the 8051 fetches code
between addresses 0x0000 and 0x3FFF. If EA = 0 the 8051 fetches
this code from its internal RAM. IF EA = 1 the 8051 fetches this code
from external memory.
12 11 12 5 XTALIN Input N/A Crystal Input. Connect this signal to a 24 MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
It is also correct to drive the XTALIN with an external 24 MHz square
wave derived from another clock source. When driving from an external
source, the driving signal must be a 3.3 V square wave.
11 10 11 4 XTALOUT Output N/A Crystal Output. Connect this signal to a 24 MHz parallel-resonant,
fundamental mode crystal and load capacitor to GND.
If an external clock is used to drive XTALIN, lea ve this pin open.
1 100 5 54 CLKOUT O/Z 12
MHz CLKOUT: 12, 24 or 48 MHz clock, phase locked to the 24 MHz input
clock. The 8051 defaults to 12 MHz operation. The 8051 may
three-state this output by setting CPUCS.1 = 1.
Port A
82 67 40 33 PA 0 or
INT0# I/O/Z I
(PA0) Multiple xed pin whose function is selected by PORTACFG.0
PA0 is a bidirectional I/O port pin.
INT0# is the active-LOW 8051 INT0 interrupt input signal, which is
either edge triggered (IT0 = 1) or level triggered (IT0 = 0).
83 68 41 34 PA 1 or
INT1# I/O/Z I
(PA1) Multiplexed pin whose function is selected by:
PORTACFG.1
PA1 is a bidirectional I/O port pin.
INT1# is the active-LOW 8051 INT1 interrupt input signal, which is
either edge triggered (IT1 = 1) or level triggered (IT1 = 0).
84 69 42 35 PA 2 or
SLOE I/O/Z I
(PA2) Multiplexed pin whose function is selected by two bits:
IFCONFIG[1:0].
PA2 is a bidirectional I/O port pin.
SLOE is an input-only output enable with programmable polarity
(FIFOPINPOLAR.4) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
85 70 43 36 PA3 or
WU2 I/O/Z I
(PA3) Multiplexed pin whose function is selected by:
WAKEUP.7 and OEA.3
PA3 is a bidirectional I/O port pin.
WU2 is an alternate source for USB W akeup, enabled by WU2EN bit
(W AKEUP.1) and polarity set by WU2POL (W AKEUP.4). If the 8051 is
in suspend and WU2EN = 1, a transition on this pin starts up the oscil-
lator and interrupts the 8051 to allow it to exit the suspend mode.
Asserting th is pi n inhibits the chip from suspending, i f WU 2EN = 1.
89 71 44 37 PA 4 or
FIFOADR0 I/O/Z I
(PA4) Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA4 is a bidirectional I/O port pin.
FIFOADR0 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
Table 8. FX1 Pin Definitions (continued)
128
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TQFP 56
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90 72 45 38 PA 5 or
FIFOADR1 I/O/Z I
(PA5) Multiplexed pin whose function is selected by:
IFCONFIG[1..0].
PA5 is a bidirectional I/O port pin.
FIFOADR1 is an input-only address select for the slave FIFOs
connected to FD[7..0] or FD[15..0].
91 73 46 39 PA6 or
PKTEND I/O/Z I
(PA6) Multiplexed pin whose function is selected by the IFCONFIG[1:0] bits.
PA6 is a bidirectional I/O port pin.
PKTEND is an input used to commit the FIFO packet data to the
endpoint and whose polarity is programmable via FIFOPINPOLAR.5.
92 74 47 40 PA7 or
FLAGD or
SLCS#
I/O/Z I
(PA7) Multiplexed pin whose function is selected by the IFCONFIG[1:0] and
PORTACFG.7 bits.
PA7 is a bidirectional I/O port pin.
FLAGD is a programmable slave- FIFO output status flag signal.
SLCS# gates all other slave FIFO enab le/strobes
Port B
44 34 25 18 PB0 or
FD[0] I/O/Z I
(PB0) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB0 is a bidirectional I/O port pin.
FD[0] is the bidirectional FI FO/GPIF data bus.
45 35 26 19 PB1 or
FD[1] I/O/Z I
(PB1) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB1 is a bidirectional I/O port pin.
FD[1] is the bidirectional FI FO/GPIF data bus.
46 36 27 20 PB2 or
FD[2] I/O/Z I
(PB2) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB2 is a bidirectional I/O port pin.
FD[2] is the bidirectional FI FO/GPIF data bus.
47 37 28 21 PB3 or
FD[3] I/O/Z I
(PB3) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB3 is a bidirectional I/O port pin.
FD[3] is the bidirectional FI FO/GPIF data bus.
54 44 29 22 PB4 or
FD[4] I/O/Z I
(PB4) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB4 is a bidirectional I/O port pin.
FD[4] is the bidirectional FI FO/GPIF data bus.
55 45 30 23 PB5 or
FD[5] I/O/Z I
(PB5) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB5 is a bidirectional I/O port pin.
FD[5] is the bidirectional FI FO/GPIF data bus.
56 46 31 24 PB6 or
FD[6] I/O/Z I
(PB6) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB6 is a bidirectional I/O port pin.
FD[6] is the bidirectional FI FO/GPIF data bus.
57 47 32 25 PB7 or
FD[7] I/O/Z I
(PB7) Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
PB7 is a bidirectional I/O port pin.
FD[7] is the bidirectional FI FO/GPIF data bus.
Table 8. FX1 Pin Definitions (continued)
128
TQFP 100
TQFP 56
SSOP 56
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PORT C
72 57 PC0 or
GPIFADR0 I/O/Z I
(PC0) Multiplexed pin whose function is selected by PORTCCFG.0
PC0 is a bidirectional I/O port pin.
GPIFADR0 is a GPIF address output pin.
73 58 PC1 or
GPIFADR1 I/O/Z I
(PC1) Multiplexed pin whose function is selected by PORTCCFG.1
PC1 is a bidirectional I/O port pin.
GPIFADR1 is a GPIF address output pin.
74 59 PC2 or
GPIFADR2 I/O/Z I
(PC2) Multiplexed pin whose function is selected by PORTCCFG.2
PC2 is a bidirectional I/O port pin.
GPIFADR2 is a GPIF address output pin.
75 60 PC3 or
GPIFADR3 I/O/Z I
(PC3) Multiplexed pin whose function is selected by PORTCCFG.3
PC3 is a bidirectional I/O port pin.
GPIFADR3 is a GPIF address output pin.
76 61 PC4 or
GPIFADR4 I/O/Z I
(PC4) Multiplexed pin whose function is selected by PORTCCFG.4
PC4 is a bidirectional I/O port pin.
GPIFADR4 is a GPIF address output pin.
77 62 PC5 or
GPIFADR5 I/O/Z I
(PC5) Multiplexed pin whose function is selected by PORTCCFG.5
PC5 is a bidirectional I/O port pin.
GPIFADR5 is a GPIF address output pin.
78 63 PC6 or
GPIFADR6 I/O/Z I
(PC6) Multiplexed pin whose function is selected by PORTCCFG.6
PC6 is a bidirectional I/O port pin.
GPIFADR6 is a GPIF address output pin.
79 64 PC7 or
GPIFADR7 I/O/Z I
(PC7) Multiplexed pin whose function is selected by PORTCCFG.7
PC7 is a bidirectional I/O port pin.
GPIFADR7 is a GPIF address output pin.
PORT D
102 80 52 45 PD0 or
FD[8] I/O/Z I
(PD0) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[8] is the bidirectional FI FO/GPIF data bus.
103 81 53 46 PD1 or
FD[9] I/O/Z I
(PD1) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[9] is the bidirectional FI FO/GPIF data bus.
104 82 54 47 PD2 or
FD[10] I/O/Z I
(PD2) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[10] is the bidirectional FIFO/GPIF data bus.
105 83 55 48 PD3 or
FD[11] I/O/Z I
(PD3) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[11] is the bidirectional FIFO/GPIF data bus.
121 95 56 49 PD4 or
FD[12] I/O/Z I
(PD4) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[12] is the bidirectional FIFO/GPIF data bus.
122 96 1 50 PD5 or
FD[13] I/O/Z I
(PD5) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[13] is the bidirectional FIFO/GPIF data bus.
123 97 2 51 PD6 or
FD[14] I/O/Z I
(PD6) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[14] is the bidirectional FIFO/GPIF data bus.
124 98 3 52 PD7 or
FD[15] I/O/Z I
(PD7) Multiplexed pin whose function is selected by the IFCONFIG[1..0] and
EPxFIFOCFG.0 (wordwide) bits.
FD[15] is the bidirectional FIFO/GPIF data bus.
Table 8. FX1 Pin Definitions (continued)
128
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TQFP 56
SSOP 56
QFN Name Type Default Description
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Port E
108 86 PE0 or
T0OUT I/O/Z I
(PE0) Multiplexed pin whose function is selected by the PORTECFG.0 bit.
PE0 is a bidirectional I/O port pin.
T0OUT is an active HIGH signal from 8051 T imer-counter0. T0OUT
outputs a high level for one CLKOUT clock cycle when Timer0
overflows. If Timer0 is operated in Mode 3 (two separate
timer/counters), T0OUT is active when the low byte timer/counter
overflows.
109 87 PE1 or
T1OUT I/O/Z I
(PE1) Multiplexed pin whose function is selected by the PORTECFG.1 bit.
PE1 is a bidirectional I/O port pin.
T1OUT is an active HIGH signal from 8051 T imer-counter1. T1OUT
outputs a high level for one CLKOUT clock cycle when Timer1
overflows. If Timer1 is operated in Mode 3 (two separate
timer/counters), T1OUT is active when the low byte timer/counter
overflows.
110 88 PE2 or
T2OUT I/O/Z I
(PE2) Multiplexed pin whose function is selected by the PORTECFG.2 bit.
PE2 is a bidirectional I/O port pin.
T2OUT is the active HIGH output signal from 8051 T imer2. T2OUT is
active (HIGH) for one clock cycle when Timer/Counter 2 overflows.
111 89 PE3 or
RXD0OUT I/O/Z I
(PE3) Multiplexed pin whose function is selected by the PORTECFG.3 bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active HIGH signal from 8051 UART0. If RXD0OUT
is selected and UART0 is in Mode 0, this pin provides the output data
for UART0 only when it is in sync mode. Otherwise it is a 1.
112 90 PE4 or
RXD1OUT I/O/Z I
(PE4) Multiplexed pin whose function is selected by the PORTECFG.4 bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active HIGH output from 8051 UART1. When the
RXD1OUT is selected and UART1 is in Mode 0, this pin provides the
output data for UART1 only when it is in sync mode. In Modes 1, 2, and
3, this pin is HIGH.
113 91 PE5 or
INT6 I/O/Z I
(PE5) Multiplexed pin whose function is selected by the PORTECFG.5 bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT6 interrupt request input signal. The INT6 pin is
edge-sensitive, active HIGH.
114 92 PE6 or
T2EX I/O/Z I
(PE6) Multiplexed pin whose function is selected by the PORTECFG.6 bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active HIGH input signal to the 8051 Timer2. T2EX reloads
timer 2 on its falling edge. T2EX is active only if the EXEN2 bit is set in
T2CON.
115 93 PE7 or
GPIFADR8 I/O/Z I
(PE7) Multiplexed pin whose function is selected by the PORTECFG.7 bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
4381RDY0 or
SLRD Input N/A Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity
(FIFOPINPOLAR.3) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
5492RDY1 or
SLWR Input N/A Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the inpu t-only write strobe with programmable polarity
(FIFOPINPOLAR.2) for the slave FIFOs connected to FD[7..0] or
FD[15..0].
Table 8. FX1 Pin Definitions (continued)
128
TQFP 100
TQFP 56
SSOP 56
QFN Name Type Default Description
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6 5 RDY2 Input N/A RDY2 is a GPIF input signal.
7 6 RDY3 Input N/A RDY3 is a GPIF input signal.
8 7 RDY4 Input N/A RDY4 is a GPIF input signal.
9 8 RDY5 Input N/A RDY5 is a GPIF input signal.
69 54 36 29 CTL0 or
FLAGA O/Z H Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave- FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the FIFOADR[1:0]
pins.
70 55 37 30 CTL1 or
FLAGB O/Z H Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave- FIFO output status flag signal.
Defaults to FULL for the FIFO selected by th e FIF OAD R [1:0] pins.
71 56 38 31 CTL2 or
FLAGC O/Z H Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave- FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
66 51 CTL3 O/Z H CTL3 is a GPIF control output.
67 52 CTL4 Output H CTL4 is a GPIF control output.
98 76 CTL5 Output H CTL5 is a GPIF control output.
32 26 20 13 IFCLK I/O/Z Z Interface Clock, used for synchronously clocking data into or out of the
slave FIFOs. IFCLK also serves as a timing reference for all slave FIFO
control signals and GPIF. When internal clocking is used
(IFCONFIG.7 = 1) the IFCLK pin is configured to output 30/48 MHz by
bits IFCONFIG.5 and IFCONFIG.6. IFCL K may be inverted, whether
internally or externally sourced, by setting the bit IFCON FIG.4 = 1.
28 22 INT4 Input N/A INT4 is the 8051 INT4 interrupt request input signal. The INT4 pin is
edge-sensitive, active HIGH.
106 84 INT5# Input N/A INT5# is the 8051 INT5 interrupt request input signal. The INT5 pin is
edge-sensitive, active LOW.
31 25 T2 Input N/A T2 is the active-HIGH T2 input signal to 8051 Timer2, which provides
the input to Timer2 when C/T2 = 1. When C/T2 = 0, Timer2 does not
use this pin.
30 24 T1 Input N/A T1 is the active-HIGH T1 signal for 8051 Timer1, which provides the
input to T imer1 when C/T1 is 1. When C/T1 is 0, Timer1 does not use
this bit.
29 23 T0 Input N/A T0 is the active-HIGH T0 signal for 8051 Timer0, which provides the
input to T imer0 when C/T0 is 1. When C/T0 is 0, Timer0 does not use
this bit.
53 43 RXD1 Input N/A RXD1is an active-HIGH input signal for 8051 UART1, which provides
data to the UART in all modes.
52 42 TXD1 Output H TXD1is an active-HIGH output pin from 8051 UART1, which provides
the output clock in sync mode, and the output data in async mode.
51 41 RXD0 Input N/A RXD0 is the active-HIGH RXD0 input to 8051 UART0, which provides
data to the UART in all modes.
50 40 TXD0 Output H TXD0 is the active-HIGH TXD0 output from 8051 UART0, which
provides the output clock in sync mode, and the output data in async
mode.
Table 8. FX1 Pin Definitions (continued)
128
TQFP 100
TQFP 56
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QFN Name Type Default Description
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42 CS# Output H CS# is the active-LOW chip select for external memory.
41 32 WR# Output H WR# is the active-LOW write strobe output for external memory.
40 31 RD# Output H RD# is the active-LOW read strobe output for external memory.
38 OE# Output H OE# is the active LOW output enable fo r external memory.
33 27 21 14 Reserved Input N/A Reserved. Connect to ground.
101 79 51 44 WAKEUP Input N/A USB Wakeup. If the 8051 is in suspend, asserting this pin starts up the
oscillator and interrupts the 8051 to allow it to exit the suspend mode.
Holding W AKEUP as serted inhibi ts the EZ-USB FX1 chip from
suspending. This pin has programmable polarity (WAKEUP.4).
36 29 22 15 SCL OD Z Clock for the I2C inter face. Connect to VCC with a 2.2K resistor , even
if no I2C peripheral is attached.
37 30 23 16 SDA OD Z Data for I2C interf ace. Connect to VCC with a 2.2K resistor, even if
no I2C peripheral is attached.
2 1 6 55 VCC Power N/A VCC. Connect to 3.3 V power source.
26 20 18 11 VCC Power N/A VCC. Connect to 3.3 V power source.
43 33 24 17 VCC Power N/A VCC. Connect to 3.3 V power source.
48 38 VCC Power N/A VCC. Connect to 3.3 V power source.
64 49 34 27 VCC Power N/A VCC. Connect to 3.3 V power source.
68 53 VCC Power N/A VCC. Connect to 3.3 V power source.
81 66 39 32 VCC Power N/A VCC. Connect to 3.3 V power source.
100 78 50 43 VCC Power N/A VCC. Connect to 3.3 V power source.
107 85 VCC Power N/A VCC. Connect to 3.3 V power source.
3 2 7 56 GND Ground N/A Ground.
27 21 19 12 GND Ground N/A Ground.
49 39 GND Ground N/A Ground.
58 48 33 26 GND Ground N/A Ground.
65 50 35 28 GND Ground N/A Ground.
80 65 GND Ground N/A Ground.
93 75 48 41 GND Ground N/A Ground.
116 94 GND Ground N/A Ground.
125 99 4 53 GND Ground N/A Ground.
14 13 NC N/A N/A No Connect. This pin must be left open.
15 14 NC N/A N/A No Connect. This pin must be left open.
16 15 NC N/A N/A No Connect. This pin must be left open.
Table 8. FX1 Pin Definitions (continued)
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TQFP 56
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Register Summary
FX1 register bit definitions are described in the EZ-USB TRM in greater detail.
Tab le 9. FX1 Register Summary
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
GPIF Wave form Memories
E400 128 WAVEDATA GPIF Waveform
Descriptor 0, 1, 2, 3 data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E480 128 reserved
GENERAL CONFIGURATION
E600 1CPUCS CPU Control & Status 0 0 PORTCSTB CLKSPD1 CLKSPD0 CLKINV CLKOE 8051RES 00000010 rrbbbbbr
E601 1IFCONFIG Interface Co nfiguration
(Ports, GPI F, slave FIFOs)IFCLKSRC 3048MHZ IFCLKOE IFCLKPOL ASYNC GSTATE IFCFG1 IFCFG0 10000000 RW
E602 1PINFLAGSAB[9]
Slave FIFO FLAGA and
FLAGB Pin Configuratio n FLAGB3 FLAGB2 FLAGB1 FLAGB0 FLAGA3 FLAGA2 FLAGA1 FLAGA0 00000000 RW
E603 1PINFLAGSCD[9] Slave FIFO FLAGC and
FLAGD Pin Configur ati o n FLAGD3 FLAGD2 FLAGD1 FLAGD0 FLAGC3 FLAGC2 FLAGC1 FLAGC0 00000000 RW
E604 1FIFORESET[9]
Restore F IFOS to def ault
state NAKALL 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
E605 1BREAKPT Breakpoint Control 0 0 0 0 BREAK BPPULSE BPEN 000000000 rrrrbbbr
E606 1BPADDRH Breakpoint Address H A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
E607 1BPADDRL Breakpoint Address L A7 A6 A5 A4 A3 A2 A1 A0 xxxxxxxx RW
E608 1UART230 230 Kbaud internally
generated ref. clock 0 0 0 0 0 0 230UART1 230UART0 00000000 rrrrrrbb
E609 1FIFOPINPOLAR[9]
Slave FIFO Interf ace pins
polarity 0 0 PKTEND SLOE SLRD SLWR EF FF 00000000 rrbbbbbb
E60A 1REVID Chip Revision rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 RevA
00000001 R
E60B 1REVCTL[9] Chip Revision Control 0 0 0 0 0 0 dyn_out enh_pkt 00000000 rrrrrrbb
UDMA
E60C 1GPIFHOLDAMOUNT MSTB Hold Time
(for UDMA) 0 0 0 0 0 0 HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
3reserved
ENDPOI NT CO NF IGURATION
E610 1EP1OUTCFG Endpoint 1-OUT
Configuration VALID 0TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
E611 1EP1INCFG Endpoint 1-IN
Configuration VALID 0TYPE1 TYPE0 0 0 0 0 10100000 brbbrrrr
E612 1EP2CFG Endpoint 2 Configuration VALID DIR TYPE1 TYPE0 SIZE 0BUF1 BUF0 10100010 bbbbbrbb
E613 1EP4CFG Endpoint 4 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 10100000 bbbbrrrr
E614 1EP6CFG Endpoint 6 Configuration VALID DIR TYPE1 TYPE0 SIZE 0BUF1 BUF0 11100010 bbbbbrbb
E615 1EP8CFG Endpoint 8 Configuration VALID DIR TYPE1 TYPE0 0 0 0 0 11100000 bbbbrrrr
2reserved
E618 1EP2FIFOCFG[9]
Endpoint 2 / slave FIFO
configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E619 1EP4FIFOCFG[9]
Endpoint 4 / slave FIFO
configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E61A 1EP6FIFOCFG[9]
Endpoint 6 / slave FIFO
configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E61B 1EP8FIFOCFG[9]
Endpoint 8 / slave FIFO
configuration 0INFM1 OEP1 AUTOOUT AUTOIN ZEROLENIN 0WORDWIDE 00000101 rbbbbbrb
E61C 4reserved
E620 1EP2AUTOINLENH[9] Endpoint 2 AUTOIN
Packet Length H 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
E621 1EP2AUTOINLENL[9] Endpoint 2 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E622 1EP4AUTOINLENH[9] Endpoint 4 AUTOIN
Packet Length H 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
E623 1EP4AUTOINLENL[9] Endpoint 4 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E624 1EP6AUTOINLENH[9] Endpoint 6 AUTOIN
Packet Length H 0 0 0 0 0 PL10 PL9 PL8 00000010 rrrrrbbb
E625 1EP6AUTOINLENL[9] Endpoint 6 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E626 1EP8AUTOINLENH[9] Endpoint 8 AUTOIN
Packet Length H 0 0 0 0 0 0 PL9 PL8 00000010 rrrrrrbb
E627 1EP8AUTOINLENL[9] Endpoint 8 AUTOIN
Packet Length L PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0 00000000 RW
E628 1ECCCFG ECC Configuration 0 0 0 0 0 0 0 ECCM 00000000 rrrrrrrb
E629 1ECCRESET ECC Reset x x x x x x x x 00000000 W
E62A 1ECC1B0 ECC1 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 11111111 R
E62B 1ECC1B1 ECC1 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 11111111 R
Notes
7. SFRs not part of the standard 8051 architecture.
8. The register can only be reset. It cannot be set.
9. Read and writes to these register may require synchronization delay, see the section “Synchronization Delay” in the EZ-USB TRM.
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E62C 1ECC1B2 ECC1 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 LINE17 LINE16 11111111 R
E62D 1ECC2B0 ECC2 Byte 0 Address LINE15 LINE14 LINE13 LINE12 LINE11 LINE10 LINE9 LINE8 11111111 R
E62E 1ECC2B1 ECC2 Byte 1 Address LINE7 LINE6 LINE5 LINE4 LINE3 LINE2 LINE1 LINE0 11111111 R
E62F 1ECC2B2 ECC2 Byte 2 Address COL5 COL4 COL3 COL2 COL1 COL0 0 0 11111111 R
E630 1EP2FIFOPFH[9]
Endpoint 2 / slave FIFO
Programmable Flag H ISO
Mode
DECIS PKTSTAT IN: PKTS[2]
OUT:PFC12 IN: PKTS[1]
OUT:PFC11 IN: PKTS[0]
OUT:PFC10 0PFC9 PFC8 10001000 bbbbbrbb
E630 1EP2FIFOPFH[9]
Endpoint 2 / slave FIFO
Programmable Flag H
Non-ISO Mode
DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0PFC9 IN:PKTS[2]
OUT:PFC8 10001000 bbbbbrbb
E631 1EP2FIFOPFL[9]
Endpoint 2 / slave FIFO
Programmable Flag L IN:PKTS[1]
OUT:PFC7 IN:PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E632 1EP4FIFOPFH[9]
Endpoint 4 / slave FIFO
Programmable Flag H ISO
Mode
DECIS PKTSTAT 0IN: PKTS[1]
OUT:PFC10 IN: PKTS[0]
OUT:PFC9 0 0 PFC8 10001000 bbrbbrrb
E632 1EP4FIFOPFH[9]
Endpoint 4 / slave FIFO
Programmable Flag H
Non-ISO Mode
DECIS PKTSTAT 0OUT:PFC10 OUT:PFC9 0 0 PFC8 10001000 bbrbbrrb
E633 1EP4FIFOPFL[9]
Endpoint 4 / slave FIFO
Programmable Flag L IN: PKTS[1]
OUT:PFC7 IN: PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E634 1EP6FIFOPFH[9]
Endpoint 6 / slave FIFO
Programmable Flag H ISO
Mode
DECIS PKTSTAT INPKTS[2]
OUT:PFC12 IN: PKTS[1]
OUT:PFC11 IN: PKTS[0]
OUT:PFC10 0PFC9 PFC8 00001000 bbbbbrbb
E634 1EP6FIFOPFH[9]
Endpoint 6 / slave FIFO
Programmable Flag H
Non-ISO Mode
DECIS PKTSTAT OUT:PFC12 OUT:PFC11 OUT:PFC10 0PFC9 IN:PKTS[2]
OUT:PFC8 00001000 bbbbbrbb
E635 1EP6FIFOPFL[9]
Endpoint 6 / slave FIFO
Programmable Flag L IN:PKTS[1]
OUT:PFC7 IN:PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E636 1EP8FIFOPFH[9]
Endpoint 8 / slave FIFO
Programmable Flag H ISO
Mode
DECIS PKTSTAT 0IN: PKTS[1]
OUT:PFC10 IN: PKTS[0]
OUT:PFC9 0 0 PFC8 00001000 bbrbbrrb
E636 1EP8FIFOPFH[9]
Endpoint 8 / slave FIFO
Programmable Flag H
Non-ISO Mode
DECIS PKTSTAT 0OUT:PFC10 OUT:PFC9 0 0 PFC8 00001000 bbrbbrrb
E637 1EP8FIFOPFL[9]
ISO Mode Endpoint 8 / slave FIFO
Programmable Flag L PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
E637 1EP8FIFOPFL[9]
Non-ISO Mode Endpoint 8 / slave FIFO
Programmable Flag L IN: PKTS[1]
OUT:PFC7 IN: PKTS[0]
OUT:PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0 00000000 RW
8reserved
E640 1reserved
E641 1reserved
E642 1reserved
E643 1reserved
E644 4reserved
E648 1INPKTEND[9] Force IN Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
E649 7OUTPKTEND[9] Force OUT Packet End Skip 0 0 0 EP3 EP2 EP1 EP0 xxxxxxxx W
INTERRUPTS
E650 1EP2FIFOIE[9]
Endpoint 2 slave FIFO
Flag Interrupt Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E651 1EP2FIFOIRQ[9,7] Endpoint 2 slave FIFO
Flag Interrupt Request 0 0 0 0 0 PF EF FF 00000111 rrrrrbbb
E652 1EP4FIFOIE[9]
Endpoint 4 slave FIFO
Flag Interrupt Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E653 1EP4FIFOIRQ[9,7] Endpoint 4 slave FIFO
Flag Interrupt Request 0 0 0 0 0 PF EF FF 00000111 rrrrrbbb
E654 1EP6FIFOIE[9]
Endpoint 6 slave FIFO
Flag Interrupt Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E655 1EP6FIFOIRQ[9,7] Endpoint 6 slave FIFO
Flag Interrupt Request 0 0 0 0 0 PF EF FF 00000110 rrrrrbbb
E656 1EP8FIFOIE[9]
Endpoint 8 slave FIFO
Flag Interrupt Enable 0 0 0 0 EDGEPF PF EF FF 00000000 RW
E657 1EP8FIFOIRQ[9,7] Endpoint 8 slave FIFO
Flag Interrupt Request 0 0 0 0 0 PF EF FF 00000110 rrrrrbbb
Tab le 9. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 28 of 58
E658 1IBNIE IN-BULK-NAK Interrupt
Enable 0 0 EP8 EP6 EP4 EP2 EP1 EP0 00000000 RW
E659 1 IBNIRQ[7] IN-BULK-NAK interrupt
Request 0 0 EP8 EP6 EP4 EP2 EP1 EP0 00xxxxxx rrbbbbbb
E65A 1NAKIE Endpoint Ping-NAK / IBN
Interrupt Enable EP8 EP6 EP4 EP2 EP1 EP0 0IBN 00000000 RW
E65B 1NAKIRQ[7] Endpoint Ping-NAK / IBN
Interrupt Request EP8 EP6 EP4 EP2 EP1 EP0 0IBN xxxxxx0x bbbbbbrb
E65C 1USBIE USB Int Enables 0EP0ACK 0URES SUSP SUTOK SOF SUDAV 00000000 RW
E65D 1USBIRQ[7] USB Interrupt Requests 0EP0ACK 0URES SUSP SUTOK SOF SUDAV 0xxxxxxx rbbbbbbb
E65E 1EPIE Endpoint Interrupt
Enables EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 00000000 RW
E65F 1EPIRQ[7] Endpoint Interrupt
Requests EP8 EP6 EP4 EP2 EP1OUT EP1IN EP0OUT EP0IN 0RW
E660 1GPIFIE[9] GPIF Interrupt Enable 0 0 0 0 0 0 GPIFWF GPIFDONE 00000000 RW
E661 1GPIFIRQ[9] GPIF Interrupt Request 0 0 0 0 0 0 GPIFWF GPIFDONE 000000xx RW
E662 1USBERRIE USB Error Interrupt
Enables ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 00000000 RW
E663 1USBERRIRQ[7] USB Error Interrupt
Requests ISOEP8 ISOEP6 ISOEP4 ISOEP2 0 0 0 ERRLIMIT 0000000x bbbbrrrb
E664 1ERRCNTLIM USB Error counter and
limit EC3 EC2 EC1 EC0 LIMIT3 LIMIT2 LIMIT1 LIMIT0 xxxx0100 rrrrbbbb
E665 1CLRERRCNT Clear Error Counter EC3:0x x x x x x x x xxxxxxxx W
E666 1INT2IVEC Interru pt 2 (USB )
Autovector 0I2V4 I2V3 I2V2 I2V1 I2V0 0 0 00000000 R
E667 1INT4IVEC Interrupt 4 (slave FIFO &
GPIF) Autovector 1 0 I4V3 I4V2 I4V1 I4V0 0 0 10000000 R
E668 1INTSETUP Interrupt 2&4 setup 0 0 0 0 AV2EN 0INT4SRC AV4EN 00000000 RW
E669 7reserved
INPUT / OUTPUT
E670 1PORTACFG I/O PORTA Alternate
Configuration FLAGD SLCS 0 0 0 0 INT1 INT0 00000000 RW
E671 1PORTCCFG I/O PORTC Alternate
Configuration GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW
E672 1PORTECFG I/O PORTE Alternate
Configuration GPIFA8 T2EX INT6 RXD1OUT RXD0OUT T2OUT T1OUT T0OUT 00000000 RW
E673 4XTALINSRC XTALIN Clock Source 0 0 0 0 0 0 0 EXTCLK 00000000 rrrrrrrb
E677 1reserved
E678 1I2CS I²C Bus
Control & Status START STOP LASTRD ID1 ID0 BERR ACK DONE 000xx000 bbbrrrrr
E679 1I2DAT I²C Bus
Data d7 d6 d5 d4 d3 d2 d1 d0 xxxxxxxx RW
E67A 1I2CTL I²C Bus
Control 0 0 0 0 0 0 STOPIE 400KHZ 00000000 RW
E67B 1XAUTODAT1 Autoptr1 MOVX access,
when APTREN=1 D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E67C 1XAUTODAT2 Autoptr2 MOVX access,
when APTREN=1 D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
UDMA CRC
E67D 1UDMACRCH[9] UDMA CRC MSB CRC15 CRC14 CRC13 CRC12 CRC11 CRC10 CRC9 CRC8 01001010 RW
E67E 1UDMACRCL[9] UDMA CRC LSB CRC7 CRC6 CRC5 CRC4 CRC3 CRC2 CRC1 CRC0 10111010 RW
E67F 1UDMACRC-
QUALIFIER UDMA CRC Qualifier QENABLE 0 0 0 QSTATE QSIGNAL2 QSIGNAL1 QSIGNAL0 00000000 brrrbbbb
USB CONTROL
E680 1USBCS USB Control & Status 0 0 0 0 DISCON NOSYNSOF RENUM SIGRSUME x0000000 rrrrbbbb
E681 1SUSPEND Put chip into suspend x x x x x x x x xxxxxxxx W
E682 1WAKEUPCS Wakeup Control & Status WU2 WU WU2POL WUPOL 0DPEN WU2EN WUEN xx000101 bbbbrbbb
E683 1TOGCTL Toggle Control Q S R I/O EP3 EP2 EP1 EP0 x0000000 rrrbbbbb
E684 1USBFRAMEH USB Frame count H 0 0 0 0 0 FC10 FC9 FC8 00000xxx R
E685 1USBFRAMEL USB Frame count L FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 xxxxxxxx R
E686 1reserved
E687 1FNADDR USB Functi on address 0FA6 FA5 FA4 FA3 FA2 FA1 FA0 0xxxxxxx R
E688 2reserved
ENDPOINTS
E68A 1EP0BCH[9] Endpoint 0 Byte Count H (BC15) (BC14) (BC13) (BC12) (BC11) (BC10) (BC9) (BC8) xxxxxxxx RW
E68B 1EP0BCL[9] Endpoint 0 Byte Count L (BC7) BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E68C 1reserved
E68D 1EP1OUTBC Endpoint 1 OUT Byte
Count 0BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E68E 1reserved
E68F 1EP1INBC Endpoint 1 IN Byte Count 0BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E690 1EP2BCH[9] Endpoint 2 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 xxxxxxxx RW
Tab le 9. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 29 of 58
E691 1EP2BCL[9] Endpoint 2 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E692 2reserved
E694 1EP4BCH[9] Endpoint 4 Byte Count H 0 0 0 0 0 0 BC9 BC8 xxxxxxxx RW
E695 1EP4BCL[9] Endpoint 4 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E696 2reserved
E698 1EP6BCH[9] Endpoint 6 Byte Count H 0 0 0 0 0 BC10 BC9 BC8 xxxxxxxx RW
E699 1EP6BCL[9] Endpoint 6 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E69A 2reserved
E69C 1EP8BCH[9] Endpoint 8 Byte Count H 0 0 0 0 0 0 BC9 BC8 xxxxxxxx RW
E69D 1EP8BCL[9] Endpoint 8 Byte Count L BC7/SKIP BC6 BC5 BC4 BC3 BC2 BC1 BC0 xxxxxxxx RW
E69E 2reserved
E6A0 1EP0CS Endpoint 0 Control and
Status HSNAK 0 0 0 0 0 BUSY STALL 10000000 bbbbbbrb
E6A1 1EP1OUTCS Endpoint 1 OUT Control
and Status 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb
E6A2 1EP1INCS Endpoint 1 IN Control and
Status 0 0 0 0 0 0 BUSY STALL 00000000 bbbbbbrb
E6A3 1EP2CS Endpoint 2 Control and
Status 0NPAK2 NPAK1 NPAK0 FULL EMPTY 0STALL 00101000 rrrrrrrb
E6A4 1EP4CS Endpoint 4 Control and
Status 0 0 NPAK1 NPAK0 FULL EMPTY 0STALL 00101000 rrrrrrrb
E6A5 1EP6CS Endpoint 6 Control and
Status 0NPAK2 NPAK1 NPAK0 FULL EMPTY 0STALL 00000100 rrrrrrrb
E6A6 1EP8CS Endpoint 8 Control and
Status 0 0 NPAK1 NPAK0 FULL EMPTY 0STALL 00000100 rrrrrrrb
E6A7 1EP2FIFOFLGS Endpoint 2 slave FIFO
Flags 0 0 0 0 0 PF EF FF 00000010 R
E6A8 1EP4FIFOFLGS Endpoint 4 slave FIFO
Flags 0 0 0 0 0 PF EF FF 00000010 R
E6A9 1EP6FIFOFLGS Endpoint 6 slave FIFO
Flags 0 0 0 0 0 PF EF FF 00000110 R
E6AA 1EP8FIFOFLGS Endpoint 8 slave FIFO
Flags 0 0 0 0 0 PF EF FF 00000110 R
E6AB 1EP2FIFOBCH Endpoint 2 slave FIFO
total byte count H 0 0 0 BC12 BC11 BC10 BC9 BC8 00000000 R
E6AC 1EP2FIFOBCL Endpoint 2 slave FIFO
total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6AD 1EP4FIFOBCH Endpoint 4 slave FIFO
total byte count H 0 0 0 0 0 BC10 BC9 BC8 00000000 R
E6AE 1EP4FIFOBCL Endpoint 4 slave FIFO
total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6AF 1EP6FIFOBCH Endpoint 6 slave FIFO
total byte count H 0 0 0 0 BC11 BC10 BC9 BC8 00000000 R
E6B0 1EP6FIFOBCL Endpoint 6 slave FIFO
total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6B1 1EP8FIFOBCH Endpoint 8 slave FIFO
total byte count H 0 0 0 0 0 BC10 BC9 BC8 00000000 R
E6B2 1EP8FIFOBCL Endpoint 8 slave FIFO
total byte count L BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 00000000 R
E6B3 1SUDPTRH Setup Data Pointer high
address byte A15 A14 A13 A12 A11 A10 A9 A8 xxxxxxxx RW
E6B4 1SUDPTRL Setup Data Pointer low ad-
dress byte A7 A6 A5 A4 A3 A2 A1 0 xxxxxxx0 bbbbbbbr
E6B5 1SUDPTRCTL Setup Data Pointer Auto
Mode 0 0 0 0 0 0 0 SDPAUTO 00000001 RW
2reserved
E6B8 8SETUPDAT 8 bytes of setup data D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
SETUPDAT[0] =
bmRequestType
SETUPDAT[1] =
bmRequest
SETUPDAT[2:3] = wValue
SETUPDAT[4:5] = wIndex
SETUPDAT[6:7] =
wLength
GPIF
E6C0 1GPIFWFSELECT Waveform Selector SINGLEWR1 SINGLEWR0SINGLERD1 SINGLERD0 FIFOWR1 FIFOWR0 FIFORD1 FIFORD0 11100100 RW
E6C1 1GPIFIDLECS GPIF Done, GPIF IDLE
drive mode DONE 0 0 0 0 0 0 IDLEDRV 10000000 RW
E6C2 1GPIFIDLECTL Inactive Bus, CTL states 0 0 CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 11111111 RW
E6C3 1GPIFCTLCFG CTL Drive Type TRICTL 0CTL5 CTL4 CTL3 CTL2 CTL1 CTL0 00000000 RW
E6C4 1GPIFADRH[9] GPIF Address H 0 0 0 0 0 0 0 GPIFA8 00000000 RW
E6C5 1GPIFADRL[9] GPIF Address L GPIFA7 GPIFA6 GPIFA5 GPIFA4 GPIFA3 GPIFA2 GPIFA1 GPIFA0 00000000 RW
FLOWSTATE
E6C6 1 FLOWSTATE Flowstate Enable and
Selector FSE 0 0 0 0 FS2 FS1 FS0 00000000 brrrrbbb
Tab le 9. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 30 of 58
E6C7 1FLOWLOGIC Flow st a t e Log ic LFUNC1 LFUNC0 TERMA2 TERMA1 TERMA0 TERMB2 TERMB1 TERMB0 00000000 RW
E6C8 1FLOWEQ0CTL CTL-Pin States in
Flowstate
(when Logic = 0)
CTL0E3 CTL0E2 CTL0E1/
CTL5 CTL0E0/
CTL4 CTL3 CTL2 CTL1 CTL0 00000000 RW
E6C9 1FLOWEQ1CTL CTL-Pin States in Flow-
state (when Lo gi c = 1) CTL0E3 CTL0E2 CTL0E1/
CTL5 CTL0E0/
CTL4 CTL3 CTL2 CTL1 CTL0 00000000 RW
E6CA 1FLOWHOLDOFF Holdoff Configuration HOPERIOD3 HOPERIOD2HOPERIOD1 HOPERIOD
0HOSTATE HOCTL2 HOCTL1 HOCTL0 00000000 RW
E6CB 1FLOWSTB Flowstate Strobe
Configuration SLAVE RDYASYNC CTLTOGL SUSTAIN 0MSTB2 MSTB1 MSTB0 00100000 RW
E6CC 1FLOWSTBEDGE Flowstate Rising/Falling
Edge Configur ati o n 0 0 0 0 0 0 FALLING RISING 00000001 rrrrrrbb
E6CD 1FLOWSTBPERIOD Master-Strobe Half-P eriodD7 D6 D5 D4 D3 D2 D1 D0 00000010 RW
E6CE 1GPIFTCB3[9] GPIF T r an sact ion Count
Byte 3 TC31 TC30 TC29 TC28 TC27 TC26 TC25 TC24 00000000 RW
E6CF 1GPIFTCB2[9] GPIF T r an sact ion Count
Byte 2 TC23 TC22 TC21 TC20 TC19 TC18 TC17 TC16 00000000 RW
E6D0 1GPIFTCB1[9] GPIF T r an sact ion Count
Byte 1 TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 00000000 RW
E6D1 1GPIFTCB0[9] GPIF T r an sact ion Count
Byte 0 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TC0 00000001 RW
2reserved 00000000 RW
reserved
reserved
E6D2 1EP2GPIFFLGSEL[9] Endpoint 2 GPIF Flag
select 0 0 0 0 0 0 FS1 FS0 00000000 RW
E6D3 1EP2GPIFPFSTOP Endpoint 2 GPIF stop
transaction on prog. flag 0 0 0 0 0 0 0 FIFO2FLAG 00000000 RW
E6D4 1EP2GPIFTRIG[9] Endpoint 2 GPIF Trigger x x x x x x x x xxxxxxxx W
3reserved
reserved
reserved
E6DA 1EP4GPIFFLGSEL[9] Endpoint 4 GPIF Flag
select 0 0 0 0 0 0 FS1 FS0 00000000 RW
E6DB 1EP4GPIFPFSTOP Endpoint 4 GPIF stop
transaction on GPIF Flag 0 0 0 0 0 0 0 FIFO4FLAG 00000000 RW
E6DC 1EP4GPIFTRIG[9] Endpoint 4 GPIF Trigger x x x x x x x x xxxxxxxx W
3reserved
reserved
reserved
E6E2 1EP6GPIFFLGSEL[9] Endpoint 6 GPIF Flag
select 0 0 0 0 0 0 FS1 FS0 00000000 RW
E6E3 1EP6GPIFPFSTOP Endpoint 6 GPIF stop
transaction on prog. flag 0 0 0 0 0 0 0 FIFO6FLAG 00000000 RW
E6E4 1EP6GPIFTRIG[9] Endpoint 6 GPIF Trigger x x x x x x x x xxxxxxxx W
3reserved
reserved
reserved
E6EA 1EP8GPIFFLGSEL[9] Endpoint 8 GPIF Flag
select 0 0 0 0 0 0 FS1 FS0 00000000 RW
E6EB 1EP8GPIFPFSTOP Endpoint 8 GPIF stop
transaction on prog. flag 0 0 0 0 0 0 0 FIFO8FLAG 00000000 RW
E6EC 1EP8GPIFTRIG[9] Endpoint 8 GPIF Trigger x x x x x x x x xxxxxxxx W
3reserved
E6F0 1 XGPIFSGLDATH GPIF Data H
(16-bit mode onl y) D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW
E6F1 1XGPIFSGLDATLX Read/Write GPIF Data L &
trigger transa cti on D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E6F2 1XGPIFSGLDATL-
NOX Read GPIF Data L, no
transaction trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
E6F3 1GPIFREADYCFG Internal RDY , Sync/Async,
RDY pin states INTRDY SAS TCXRDY5 0 0 0 0 0 00000000 bbbrrrrr
E6F4 1GPIFREADYSTAT GPIF Ready Status 0 0 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0 00xxxxxx R
E6F5 1GPIFABORT Abort GPIF Waveforms x x x x x x x x xxxxxxxx W
E6F6 2reserved
ENDPOINT BUFFERS
E740 64 EP0BUF EP0-IN/-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E780 64 EP10UTBUF EP1-OUT buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
E7C0 64 EP1INBUF EP1-IN buffer D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
2048reserved RW
F000 1023EP2FIFOBUF 64/1023-byte EP 2 / slave
FIFO buffer (IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
F400 64 EP4FIFOBUF 64 byte EP 4 / slave FIFO
buffer (IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
Tab le 9. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 31 of 58
F600 64 reserved
F800 1023EP6FIFOBUF 64/1023-byte EP 6 / slave
FIFO buffer (IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
FC00 64 EP8FIFOBUF 64 byte EP 8 / slave FIFO
buffer (IN or OUT) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
FE00 64 reserved
xxxx I²C Configuration Byte 0DISCON 0 0 0 0 0 400KHZ xxxxxxxx
[[10]] n/a
Special Function Registers (SFRs)
80 1IOA[7] Port A (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
81 1SP Stack Pointer D7 D6 D5 D4 D3 D2 D1 D0 00000111 RW
82 1DPL0 Data Pointer 0 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
83 1DPH0 Data Pointer 0 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
84 1DPL1[7] Data Pointer 1 L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
85 1DPH1[7] Data Pointer 1 H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
86 1DPS[7] Data Pointer 0/1 select 0 0 0 0 0 0 0 SEL 00000000 RW
87 1PCON Power Control SMOD0 x 1 1 x x x IDLE 00110000 RW
88 1TCON Timer/Counter Control
(bit addressable) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00000000 RW
89 1TMOD Timer/Counter Mode
Control GATE CT M1 M0 GATE CT M1 M0 00000000 RW
8A 1TL0 Timer 0 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
8B 1TL1 Timer 1 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
8C 1TH0 Timer 0 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
8D 1TH1 Timer 1 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
8E 1CKCON[7] Clock Control x x T2M T1M T0M MD2 MD1 MD0 00000001 RW
8F 1reserved
90 1IOB[7] Port B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
91 1EXIF[7] External Interrupt Flag(s) IE5 IE4 I²CINT USBNT 1 0 0 0 00001000 RW
92 1MPAGE[7] Upper Addr Byte of MOVX
using @R0 / @R1 A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
93 5reserved
98 1SCON0 Serial Port 0 Cont rol
(bit addressable) SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 TI_0 RI_0 00000000 RW
99 1SBUF0 Serial Port 0 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
9A 1AUTOPTRH1[7] Autopointer 1 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
9B 1AUTOPTRL1[7] Autopointer 1 Address L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
9C 1reserved
9D 1AUTOPTRH2[7] Autopointer 2 Address H A15 A14 A13 A12 A11 A10 A9 A8 00000000 RW
9E 1AUTOPTRL2[7] Autopointer 2 Address L A7 A6 A5 A4 A3 A2 A1 A0 00000000 RW
9F 1reserved
A0 1IOC[7] Port C (bit address abl e) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
A1 1INT2CLR[7] Interrupt 2 clear x x x x x x x x xxxxxxxx W
A2 1INT4CLR[7] Interrupt 4 clear x x x x x x x x xxxxxxxx W
A3 5reserved
A8 1IE Interrupt Enable
(bit addressable) EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 00000000 RW
A9 1reserved
AA 1EP2468STAT[7] Endpoint 2,4,6,8 status
flags EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E 01011010 R
AB 1EP24FIFOFLGS
[7] Endpoint 2,4 slave FIFO
status flags 0EP4PF EP4EF EP4FF 0EP2PF EP2EF EP2FF 00100010 R
AC 1EP68FIFOFLGS
[7] Endpoint 6,8 slave FIFO
status flags 0EP8PF EP8EF EP8FF 0EP6PF EP6EF EP6FF 01100110 R
AD 2reserved
AF 1AUTOPTRSETUP[7] Autopointer 1&2 setup 0 0 0 0 0 APTR2INC APTR1INC APTREN 00000110 RW
B0 1IOD[7] Port D (bit address abl e) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
B1 1IOE[7] Port E
(NOT bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
B2 1OEA[7] Port A Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B3 1OEB[7] Port B Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B4 1OEC[7] Port C Output Enabl e D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B5 1OED[7] Port D Output Enabl e D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B6 1OEE[7] Port E Output Enable D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
B7 1reserved
B8 1IP Interrupt Priority (bit ad-
dressable) 1PS1 PT2 PS0 PT1 PX1 PT0 PX0 10000000 RW
B9 1reserved
BA 1EP01STAT[7] Endpoint 0&1 Status 0 0 0 0 0 EP1INBSY EP1OUTBS
YEP0BSY 00000000 R
BB 1GPIFTRIG[7] [9] Endpoint 2,4,6,8 GPIF
slave FIFO Trig ge r DONE 0 0 0 0 RW EP1 EP0 10000xxx brrrrbbb
Tab le 9. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
[+] Feedback
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BC 1reserved
BD 1GPIFSGLDATH[7] GPIF Data H (16-bit mo de
only) D15 D14 D13 D12 D11 D10 D9 D8 xxxxxxxx RW
BE 1GPIFSGLDATLX[7] GPIF Data L w/ Trigger D7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx RW
BF 1GPIFSGLDAT
LNOX[7] GPIF Data L w/ No T riggerD7 D6 D5 D4 D3 D2 D1 D0 xxxxxxxx R
C0 1SCON1[7] Serial Port 1 Cont rol (bit
addressable) SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00000000 RW
C1 1SBUF1[7] Serial Port 1 Data Buffer D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
C2 6reserved
C8 1T2CON Timer/Counter 2 Control
(bit addressable) TF2 EXF2 RCLK TCLK EXEN2 TR2 CT2 CPRL2 00000000 RW
C9 1reserved
CA 1RCAP2L Capture for Timer 2, au-
to-reload , up-counter D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
CB 1RCAP2H Capture for Timer 2, au-
to-reload , up-counter D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
CC 1TL2 Timer 2 reload L D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
CD 1TH2 Timer 2 reload H D15 D14 D13 D12 D11 D10 D9 D8 00000000 RW
CE 2reserved
D0 1PSW Program Status Word (bit
addressable) CY AC F0 RS1 RS0 OV F1 P00000000 RW
D1 7reserved
D8 1EICON[7] External Interrupt Control SMOD1 1ERESI RESI INT6 0 0 0 01000000 RW
D9 7reserved
E0 1ACC Accumulator (bit address-
able) D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
E1 7reserved
E8 1EIE[7] External Interrupt En-
able(s) 1 1 1 EX6 EX5 EX4 EI²C EUSB 11100000 RW
E9 7reserved
F0 1 B B (bit addressable) D7 D6 D5 D4 D3 D2 D1 D0 00000000 RW
F1 7reserved
F8 1EIP[7] External In terrupt Priority
Control 1 1 1 PX6 PX5 PX4 PI²C PUSB 11100000 RW
F9 7reserved
Legend (For the Access column)
R = all bits read-only
W = all bits write-only
r = read-only bit
w = write-only bit
b = both read/write bit
Tab le 9. FX1 Register Summary (continued)
Hex Size Name Description b7 b6 b5 b4 b3 b2 b1 b0 Default Access
Notes
10.If no EEPROM is detected by the SIE then the default is 00000000.
11. It is recommended to not power I/O when chip power is off.
12.CLKOUT is shown with positive polarity.
13.tACC1 is computed from the parameters in Table 11 as follows:
tACC1(24 MHz) = 3*tCL – tAV – tDSU = 106 ns
tACC1(48 MHz) = 3*tCL – tAV – tDSU = 43 ns.
[+] Feedback
CY7C64713
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Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User gui d el i ne s are not tested.
Storage Temperature................................ –65 °C to +150 °C
Ambient Temp erature with Power Supplied.... 0 °C to +70 °C
Supply Voltage to Ground Potential..............–0.5 V to +4.0 V
DC Input Voltage to Any Input Pin................... ... ... 5.25 V[11]
DC Voltage Applied to Outputs
in High Z State................................... –0.5 V to VCC + 0.5 V
Power Dissipation................... ................................. 235 mW
S tatic Discharge V oltage......................................... > 2000 V
Max Output Current, per I/O port................................ 10 mA
Max Output Current, all five I/O ports
(128 and 100 pin packages)....................................... 50 mA
Operating Conditions
TA (Ambient Temperature Under Bias)........... 0 °C to +70 °C
Supply Voltage..........................................+3.15 V to +3.45 V
Ground Voltage.................................................................0 V
FOSC (Oscillator or Crystal Frequency)....24 MHz ± 100 ppm
Parallel Resonant
DC Characteristics
USB Transceiver
USB 2.0 compliant in full speed mode.
Table 10. DC Characteristic s
Parameter Description Conditions Min Typ Max Unit
VCC Supply Voltage 3.15 3.3 3.45 V
VCC Ramp Up 0 to 3.3 V 200 μs
VIH Input HIGH Voltage 2 5.25 V
VIL Input LOW Voltage –0.5 0.8 V
VIH_X Crystal input HIGH Voltage 2 5.25 V
VIL_X Crystal input LOW Voltage –0.05 0.8 V
IIInput Leakage Current 0< VIN < VCC ±10 μA
VOH Output Voltage HIGH IOUT = 4 mA 2.4 V
VOL Output LOW Voltage IOUT = –4 mA 0.4 V
IOH Output Current HIGH 4mA
IOL Output Current LOW 4mA
CIN Input Pin Capacitance Except D+/D– 3.29 10 pF
D+/D– 12.96 15 pF
ISUSP Suspend Current Connected .5 1.2 mA
Disconnected .3 1.0 mA
ICC Supply Current 8051 running, connected to USB 35 65 mA
TRESET Reset Time after Valid Power VCC min = 3.0 V 5.0 ms
Pin Reset after powered on 200 μs
Note
14.tACC2 and tACC3 are computed from the paramet ers in Table 12 as follows:
tACC2(24 MHz) = 3*tCL – tAV – tDSU = 106 ns
tACC2(48 MHz) = 3*tCL – tAV – tDSU = 43 ns
tACC3(24 MHz) = 5*tCL – tAV – tDSU = 190 ns
tACC3(48 MHz) = 5*tCL – tAV – tDSU = 86 ns.
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 34 of 58
AC Electrical Characteristics
USB Transceiver
USB 2.0 compliant in full speed mode.
Figure 12. Program Memory Read Timing Diagram
tCL
tDH
tSOEL
tSCSL
PSEN#
D[7..0]
OE#
A[15..0]
CS#
tSTBL
data in
tACC1
tAV
tSTBH
tAV
CLKOUT[12]
[13]
Table 11. Program Memory Read Parameters
Parameter Description Min Typ Max Unit Notes
tCL 1/CLKOUT Frequency 20.83 ns 48 MHz
41.66 ns 24 MHz
83.2 ns 12 MHz
tAV Delay from Clock to Valid Address 0 10.7 ns
tSTBL Clock to PSEN Low 0 8 ns
tSTBH Clock to PSEN High 0 8 ns
tSOEL Clock to OE Low 11.1 ns
tSCSL Clock to CS Low 13 ns
tDSU Data Setup to Clock 9.6 ns
tDH Data Hold Time 0 ns
[+] Feedback
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Figure 13. Data Memory Read Timing Diagram
When using the AUTPOPTR1 or AUTOP TR2 to address external memory, the address of AUTOPTR1 is active only when either RD#
or WR# are active. The address of AUTOPTR2 is active througho ut the cycle and meets the above address valid time for which is
based on the stretch value.
data in
tCL
A[15..0]
tAV tAV
RD# tSTBL tSTBH
tDH
D[7..0] data in
tACC1
[14 tDSU
Stretch = 0
Stretch = 1
tCL
A[15..0]
tAV
RD#
tDH
D[7..0] tACC1[14] tDSU
CS#
CS# tSCSL
OE# tSOEL
CLKOUT[12]
CLKOUT[12]
Table 12. Data Memory Read Parameters
Parameter Description Min Typ Max Unit Notes
tCL 1/CLKOUT Frequency 20.83 ns 48 MHz
41.66 ns 24 MHz
83.2 ns 12 MHz
tAV Delay from Clock to Valid Address 10.7 ns
tSTBL Clock to RD LOW 11 ns
tSTBH Clock to RD HIGH 11 ns
tSCSL Clock to CS LOW 13 ns
tSOEL Clock to OE LOW 11.1 ns
tDSU Data Setup to Clock 9.6 ns
tDH Data Hold Time 0 ns
[+] Feedback
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Document #: 38-08039 Rev. *I Page 36 of 58
Figure 14. Data Memory Write Timing Diagram
When using the AUTPOPTR1 or AUTOP TR2 to address external memory, the address of AUTOPTR1 is active only when either RD#
or WR# are active. The address of AUTOPTR2 is active througho ut the cycle and meets the above address valid time for which is
based on the stretch value.
tOFF1
CLKOUT
A[15..0]
WR#
tAV
D[7..0]
tCL
tSTBL tSTBH
data out
tOFF1
CLKOUT
A[15..0]
WR#
tAV
D[7..0]
tCL
data out
Stretch = 1
tON1
tSCSL
tAV
CS#
tON1
CS#
Tab le 13. Data Memory Write Parameters
Parameter Description Min Max Unit Notes
tAV Delay from Clock to Valid Address 0 10.7 ns
tSTBL Clock to WR Pulse LOW 0 11.2 ns
tSTBH Clock to WR Pulse HIGH 0 11.2 ns
tSCSL Clock to CS Pulse LOW 13.0 ns
tON1 Clock to Data Turn-on 0 13.1 ns
tOFF1 Clock to Data Hold Time 0 13.1 ns
Notes
15.GPIF asynchronous RDYx signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
16.IFCLK must not exceed 48 MHz.
[+] Feedback
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PORTC Strobe Feature Timings
The RD# and WR# are present in the 100 pin version and the
128 pin package. In these 100 pin and 128 pin versions, an 8051
control bit is set to pulse the RD# and WR# pins when the 8051
reads from or writes to the PORTC. This feature is enabled by
setting the PORTCSTB bit in CPUCS register.
The RD# and WR# strobes are asserted for two CLKOUT cycles
when the PORTC is accessed.
The WR# strobe is asserted two clock cycles after the PORTC is
updated and is active for two clock cycles after that as shown in
Figure 16.
As for read, the value of the PORTC three clock cycles before
the assertion of RD# is the value that the 8051 reads in. The RD#
is pulsed for 2 clock cycles after 3 clock cycles from the point
when the 8051 has performed a read function on PORTC.
In this feature the RD# signal prompts the external logic to
prepare the next data byte. Nothing gets sampled internal ly on
assertion of the RD# signal itself. It is just a “prefetch” type signal
to get the next data byte prepared. Therefore, using it meets the
set up time to the next read.
The purpose of this pulsing of RD# is to let the external peripheral
know that the 8051 is done reading PORTC and that the data
was latched into the PORTC three CLKOUT cycles prior to
asserting the RD# signal. After the RD# is pulsed the external
logic may update the data on PORTC.
The timing diagram of the read and write strobing function on
accessing PORTC follows. Refer to Figure 13 on page 35 and
Figure 14 on page 36 for details on propagation delay of RD#
and WR# signals.
Figure 16. WR# Strobe Function when PORTC is Access ed by 8051
Figure 17. RD# Strobe Function when PORTC is Accessed by 8051
CLKOUT
WR#
tCLKOUT
PORTC IS UPDATED
tSTBL tSTBH
CLKOUT
tCLKOUT
DATA MUST BE HELD FOR 3 CLK CYLCES DATA IS UPDATED BY EXTERNAL LOGIC
8051 READS PORTC
RD#
tSTBL tSTBH
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 38 of 58
GPIF Synchronous Signals
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 18. GPIF Synchronous Signals Timing Diagram
The following table provides the GPIF Synchronous Signals Parameters with Internally Sourced IFCLK. [15, 16 ]
The following table provides the GPIF Synchronous Signals Parameters with Externally Sourced IFCLK.[16]
DATA(output)
tXGD
IFCLK
RDYX
DATA(input) valid
tSRY
tRYH
tIFCLK
tSGD
CTLX
tXCTL
tDAH
NN+1
GPIFADR[8:0]
tSGA
Table 14. GPIF Synchron ous Signals Parameters with Internally Sourced IFCLK
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 ns
tSRY RDYX to Clock Setup Time 8.9 ns
tRYH Clock to RDYX 0ns
tSGD GPIF Data to Clock Setup Time 9.2 ns
tDAH GPIF Data Hold Time 0 ns
tSGA Clock to GPIF Address Propagation Delay 7.5 ns
tXGD Clock to GPIF Data Output Propagation Delay 11 ns
tXCTL Clock to CTLX Output Propagation Delay 6.7 ns
Table 15. GPIF Synchron ous Signals Parameters with Externally Sourced IFCLK
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 200 ns
tSRY RDYX to Clock Setup Time 2.9 ns
tRYH Clock to RDYX 3.7 ns
tSGD GPIF Data to Clock Setup Time 3.2 ns
tDAH GPIF Data Hold Time 4.5 ns
tSGA Clock to GPIF Address Propagation Delay 11.5 ns
tXGD Clock to GPIF Data Output Propagation Delay 15 ns
tXCTL Clock to CTLX Output Propagation Delay 10.7 ns
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 39 of 58
Slave FIFO Synchronous Read
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 19. Slave FIFO Synchronous Read Timing Diagram
The following table provides the Slave FIFO Synchronous Read Parameters with Inte rnally Sourced IFCLK. [16]
The following table provides the Slave FIFO Synchronous Read Parameters with Externally Sourced IFCLK.[16]
IFCLK
SLRD
FLAGS
SLOE
tSRD tRDH
tOEon tXFD
tXFLG
DATA
tIFCLK
N+1
tOEoff
N
Tab le 16. Slave FIFO Synchronous Read Parameters with Interna lly Sou rced IFCLK
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 ns
tSRD SLRD to Clock Setup Time 18.7 ns
tRDH Clock to SLRD Hold Time 0 ns
tOEon SLOE Turn on to FIFO Data Valid 10.5 ns
tOEoff SLOE Turn off to FIFO Data Hold 10.5 ns
tXFLG Clock to FLAGS Output Propagation Delay 9.5 ns
tXFD Clock to FIFO Data Output Propagation Delay 11 ns
Tab le 17. Slave FIFO Synchronous Read Parameters with Externa lly Sou rced IFCLK
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 200 ns
tSRD SLRD to Clock Setup Time 12.7 ns
tRDH Clock to SLRD Hold Time 3.7 ns
tOEon SLOE Turn on to FIFO Data Valid 10.5 ns
tOEoff SLOE Turn off to FIFO Data Hold 10.5 ns
tXFLG Clock to FLAGS Output Propagation Delay 13.5 ns
tXFD Clock to FIFO Data Output Propagation Delay 15 ns
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 40 of 58
Slave FIFO Asynchronous Read
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 20. Slave FIFO Asynchronous Read Timing Diagram
In the following table, the Slave FIFO asynchronou s parameter values use internal IFCLK setting at 48 MHz.
Tab le 18 . Slave FIFO Asynchronous Read Parameters
Parameter Description Min Max Unit
tRDpwl SLRD Pulse Width LOW 50 ns
tRDpwh SLRD Pulse Width HIGH 50 ns
tXFLG SLRD to FLAGS Output Propagation Delay 70 ns
tXFD SLRD to FIFO Data Output Propagation Delay 15 ns
tOEon SLOE Turn-on to FIFO Data Valid 10.5 ns
tOEoff SLOE Turn-off to FIFO Data Hold 10.5 ns
SLRD
FLAGS
tRDpwl
tRDpwh
SLOE
tXFLG
tXFD
DATA
tOEon tOEoff
N+1
N
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 41 of 58
Slave FIFO Synchronous Write
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 21. Slave FIFO Synchronous Write Timing Diagram
The following table provides the Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK. [16]
The following table provides the Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK. [16]
Tab le 19. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 ns
tSWR SLWR to Clock Setup Time 18.1 ns
tWRH Clock to SLWR Hold Time 0 ns
tSFD FIFO Data to Clock Setup Time 9.2 ns
tFDH Clock to FIFO Data Hold Time 0 ns
tXFLG Clock to FLAGS Output Propagation Time 9.5 ns
Tab le 20. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK [16]
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 200 ns
tSWR SLWR to Clock Setup Time 12.1 ns
tWRH Clock to SLWR Hold Time 3.6 ns
tSFD FIFO Data to Clock Setup Time 3.2 ns
tFDH Clock to FIFO Data Hold Time 4.5 ns
tXFLG Clock to FLAGS Output Propagation Time 13.5 ns
Z
Z
tSFD tFDH
DATA
IFCLK
SLWR
FLAGS
tWRH
tXFLG
tIFCLK
tSWR
N
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 42 of 58
Slave FIFO Asynchronous Write
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 22. Slave FIFO Asynchronous Write Timing Diagram
In the following table, the Slave FIFO asynchronou s parameter values use internal IFCLK setting at 48 MHz.
Slave FIFO Synchronous Packet End Strobe
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 23. Slave FIFO Synchronous Packet End Strobe Timing Diagram
The following table provides the Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK. [16]
DATA
tSFD tFDH
FLAGS tXFD
SLWR/SLCS#
tWRpwh
tWRpwl
Tab le 21. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
Parameter Description Min Max Unit
tWRpwl SLWR Pulse LOW 50 ns
tWRpwh SLWR Pulse HIGH 70 ns
tSFD SLWR to FIFO DATA Setup Time 10 ns
tFDH FIFO DATA to SLWR Hold Time 10 ns
tXFD SLWR to FLAGS Output Propagation Delay 70 ns
FLAGS
tXFLG
IFCLK
PKTEND tSPE
tPEH
Tab le 22. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 ns
tSPE PKTEND to Clock Setup Time 14.6 ns
tPEH Clock to PKTEND Hold Time 0 ns
tXFLG Clock to FLAGS Output Propagation Delay 9.5 ns
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 43 of 58
The following table provides the Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK. [16]
There is no specific timing requirement that needs to be met for
asserting the PKTEND pin concerning asserting SLWR.
PKTEND is asserted with the last data value clocked into the
FIFOs or thereafter. The only consideration is that the set up time
tSPE and the hold time tPEH for PKTEND must be met.
Although there are no specific timing requirements for asserting
PKTEND in relation to SLWR, there exists a specific case
condition that needs attention. When using the PKTEND to
commit a one byte or word packet, an additional timing
requirement must be met when the FIFO is configured to operate
in auto mode and it is necessary to send two packets back to
back:
A full packet (defined as the number of bytes in the FIFO
meeting the level set in the AUTOINLEN register) committed
automatically followed by
A short one byte or word packet committed manually using the
PKTEND pin.
In this particular scenario, the developer must assert the
PKTEND at least one clock cycle after the rising edge that
caused the last byte or word to be clocked into the previous auto
committed packet. Figure 24 shows this scenario. X is the value
the AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
Figure 24 shows a scenario where two packets are being
committed. The first packet is committed automatically when the
number of bytes in the FIFO reaches X (value set in AUTOINLEN
register) and the second one byte or word short packet being
committed manually using PKTEND. Note that there is at least
one IFCLK cycle timing between asserting PKTEND and
clocking of the last byte of the previous packet (causing the
packet to be committed automatically). Failing to a dhere to this
timing results in the FX2 failing to send the one byte or word short
packet.
Figure 24. Slave FIFO Synchronous Write Sequence and Timing Diagram
Tab le 23 . Slave FIFO Synchronous Packet End Strobe Parameters with Externally Sourced IFCLK
Parameter Description Min Max Unit
tIFCLK IFCLK Period 20.83 200 ns
tSPE PKTEND to Clock Setup Time 8.6 ns
tPEH Clock to PKTEND Hold Time 2.5 ns
tXFLG Clock to FLAGS Output Propagation Delay 13.5 ns
IFCLK
SLWR
DATA
tIFCLK
>= tSWR >= tWRH
X-2
PKTEND
X-3
tFAH
tSPE tPEH
FIFOADR
tSFD tSFD tSFD
X-4
tFDH
tFDH
tFDH
tSFA
1
X
tSFD tSFD tSFD
X-1
tFDH
tFDH
tFDH
At least one IFCLK cycle
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 44 of 58
Slave FIFO Asynchronous Packet End Strobe
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 25. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
In the following table, the Slave FIFO asynchronou s parameter values use internal IFCLK setting at 48 MHz.
Slave FIFO Output Enable
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 26. Slave FIFO Output Enable Timing Diagram
Slave FIFO Address to Flags/Data
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 27. Slave FIFO Address to Flags/Data Timing Diagr am
Tab le 24. Slave FIFO Asynchronous Pack et End Strobe Parameters
Parameter Description Min Max Unit
tPEpwl PKTEND Pulse Width LOW 50 ns
tPWpwh PKTEND Pulse Width HIGH 50 ns
tXFLG PKTEND to FLAGS Output Propagation Delay 115 ns
FLAGS tXFLG
PKTEND tPEpwl
tPEpwh
Tab le 25 . Slave FIFO Output Enable Parameters
Parameter Description Max Unit
tOEon SLOE Assert to FIFO DATA Output 10.5 ns
tOEoff SLOE Deassert to FIFO DATA Hold 10.5 ns
SLOE
DATA tOEon tOEoff
Table 26. Slave FIFO Address to Flags/Data Parameters
Parameter Description Max Unit
tXFLG FIFOADR[1:0] to FLAGS Output Propagation Delay 10.7 ns
tXFD FIFOADR[1:0] to FIFODATA Output Propagation Delay 14.3 ns
FIFOADR [1.0]
DATA
tXFLG
tXFD
FLAGS
NN+1
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 45 of 58
Slave FIFO Synchronous Address
Figure 28. Slave FIFO Synchronous Add res s Timing Diagram
The following table provides the Slave FIFO Synchronous Address Parameters.[16]
Slave FIFO Asynchronous Address
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 29. Slave FIFO Asynchron ou s Address Timing Diagram
In the following table, the Slave FIFO asynchronou s parameter values use internal IFCLK setting at 48 MHz.
IFCLK
SLCS/FIFOADR [1:0]
tSFA tFAH
Table 27. Slave FIFO Synchro nous Address Parameters
Parameter Description Min Max Unit
tIFCLK Interface Clock Period 20.83 200 ns
tSFA FIFOADR[1:0] to Clock Setup Time 25 ns
tFAH Clock to FIFOADR[1:0] Hold Time 10 ns
Tab le 28. Slave FIFO Asynchronous Address Parameters
Parameter Description Min Unit
tSFA FIFOADR[1:0] to RD/WR/PKTEND Setup Time 10 ns
tFAH RD/WR/PKTEND to FIFOADR[1:0] Hold Time 10 ns
RD/WR/PKTEND
SLCS/FIFOADR [1:0]
tSFA tFAH
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 46 of 58
Sequence Diagram
Single and Burst Synchronous Read Example
Figure 30. Slave FIFO Synchronous Read Sequence and Timing Diagram
Figure 31. Slave FIFO Synchronous Sequence of Event s Diagram
Figure 30 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. This diagram illustrates a single read
followed by a burst read.
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the F IFO add ress setup time is more than
one IFCLK cycle.
At t = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that is
driven on the bus is the data that the internal FIFO pointer is
currently pointing to. In this example it is the first data value in
the FIFO.
Note The data is pre-fetched and is driven on the bus when
SLOE is asserted.
At t = 2, SLRD is asserted. SLRD must meet the setup time of
tSRD (time from asserting the SLRD signal to the rising edge of
the IFCLK) and maintain a minimum hold time of tRDH (time
from the IFCLK edge to the deassertion of the SLRD signal).
If the SLCS signal is used, it must be asserted with SLRD, or
before SLRD is asserted (that is, the SLCS and SLRD signals
must both be asserted to start a valid read condition).
The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tXFD (measured from the rising edge of
IFCLK) the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
MUST also be asserted.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5.
IFCLK
SLRD
FLAGS
SLOE
DATA
tSRD tRDH
tOEon
tXFD
tXFLG
tIFCLK
N+1
Data Driven: N
>= tSRD
tOEon
tXFD
N+2
tXFD tXFD
>= tRDH
tOEoff
N+4
N+3
tOEoff
tSFA tFAH
FIFOADR
SLCS
t=0
N+1
t=1
t=2 t=3
t=4
tFAH
T=0
tSFA
T=1
T=2 T=3
T=4
NNN+1 N+2
FIFO POINTER N+3
FIFO DATA BUS
N+4
Not Driven Driven: N
SLOE SLRD
N+1 N+2 N+3 Not Driven
SLRD
SLOE
IFCLK IFCLK IFCLK IFCLK IFCLK N+4
N+4
IFCLK IFCLK
IFCLK IFCLK
SLRD
N+1
SLRD
N+1
N+1
SLOE
Not Driven
N+4
N+4
IFCLK
SLOE
[+] Feedback
CY7C64713
Document #: 38-08039 Rev. *I Page 47 of 58
Note For the burst mode, the SLRD and SLOE are left asserted during the entire duration of the read. In the burst read mode, when
SLOE is asserted, data indexed by the FIFO pointer is on the data bus. During the first read cycle, on the rising edge of the clock the
FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK, while the SLRD is
asserted, the FIFO pointer is increm ented and the next data value is placed on the data bus.
Single and Burst Synchronous Write
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 32. Slave FIFO Synchronous Write Sequence and Timing Diagram
Figure 32 shows the timing relationship of the SLAVE FIFO
signals during a synchronous write using IFCLK as the synchro-
nizing clock. This diagram illustrates a single write followed by
burst write of 3 bytes and committing all 4 bytes as a short packet
using the PKTEND pin.
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note tSFA has a minimum of 25 ns. This means when IFCLK is
running at 48 MHz, the FIFO address setup time is more than
one IFCLK cycle.
At t = 1, the external master or peripheral must output the data
value onto th e da ta bus with a minimum set up time of tSFD
before the rising edge of IFCLK.
At t = 2, SLWR is asserted. The SLWR must meet the setup
time of tSWR (time from asserting the SL WR signal to the rising
edge of IFCLK) and maintain a minimum hold time of tWRH (time
from the IFCLK edge to the deassertion of the SLWR signal).
If SLCS signal is used, it must be asserted with SLWR or before
SLWR is asserted. (that is the SLCS and SLWR signals must
both be asserted to start a valid write condition).
While the SL WR is asserted, data is written to the FIFO and on
the rising edge of the IFCLK, the FIFO pointer is incremented.
The FIFO flag is also updated after a delay of tXFLG from the
rising edge of the clock.
The same sequence of events are also sh own for a burst write
and are marked with the time indicators of T = 0 through 5.
Note For the burst mode, SLWR and SLCS are left asserted for
the entire d uration of writin g all th e required d ata values. In this
burst write mode, after the SLWR is asserted, the data on the
FIFO data bus is written to the FIFO on every rising edge of
IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In Figure 32, after the four bytes are written to the FIFO,
SL WR is deasserted. The short 4-byte packet is committed to the
host by asserting th e PKTEN D sig n al .
There is no specific timing requirement that must be met for
asserting the PKTEND signal with regards to asserting the
SLWR signal. PKTEND is asserted with the last data value or
thereafter. The only consideration is the setup time tSPE and the
hold time tPEH must be met. In the scenario of Figure 32, the
number of data values committed includes the last value written
to the FIFO. In this example, both the data value and the
PKTEND signal are clocked on the same rising edge of IFCLK.
PKTEND is asserted in subsequent clock cycles. The
FIFOADDR lines must be held constant during the PKTEND
assertion.
IFCLK
SLWR
FLAGS
DATA
tSWR tWRH
tSFD
tXFLG
tIFCLK
N
>= tSWR >= tWRH
N+3
PKTEND
N+2
tXFLG
tSFA tFAH
tSPE tPEH
FIFOADR
SLCS
tSFD tSFD tSFD
N+1
tFDH
tFDH
tFDH tFDH
t=0
t=1
t=2 t=3
tSFA
tFAH
T=1
T=0
T=2 T=5
T=3 T=4
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CY7C64713
Document #: 38-08039 Rev. *I Page 48 of 58
Although there are no specific timing requirement for asserting
PKTEND, there is a specific corner case condition that needs
attention while using the PKTEND to commit a one byte or word
packet. Additional timing requirements exist when the FIFO is
configured to operate i n auto mode and it is necessary to send
two packets: a full packet (full defined as the number of bytes in
the FIFO meeting the level set in AUTOINLEN register)
committed automatically followed by a short one byte or word
packet committed manually using the PKTEND pin. In this case,
the external master must make su re to assert the PKTEND pin
at least one clock cycle after the rising edge that caused the last
byte or word to be clocked into the previous auto committed
packet (the packet with the number of bytes equal to what is set
in the AUTOINLEN register). Refer to Table 20 on page 41 for
further details on this timing.
Sequence Diagram of a Single and Burst Asynchronous Read
Figure 33. Slave FIFO Asynchronous Read Sequence and Timing Diagram
Figure 34. Slave FIFO Asynchronous Read Sequence of Events Diagram
Figure 33 shows the timing relationship of the SLAVE FIFO
signals during an asynchronous FIFO read. It shows a single
read followed by a burst read.
At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
At t = 2, SLRD is asserted. The SLRD must meet the minimum
active pulse of tRDpwl and minimum de-active pulse width of
tRDpwh. If SLCS is used then, SLCS must be in asserted with
SLRD or before SLRD is asserted (that is, the SLCS and SLRD
signals must both be asserted to start a valid read condition).
The data that drives after asserting SLRD, is the updated data
from the FIFO. This data is valid after a propagation delay of
tXFD from the activating edge of SLRD. In Figure 33, data N is
the first valid data read from the FIFO. For data to appear on
the data bus during the read cycle (that is, SLRD is asserted),
SLOE MUST be in an asserted state. SLRD and SLOE can
also be tied together.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5.
Note In burst read mode, during SLOE is assertion, the data bus
is in a driven state and outputs the previous data. After the SLRD
is asserted, the data from the FIFO is driven on the data bus
(SLOE must also be asserted) and then the FIFO pointer is incre-
mented.
SLRD
FLAGS
SLOE
DATA
tRDpwh
tRDpwl
tOEon
tXFD
tXFLG
N
Data (X)
tXFD
N+1
tXFD
tOEoff
N+3
N+2
tOEoff
tXFLG
tSFA tFAH
FIFOADR
SLCS
Driven
tXFD
tOEon
tRDpwh
tRDpwl tRDpwh
tRDpwl tRDpwh
tRDpwl
tFAH tSFA
N
t=0 T=0
T=1 T=7
T=2 T=3 T=4 T=5 T=6
t=1
t=2 t=3
t=4
NN
SLOE SLRD
FIFO POINTER
N+3
FIFO DATA BUS Not Driven Driven: X N Not Driven
SLOE
N
N+2
N+3
SLRD
N
N+1
SLRD
N+1
SLRD
N+1
N+2
SLRD
N+2
SLRD
N+2
N+1
SLOE
Not Driven
SLOE
N
N+1
N+1
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CY7C64713
Document #: 38-08039 Rev. *I Page 49 of 58
Sequence Diagram of a Single and Burst Asynchronous Write
In the following figure, dashed lines indi cate signals with programmable polarity.
Figure 35. Slave FIFO Asynch ronous Write Sequence and Timing Diagram
Figure 35 shows the timing relationship of the SLA VE FIFO write
in an asynchronous mode. This diagram shows a single write
followed by a burst write of 3 bytes and committing the
4-byte-short packet using PKTEND.
At t = 0 the FIFO address is applied, insuring that it meets the
setup time of tSFA. If SLCS is used, it must also be asserted
(SLCS may be tied low in some applications).
At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of tWRpwl and minimum de-active pulse width of
tWRpwh. If the SLCS is used, it must be in asserted with SLWR
or before SLWR is asserted.
At t = 2, data must be present on the bus tSFD before the
deasserting edge of SLWR.
At t = 3, deasserting SL WR causes the data to be written from
the data bus to the FIFO and then increments the FIFO pointer.
The FIFO flag is also updated after tXFLG from the deasserting
edge of SLWR.
The same sequence of events are shown for a burst write and is
indicated by the timing marks of T = 0 through 5.
Note In the burst write mode, after SL WR is deasserted, the data
is written to th e FIFO and then the FIFO pointer i s incremented
to the next byte in the FIFO. The FIFO pointer is post incre-
mented.
In Figure 35, after the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet is committed to the
host using the PKTEND. The external device must be designed
to not assert SLWR and the PKTEND signal at the same time. It
must be designed to assert the PKTEND after SLWR is
deasserted and has met the minimum deasserted pulse width.
The FIFOADDR lines are to be held constant during the
PKTEND assertion.
PKTEND
SLWR
FLAGS
DATA
tWRpwh
tWRpwl
tXFLG
N
tSFD
N+1
tXFLG
tSFA tFAH
FIFOADR
SLCS
tWRpwh
tWRpwl tWRpwh
tWRpwl tWRpwh
tWRpwl
tFAH tSFA
tFDH tSFD
N+2
tFDH tSFD
N+3
tFDH
tSFD tFDH
tPEpwh
tPEpwl
t=0
t=2
t =1 t=3
T=0
T=2
T=1 T=3 T=6 T=9
T=5 T=8
T=4 T=7
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CY7C64713
Document #: 38-08039 Rev. *I Page 50 of 58
Ordering Information
Ordering Code Definitions
Table 29. Ordering Information
Ordering Code Package Type RAM Size # Prog I/Os 8051
Address
/Data Busses
CY7C64713-128AXC 128 TQF P - Pb-free 16K 40 16/8 bit
CY7C64713-100AXC 100 TQF P - Pb-free 16K 40 -
CY7C64713-56PVXC 56 SSOP - Pb-free 16K 24 -
CY7C64713-56LTXC 56 QFN - Pb-free 16K 24 -
CY3674 EZ-USB FX1 Development Kit
CY
Marketing Code: 7 = Cypress Prod ucts
7C64
Technology Code: C = C M OS
Company ID: CY = Cypress
XXX
Family Code: 64 = Full Speed U S B
Part Number
- (AX, PVX, LTX)
Package Type:
AX = TQFP Pb-free
PVX = SSO P Pb-free
LTX = QFN Pb-free
(C, I)
Thermal Rating:
C = Commercial
I = Ind u strial
(T) Tape and Reel
(128, 100, 56)
Number of pins on package
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CY7C64713
Document #: 38-08039 Rev. *I Page 51 of 58
Package Diagrams
The FX1 is available in four packages:
56 Pin SSOP
56 Pin QFN
100 Pin TQFP
128 Pin TQFP
Figure 36. 56-Pin Shrunk Small Outline Package O56
51-85062-*D
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CY7C64713
Document #: 38-08039 Rev. *I Page 52 of 58
Figure 37. 56-Pin QFN 8 x 8 mm LF56A
Figure 38. 56-Pin QFN 8 x 8 mm (Sawn Version)
51-85144-*I
51-85187 *E
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CY7C64713
Document #: 38-08039 Rev. *I Page 53 of 58
Figure 39. 100-Pin Thin Plastic Quad Fla tpack (14 x 20 x 1.4 mm) A101
51-85050-*D
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CY7C64713
Document #: 38-08039 Rev. *I Page 54 of 58
Figure 40. 128-Pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A128
Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. As a result, special attention is required to
the heat transfer area below the package to provide a good
thermal bond to the circuit board. A Copper (Cu) fill is to be
designed into the PCB as a thermal pad under the package. Heat
is transferred from the FX1 through the device’s metal paddle on
the bottom side of the package. Heat from here, is conducted to
the PCB at the thermal pad. It is then conducted from the thermal
pad to the PCB inner ground plane by a 5 x 5 array of via. A via
is a plated th rough hole in the PCB with a finished diameter of
13 mil. The QFN’s metal die paddle must be soldered to the
PCB’s thermal pad. Solder mask is placed on the board top side
over each via to resist sold er flow into the via. T he mask on the
top side also minimizes outgassing during the solder reflow
process.
For further information on this package design please refer to
‘Application Notes for Surface Mount Assembly of Amkor's
MicroLeadFrame (MLF) Packages’. This can be found on
Amkor's website http://www.amkor.com.
The application note provides detailed information on board
mounting guidelines, soldering flow, rework process, and so on.
Figure 41 on page 55 displays a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50% solder
coverage. The thickness of the solder paste template must be
5 mil. It is recommended that ‘No Clean’ typ e 3 solder paste is
used for mounting the part. Nitrogen purge is recommended
during reflow .
Figure 42 on page 55 is a plot of the solder mask pattern and
Figure 43 on page 55 displays an X-Ray image of the assembly
(darker areas indicate solder).
51-85101 *E
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CY7C64713
Document #: 38-08039 Rev. *I Page 55 of 58
Figure 41. Cross section o f the Area Underneath the QFN Package
Figure 42. Plot of the Solder Mask (Whi te Are a )
Figure 43. X-ray Image of the Assembly
0.017” dia
Solder Mask Cu Fill
Cu Fill
PCB Material
PCB Material 0.013” dia
Via hole for thermally connecting the
QFN to the circuit board ground plane. This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and
the Ground Plane.
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CY7C64713
Document #: 38-08039 Rev. *I Page 56 of 58
Acronyms Document Conventions
Units of Measure
Acronyms Used in this Document
Acronym Description
ASIC application specific integrated circuit
ATA advanced techno lo gy attachment
DID device identifier
DSL digital service line
DSP digital signal processor
ECC error correction code
EEPROM electrically erasable programma ble read only
memory
EPP en hanced parallel port
FIFO first in first out
GPIF general programmable interface
GPIO general purpose input output
I/O input output
LAN local area network
MPEG moving picture experts group
PCMCIA personal computer memory card international
association
PID product identifier
PLL phase locked loop
QFN quad flat no leads
RAM random access memory
SIE serial interface engine
SOF start of frame
SSOP super small outline p a cka g e
TQFP thin quad flat pack
USARTS universal serial asynchronous receiver/trans-
mitter
USB universal serial bus
UTOPIA universal test and operati ons physical-layer
interface
VFBGA very fi ne ball grid array
VID vendor identifier
Symbol Unit of Measure
KHz kilohertz
mA milliamperes
Mbps megabits per second
MBPs megabytes per second
MHz megahertz
uA microamperes
V volts
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CY7C64713
Document #: 38-08039 Rev. *I Page 57 of 58
Document History Page
Document Title: CY7C64713 EZ-USB FX1™ USB Microcontroller Fu ll Speed USB Peripheral Controller
Document Number: 38-08039
Revision ECN Orig. of
Change Submission
Date Description of Change
** 132091 KKU 02/10/04 New Datasheet.
*A 230709 KKU SEE ECN Changed Lead free Marketing part numbers in Table 29 according to spec
change in 28-00054.
*B 307474 BHA SEE ECN Changed default PID in Table 2 on page 5.
Updated register table.
Removed word compatible where associated with I2C.
Changed Set-up to Setup.
Added Power Dissipation.
Changed Vcc from ± 10% to ± 5%
Added values for VIH_X, VIL_X
Added values for ICC
Added values for ISUSP
Removed IUNCONFIGURED from Tab l e 10 on page 33.
Changed PKTEND to FLAGS output propagation delay (asynchronou s
interface) in Table 10-14 from a maximu m value of 70 ns to 115 ns.
Removed 56 SSOP and added 56 QFN package.
Provided additional timing restrictions and requirement regarding the use of
PKTEND pin to commit a short one byte/word packet subsequent to committing
a packet automatically (when in auto mode).
Added part number CY7C64714 ideal for battery powered applications.
Changed Supply V oltage in section 8 to read +3.15V to +3.45V.
Added Min Vcc Ramp Up time (0 to 3.3 V).
Removed Preliminary.
*C 392702 BHA SEE ECN Corrected signal name for pin 54 in Figure 10 on page 17.
Added information on the AUTOPTR1/AUTOPTR2 address timing with regards
to data memory read/write timing diagram.
Removed TBD in Table 16 on page 39.
Added section “PORTC Strobe Feature Timings” on page 37.
*D 1664787 CMCC/
JASM See ECN Added the 56 pin SSOP pinout and package information.
Delete CY7C64714.
*E 2088446 JASM See ECN Updated package diagrams.
*F 2710327 DPT 05/22/2009 Added 56-Pin QFN (8 × 8 mm) package diagram
Updated ordering information for CY7C64713 -56LTXC part
*G 2765406 ODC 09/17/2009 Added Pb-free for the CY7C64713-56LTXC part in the ordering information
table.
Updated 56-Pin Sawn QFN package diagram.
*H 2896318 ODC 03/18/2010 Removed obsolete part CY7C64713-56LFXC. Updated all package diagrams.
*I 3186891 ODC 03/03/2011 Template updates.
Updated package diagrams: 51-85144 , 51-85050, 51-85101
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Document #: 38-08039 Rev. *I Revised March 4, 2011 Page 58 of 58
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these component s in an I2C system, provided
that the system conforms to the I2C Stan dard Specification as d efined by Philips. EZ-USB FX1, EZ-USB FX2LP, EZ-USB FX2, and ReNumeration are tr ademarks, and EZ-USB is a reg istered trademark,
of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
CY7C64713
© Cypress Semico nducto r Co rpor ation , 20 04-2 011. The information cont ained he rein is subje ct to chang e with out no tice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products ar e not war ran t ed no r int e nded to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to an express written agreement wit h Cypr ess. Fu rth er mor e, Cypre ss does not auth or iz e it s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to world wide patent pro tectio n (United States and foreign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product t o be used only in conju nction with a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permis sion of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOS E. Cypress reserves the right to make changes without further notice to th e materials described he rein. Cypress d oes not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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