MC74HC139ADR2 - ON Semiconductor - Datasheet.Directory

July, 2012 − Rev. 11

1Publication Order Number:

MC74HC139A/D

MC74HC139A

Dual 1-of-4 Decoder/

Demultiplexer

High−Performance Silicon−Gate CMOS

The MC74HC139A is identical in pinout to the LS139. The device

inputs are compatible with standard CMOS outputs; with pull−up

resistors, they are compatible with LSTTL outputs.

This device consists of two independent 1−of−4 decoders, each of

which decodes a two−bit Address to one−of−four active−low outputs.

Active−low Selects are provided to facilitate the demultiplexing and

cascading functions. The demultiplexing function is accomplished by

using the Address inputs to select the desired device output, and

utilizing the Select as a data input.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1.0 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7 A

•Chip Complexity: 100 FETs or 25 Equivalent Gates

•NLV Prefix for Automotive and Other Applications Requiring

Unique Site and Control Change Requirements; AEC−Q100

Qualified and PPAP Capable

•These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

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See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

1

16 PDIP−16

N SUFFIX

CASE 648

1

16

1

16

1

16

MC74HC139AN

AWLYYWWG

1

16

HC139AG

AWLYWW

HC

139A

ALYWG

G

1

16

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

MC74HC139A

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2

12

11

10

9

4

5

6

7

A0a

A1a

SELECTa

A0b

A1b

1

SELECTb

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b

ACTIVE−LOW

OUTPUTS

ADDRESS

INPUTS

PIN 16 = VCC

PIN 8 = GND

ACTIVE−LOW

OUTPUTS

3

2

ADDRESS

INPUTS 13

14

15

Figure 1. Pin Assignment

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

SELECTa

A1a

A0a

GND

A1b

A0b

SELECTb

VCC

Y0a

Y1a

Y2a

Y3a

Y0b

Y1b

Y2b

Y3b

FUNCTION TABLE

Inputs Outputs

Select A1 A0 Y0 Y1 Y2 Y3

HXXHHHH

LLLLHHH

LLHHLHH

LHLHHLH

LHHHHHL

X = don’t care

Figure 2. Logic Diagram

ORDERING INFORMATION

Device Package Shipping†

MC74HC139ANG PDIP−16

(Pb−Free)

2000 Units / Box

MC74HC139ADG SOIC−16

(Pb−Free)

48 Units / Rail

MC74HC139ADR2G SOIC−16

(Pb−Free)

2500 / Tape & Reel

MC74HC139ADTR2G TSSOP−16

(Pb−Free)

2500 / Tape & Reel

NLV74HC139ADR2G* SOIC−16

(Pb−Free)

2500 / Tape & Reel

NLV74HC139ADTR2G* TSSOP−16

(Pb−Free)

2500 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP

Capable

MC74HC139A

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3

MAXIMUM RATINGS

Symbol Parameter Value Unit

VCC DC Supply Voltage (Referenced to GND) 0.5 to 7.0 V

VIN DC Input Voltage (Referenced to GND) 1.5 to VCC 1.5 V

VOUT DC Output Voltage (Referenced to GND) (Note 1) 0.5 to VCC 0.5 V

IIN DC Input Current, per Pin 20 mA

IOUT DC Output Current, per Pin 25 mA

ICC DC Supply Current, VCC Pin 50 mA

IGND DC Ground Current per Ground Pin 50 mA

TSTG Storage Temperature Range 65 to 150 _C

TLLead Temperature, 1 mm from Case for 10 Seconds 260 _C

TJJunction Temperature Under Bias 150 _C

qJA Thermal Resistance PDIP

SOIC

TSSOP

78

112

148

_C/W

PDPower Dissipation in Still Air at 85_C PDIP

SOIC

TSSOP

750

500

450

mW

MSL Moisture Sensitivity Level 1

FRFlammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in

VESD ESD Withstand Voltage Human Body Model (Note 2)

Machine Model (Note 3)

Charged Device Model (Note 4)

2000

200

1000

V

ILATCHUP Latchup Performance Above VCC and Below GND at 85_C (Note 5) 300 mA

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. IO absolute maximum rating must be observed.

2. Tested to EIA/JESD22−A114−A.

3. Tested to EIA/JESD22−A115−A.

4. Tested to JESD22−C101−A.

5. Tested to EIA/JESD78.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

2.0

ÎÎÎÎ

6.0

ÎÎÎ

V

ÎÎÎÎ

VIN, VOUT

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎÎÎ

0

ÎÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎÎÎ

55

ÎÎÎÎ

125

ÎÎÎ

_C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 3) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎÎÎ

0

ÎÎÎÎ

1000

500

400

ÎÎÎ

ns

6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.

MC74HC139A

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4

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

VCC Guaranteed Limit

Symbol Parameter Test Conditions V*55_C to 25_C85_C125_CUnit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎÎ

VOUT = 0.1 V or VCC 0.1 V

|IOUT|  20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

1.5

3.15

4.2

ÎÎÎ

1.5

3.15

4.2

ÎÎÎÎ

1.5

3.15

4.2

ÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Input

Voltage

ÎÎÎÎÎÎÎÎÎÎ

VOUT = 0.1 V or VCC 0.1 V

|IOUT|  20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

0.5

1.35

1.8

ÎÎÎ

0.5

1.35

1.8

ÎÎÎÎ

0.5

1.35

1.8

ÎÎ

V

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎÎ

VIN = VIH or VIL

|IOUT|  20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎ

V

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

VIN = VIH or VIL |IOUT|  4.0 mA

|IOUT|  5.2 mA

ÎÎÎ

4.5

6.0

ÎÎÎÎÎ

3.98

5.48

ÎÎÎ

3.84

5.34

ÎÎÎÎ

3.70

5.20

ÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Output

Voltage

ÎÎÎÎÎÎÎÎÎÎ

VIN = VIH or VIL

|IOUT|  20 mA

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

0.1

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎ

V

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎ

VIN = VIH or VIL |IOUT|  4.0 mA

|IOUT|  5.2 mA

ÎÎÎ

4.5

6.0

ÎÎÎÎÎ

0.26

ÎÎÎ

0.33

ÎÎÎÎ

0.40

ÎÎ

ÎÎÎÎ

IIN

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage

Current

ÎÎÎÎÎÎÎÎÎÎ

VIN = VCC or GND

ÎÎÎ

6.0

ÎÎÎÎÎ

0.1

ÎÎÎ

1.0

ÎÎÎÎ

1.0

ÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎÎ

VIN = VCC or GND

IOUT = 0 mA

ÎÎÎ

6.0

ÎÎÎÎÎ

4

ÎÎÎ

40

ÎÎÎÎ

160

ÎÎ

mA

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

VCC Guaranteed Limit

Symbol Parameter V *55_C to 25_C85_C125_CUnit

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Select to Output Y

(Figures 1 and 3)

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

115

23

20

ÎÎÎ

145

29

25

ÎÎÎÎ

175

35

30

ÎÎ

ns

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Input A to Output Y

(Figures 2 and 3)

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

115

23

20

ÎÎÎ

145

29

25

ÎÎÎÎ

175

35

30

ÎÎ

ns

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

ÎÎÎ

2.0

4.5

6.0

ÎÎÎÎÎ

75

15

13

ÎÎÎ

95

19

16

ÎÎÎÎ

110

22

19

ÎÎ

ns

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎ

−

ÎÎÎÎÎ

10

ÎÎÎ

10

ÎÎÎÎ

10

ÎÎ

pF

7. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed

CMOS Data Book (DL129/D).

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Decoder) (Note 8) 55 pF

8. Used to determine the no−load dynamic power consumption: PD = CPD VCC2f  ICC VCC.

MC74HC139A

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5

VALID

tTHL tTLH

Figure 3. Switching Waveform

VCC

GND

tr

tPHL tPLH

OUTPUT Y

SELECT

90%

50%

10%

90%

50%

10%

Figure 4. Switching Waveform

50%

tPHL

tPLH

VCC

GND

OUTPUT Y 50%

INPUT A

* Includes all probe and jig capacitance

Figure 5. Test Circuit

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

tfVALID

MC74HC139A

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6

PIN DESCRIPTIONS

ADDRESS INPUTS

A0a, A1a, A0b, A1b (Pins 2, 3, 14, 13)

Address inputs. These inputs, when the respective 1−of−4

decoder is enabled, determine which of its four active−low

outputs is selected.

CONTROL INPUTS

Selecta, Selectb (Pins 1, 15)

Active−low select inputs. For a low level on this input, the

outputs for that particular decoder follow the Address

inputs. A high level on this input forces all outputs to a high

level.

OUTPUTS

Y0a − Y3a, Y0b − Y3b (Pins 4 − 7, 12, 11, 10, 9)

Active−low outputs. These outputs assume a low level

when addressed and the appropriate Select input is active.

These outputs remain high when not addressed or the

appropriate Select input is inactive.

SELECT

A0

A1

Y0

Y1

Y2

Y3

Figure 6. Expanded Logic Diagram

(1/2 of Device)

MC74HC139A

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7

PACKAGE DIMENSIONS

PDIP−16

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

MC74HC139A

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8

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

16

89

8X

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC139A

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9

PACKAGE DIMENSIONS

TSSOP−16

CASE 948F−01

ISSUE B

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

18

16 9

DETAIL E

J

J1

B

C

D

A

K

K1

H

G

ÉÉÉ

DETAIL E

F

M

L

2X L/2

−U−

S

U0.15 (0.006) T

S

U0.15 (0.006) T

S

U

M

0.10 (0.004) V S

T

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

N

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC74HC139A

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10

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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

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limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications

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