Philips Semiconductors Concise Catalogue 1996 INTEGRATED CIRCUITS LOGIC GENERAL PURPOSE ABT/ABT16 and MULTIBYTE series ABT and MULTIBYTE FAMILY SPECIFICATIONS General These family specifications cover the common electrical ratings and characteristics of the entire 74ABT and MULTIBYTE families, unless otherwise specified in the individual device data sheet. Introduction The ABT, ABT16 and MULTIBYTE Advanced BiCMOS (QUBiC) families combine the low power dissipation and low noise of BiCMOS with the high output drive of our bipolar logic devices. The basic families of devices designated as 74ABTxxx/74ABT16xxx and MBxxxx will operate at BICMOS input logic levels for high noise immunity, negligible quiescent supply and input current. They operate from a power supply of 4.5 to 5.5 V. Handling BiCMOS devices Inputs and outputs are protected against electrostatic effects in a wide variety of device-handling situations. However, . to be totally safe, it is desirable to take appropriate handling precautions into account. ABT features MULTIBYTE features Double-byte functionality ==> TTL compatible !/Os SS 50 PA Iegz +64/-32 mA output drive High performance, JEDEC registered 52-pin package Fastest in industry apart from ECL devices Ideal for bus driver applications Very short propagation delays 64 mA sink current; 32 mA source current Supply voltage range: 5 V +10% Standard TTL pin-out Very low noise immunity Latch-up protection exceeds 500 mA Very low simultaneous switching propagation delay Wide operating temperature range: ~40 to +85 C degradation Devices available in DIL and SO and SSOP packages Very low skew Live insertion/extraction permitted ABT16 features Muitiple-byte functionality Multiple Vec and GND pins minimize switching noise 64 mA sink current; 32 mA source current Devices available in SSOP and TSSOP packages Live insertion/extraction permitted BVS hold circuit on data inputs 3-51Philips Semiconductors Concise Catalogue 1996 LOGIC INTEGRATED CIRCUITS ABT/ABT16 and MULTIBYTE series GENERAL PURPOSE Type number designation Basic family: T4ABTXXxXx 74 ABT xxxx x UL____ = package code: N = plastic DIL; D = plastic mini-pack (SO) DB = plastic SSOP type II PW = plastic TSSOP type | 3-4 digits device number = advanced BICMOS TTL process Po 74 = standard operating temperature range > Oo A L " -40 to +85 C T4ABT16xxxx 74 ABT16 xxxx x L____ = package code: DL = plastic SSOP DGG = plastic TSSOP = 3-4 digits device number L _ ABT = advanced BiCMOS TTL process 74 = standard operating temperature range ~40 to +85 C MBxxxxx MB xxxx x To = package code: BB = plastic quad flat pack (QFP) package = 4 digits device number MB_~ = Designates MULTIBYTE productsPhilips Semiconductors Concise Catalogue 1996 INTEGRATED CIRCUITS LOGIC GENERAL PURPOSE ABT/ABT16 and MULTIBYTE series Family ratings Limiting values in accordance with the Absolute Maximum System (IEC 134) Voltages are referenced to GND (ground = 0 V) parameter conditions symbol min. max. unit DC supply voltage Voc -0.5 +7 v DC input diode current Vj,<O0V lk - 18 mA DC input voltage V, -1.2 +7 Vv DC output diode current Vo <O0V ~lox - 50 mA DC output voltage output OFF or HIGH Vo -0.5 +5.5 Vv DC output current output LOW Io - 128 mA storage temperature range Tg ~65 +150 C Recommended operating conditions Voltages are referenced to GND (ground = 0 V) parameter symbol min. max. unit DC supply voltage Voc 45 5.5 Vv Input voltage Vv, 0 Voc Vv HIGH level input voltage Vin 2.0 - V LOW level input voltage Vic - 0.8 Vv HIGH level output current lor - 32 mA LOW level output current lov - 64 mA Input transition rise or fall rate At/AV 0 5 nsV Operating ambient temperature range Tamb -40 +85 CPhilips Semiconductors Concise Catalogue 1996 LOGIC ABT/ABT16 and MULTIBYTE series INTEGRATED CIRCUITS GENERAL PURPOSE ABT DC family characteristics Voltages are referenced to GND (ground = 0 V) am PC) Voc +25 -40 to +85 conditions parameter (V) symbol min. typ. max. min. max. unit Vv, other Input clamp 45 Vw - -0.9 -1.2 - 1.2 v Iq = -18 mA voltage HIGH level 45 Vou 2.5 2.9 - 2.5 - Vo | Vapor [lg =-3 mA output voltage 5.0 3.0 3.4 - 3.0 - VoVa Ig =-3 mA 45 2.0 2.4 - 2.0 - Vv lo = -32 MA LOW level output 45 Vor - 0.42 0.55 - 0.55 Vio} Vy or | lop = 64 mA voltage Vie Power-up LOW 5.5 Vast - 0.13 0.55 - 0.55 | V |55V JIg=ima voltage? or OV Input leakage .5 1 - 40.01 40.1 - 10.1 uA | GND or current 5.5V Power-off leakage | 0.0 lore - 45.0 +100 - +100 pA Vo or V, $4.5 V current Power up/down 2.1 lpupo - +5.0 +50 - +50 BHA | Voc OF | Voge = don't cace 3-state output GND current* 3-state output 5.5 lozH - 5.0 50 - 50 WA | Vy or [V9 = 2.7 V HIGH current Vit 3-state output 5.5 loz. - -.0 ~50 - -50 HA | Vy or | Vg =0.5 V LOW current iL Output HIGH 5.5 leex - 5.0 50 - 50 HA | Voge or | Vp =2.5V leakage current GND Output HIGH 5.5 lo -50 -65 ~180 -50 -180 | mA Vo =2.5V current! Quiescent 5.5 lec - 120 250 - 250 HA | Vog or | outputs HIGH supply current 5.5 loo - 24 30 - 30 mA ;GND | outputs LOW 5.5 coz - 120 250 - 250 pA outputs 3-state Additional supply 5.5 Alec - 0.5 1.5 - 1.5 MA | Vcc OF | outputs 3-state; one current per input GND input at 3.4 V pin NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4 V. 3. For valid test results, data must not be loaded into the flip-flop or latch after applying the power. 4. This parameter is valid for any Voc between 0 V and 2.1 V, with a transition time of up to 10 ms. From V = 2.1 V to Vec = 5 V 10%, a transition time of up to 100 us is permitted. This note applies only to parts with the live insertion/extraction feature. 3-54Philips Semiconductors Concise Catalogue 1996 INTEGRATED CIRCUITS LOGIC GENERAL PURPOSE ABT/ABT16 and MULTIBYTE series ABT16 DC family characteristics Voltages are referenced to GND (ground = 0 V) Tamp (@C) Veco +25 40 to +85 conditions parameter (V) symbol min. typ. max. min. max. unit V, other Input clamp 4.5 Vix - -0.9 -1.2 - ~1.2 v Iq = -18 MA voltage HIGH level 4.5 Vou 2.5 2.9 - 2.5 - Vo iVy or |Ilg=-3 mA output voltage 5.0 3.0 3.4 - 3.0 - VV lg =-3 MA 4.5 2.0 2.4 - 2.0 - v Ig = -32 mA LOW level output 4.5 Vo. - 0.42 0.55 - 0.55 V | Vij or | Io, = 64 mA voltage Vi Power-up LOW 5.5 Vast - 0.13 0.55 - 0.55 V |55V lp =1mA voltage? or OV Input leakage 5.5 I - +0.01 10.1 - 40.1 HA | GND or current 55V ____ Power-off leakage | 0.0 | loge - +5.0 | +100 - +100 | pA Vg or V, $4.5 V = current Power up/down 2.1 lewep - +5.0 +50 - +60 WA | Voc OF | Voge = don't cace 3-state output GND current@ 3-state output 5.5 loz - 5.0 50 - 50 HA TV or |V5=2.7V HIGH current Vie 3-state output 5.5 loz. - -5.0 -50 ~ -50 HA TVi,0or |V5o=05V LOW current Vit Output HIGH 5.5 loex - 5.0 50 - 50 HA [Vog or [Vp = 2.5 V leakage current GND Output HIGH 5.5 lo -50 - -200 -50 -200 | mA Vo =2.5V current Quiescent 5.5 locy - ~ 2 - 2 MA | Vee or | outputs HIGH supply current 5.5 loot - - 41 - 44 mA |GND | outputs LOW 5.5 loez - - 2 - 2 mA outputs 3-state Additional supply 5.5 Aloc - - 1.5 - 1.5 MA | Voc OF | outputs 3-state; one current per input GND input at 3.4 V in? pin NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4 V. 3. For vatid test results, data must not be loaded into the flip-flop or latch after applying the power. 4. This parameter is valid for any Ve, between 0 V and 2.1 V, with a transition time of up to 10 ms. From Vc = 2.1 V to Voc = 5 V 10%, a transition time of up to 100 ys is permitted. This note applies only to parts with the live insertion/extraction feature. 3-55Philips Semiconductors Concise Catalogue 1996 LOGIC ABT/ABT16 and MULTIBYTE series INTEGRATED CIRCUITS GENERAL PURPOSE MULTIBYTE DC family characteristics Voltages are referenced to GND (ground = 0 V) Tamp (C) Voc +25 ~40 to +85 conditions parameter (V) symbol min. typ. max. min. max. unit Vv, other Input clamp 4.5 Vix - -0.9 -1.2 - -1.2 V lye = -18 MA voltage HIGH level 4.5 Vou 2.5 2.9 - 2.5 - Vo[Viyor jig =-3 mA output voltage 5.0 3.0 3.4 - 3.0 - VIM lp = -3 mA 45 2.0 2.4 - 2.0 - Vv |p = -32 mA LOW level output 45 Vor - 0.42 0.55 - 0.55 Vio) Vy, Or | lop = 64 mA voltage IL Power-up LOW 5.5 Vast - 0.13 0.55 - 0.55 V |55V lp =4mA voltage ord0V Input leakage 5.5 l, - 40.01 10.1 - 40.1 BHA | GND or current 55V Power-off leakage | 0.0 loge - +5.0 +100 - +100 pA Vo or V, $4.5 V current Power up/down 2.1 lpurpp - +5.0 +50 - +50 HA | Vee OF | Voge = don't cace 3-state output GND current* 3-state output 5.5 lozy - 5.0 50 - 50 pA | Vapor | VQ =2.7V HIGH current Viv 3-state output 5.5 loz. - -5.0 -50 - ~50 HA | Vy, or [Vo =0.5V LOW current iL Output HIGH 5.5 logx - 5.0 50 - 50 BA | Voc or | Vg = 2.5 V leakage current GND Output HIGH 5.5 lo -50 - ~-180 ~50 -180 mA Vp =2.5V current! Quiescent 5.5 lecu - - 250 - 250 HA | Vee or | outputs HIGH supply current 5.5 och - - 60 - 60 mA | GND outputs LOW 5.5 ord - - 250 - 250 pA outputs 3-state Additional supply 5.5 Alec - 0.5 1.5 - 1.5 MA | Veo or | outputs 3-state; one current per input GND input at 3.4 V pin? NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. This is the increase in supply current for each input at 3.4 V. 2. 3. For valid test results, data must not be loaded into the flip-flop or latch after applying the power. 4, This parameter is valid for any Vc, between 0 V and 2.1 V, with a transition time of up to 10 ms. From Ve, = 2.1 V to Veco = V 10%, a transition time of up to 100 us is permitted. This note applies only to parts with the live insertion/extraction feature. 3-56Philips Semiconductors Concise Catalogue 1996 INTEGRATED CIRCUITS LOGIC GENERAL PURPOSE ABT/ABT16 and MULTIBYTE series ABT/ABT16 & MULTIBYTE SERIES ABT ABT16 MB GATES 00 Quad 2-input NAND gate 02 Quad 2-input NOR gate ____- 04 Hex inverter e_ 08 Quad 2-input AND gate o__- 10 Triple 3-input NAND gate e________ 20 Dual 4-input NAND gate o___- 32 Quad 2-input OR gate o___ BUFFERS/LINE DRIVERS 125 Quad buffer; 3-state .__. 126 Quad buffer; 3-state Sa <A 240 Octal inverting buffer; 3-state e______ 240 16-bit inverting buffer; 3-state 0 240-1 Octal inverting buffer with 30 Q termination resistors; 3-state SS 240-1 16-bit inverting buffer; 3-state _e_ 241 Octal buffer/line driver; 3-state Sak _ a 241 16-bit buffer/line driver; 3-state _o__- 244 Octai buffer/line driver; 3-state 3 244A 16-bit buffer/line driver; 3-state _o___- 244-1 Octal buffer/ine driver with 30 Q termination resistors; 3-state 3a__- 244-1 16-bit buffer/line driver with 30 Q termination resistors; 3-state Sh a 540 Octal buffer; inverting; 3-state o___ 541 Octal buffer/line driver; 3-state oe 827 10-bit buffer/line driver; non-inverting; 3-state o____ 827A 20-bit buffer/line driver; non-inverting; 3-state oe 2240 Octal inverting buffer with 30 Q termination resistors; 3-state a 2240 16-bit inverting buffer; 3-state o__o 2241 16-bit buffer/line driver; 3-state Oo 2244 Octal buffer/line driver with 30 Q termination resistors; 3-state So 2244 16-bit buffer/line driver with 30 Q termination resistors; 3-state a 2244 16-bit buffer/line driver; 3-state _o 2541 16-bit buffer/line driver; 3-state _o 2827 20-bit buffer/line driver; non-inverting; 3-state OO D-type FLIP-FLOPS/LATCHES 74 Dual D-type edge triggered flip-flop oe 273 16-bit D flip-flop -__ 273A Octal D flip-flop I 273A 16-bit D flip-flop o 373A Octal D-type transparent latch; 3-state 3_ 373B 16-bit D-type transparent latch; 3-state o_ 374A Octal D-type flip-flop; positive-edge trigger; 3-state a 374B 16-bit D-type flip-flop; positive-edge trigger; 3-state x77 377 Octal D-type flip-flop with enable e_____- 534 Octal D-type flip-flop; inverting; 3-state ----_____ 573A Octal D-type transparent latch; 3-state ae 574A Octal D-type flip-flop; 3-state 3 821 10-bit D-type flip-flop; positive-edge trigger; 3-state Sh: 821A 20-bit D-type flip-flop; positive-edge trigger; 3-state o 823 9-bit D-type fiip-flop with reset and enable; 3-state o_ 823A 18-bit D-type flip-flop with reset and enable; 3-state _o__ 825A 16-bit bus interface register; non-inverting; 3-state o-__- 841 10-bit bus interface latch; 3-state o_ 841A 20-bit bus interface latch; 3-state e 843 9-bit bus interface latch with set and reset; 3-state e__-- 845 8-bit bus interface latch with set and reset; 3-state SS 2373 16-bit D-type transparent latch; 3-state _3_ 2374 16-bit D-type flip-flop; positive-edge trigger; 3-state -7 2377 16-bit D-type flip-flop with enable __6 3-57Philips Semiconductors Concise Catalogue 1996 LOGIC INTEGRATED CIRCUITS ABT/ABT16 and MULTIBYTE series GENERAL PURPOSE ABT/ABT16 & MULTIBYTE SERIES ABT ABT16 MB 2821 20-bit D-type flip-flop; positive-edge trigger; 3-state ___o. 2823 18-bit D-type flip-flop with reset and enable; 3-state 1 2841 20-bit bus interface latch; 3-state oo 5074 Synchronizing dual D-type flip-flop/clock driver Sa TRANSCEIVERS 245 Octal transceiver with direction pin; 3-state I 245B 16-bit transceiver with direction pin; 3-state o___ 245-1 Octal transceiver with direction pin; 3-state 3___ 245A-1 16-bit transceiver with 30 termination resistors and direction pin; 3-state $$o_ 500C 18-bit universal bus tranceiver; 3-state o_ SO1A 18-bit universal bus tranceiver; 3-state __ HO 543 16-bit latched transceiver with dual enable; 3-state 7 543A Octal latched transceiver with dual enable; 3-state SS 2543 16-bit latched transceiver with dual enable and 30 Q termination resistors; 3-state 7 544 Octal latched transceiver with dual enable; inverting; 3-state 3 620 Octal transceiver with dual enable; inverting; 3-state SS 623 Octal transceiver with dual enable; non-inverting; 3-state Sa 640 Octal transceiver with direction pin; inverting; 3-state 3 646A Octal bus transceiver/register; 3-state a 646 16-bit bus transceiver/register; 3-state _o__. 648 Octal bus transceiver/register; inverting; 3-state o_ 651 Octal bus transceiver/register; inverting; 3-state ea 652A Octal transceiver/register; non-inverting; 3-state I _____- 652 16-bit transceiver/register; non-inverting; 3-state _o__ 657 Octal transceiver with parity generator/checker; 3-state 9- 833 Octal transceiver with parity generator/checker; 3-state Sa - T 853 8-bit transceiver with 9-bit parity checker/generator and flag latch; 3-state 3__ 861 10-bit bus transceiver; 3-state oa 863 9-bit bus transceiver; 3-state Ss 899 9-bit dual latch transceiver with 8-bit parity generator/checker; 3-state oe 899 16-bit dual latch transceiver with 8-bit parity generator/checker; 3-state oa 952A Dual! octal registered transceiver _9___ 1543 Dual octal latched transceiver with dual enable and clear; 3-state o- 2052 16-bit registered transceiver; 3-state -o0- 2245 Octal transceiver with direction pin; 3-state o__ 2245 16-bit transceiver with direction pin; 3-state _o_o 2543 16-bit latched transceiver with dual enable; 3-state _o 2623 16-bit transceiver with dual enable; non-inverting; 3-state o_ 2646 16-bit bus transceiver/register; 3-state o 2652 16-bit transceiver/register; non-inverting; 3-state o_ 2861 Dual 10-bit bus transceiver; 3-state e 2952 Octal registered tranceiver; 3-state oa 2953 Octal registered tranceiver; inverting; 3-state 3a 3205 10-bit BTL transceiver Se 3-58