LMH6739 www.ti.com SNOSAD2G - MAY 2004 - REVISED MARCH 2013 LMH6739 Very Wideband, Low Distortion Triple Video Buffer Check for Samples: LMH6739 FEATURES 1 * 2 * * * * * * * DESCRIPTION 750 MHz -3 dB small signal bandwidth (AV = +1) -85 dBc 3rd harmonic distortion (20 MHz) 2.3 nV/Hz input noise voltage 3300 V/s slew rate 32 mA supply current (10.6 mA per op amp) 90 mA linear output current 0.02/0.01 Diff. Gain/ Diff. Phase (RL = 150) 2mA shutdown current The LMH6739 is a very wideband, DC coupled monolithic selectable gain buffer designed specifically for ultra high resolution video systems as well as wide dynamic range systems requiring exceptional signal fidelity. Benefiting from current feedback architecture, the LMH6739 offers gains of -1, 1 and 2. At a gain of +2 the LMH6739 supports ultra high resolution video systems with a 400 MHz 2 VPP3 dB Bandwidth. With 12-bit distortion level through 30 MHz (RL = 100), 2.3nV/Hz input referred noise, the LMH6739 is the ideal driver or buffer for high speed flash A/D and D/A converters. Wide dynamic range systems such as radar and communication receivers requiring a wideband amplifier offering exceptional signal purity will find the LMH6739 low input referred noise and low harmonic distortion make it an attractive solution. The LMH6739 is offered in a space saving SSOP package. APPLICATIONS * * * * * * * * * RGB video driver High resolution projectors Flash A/D driver D/A transimpedance buffer Wide dynamic range IF amp Radar/communication receivers DDS post-amps Wideband inverting summer Line driver CONNECTION DIAGRAM 16-Pin SSOP Top View -IN A 1 +IN A 2 DIS B 3 -IN B 4 +IN B 5 DIS C 6 -IN C 7 +IN C 8 16 + DIS A 15 +VS 14 OUT A + 13 -VS 12 OUT B 11 +VS + 10 OUT C 9 -VS See Package Number DBQ0016A 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2013, Texas Instruments Incorporated LMH6739 SNOSAD2G - MAY 2004 - REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) Human Body Model 2000V Machine Model 200V + - Supply Voltage (V - V ) 13.2V (3) IOUT Common Mode Input Voltage VCC Maximum Junction Temperature +150C -65C to +150C Storage Temperature Range Soldering Information Infrared or Convection (20 sec.) 235C Wave Soldering (10 sec.) 260C -65C to +150C Storage Temperature Range (1) (2) (3) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical Characteristics tables. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the Application Information for more details. Operating Ratings (1) (2) Temperature Range (3) -40C to +85C + Supply Voltage (V - V-) 8V to 12V Thermal Resistance Package 16-Pin SSOP (1) (2) (3) 2 (JC) (JA) 36C/W 120C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical Characteristics tables. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum power dissipation is a function of TJ(MAX), JA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/ JA. All numbers apply for packages soldered directly onto a PC Board. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 LMH6739 www.ti.com SNOSAD2G - MAY 2004 - REVISED MARCH 2013 Electrical Characteristics (1) TA = 25C, AV = +2, VCC = 5V, RL = 100; unless otherwise specified. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units Frequency Domain Performance UGBW -3 dB Bandwidth Unity Gain, VOUT = 200 mVPP 750 SSBW -3 dB Bandwidth VOUT = 200 mVPP 480 VOUT = 2 VPP 400 0.1 dB Bandwidth VOUT = 2 VPP 150 MHz Rolloff at 300 MHz, VOUT = 2 VPP 1.0 dB Rise and Fall Time (10% to 90%) 2V Step 0.9 5V Step 1.7 SR Slew Rate 5V Step 3300 V/s ts Settling Time to 0.1% 2V Step 10 ns te Enable Time From Disable = rising edge. 7.3 ns td Disable Time From Disable = falling edge. 4.5 ns 2 VPP, 5 MHz -80 2 VPP, 20 MHz -71 2 VPP, 50 MHz -55 2 VPP, 5 MHz -90 2 VPP, 20 MHz -85 2 VPP, 50 MHz -65 LSBW GFR2 MHz MHz Time Domain Response TRS TRL ns Distortion HD2L HD2 2nd Harmonic Distortion HD2H HD3L HD3 3rd Harmonic Distortion HD3H dBc dBc Equivalent Input Noise VN Non-Inverting Voltage >1 MHz 2.3 nV/Hz ICN Inverting Current >1 MHz 12 pA/Hz NCN Non-Inverting Current >1 MHz 3 pA/Hz Video Performance DG Differential Gain 4.43 MHz, RL = 150 .02 % DP Differential Phase 4.43 MHz, RL = 150 .01 degree Static, DC Performance (4) VOS Input Offset Voltage IBN Input Bias Current (4) Non-Inverting IBI Input Bias Current (4) Inverting PSRR Power Supply Rejection Ratio CMRR Common Mode Rejection Ratio ICC Supply Current (4) (4) (4) (2) (3) (4) 2.5 4.5 mV -8 0 +5 V -2 30 40 A 50 48.5 53 dB 46 44 50 dB All three amps Enabled, No Load 32 35 40 mA Supply Current Disabled V+ RL = 1.9 2.2 mA - RL = 1.1 1.3 mA Supply Current Disabled V (1) -16 -21 0.5 Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. Parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ> TA. See Applications Information for information on temperature de-rating of this device. Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Limits are 100% production tested at 25C. Limits over the operating temperature range are through correlations using the Statistical Quality Control (SQC) method. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested on shipped production material. Parameter 100% production tested at 25 C. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 3 LMH6739 SNOSAD2G - MAY 2004 - REVISED MARCH 2013 www.ti.com Electrical Characteristics (1) (continued) TA = 25C, AV = +2, VCC = 5V, RL = 100; unless otherwise specified. Symbol Parameter Conditions Internal Feedback & Gain Set Resistor Value Min (2) Typ (3) Max (2) Units 375 450 525 0.2 1.1 % RL = Gain Error Miscellaneous Performance RIN+ Non-Inverting Input Resistance CIN+ Non-Inverting Input Capacitance RIN- Inverting Input Impedance Output impedance of input buffer. RO Output Impedance DC VO Output Voltage Range CMIR Linear Output Current IO (4) pF 30 0.05 RL = 100 3.5 RL = 3.65 3.5 3.8 1.9 1.7 2.0 V 90 mA CMRR > 40 dB (5) (4) (6) k .8 3.25 3.1 (4) Common Mode Input Range 1000 VIN = 0V, VOUT < 30 mV 80 60 V ISC Short Circuit Current VIN = 2V Output Shorted to Ground 160 mA IIH Disable Pin Bias Current High Disable Pin = V+ 10 A IIL Disable Pin Bias Current Low Disable Pin = 0V -350 VDMAX Voltage for Disable Disable Pin VDMAX VDMIM Voltage for Enable Disable Pin VDMIN (5) (6) 4 A 0.8 2.0 V V The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the Application Information for more details. Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application Information for more details. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 LMH6739 www.ti.com SNOSAD2G - MAY 2004 - REVISED MARCH 2013 Typical Performance Characteristics AV = +2, VCC = 5V, RL = 100; unless otherwise specified). Large Signal Frequency Response Small Signal Frequency Response 4 4 VOUT = 2 VPP AV = +1 2 AV = +1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 2 0 -2 -4 AV = -1 -6 0 -2 -4 AV = -1 -6 AV = +2 -8 -8 AV = +2 -10 -10 1 10 100 Figure 1. Figure 2. Frequency Response vs. VOUT Frequency Response vs. Supply Voltage 1 0 -2 VOUT = 2 VPP -5 VOUT = 1 VPP -6 -7 -8 A = 2 V/V V -9 10 -1 NORMALIZED GAIN (dB) VOUT = 4 VPP -3 1000 VS = 7V -2 -3 VS = 9V -4 -5 VS = 12.5V -6 -7 VOUT = 0.5 VPP -8 VOUT = 2 VPP -9 100 FREQUENCY (MHz) 1000 10 100 1000 FREQUENCY (MHz) Figure 3. Figure 4. Gain Flatness Gain Flatness, Dual Input Buffer 0.5 0.5 VOUT = 0.5 VPP 0.4 VOUT 250 mVPP GAIN = +1 0.4 0.3 0.3 AV = +1 0.2 0.2 NON-INVERTING 0.1 GAIN (dB) NORMALIZED GAIN (dB) 100 FREQUENCY (MHz) 1 -4 10 FREQUENCY (MHz) 0 -1 GAIN (dB) 1 1000 0 -0.1 0 -0.1 BOTH AV = -1 -0.2 0.1 -0.2 -0.3 -0.3 AV = +2 -0.4 -0.4 -0.5 -0.5 1 10 100 1000 FREQUENCY (MHz) 1 10 100 1000 FREQUENCY (MHz) Figure 5. Figure 6. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 5 LMH6739 SNOSAD2G - MAY 2004 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) AV = +2, VCC = 5V, RL = 100; unless otherwise specified). Frequency Response vs. Capacitive Load Pulse Response 1.5 2 1 0 0.5 -2 CL = 4.7 pF, RS = 70: GAIN (dB) VOUT (V) CL = 15 pF, RS = 44: 0 CL = 47 pF, RS = 24: -4 CL = 100 pF, RS = 17: -0.5 -6 -1 -8 -1.5 -10 VOUT = 1 VPP, CL || 1 k: 0 4 8 12 16 20 1 10 100 1000 FREQUENCY (MHz) TIME (ns) Figure 7. Figure 8. Series Output Resistance vs. Capacitive Load Open Loop Gain and Phase 80 120 LOAD = 1 k: || CL 110 MAGNITUDE 60 50 40 30 20 100 90 80 0 70 -45 -90 60 PHASE 10 -135 50 0 0 20 40 60 80 100 120 40 0.01 -180 1000 100 FREQUENCY (MHz) Figure 9. Figure 10. Distortion vs. Frequency 10 MHz HD vs. Output Level -40 -40 VOUT = 2 VPP -45 f = 10 MHz -45 -50 -50 -55 -55 -60 DISTORTION (dBc) DISTORTION (dBc) 10 1 0.1 CAPACITIVE LOAD (pF) -60 HD2 -65 -70 -75 -80 HD3 -65 -70 HD2 -75 -80 -85 -85 HD3 -90 -90 -95 -100 -100 -95 1 10 100 FREQUENCY (MHz) 0 1 2 3 4 5 6 7 8 OUTPUT VOLTAGE (VPP) Figure 11. 6 PHASE () MAGNITUDE, |Z| (dB:) RECOMMENDED RS (:) 70 Figure 12. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 LMH6739 www.ti.com SNOSAD2G - MAY 2004 - REVISED MARCH 2013 Typical Performance Characteristics (continued) AV = +2, VCC = 5V, RL = 100; unless otherwise specified). Distortion vs. Supply Voltage CMRR vs. Frequency 50 -65 VOUT = 2VPP f = 10 MHz HD2 -70 45 DISTORTION (dBc) 40 -75 CMRR (dB) 35 -80 HD3 -85 30 25 20 15 -90 10 -95 5 -100 0 6.8 7.6 8.4 9.2 0.01 10.8 11.6 12.4 10 10 1 0.1 100 1000 FREQUENCY (MHz) TOTAL SUPPLY VOLTAGE (V) Figure 13. Figure 14. PSRR vs. Frequency Closed Loop Output Impedance |Z| 100 60 PSRR + AV = 2 V/V VIN = 0V 50 10 PSRR |Z| (:) PSRR (dB) 40 30 1 20 0.1 10 0.01 0.001 0.01 0 0.1 1 10 100 1000 0.1 1 100 10 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 15. Figure 16. Disable Timing DC Errors vs. Temperature 0.6 1 6 VOUT DISABLE (V) OUTPUT (V) 0.2 0.0 -0.2 -0.4 -0.6 3 1 OFFSET VOLTAGE (mV) 0.4 0.8 4 0.6 2 0.4 0 VOS 0.2 -2 0 -4 -0.2 -6 -0.4 -8 IBN DISABLE -1 0 10 20 30 40 BIAS CURRENT (PA) IBI 50 60 70 -0.6 -40 TIME (ns) -10 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 17. Figure 18. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 7 LMH6739 SNOSAD2G - MAY 2004 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) AV = +2, VCC = 5V, RL = 100; unless otherwise specified). Crosstalk vs. Frequency Disabled Channel Isolation vs. Frequency -30 -30 CH A & C VOUT = 2 VPP MEASURE CH B -40 CROSSTALK (dBc) CROSSTALK (dBc) -40 -50 -60 -70 -80 VS = 5V -50 -60 -70 -80 -90 -100 -90 1 10 100 1000 0.1 1 10 100 1000 FREQUENCY (MHz) FREQUENCY (MHz) Figure 19. 8 VIN = 2 VPP Figure 20. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 LMH6739 www.ti.com SNOSAD2G - MAY 2004 - REVISED MARCH 2013 APPLICATION INFORMATION +5V +5V 6.8 F 6.8 F 0.01 F VIN RIN 0.01 F VIN CPOS CSS 0.1 F + VOUT - RIN CPOS + CSS 0.1 F VOUT - NC CNEG 0.01 F CNEG 0.01 F 6.8 F 6.8 F -5V -5V Figure 21. Recommended Non-Inverting Gain Circuit, Gain = +2 Figure 22. Recommended Non-Inverting Gain Circuit, Gain +1 +5V 6.8 F 0.01 F CPOS + CSS VOUT 0.1 F - VIN CNEG RIN 0.01 F 6.8 F -5V Figure 23. Recommended Inverting Gain Circuit, Gain = -1 GENERAL INFORMATION The LMH6739 is a high speed current feedback selectable gain buffer (SGB), optimized for very high speed and low distortion. With its internal feedback and gain-setting resistors the LMH6739 offers excellent AC performance while simplifying board layout and minimizing the affects of layout related parasitic components. The LMH6739 has no internal ground reference so single or split supply configurations are both equally useful. SETTING THE CLOSED LOOP GAIN The LMH6739 is a current feedback amplifier with on-chip RF = RG = 450. As such it can be configured with an AV = +2, AV = +1, or an AV = -1 by connecting pins 3 and 4 as described in Table 1. Table 1. Input Connections for all 3 Gain Possibilities GAIN AV INPUT CONNECTIONS Non-Inverting Inverting -1 V/V Ground Input Signal +1 V/V Input Signal NC (Open) +2 V/V Input Signal Ground Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 9 LMH6739 SNOSAD2G - MAY 2004 - REVISED MARCH 2013 www.ti.com The gain of the LMH6739 is accurate to 1% and stable over temperature. The internal gain setting resistors, RF and RG, match very well. However, over process and temperature their absolute value will change. Using external resistors in series with RG to change the gain will result in poor gain accuracy over temperature and from part to part. 4 RS 100: VIN CP 3.3 pF + 3 UNCOMPENSATED 2 VOUT 1 - 0 GAIN (dB) RIN 50: ROUT 50: -1 CP = 1.7 pF -2 -3 CP = 3.3 pF -4 -5 -6 -7 -8 VOUT = 250 mVPP 10 1 100 1000 FREQUENCY (MHz) Figure 24. Correction for Unity Gain Peaking Figure 25. Frequency Response for Circuit in Figure 24 UNITY GAIN COMPENSATION With a current feedback Selectable Gain Buffer like the LMH6739, the feedback resistor is a compromise between the value needed for stability at unity gain and the optimized value used at a gain of two. The result of this compromise is substantial peaking at unity gain. If this peaking is undesirable a simple RC filter at the input of the buffer will smooth the frequency response shown as Figure 24. Figure 25 shows the results of a simple filter placed on the non-inverting input. See Figure 26 and Figure 27 for another method for reducing unity gain peaking. +5V 4 6.8 F 3 PIN 4 FLOATING 2 0.01 F 1 VIN GAIN (dB) RIN 0 CPOS + CSS 0.1 F VOUT - CNEG -1 -2 PIN 4 SHORTED TO PIN 3 -3 -4 -5 0.01 F -6 VOUT = 250 mVPP -7 -8 GAIN = +1 1 6.8 F 10 100 1000 FREQUENCY (MHz) -5V Figure 26. Alternate Unity Gain Compensation Figure 27. Frequency Response for Circuit in Figure 26 X1 + RIN 51: - + - ROUT 51: CL 10 pF RL 1 k: Figure 28. Decoupling Capacitive Loads 10 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 LMH6739 www.ti.com SNOSAD2G - MAY 2004 - REVISED MARCH 2013 DRIVING CAPACITIVE LOADS Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Figure 28 shows the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. The charts "Suggested ROUT vs. Cap Load" give a recommended value for selecting a series output resistor for mitigating capacitive loads. The values suggested in the charts are selected for .5 dB or less of peaking in the frequency response. This gives a good compromise between settling time and bandwidth. For applications where maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the recommended values. LAYOUT CONSIDERATIONS Whenever questions about layout arise, use the evaluation board as a guide. The LMH730275 is the evaluation board for the LMH6739. To reduce parasitic capacitances ground and power planes should be removed near the input and output pins. Components in the feedback loop should be placed as close to the device as possible. For long signal paths controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller ceramic capacitors should be placed as close to the device as possible. The LMH6739 has multiple power and ground pins for enhanced supply bypassing. Every pin should ideally have a separate bypass capacitor. Sharing bypass capacitors may slightly degrade second order harmonic performance, especially if the supply traces are thin and /or long. In Figure 21 and Figure 22 CSS is optional, but is recommended for best second harmonic distortion. Another option to using CSS is to use pairs of .01 F and 0.1 F ceramic capacitors for each supply bypass. VIDEO PERFORMANCE The LMH6739 has been designed to provide excellent performance with production quality video signals in a wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless. Best performance will be obtained with back terminated loads. The back termination reduces reflections from the transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier output stage. Figure 24 shows a typical configuration for driving a 75 Cable. The amplifier is configured for a gain of two to make up for the 6 dB of loss in ROUT. MAXIMUM POWER DISSIPATION (W) 2 1.8 225 LFPM FORCED AIR 1.6 1.4 1.2 1 STILL AIR 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 29. Maximum Power Dissipation Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 11 LMH6739 SNOSAD2G - MAY 2004 - REVISED MARCH 2013 www.ti.com POWER DISSIPATION The LMH6739 is optimized for maximum speed and performance in the small form factor of the standard SSOP16 package. To achieve its high level of performance, the LMH6739 consumes an appreciable amount of quiescent current which cannot be neglected when considering the total package power dissipation limit. The quiescent current contributes to about 40 C rise in junction temperature when no additional heat sink is used (VS = 5V, all 3 channels on). Therefore, it is easy to see the need for proper precautions to be taken in order to make sure the junction temperature's absolute maximum rating of 150C is not violated. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation (all 3 channels). With the LMH6739 used in a back-terminated 75 RGB analog video system (with 2 VPP output voltage), the total power dissipation is around 435 mW of which 340 mW is due to the quiescent device dissipation (output black level at 0V). With no additional heat sink used, that puts the junction temperature to about 140 C when operated at 85C ambient. To reduce the junction temperature many options are available. Forced air cooling is the easiest option. An external add-on heat-sink can be added to the SSOP-16 package, or alternatively, additional board metal (copper) area can be utilized as heat-sink. An effective way to reduce the junction temperature for the SSOP-16 package (and other plastic packages) is to use the copper board area to conduct heat. With no enhancement the major heat flow path in this package is from the die through the metal lead frame (inside the package) and onto the surrounding copper through the interconnecting leads. Since high frequency performance requires limited metal near the device pins the best way to use board copper to remove heat is through the bottom of the package. A gap filler with high thermal conductivity can be used to conduct heat from the bottom of the package to copper on the circuit board. Vias to a ground or power plane on the back side of the circuit board will provide additional heat dissipation. A combination of front side copper and vias to the back side can be combined as well. Follow these steps to determine the maximum power dissipation for the LMH6739: 1. Calculate the quiescent (no-load) power: PAMP = ICC x (VS) VS = V+-V- (1) 2. Calculate the RMS power dissipated in the output stage: PD (rms) = rms ((VS - VOUT)*IOUT) (2) where VOUT and IOUT are the voltage and current across the external load and VS is the total supply current 3. Calculate the total RMS power: PT = PAMP+PD (3) The maximum power that the LMH6739 package can dissipate at a given temperature can be derived with the following equation (See Figure 29): PMAX = (150 - TAMB)/ JA, where TAMB = Ambient temperature (C) and JA = Thermal resistance, from junction to ambient, for a given package (C/W). For the SSOP package JA is 120C/W. ESD PROTECTION The LMH6739 is protected against electrostatic discharge (ESD) on all pins. The LMH6739 will survive 2000V Human Body model and 200V Machine model events. Under closed loop operation the ESD diodes have no effect on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6739 is driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to power up a chip with a large signal applied to the input pins. Shorting the power pins to each other will prevent the chip from being powered up through the input. 12 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 LMH6739 www.ti.com SNOSAD2G - MAY 2004 - REVISED MARCH 2013 REVISION HISTORY Changes from Revision F (March 2013) to Revision G * Page Changed layout of National Data Sheet to TI format .......................................................................................................... 12 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMH6739 13 PACKAGE OPTION ADDENDUM www.ti.com 24-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMH6739MQ/NOPB ACTIVE SSOP DBQ 16 95 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LH67 39MQ LMH6739MQX/NOPB ACTIVE SSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LH67 39MQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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