1
2
3
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7
89
10
11
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16
-
+
-
+
-
+
-IN A
+IN A
-IN B
+IN B
DIS B
DIS C
-IN C
+IN C -VS
OUT C
+VS
OUT B
-VS
OUT A
+VS
DIS A
LMH6739
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SNOSAD2G –MAY 2004–REVISED MARCH 2013
LMH6739 Very Wideband, Low Distortion Triple Video Buffer
Check for Samples: LMH6739
1FEATURES DESCRIPTION
2• 750 MHz −3 dB small signal bandwidth The LMH6739 is a very wideband, DC coupled
(AV= +1) monolithic selectable gain buffer designed specifically
•−85 dBc 3rd harmonic distortion (20 MHz) for ultra high resolution video systems as well as wide
• 2.3 nV/√Hz input noise voltage dynamic range systems requiring exceptional signal
fidelity. Benefiting from current feedback architecture,
• 3300 V/μs slew rate the LMH6739 offers gains of −1, 1 and 2. At a gain of
• 32 mA supply current (10.6 mA per op amp) +2 the LMH6739 supports ultra high resolution video
• 90 mA linear output current systems with a 400 MHz 2 VPP3 dB Bandwidth. With
12-bit distortion level through 30 MHz (RL= 100Ω),
• 0.02/0.01 Diff. Gain/ Diff. Phase (RL= 150Ω)2.3nV/√Hz input referred noise, the LMH6739 is the
• 2mA shutdown current ideal driver or buffer for high speed flash A/D and D/A
converters. Wide dynamic range systems such as
APPLICATIONS radar and communication receivers requiring a
wideband amplifier offering exceptional signal purity
• RGB video driver will find the LMH6739 low input referred noise and
• High resolution projectors low harmonic distortion make it an attractive solution.
• Flash A/D driver The LMH6739 is offered in a space saving SSOP
• D/A transimpedance buffer package.
• Wide dynamic range IF amp
• Radar/communication receivers
• DDS post-amps
• Wideband inverting summer
• Line driver
CONNECTION DIAGRAM
16-Pin SSOP
Top View
See Package Number DBQ0016A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMH6739
SNOSAD2G –MAY 2004–REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
ESD Tolerance (2)
Human Body Model 2000V
Machine Model 200V
Supply Voltage (V+- V–) 13.2V
IOUT (3)
Common Mode Input Voltage ±VCC
Maximum Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Soldering Information
Infrared or Convection (20 sec.) 235°C
Wave Soldering (10 sec.) 260°C
Storage Temperature Range −65°C to +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(3) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Application Information for more details.
Operating Ratings(1)(2)
Temperature Range (3) −40°C to +85°C
Supply Voltage (V+- V–) 8V to 12V
Thermal Resistance
Package (θJC) (θJA)
16-Pin SSOP 36°C/W 120°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications, see the Electrical
Characteristics tables.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(3) The maximum power dissipation is a function of TJ(MAX),θJA. The maximum allowable power dissipation at any ambient temperature is
PD= (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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Electrical Characteristics (1)
TA= 25°C, AV= +2, VCC = ±5V, RL= 100Ω; unless otherwise specified.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
Frequency Domain Performance
UGBW −3 dB Bandwidth Unity Gain, VOUT = 200 mVPP 750 MHz
SSBW −3 dB Bandwidth VOUT = 200 mVPP 480 MHz
LSBW VOUT = 2 VPP 400
0.1 dB Bandwidth VOUT = 2 VPP 150 MHz
GFR2 Rolloff at 300 MHz, VOUT = 2 VPP 1.0 dB
Time Domain Response
TRS Rise and Fall Time 2V Step 0.9 ns
(10% to 90%)
TRL 5V Step 1.7
SR Slew Rate 5V Step 3300 V/µs
tsSettling Time to 0.1% 2V Step 10 ns
teEnable Time From Disable = rising edge. 7.3 ns
tdDisable Time From Disable = falling edge. 4.5 ns
Distortion
HD2L 2 VPP, 5 MHz −80
HD2 2nd Harmonic Distortion 2 VPP, 20 MHz −71 dBc
HD2H 2 VPP, 50 MHz −55
HD3L 2 VPP, 5 MHz −90
HD3 3rd Harmonic Distortion 2 VPP, 20 MHz −85 dBc
HD3H 2 VPP, 50 MHz −65
Equivalent Input Noise
VNNon-Inverting Voltage >1 MHz 2.3 nV/√Hz
ICN Inverting Current >1 MHz 12 pA/√Hz
NCN Non-Inverting Current >1 MHz 3 pA/√Hz
Video Performance
DG Differential Gain 4.43 MHz, RL= 150Ω.02 %
DP Differential Phase 4.43 MHz, RL= 150Ω.01 degree
Static, DC Performance
VOS Input Offset Voltage (4) 0.5 ±2.5 mV
±4.5
IBN Input Bias Current (4) Non-Inverting −16 −8 0 µV
−21 +5
IBI Input Bias Current (4) Inverting −2 ±30 μA
±40
PSRR Power Supply Rejection Ratio (4) 50 53 dB
48.5
CMRR Common Mode Rejection Ratio (4) 46 50 dB
44
ICC Supply Current (4) All three amps Enabled, No Load 32 35 mA
40
Supply Current Disabled V+RL=∞1.9 2.2 mA
Supply Current Disabled V−RL=∞1.1 1.3 mA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. Parametric performance is indicated in the electrical tables under conditions of
internal self heating where TJ> TA. See Applications Information for information on temperature de-rating of this device. Min/Max ratings
are based on product characterization and simulation. Individual parameters are tested as noted.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are through correlations using the Statistical
Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested on shipped production material.
(4) Parameter 100% production tested at 25° C.
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Electrical Characteristics (1) (continued)
TA= 25°C, AV= +2, VCC = ±5V, RL= 100Ω; unless otherwise specified.
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
Internal Feedback & Gain Set 375 450 525 Ω
Resistor Value
Gain Error RL=∞0.2 ±1.1 %
Miscellaneous Performance
RIN+ Non-Inverting Input Resistance 1000 kΩ
CIN+ Non-Inverting Input Capacitance .8 pF
RIN−Inverting Input Impedance Output impedance of input buffer. 30 Ω
ROOutput Impedance DC 0.05 Ω
±3.25 ±3.5
RL= 100Ω±3.1
VOOutput Voltage Range (4) V
±3.65 ±3.8
RL=∞±3.5
CMIR Common Mode Input Range (4) CMRR > 40 dB ±1.9 ±2.0 V
±1.7
Linear Output Current (5) (4) 80
IOVIN = 0V, VOUT < ±30 mV 90 mA
60
ISC Short Circuit Current (6) VIN = 2V Output Shorted to Ground 160 mA
IIH Disable Pin Bias Current High Disable Pin = V+10 μA
IIL Disable Pin Bias Current Low Disable Pin = 0V −350 μA
VDMAX Voltage for Disable Disable Pin ≤VDMAX 0.8 V
VDMIM Voltage for Enable Disable Pin ≥VDMIN 2.0 V
(5) The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of the
Application Information for more details.
(6) Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of the Application
Information for more details.
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110 100 1000
FREQUENCY (MHz)
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
NORMALIZED GAIN (dB)
VOUT = 0.5 VPP
AV = +1
AV = +2
AV = -1
110 100 1000
FREQUENCY (MHz)
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
GAIN (dB)
NON-INVERTING
BOTH
VOUT ± 250 mVPP
GAIN = +1
10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
NORMALIZED GAIN (dB)
VS = 7V
VOUT = 2 VPP
VS = 9V
VS = 12.5V
10 100 1000
FREQUENCY (MHz)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
GAIN (dB)
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 2 VPP
VOUT = 4 VPP
AV = 2 V/V
110 100 1000
FREQUENCY (MHz)
-10
-8
-6
-4
-2
0
2
4
NORMALIZED GAIN (dB)
AV = +1
AV = +2
AV = -1
VOUT = 2 VPP
110 100 1000
FREQUENCY (MHz)
-10
-8
-6
-4
-2
0
2
4
NORMALIZED GAIN (dB)
AV = +1
AV = +2
AV = -1
LMH6739
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SNOSAD2G –MAY 2004–REVISED MARCH 2013
Typical Performance Characteristics
AV= +2, VCC = ±5V, RL= 100Ω; unless otherwise specified).
Large Signal Frequency Response Small Signal Frequency Response
Figure 1. Figure 2.
Frequency Response
vs. Frequency Response vs.
VOUT Supply Voltage
Figure 3. Figure 4.
Gain Flatness Gain Flatness, Dual Input Buffer
Figure 5. Figure 6.
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0 1 2 3 4 5 6 7 8
-100
-40
DISTORTION (dBc)
OUTPUT VOLTAGE (VPP)
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
-45
HD3
HD2
f = 10 MHz
1100
FREQUENCY (MHz)
-100
-80
-60
-40
DISTORTION (dBc)
10
-50
-70
-90
-45
-55
-65
-75
-85
-95
VOUT = 2 VPP
HD2
HD3
020 40 60 80 100 120
CAPACITIVE LOAD (pF)
0
10
20
30
40
50
60
70
80
RECOMMENDED RS (:)
LOAD = 1 k: || CL
120
0.01 11000
FREQUENCY (MHz)
MAGNITUDE, |Z| (dB:)
100
10
0.1
100
90
110
MAGNITUDE
PHASE
40
70
60
50
80
-180
-45
-90
-135
0
PHASE (°)
0 4 8 12 16 20
-1.5
-1
-0.5
0
0.5
1
1.5
VOUT (V)
TIME (ns)
110 100 1000
FREQUENCY (MHz)
-10
-8
-6
-4
-2
0
2
GAIN (dB)
CL = 4.7 pF, RS = 70:
CL = 15 pF, RS = 44:
CL = 47 pF, RS = 24:
CL = 100 pF, RS = 17:
VOUT = 1 VPP, CL || 1 k:
LMH6739
SNOSAD2G –MAY 2004–REVISED MARCH 2013
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Typical Performance Characteristics (continued)
AV= +2, VCC = ±5V, RL= 100Ω; unless otherwise specified). Frequency Response vs.
Pulse Response Capacitive Load
Figure 7. Figure 8.
Series Output Resistance vs.
Capacitive Load Open Loop Gain and Phase
Figure 9. Figure 10.
Distortion vs. 10 MHz HD vs.
Frequency Output Level
Figure 11. Figure 12.
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-40 -20 0 20 80 100
OFFSET VOLTAGE (mV)
TEMPERATURE (°C)
40 60
-0.6
-0.4
0
0.2
0.4
0.6
0.8
1
-0.2
-10
-8
-4
-2
0
2
4
6
-6
BIAS CURRENT (PA)
IBI
VOS
IBN
0.1 1 10 100 1000
FREQUENCY (MHz)
0
10
20
30
40
50
60
PSRR (dB)
PSRR +
PSRR -
0.001 0.1 10 1000
0.01
0.1
10
100
100
1
0.01
1
FREQUENCY (MHz)
|Z| (:)
AV = 2 V/V
VIN = 0V
6.8 7.6 8.4 9.2 11.6 12.4
-100
-95
-85
-80
-75
-70
-65
DISTORTION (dBc)
TOTAL SUPPLY VOLTAGE (V)
-90
10 10.8
VOUT = 2VPP
f = 10 MHz
HD2
HD3
0.01 11000
FREQUENCY (MHz)
0
20
50
CMRR (dB)
100
10
0.1
40
30
10
45
35
25
15
5
LMH6739
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SNOSAD2G –MAY 2004–REVISED MARCH 2013
Typical Performance Characteristics (continued)
AV= +2, VCC = ±5V, RL= 100Ω; unless otherwise specified).
Distortion vs. CMRR vs.
Supply Voltage Frequency
Figure 13. Figure 14.
PSRR vs.
Frequency Closed Loop Output Impedance |Z|
Figure 15. Figure 16.
DC Errors vs.
Disable Timing Temperature
Figure 17. Figure 18.
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110 100 1000
FREQUENCY (MHz)
-90
-80
-70
-60
-50
-40
-30
CROSSTALK (dBc)
CH A & C VOUT = 2 VPP
MEASURE CH B
0.1 1 10 100 1000
FREQUENCY (MHz)
-100
-90
-80
-70
-60
-50
-40
-30
CROSSTALK (dBc)
VIN = 2 VPP
VS = ±5V
LMH6739
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Typical Performance Characteristics (continued)
AV= +2, VCC = ±5V, RL= 100Ω; unless otherwise specified).
Crosstalk vs. Disabled Channel Isolation vs.
Frequency Frequency
Figure 19. Figure 20.
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VOUT
+
-
+5V
-5V
CPOS
6.8 µF
0.01 µF
6.8 µF
CNEG
0.01 µF
0.1 µF
CSS
RIN
VIN
VOUT
+
-
VIN
+5V
-5V
CPOS
6.8 µF
0.01 µF
6.8 µF
CNEG
0.01 µF
RIN 0.1 µF
CSS
VOUT
+
-
VIN
+5V
-5V
CPOS
6.8 µF
0.01 µF
6.8 µF
CNEG
0.01 µF
RIN 0.1 µF
CSS
NC
LMH6739
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SNOSAD2G –MAY 2004–REVISED MARCH 2013
APPLICATION INFORMATION
Figure 21. Recommended Non-Inverting Gain Figure 22. Recommended Non-Inverting Gain
Circuit, Gain = +2 Circuit, Gain +1
Figure 23. Recommended Inverting Gain Circuit,
Gain = –1
GENERAL INFORMATION
The LMH6739 is a high speed current feedback selectable gain buffer (SGB), optimized for very high speed and
low distortion. With its internal feedback and gain-setting resistors the LMH6739 offers excellent AC performance
while simplifying board layout and minimizing the affects of layout related parasitic components. The LMH6739
has no internal ground reference so single or split supply configurations are both equally useful.
SETTING THE CLOSED LOOP GAIN
The LMH6739 is a current feedback amplifier with on-chip RF= RG= 450Ω. As such it can be configured with an
AV= +2, AV= +1, or an AV=−1 by connecting pins 3 and 4 as described in Table 1.
Table 1. Input Connections for all 3 Gain Possibilities
INPUT CONNECTIONS
GAIN AVNon-Inverting Inverting
−1 V/V Ground Input Signal
+1 V/V Input Signal NC (Open)
+2 V/V Input Signal Ground
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+
-
RIN
51:
X1
-
+ROUT
51:
CL
10 pF RL
1 k:
VOUT
+
-
VIN
+5V
-5V
CPOS
6.8 µF
0.01 µF
6.8 µF
CNEG
0.01 µF
RIN 0.1 µF
CSS
11000
FREQUENCY (MHz)
-8
-4
0
4
GAIN (dB)
100
10
-2
-6
-7
-5
-3
-1
1
2
3
VOUT = 250 mVPP
GAIN = +1
PIN 4 FLOATING
PIN 4 SHORTED TO PIN 3
110 1000
FREQUENCY (MHz)
100
-8
-4
0
4
GAIN (dB)
2
-2
-6
3
1
-1
-3
-5
-7 VOUT = 250 mVPP
UNCOMPENSATED
CP = 1.7 pF
CP = 3.3 pF
+
-
RIN
50:
RS
100:ROUT
50:
CP
3.3 pF
VIN VOUT
LMH6739
SNOSAD2G –MAY 2004–REVISED MARCH 2013
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The gain of the LMH6739 is accurate to ±1% and stable over temperature. The internal gain setting resistors, RF
and RG, match very well. However, over process and temperature their absolute value will change. Using
external resistors in series with RGto change the gain will result in poor gain accuracy over temperature and
from part to part.
Figure 24. Correction for Unity Gain Peaking Figure 25. Frequency Response for Circuit in
Figure 24
UNITY GAIN COMPENSATION
With a current feedback Selectable Gain Buffer like the LMH6739, the feedback resistor is a compromise
between the value needed for stability at unity gain and the optimized value used at a gain of two. The result of
this compromise is substantial peaking at unity gain. If this peaking is undesirable a simple RC filter at the input
of the buffer will smooth the frequency response shown as Figure 24.Figure 25 shows the results of a simple
filter placed on the non-inverting input. See Figure 26 and Figure 27 for another method for reducing unity gain
peaking.
Figure 26. Alternate Unity Gain Compensation Figure 27. Frequency Response for Circuit in
Figure 26
Figure 28. Decoupling Capacitive Loads
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-40 -20 0 20 40 60 80 100
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
MAXIMUM POWER DISSIPATION (W)
TEMPERATURE (°C)
225 LFPM FORCED AIR
STILL AIR
LMH6739
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SNOSAD2G –MAY 2004–REVISED MARCH 2013
DRIVING CAPACITIVE LOADS
Capacitive output loading applications will benefit from the use of a series output resistor ROUT.Figure 28 shows
the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive
loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation.
The charts “Suggested ROUT vs. Cap Load” give a recommended value for selecting a series output resistor for
mitigating capacitive loads. The values suggested in the charts are selected for .5 dB or less of peaking in the
frequency response. This gives a good compromise between settling time and bandwidth. For applications where
maximum frequency response is needed and some peaking is tolerable, the value of ROUT can be reduced
slightly from the recommended values.
LAYOUT CONSIDERATIONS
Whenever questions about layout arise, use the evaluation board as a guide. The LMH730275 is the evaluation
board for the LMH6739.
To reduce parasitic capacitances ground and power planes should be removed near the input and output pins.
Components in the feedback loop should be placed as close to the device as possible. For long signal paths
controlled impedance lines should be used, along with impedance matching elements at both ends.
Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to
ground are applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the
smaller ceramic capacitors should be placed as close to the device as possible. The LMH6739 has multiple
power and ground pins for enhanced supply bypassing. Every pin should ideally have a separate bypass
capacitor. Sharing bypass capacitors may slightly degrade second order harmonic performance, especially if the
supply traces are thin and /or long. In Figure 21 and Figure 22 CSS is optional, but is recommended for best
second harmonic distortion. Another option to using CSS is to use pairs of .01 μF and 0.1 μF ceramic capacitors
for each supply bypass.
VIDEO PERFORMANCE
The LMH6739 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless.
Best performance will be obtained with back terminated loads. The back termination reduces reflections from the
transmission line and effectively masks transmission line and other parasitic capacitances from the amplifier
output stage. Figure 24 shows a typical configuration for driving a 75ΩCable. The amplifier is configured for a
gain of two to make up for the 6 dB of loss in ROUT.
Figure 29. Maximum Power Dissipation
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POWER DISSIPATION
The LMH6739 is optimized for maximum speed and performance in the small form factor of the standard SSOP-
16 package. To achieve its high level of performance, the LMH6739 consumes an appreciable amount of
quiescent current which cannot be neglected when considering the total package power dissipation limit. The
quiescent current contributes to about 40° C rise in junction temperature when no additional heat sink is used (VS
= ±5V, all 3 channels on). Therefore, it is easy to see the need for proper precautions to be taken in order to
make sure the junction temperature’s absolute maximum rating of 150°C is not violated.
To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of
utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation (all 3
channels).
With the LMH6739 used in a back-terminated 75ΩRGB analog video system (with 2 VPP output voltage), the
total power dissipation is around 435 mW of which 340 mW is due to the quiescent device dissipation (output
black level at 0V). With no additional heat sink used, that puts the junction temperature to about 140° C when
operated at 85°C ambient.
To reduce the junction temperature many options are available. Forced air cooling is the easiest option. An
external add-on heat-sink can be added to the SSOP-16 package, or alternatively, additional board metal
(copper) area can be utilized as heat-sink.
An effective way to reduce the junction temperature for the SSOP-16 package (and other plastic packages) is to
use the copper board area to conduct heat. With no enhancement the major heat flow path in this package is
from the die through the metal lead frame (inside the package) and onto the surrounding copper through the
interconnecting leads. Since high frequency performance requires limited metal near the device pins the best
way to use board copper to remove heat is through the bottom of the package. A gap filler with high thermal
conductivity can be used to conduct heat from the bottom of the package to copper on the circuit board. Vias to a
ground or power plane on the back side of the circuit board will provide additional heat dissipation. A combination
of front side copper and vias to the back side can be combined as well.
Follow these steps to determine the maximum power dissipation for the LMH6739:
1. Calculate the quiescent (no-load) power:
PAMP = ICC x (VS) VS= V+-V−(1)
2. Calculate the RMS power dissipated in the output stage:
PD(rms) = rms ((VS- VOUT)*IOUT) (2)
where VOUT and IOUT are the voltage and current across the external load and VSis the total supply current
3. Calculate the total RMS power:
PT= PAMP+PD(3)
The maximum power that the LMH6739 package can dissipate at a given temperature can be derived with the
following equation (See Figure 29):
PMAX = (150º – TAMB)/ θJA, where TAMB = Ambient temperature (°C) and θJA = Thermal resistance, from junction
to ambient, for a given package (°C/W). For the SSOP package θJA is 120°C/W.
ESD PROTECTION
The LMH6739 is protected against electrostatic discharge (ESD) on all pins. The LMH6739 will survive 2000V
Human Body model and 200V Machine model events.
Under closed loop operation the ESD diodes have no effect on circuit performance. There are occasions,
however, when the ESD diodes will be evident. If the LMH6739 is driven by a large signal while the device is
powered down the ESD diodes will conduct.
The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through
the device, hence it is possible to power up a chip with a large signal applied to the input pins. Shorting the
power pins to each other will prevent the chip from being powered up through the input.
12 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMH6739
LMH6739
www.ti.com
SNOSAD2G –MAY 2004–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision F (March 2013) to Revision G Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 12
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMH6739
PACKAGE OPTION ADDENDUM
www.ti.com 24-Oct-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6739MQ/NOPB ACTIVE SSOP DBQ 16 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LH67
39MQ
LMH6739MQX/NOPB ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LH67
39MQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 24-Oct-2013
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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