TOSHIBA TMP82C59A TOSHIBA MOS TYPE DEGITAL INTEGRATED CIRCUIT Silicon Monolithic CMOS Silicon Gate TMP82C59AP-2/TMP82C59AM-2 PROGRAMMABLE INTERRUPT CONTROLLER 1. GENERAL DESCRIPTION TMP82C59AP-2/AM-2 (hereinafter referred to as TMP82C59A) is a programmable interrupt controller. It handles up to eight vectored priority interrupts for the MPU. It is cascadable for up to 64 vectored priority interrupts without additional circuitry. Interrupt Modes, Interrupt Mask, Vectored Address Programmable. Supports 8085A, 8086 Microcomputer Interrupt Sequence. FEATURES e Eight Level Priority Controller. e Expandable to 64 Level. e Single +5V Power Supply. e e TTL Compatible. 2. PIN CONNECTIONS (TOP VIEW) TMP82C59AP-2/FMP82CS9AM-2 a WR RD D7 Dg Ds Da D3 D3 D; Do CAS CAS, Vss (GND) O1 SY 5g Tl] Vee 2 270 Ao C3 26 1 INTA ca 25 7 IR? os 2417 IRg C6 23 01 IRs 7 22 [1 IRg 8 210 IR3 9 20 0 iR2 C10 19 7) IR, O11 18 1 IR [12 17 0 INT 13 16 0 SP/EN O14 15 1) CAS? osoare MPU85-172TOSHIBA TMP82C59A 3. PIN NAMES AND DESCRIPTION Table 3.1 Pin Name | Input/Output Function te Input Chip Select Input. A low on this pin enables RD and WR communication P between the MPU and the TMP82C59A. INTA functions are independent of CS. Write Control Input. A low on this pin when CS is low enables the TMP82C59A WR Input . to receive command words from MPU. =~ Read Control Input. A low on this pin when C$ is low enables the TMP82C59A RD Input to output status onto the data bus forthe MPU. Bidirectional Data Bus. Command status and interrupt-vector information is D D | otoD7 | Input/Output transferred via this bus. CAS to Cascade Lines. The CAS lines from a private TMP82C59A bus to control a CAS Input/Output] multiple TMP82C59A structure. These pins are outputs for a master 2 TMP82C59A and inputs for aslave TMP82C59A. Slave Program / Enable buffer. This is a dual function pin. in the buffered SP/EN | Inout /Outout mode, it can be used as an output to control buffer transceivers (EN). In the P P non-buffered mode, it is used as an input to designate a master TMP82C59A (SP = 1) or aslave one (SP =0). Interrupt Request Cutput. This pin goes high whenever a valid interrupt INT Output request is asserted. It is used to interrupt the MPU. It is cannected to MPU's interrupt pin. Interrupt Request Inputs. An interrupt request is executed by raising an IR IRg to IR7 Input input (iow to high), and holding it high until it is acknowiedged (Edge Triggered Mode), or just by a high level on aiR input (Level Triggered Mode. } Interrupt Acknowledge Input. This pin is used to output interrupt-vector data INTA Input onto the data bus by a sequence of interrupt acknowledge pulses issued by the MPU. Address Line. This pin acts in conjunction with the CS, WR and RD pins. It is A input used by the TMP82C59A to decipher various command words the MPU writes 0 P and status the MPU wishes to read. It is typically connected to the MPU Ag address line. vcc + 5V Power Supply vss Ground 050489 MPU85-173TOSHIBA TMP82C59A 4. FUNCTIONAL DESCRIPTION INTA CONTROL LOGIC INT Dem D DATA BUS ue BUFFER RD IRo WR iN INTERR- in A SERVICE UPT 2 REG PRIORITY REQUEST IR3 ESOLVE REG cs (ISR) [Ra (IRR} IRs CASo CASCADE IRE CAS} BUFFER / IR7 CAS> COMPARATOR SB /EN INTERRUPT MASK REG. Vec SP/E Ut (IMR) Vss INTERNAL BUS 050489 Figure 4.1 BLOCK DIAGRAM The TMP82CS9A is connected to the system bus as shown in Figure 4.2 and operates as an interrupt controller. ADDRESS BUS 16 CONTROL BUS DATA BUS 8 8 a QO 2 2 CS Ag Dy~Dp RD WR INT INTA = | CAS9 CASCADE LINE ~*|CASi ~> CAS? SP/EN IR? IRg IRs {Rg IR3 IR2 IRi IRo WE EEL ET] SLAVE PROGRAM / ENABLE BUFFER INTERRUPT REQUESTS 950489 Figure 4.2 Interface to the System Bus MPU85-174TOSHIBA TMP82C59A 4.1. GENERAL DESCRIPTION Whenever an interrupt request is received via IRn, the TMP82C59A, judging its mask status and priority, set INT high for requesting interrupt to MPU. Then, according to response signal (INTA signal) from MPU or the system controller, the TMP82C59A outputs CALL op-code and vectored address data on to the data bus. MPU starts the interrupt service routine and the TMP82C59A stores which interrupt request has been serviced. At the end of the service routine, MPU resets it and informs the TMP82C594 of its end. Table 4.1 Basic Operation Ao | Da | D3 | RD | WR] CS READ OPERATION 0 0 1 O JIRR, ISR or interrupt request level > Data bus 1 0 1 0 |IMR ~~ Data bus Ao | Da | D3 | RD | WR] CS WRITE OPERATION 0 Q Q 1 0 0 Data bus OCW2 0 0 1 1 0 0 Data bus OCW3 0 1 x 1 0 0 | Data bus > 1CW1 1 x x 1 0 GQ | Data bus > OCW1, ICW2, ICW3 or ICW4 Ao | Da | D3 | RD | WR] CS HIGH IMPEDANCE x x x 1 1 O | Data bus (D7 to Do) High impedance x x x x x 1 | Data bus (D7 to Dg) High impedance 050489 4.2 SYSTEM CONFIGURATION The TMP82C59A consists of the following components. (1} Interrupt Request Register (IRR) and Inservice Register (ISR) (2) Priority Resolver (3) Interrupt Mask Register (IMR) (4) Data Bus Buffer (5) Read/Write Logic (6) Cascade Buffer/Comparator (7) Interrupt Request Register (IRR) and Inservice Register (ISR) Interrupt requests from [Rn inputs are processed by 2 registers, IRR and ISR. IRR holds interrupt request from the respective [Rn inputs while ISR holds all interrupt levels that are being serviced by the MPU. Contents of IRR and ISR can be read out by the MPU. MPU85-175TOSHIBA TMP82C59A (2) (3) (4) Priority Resolver The priority resolver is the block that decides the interrupt request to be sent to MPU by judging priority. If the interrupt mask register (IMR) bit corresponding to IRn input is not set to 1, IRR sends the interrupt requests to the priority resolver. Normally, when the interrupt request level having the highest priority among these interrupt request is higher than the content of ISR, that is, the priority of the interrupt request being serviced by the MPU, the TMP82C59A sends INT signal to the MPU. When INTA signal is input as a response from the MPU the TMP82C59A sends CALL op-code and the vectored address corresponding to an interrupt request of the highest priority to MPU, and resetting IRR bit corresponding to this interrupt request sets ISR bits. The MPU processes the interrupt service, sends a command to the TMP82C59A to accept interrupt requests of lower priority at the end of the interrupt service, and resets the corresponding ISR bits. The priority resolver has a register to assign the interrupt request input of lowest priority. Interrupt Mask Register (IMR) The interrupt mask register normaly acts only on IRR, and disables interrupt requests from the masked IRn input. The mask for an interrupt request input does not affect its lower priority interrupt requests. In the special mask mode, this register also acts on ISR and enables acceptance of lower level interrupt requests than the interrupt request being serviced. The content of IMR can be read out. Data Bus Buffer The data bus buffer consists of 8 bit 3 state bidirectional bus buffer interfacing with the system bus. Command words, status information CALL op-code and vectored addresses are transfered via this bus buffer. Read/Write Logic This circuit controls the functions for decoding and accepting command words from MPU and for feeding status information to the data bus. In addition, this circuit controls operations including ICW (Initialization Command Word) register and OCW (Operation Set Command Word) register. : Low level input to CS enables RD orWR input operation. : When WR =CS=0, a command write to the TMP82CS59A is enabled. Hag : When RD=CS=0, the contents of ISR, IRR and IMR and interrupt level in the poil mode can be read. MPU85-176TOSHIBA TMP82C59A (6) 43 (1) Ag : Ag is used together with WR and RD signals for command write or status readout. It acts as a select signal for the one of command words or status information. It is normally connected to the one of address lines. Cascade Buffer/Comparator When programmed as a slave device, this block stores the identification code as the slave and compares this identification code with the data on the 3 bit cascade lines (CASg-9). When both agree, the slave interpretes that the slave itself is selected. In the case of the master, an identification signal corresponding to the accepted interrupt request inputs of the slave device are output for a period from the first INTA signal to the last INTA signal (second or third signal). INTERRUPT SEQUENCE When the 8085A is used as the MPU (a) When one or more interrupt request become high level, IRR bits corresponding to that input are set. (b) The TMP82C59A judges the mask status and priority of these interrupt and outputs INT signal to MPU as necessary. (c) MPU outputs INTA signal in response to INT signal. (d) Upon receipt of INTA signal, the TMP82C59A outputs CALL op-code on the data bus. (e) Since CALL is a 3-byte instruction, additional two INTA signals are consecutively sent from MPU. (f) Upon receipt of these two INTA signals, the TMP82C59A outputs the programmed vector address corresponding to the highest priority interrupt request. The TMP82C59A outputs the low-order address and then, the high-order address. Furthermore, the TMP82C59A sets the ISR bit corresponding to the interrupt request and resets IRR bit. (g) The above operations complete CALL instruction and MPU executes the interrupt service. In AEOI mode, ISR bits are automatically reset immediately after the above operations. Otherwise, ISR bits are kept in the set status till EOI command is input. MPU85-177TOSHIBA TMP82C59A (2) 44 (1) (2) When the 8086 is used as MPU (a) to (c) Same as (a) to (c) for the 8085A. (d) Even when INTA signal is received, the TMP82C59A keeps the data bus in high impedance state. (e) Another INTA signal is sent from MPU. The TMP82C59A outputs 8 bit pointer on the data bus, and sets the corresponding ISR bit and resets the IRR bit. (f) The above operations complete the interrupt acknowledge cycle. In AEOI mode, the ISR bit is automatically reset after the final INTA signal is received. Otherwise, ISR bits are kept in the set status till EOI command is input. Further, if there is no interrupt request at the time of step (d) of the above interrupt sequence, (i.e., the request was too short in duration), the TMP82C59A performs the same operations as those when interrupt request are generated at IR7, but ISR bits are not set. INTERRUPT SEQUENCE OUTPUT When the 8085A is used as the MPU CALL op-code is output on the data bus upon receipt of the first INTA signal and the low-order vectored address and the high-order vectored address on the data bus upon receipt of the second and third INTA signals, respectively. The vectored address As to Ays on Table 4.3, 4.4 must be programmed in advance on the TMP82C59A. The remaining bits of the vectored addresses are produced by the TMP82C59A corresponding to interrupt request. When the 8086 is used as the MPU When the first INTA signal is received, the data bus is placed in the high impedance state. When the second INTA signals is received, 8 bit pointer is output on the data bus. The 8 bit pointers T7 to T3 shown in Table 4.5 must be programmed in advance on the TMP82C59A. The remaining bits are automatically produced by the TMP82C59A corresponding to interrupts. MPU85-178TOSHIBA TMP82C59A {1} 8085A MODE . Table 4.2 For First INTA Dy D Ds D4 D3 D2 Dy Do [rps pote ps pr pepe] Table 4.3 For Second INTA IR INTERVAL =4 D7 Dg Ds D4 D3 D> Dy Do IR7 AZ Ags As 1 1 1 0 0 IRg Az A6 As 1 ] 0 0 0 IRs AZ Ag As 1 0 1 0 0 iRg AZ Ag As 1 0 0 0 0 IR3 Aj Ag As 0 1 1 0 0 IR AZ Ag6 As 0 1 0 0 0 IR4 Aq Ag As 0 0 1 0 0 IRo AZ Ag As 0 0 0 0 0 050489 IR INTERVAL =8 D7 D Ds Da D3 D2 Dy Do IR7 Az Ag 1 4 1 0 0 0 IR6 Ay Ag 1 1 Q 0 0 0 IRs Ay; Ag 1 0 1 0 Q 6 IRq A; Ag i 0 Q 0 Q 0 IR3 Ay Ag a 1 1 0 QO 0 IR2 Az Ab Q 1 0 0 0 0 IR4 AT Ag6 0 0 1 0 0 0 IRo AT Ag 0 0 0 0 Q 0 050489 Table 4.2 For Third INTA Dy Dg Ds Dg D3 D> Dy Do | Ars | Ara A13 | A12 Ant | A10 | Ag | Ag a50489 (2) 8086 MODE Table 4.5 Second INTA D7 De Ds D4 D3 Ba D, Do IR7 Tz T Ts T4 T3 1 | 1 IRe T7 T6 Ts T4 T3 1 1 0 IRs T7 Ts Ts T4 T3 1 0 1 IRq T7 Ts Ts T4 T3 j 0 0 IR3 T7 T6 Ts T4 T3 0 1 1 IR2 7 T Ts Ta T3 0 1 0 Ry T7 Ts Ts Ta T3 0 0 1 iRo T7 Te Ts Ta T3 0 0 0 050489 MPU85-179TOSHIBA TMP82C59A 4.5 (1) (2) PROGRAMMING TMP82C59A The TMP82C59A accepts the following 2 types of command words. Initialization Command Words (ICW) Prior to operating the TMP82C59A, it is necessary to program this command. Operation Command Words (OCW) This command is for operating the TMP82C59A in various operating modes and is programmable anytime during the TMP82C5Q9A is in operation. (1) ICW There are 4 kinds of commands; ICW1, ICW2, ICW3 and ICW4. Each of these command is not programmable independently. The initialization is made according to the initialization command sequence shown in Figure 4.3. ICW3 is used for cascade connection and ICW4 is for setting optional modes. NO (SNGL=1 READY TO ACCEPT INTERRUPT REQUESTS 050489 Figure 4.3 Initialization Command Sequence MPU85-180TOSHIBA TMP82C59A ICW1 When Ag=0 and D4g=1, the initialization is interpreted as ICW1 and the initialization of following 5 items are made independently of content of the command: [1] Theinterrupt mask register (IMR) is cleared. [2] The interrupt request input IR7 becomes the lowest priority. [3] The special mask mode is cleared and IRR is assigned as the register for reading status information. [4] When IC4=0, all function bits of ICW4 are set at "0". [5] The edge detection circuit of the interrupt request terminal is cleared. ICW1 makes the assignment of vector addresses A7 to As, assignment as to whether the interrupt request input is to be made in the edge trigger mode or the level trigger mode (LTIM), assignment of CALL address intervals when the 8085A is used as MPU (refer to Table 4.3) (ADD, assignment as to whether the cascade connection to be made (SNGL) and assignment as to whether ICW4 is needed (C4). ICW2 ICW2 assigns high-order vector addresses Ag to Ajs when the 8085A is used as MPU or 8-bit pointers Tg to Ty when the 8086 is used as MPU. TMP82C59A interpretes a command written with Ag input made to "H" level after ICW1 written as ICW2. MPU85-181TOSHIBA TMP82C59A Iw) Ao D7 De Ds Da D3 D2 Dy Do [ o Yar [as | as | 1 [umm aor fsnat] ica | a 1=ICW4 NEEDED 0=NO ICW4 NEEDED 1=SINGLE 0 = CASCADE MODE 1=CALL ADDRESS INTERVAL 4 Q =CALL ADDRESS INTERVAL 8 1 =LEVEL TRIGGER MODE Q =EDGE TRIGGER MODE A7 to As of Low-ORDER VECTGR ADDRESS icwe AG D7 D D5 D4 D3 D2 D1 DO Li PtP tA rr] ato | Ao | As | l l L_,. | Ais-Ag of HIGH-ORDER VECTOR ICW3 ADDRESS or T7-T3 VECTOR ADDRESS (MASTER DEVICE) Ag D7 De Ds Da D3 Dz Dy Do [1 Ts; [se [ss | se | ss [so | ss | 50 | | i | | | | | 1=IR INPUT has a SLAVE. ICW3 {SLAVE DEVICE) 0 =IR INPUT dose not have a Slave Ag D7; D D D4 D3 D2 D1 Do 1 0 0 0 0 6 SLAVE ID 112 icw4 Ao D7 D6 Ds Da D3 D2 Dy Do | 1 | o | o | o [senm| Bur | ms | acoi| nem | 1 = 8086 / 8088 MODE |0 = 80854 MODE 1=AEO!] MODE 0 =NORMAL MODE x NON BUFFERED MODE 1 0 - BUFFERED MODE /SLAVE 1 BUFFERED MODE / MASTER T= SPECIAL FULLY NESTED 7] MODE O= FULLY NESTED MODE 050489 Figure 4.4 ICW Format MPU85-182TOSHIBA TMP82C59A ICW3 [1] This is a command required for cascade connection of plural number of the TMP82C59As. When SNGL=0 in ICW1, the TMP82CS59A interpretes a command written with Ag input made at "H" level after ICW2 as ICWS. Master Mode In the master mode, the TMP82C5Q9A specifies individually as to whether a slave device is added to each interrupt request input. If the 8085A is used as MPU when addition of a slave device is specified, the master device outputs CALL op-code on the data bus upon receipt of the first INTA signal and simultaneously outputs the slave identification code to the cascade line. The master device becomes high impedance at the second and third INTA signals, and the slave devices selected by the identification code outputs vector address on the data bus. When the 8086 is used as MPU, both the master and slave devices become high impedance at the first INTA signal. Simultaneously, the master device outputs the slave identification code to the cascade line. The master device also become high impendance at the second [NTA signal and the selected slave device outputs a pointer on the data bus. When it is specified that no slave device is added, the master device outputs both CALL op-code and vector address as a response to INTA signal and simultaneously outputs "L" signal to 3 cascade lines. This is the same as the identification code of the slave device connected to IRo and therefore, in the case of the interrupt request input without the slave device, added, no slave device can be added to IRg. Further, to specify the master or slave, the SP/EN terminal must be set at "H" level or BUF must be set at 1 and M/S at 1 by ICW4. Slave Made In the slave made, the TMP82C59A specifies the slave identification code. The slave device compares its identification code with the identification code sent from the master device via the cascade line and if they agree, outputs vector addresses on the data bus upon receipt of the second and third INTA signals. Further, to specify the slave mode, the SP/EN terminal must be set at "L" level or BUF at land M/S at 0 by ICW4. MPU85-183TOSHIBA TMP82C59A ICW4 ICW4 is effective only when IC4=iin ICW1. Although ICW4 is effective for assignment of the special fully nested mode (SFNM), assignment of the buffer mode (BUF) and in the buffer mode, this command makes the assignment of the master/slave (M/S), automatic EOI (AEOD and MPU mode. When IC4=0 in ICW1, all function bits of ICW4 are set at "0". (2) OcWw There are 3 kinds of commands: OCW1, OCW2, and OCW3. Any time after ICW is programmed, these command can be programmed to set the TMP82C59A in various operation modes. OCW1 After ICW is set, the TMP82C59A interpretes the operation set command to he OCWlwhen Ag=1. This command is used for setting the content of the interrupt mask register IMR). The OCW1 format is shown in Figure 4.5. OCW2 The TMP82C59A interpretes the operation set command to be OCW2 when Agp=0, Dg=0 and Dg=0. This command is used for outputting EOL. Leg to Lo are effective only in the case of specific EOI and specific rotation. The OCW2 format is shown in Figure 4.5. OCW3 The TMP82C59A interpretes the operation set command to be OQCW3 when Ag=0, Dg=0 and Dg3=1. This command is used for assigning the special mask mode, the poll mode and register for status information readout, that is, assigning IRR or ISR. The OCW3 format is shown in Figure 4.5. MPU85-184TOSHIBA TMP82C59A OocwWw1 Ao Dz Dg Ds D4 D3 Dz D, Do Li | mr | ms [mis | Ma [ms [me [mr [ Mo | | | | | | | 1=INTERRUPT MASK SET QO =INTERRUPT MASK RESET 7 Ao D? Dg Ds Da D3 D> Dy Do Lo fr [| s feo] o | o Jt [ t [| a ||RESeTISRORINTERRUPT PRIORITY IN INTERRUPT REQUEST INPUT o,if2)/3la|s 7 O7;7/0;1/0;/1/0)1 ololilafofoli|i olololofaji]1 fa SL=1 , 0 | | 1 | NONSPECIFIC EOI COMMAND - 0 | 1 | 1 | SPECFIC EO1COMMAND 1 | 0 | 1 | ROTATE ON NON-SPECIFIC EOI COMMAND AUTOMATIC 1 | 9 | 0 | ROTATE IN AUTOMATIC EOI MODE (SET) aoe 0 | 0 | @ | ROTATE IN AUTOMATIC EOI MODE (CLEAR) 1 | 1 | 14 | ROTATEONSPECFIC EOl COMMAND SPECIFIC 1 | 1 | 0 | SET PRIORITY COMMAND OTATION o | 1 | 0 | NO OPERATION ocw3 Ao Dz De Ds Da D3 D2 D, Do | o | o [esmm[smm] o [ 1 [ eT rr | Ris | o | x | NOOPERATION 1 | 0 | READIRR REG SET 1 1 READ ISR REG SET 1=POLL COMMAND 0 =NO POLL COMMAND 0 x NO OPERATION 1 0 RESET SPECIAL MASK MDOE 1 1 SET SPECIAL MASK MODE 050489 Figure 4.5 OCW Format MPU85-185TOSHIBA TMP82C59A 4.6 (1) (2) EXPLANATION OF MODES AND COMMANDS FULLY NESTED MODE Unless the other modes are specified, the TMP82C59A operates in this mode. Under this mode, IRg is the highest priority level and IR7 bocomes the lowest. When INTA signal is input, vector address corresponding to an interrupt and request having the highest priority at the time is output together with CALL op-code on the data bus and furthermore, corresponding ISR bits are kept set till EOI command is input to the TMP82C59A before MPU returns from the service routine or to the final leading edge of INTA pulse in AEOI mode. As long as these ISR bits are kept set, lower priority interrupt requests are ignored. Priority can be changed by OCW2., EOI (END OF INTERRUPT) EOI command is used to reset ISR bits. It is necessary for MPU to output EOI command before returning from the service routine. When AEOL is set in ICW4, ISR bit are automatically reset at the leading edge of the final INTA pulse and it is therfore not necessary to output EOI command. As ISR bits are set in both the master and slave devices when cascade connected, it is necessary to output EOI command to both master device and the slave device corresponding to the master device. EOI command is available in 2 kinds: non-specific EOI and specific EOI commands. When non-specific HOI command is output to the TMP82C59A, ISR bit having the highest priority among ISR bit is reset. However, in the special mask mode it is not possible to reset ISR bit that are masked by IMR by the non-specific EOI command, and ISR bit having the highest priority among the unmasked ISR bits is reset. On the other hand, it is possible to specify ISR bit to be reset by the specific EO] command by a program. EOI command is executed by OCW2. AEOI (AUTOMATIC EO!) MODE In this mode, the non-specific EOI operation is automatically executed at the leading edge of the final INTA signal. Therefore, this mode cannot be used for nested interruptions. In addition, this mode also cannot be used in the slave TMP82C59A. The TMP82C59A can be set in AEOI mode by setting AEOI bit in ICW4 to 1. MPU85-186TOSHIBA TMP82C59A (4) (5) AUTOMATIC ROTATION This mode is effective in the application te give equal priority to the interrupt devices. In this mode, whenever the interrupt service ends, pricrity of each interrupt request is updated so that the serviced interrupt request is set at the lowest pricrity. Priority of interrupt request input IRn (n=0 to 7) that has been serviced becomes the lowest priority level 7 and becomes high in order toward IRp and then, IR7 and next IRy+ 1 become the highest priority level 0. (Rotation Priority) For instance, when the interrupt request [Rq is seviced as shown in Figure 4.6, the priority of each interrupt request input is updated. This mode specifies R=1, 5L=0 and EO[=1 by OCW2 at the end of service. Further, in case of AEOT mode, when R=1, SL=0 and EOI=0 are specified by OCW2, the internal flip-flap is set and the TMP82C59A operates in this mode. If R=0, SL=0 and EOI=0 are specified by OC W2, this mode is cleared. before Rotation (highest priority interrupt request [Rq is being serviced.) se fo fi foti1 ojo] of o | Priority! 7 | 6 [| 5 | 4 [3 | 2 [1] 0] Lowest priority sighest priority After ROTATION (Interrupt request IR4 is being serviced.) se [o[+[o[o[olefol|o| worty[2 [a ]o]l7le]s]#[3] tt Highest Lowest priority priority 050489 Figure 4.6 The Example of Interrupt Priority Transition in Automatic Rotation Mode SPECIFIC ROTATION In the automatic rotation mode, priority of each interrupt request input is updated whenever interrupt requests are serviced. Under this mode it is possible to change priority by specifying an interrupt request input to be set at the lowest priority by a program. Priority is determined according to the ratation priority. In this mode, R and SL are set at 1 by OCW2 and interrupt request input that is to be lowest priority at Lo to Lo is specified. Priority can be changed simultaneously with EOI command or independently regardless of EO] command. MPU85-187TOSHIBA TMP82C59A (6) (7) (8) INTERRUPT MASK Each interrupt request input can be masked individually by the interrupt mask register (IMR). Content of IMR can be specified by OCWI. SPECIAL MASK MODE Normally when an interrupt service routine is being executed, lower priority interrupt requests than the interrupt request being serviced are ignored unless ISR bits are reset by EOI command. This special mode is used for an application in which an interrupt request of lower priority is approved during the service. In this mode, IMR also acts as the mask for ISR. That is, the TMP82C59A processes an interrupt request by assuming that ISR bit and IRR bit corresponding to IMR bit set at "1" have not been set. This mode is set by setting ESMM=1 and SMM 1 by OCW3. Further, when ESMM=1 and SMM=0 are assigned by OC W3, this mode is cleared to the normal mode. The IMR programming is made by OCWL1. POLL COMMAND This mode is used in a state where the internal interrupt enable flip-flop of MPU is disabled and no interrupt is authorized. The service to the device is made by using the poll command. The poll command specifies P=1 in OCW3. The mode becomes now the poll mode. When the read operation (RD=0, CS=0) is made on the TMP82CS59A, the folowing output is made on the data bus: D7 De Ds D4 D3 D2 Dy Do ot t= f= P= T= [we LT wo J Wo~W2 : Binary code of highest priority interrupt request among interrupt requests to the interrupt request inputs. 1 : There isan interrupt request to MPU wheni=1. os0aa9 Figure 4.7 Poll Mode Data Format The TMP82C59A interpretes RD signal as the interrupt acknowledge and when D7=1 is output, sets corresponding ISR bit. This poll mode is valid for a period from WR (P=1 in OCW8) to next RD (CS=0). Further, an interrupt request to be serviced is determined at the time when the mode is made to the poll mode and end even when a new or high priority interrupt request is sent between WR and RD, it is not accepted. MPU85-188TOSHIBA TMP82C59A (9) (10) (11) READING STATUS MPU is capable of reading the contents of 3 registers (IRR, ISR, IMR). When the reading operation is made at Ag=0, the content of IRR or ISR can be read out. Selection of IRR and ISR is made by OC W3. When RR is set at I and RIS at 0, [RR is assigned and when RR and RIS are set at 1, ISR is assigned. This assignment is kept stored without necessity for performing at every reading operation. IMR is read when Ag=1. If the poll mode is specified before the reading operation, the poll command has priority. EDGE TRIGGERED MODE / LEVEL TRIGGERED MODE This mode is selected by LTIM of ICWI. When LTIM is 0, the edge triggered mode is selected and interrupt request is triggered at the leading edge of the interrupt request signal and kept continued by holding "H" level. When LTIM is 1, the level triggered mode is selected and interrupt request is recognized by "H" level of the interrupt request signal. For both modes it is necessary to hold the interrupt request input at "H" level by triggering it till the fast INTA signal is output from MPU. If the interrupt request input is at "L" level when INTA signal is output from MPU, the same operations as those when interrupt requests are generated at IR7 are performed but ISR bits are not set. SPECIAL FULLY NESTED MODE This mode is used to give priority to the interrupt request input fer the slave devices when they are cascade connected. This mode is assigned to the master TMP82C59A when SFNM is 1 in ICW4. With the exception of the following 2 points, this mode is identical to the fully nested mode. {1} Even when an interrupt request from a slave device is being serviced, the master device accepts a higher priority interrupt request from the same slave device without ignoring it. (In the fully nested mode, a higher priority interrupt request from the slave device that is now being serviced is ignored and interrupt requests from a higher priority slave device only are accepted.) [2] When an interrupt request from a slave device is being serviced, it is necessary to check by a software as to whether the interrupt request is only one interrupt request from that slave device. When the service ended, after the non-specific EOI is output to that slave device, MPU has to check whether all ISR bits of that slave device are "0". If they are all "0"", that slave has no interrupt request being serviced and therefore, the non-specific EOI is output to the master device to allow acceptance of interrupt request from the lower priority slave devices. Otherwise, the non-specific EOI must not be output to the master device. MPU85-189TOSHIBA TMP82C59A (12) (13) BUFFERED MODE This mode is to output an enable signal to a data bus buffer from the SP/EN terminal when the data bus buffer is needed for the data bus on a large system. Under this mode, "L" level signal is output to the SP/EN terminal whenever the data bus output of the TMP82C59A is enabled. The assignment of this mode is made by ICW4 simultaneously with the assignment of the master/slave devices. CASCADE MODE The TMP82C594A is able to process interrupt requests up to 64 levels by one master and 8 slave devices. The cascading is shown in Figure 4.8. The master TMP82C59A selects the slave devices by the identification codes fully using 3 cascade lines. INT output of each slave device is connected to the interrupt request inputs of the master device. Further, the identification codes corresponding to respective connections are assigned for the slave devices by ICW3. When interrupt request are generated at the interrupt request inputs of the slave devices and accepted, the master device outputs the identification code to the slave device at the first INTA signal trailing edge to output vector address or pointer. This identification code is kept maintained to the leading edge of the final INTA signal. Normally, the master device outputs "L" level signal to all cascade line. EOI command must be output twice; to the master and second, to the slave corresponding to the interrupt service. Further, an address decoder is required to activate to the CS input of each TMP82C59A. MPU85-190TOSHIBA TMP82C59A 16 ADDRESS BUS CONTROL BUS 8 DATA BUS te 3 8 3 8 }3 ao [e f oS CAD INT Ag INT TS Ag iNT TMP82C59A CAS9 | TMP82C59A CASo cASo TMP82C59A iC SLAVE CAS SLAVE CAS CAS MASTER CAS) be CAS? CAS2 SPIEN 7 6 5 4 3 2 + 0 SPYEN 7 6 5 4 321 0 P/EN M7z7Me Ms MaM3M2M, Mg + | RITE E Tey iT Pitty GND 7 654321 0 GND 7654321 0 Vec 7 5 4 210 f | INTERRUPT REQUEST 050489 Figure 4.8 CASCADING MPU85-191TOSHIBA TMP82C594 5.1. ABSOLUTE MAXIMUM RATINGS SYMBOL ITEM RATING vec VCC Supply Voltage (with respect te VSS (GND)} -0.5to +7V VIN Input Voltage -0.5 to Ver + 0.5V VOUT Output Voltage -0.5to Veco +0.5V PD Power Dissipation 250mW Tsol Soldering Temperature (Soldering Time 1G sec) 260C Tstg Storage Temperature -65C to +150 Topr Operating Temperature -40C ta +85 5.2 DC CHARACTERISTICS 050489 Ta= -40to + 85C, VCC =5 + 10%, Vss (GND) = OV, Unless otherwise noted. SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT VIE Input Low Voltage -0.5 _ 0.8 V VIH Input High Voltage 2.2 _ VCC +0.5 V VOL OGutput Low Voltage IOL=2.2mA _ _ 0.45 V VOH1 Output High Voltage |1OH1=-400pA 2.4 _ _ V VOH2 Output High Voltage |IOH2=-100nA VCC-0.8 - Vv HL Input Leak Current OVSEVINS VCC _ _ +10 pA NWOFL Output Leak Current |0.45VS VINS VCC _ +10 pA VIN =0V _ _ -300 pA ILIR Input Current (IR) VIN = VCC 10 pA 1fO CYCLE = ips Icc1 operating Supply VIH = VCC-0.2V - ~ 5 mA VIH =0.2V Stand-by Supply VIH = VCC-0.2V _ _ cca Current ViL=0.2V 0 BA 050489 5.3. INPUT CAPACITANCE Ta= 25C, VCC =VSS (GND) =0V SYMBOL PARAMETER TEST MIN TYP MAX UNIT CONDITIONS , , CIN INPUT CAPACITANCE fC=1 MHz ~ ~ 10 pF Unmeasured cl/o INPUT / OUTPUT CAPACITANCE pins, OV _ 20 pF 050489 MPU85-192TOSHIBA TMP82C59A 5.4 ACCHARACTERISTICS Ta= 40C to + 85C, VCC = 5V t 10%, VSS (GND) = 0V SYMBOL PARAMETER CONDITION MIN. | TYP. | MAX. | UNIT TAHRL Ao/ CS Setup Time (RD) 0 - _ ns TRHAX | Ag# CS Hold Time (RD) ) - - ns TRLRH | RD Pulse Width 160 - ~ ns TAHWL | Ago/ CS Setup Time (WR} 0 ns TWHAX =| Ag/ CS Hold Time (WR) Q - - ns TWLWH_ | WR Pulse Width 120 ~ ns TBVWH_ | Dg toD7 Setup Time (WR) 120 _ _ ns TWHDX | Do toDy Hold Time (WR) 0 _ _ ns UH Input IR Low Level Pulse width 100 _ _ ns (Edge Trigger Mode) Casecade Setup Time TCVIAL 40 _ ns (Second or Third INTA) TRHRL RD to Next Command 160 - _ ns TWHWL |WR to Next Command 190 _ ns End of Command to next Command TCHCL (Not Same) 250 - _ ns End of INTA sequence to next iINTA sequence TRLDV Valid Data Delay (RD /INTA) Dy to Do - 120 ns TRHDZ | Data Floating (RD /INTA) CL =100pF 10 - 85 | ns TJHIH interrupt Output Delay (IR) INT _ _ 300 ns TIALCV | Valid Cascade Delay (INTA) CL = 100pF _ _ 360 ns TRLEL Enable Active (RD/INTA) CASo to 3 _ _ 100 ns TRHEH | Enable Inactive (RD / NTA) CL =100pF - - 150 | ns TAHDV ; Valid Data Delay (Ag /CS) - _ 200 ns TCVDV Valid Data Delay (CASg to CAS2) i _ 200 ns 050489 AC CHARACTERISTICS TEST CONDITION AC Testing 1/O Waveform AC Testing Load Circuit 2.4 er TEST cK Dun POINT U. 0.8 0.8 0.45 - C_ = 100pF MPU85-193 050489TOSHIBA 6. TIMING WAVEFORMS WRITE OPERATION TMPB2C59A READ AND INTA OPERATION INTA EN Ag 8 *" TRLRH -__ x ITRLEL TRHEH TAHRL TRHAX TRLDV TRHDZ TAHDV Byp~D7 050449 MPU85-194TOSHIBA TMP82C59A INTA SEQUENCE TJHIH IR if TJLJH | INT / INTA f TCVIAL Do~Dy oan --- ye-t{ = TIMING TIALCV TCVIAL x - CASg~CAS2 / / TCVOV OTHER TIMING RD \ J trun INA | 7 050489 MPU85-195TOSHIBA TMP82C59A 7. EXTERNAL DIMENSION VIEW 7.1. 28 pins PRASTIC DIP DIP28-P-600 Unit: mm ) 14.040.2 outs er ort oritao ooo 1 37.0402 w +1 o t z 2 al oO 270289 Note: Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoretical position with respect to NO. 1 and NO. 28 leads. MPU85-196TOSHIBA TMP82C59A4 7.2 28 pins SMALL OUTLINE PACKAGE SOP28-P-450 Unit: mm 18.5402 MIE Monanane (450mi |) ) . fomgyur co rorye | 270289 Note: Package Width and Length do not include Mold Protrusions. Allowable Mold Protrusion is 0.15mm. MPU85-197