1. General description
The 74ALVCH16373 is 16-bit D-type tr ansparent latch fea turing separate D-typ e inputs for
each latch and 3-state outputs for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or
pull-down resistors to hold unused inputs.
One latch enable (LE) input and one output enable (OE) are provided per 8-bit section.
The 74ALVCH16373 consist s of 2 sections of eig ht D-type transparent latches with 3-state
true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition
the latches are transparent, therefore a latch output will change each time its
correspond in g D-in p ut chang es .
When LE is LOW, the latche s store the information that was present at the nDn inputs at a
set-up time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents
of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the OE input does not affect the state of the
latches.
2. Features and benefits
Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standard JESD8-B
CMOS low power consumption
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum nois e an d gr ou n d boun ce
Direct interface with TTL levels
All data inputs have bus hold
Output drive capability 50 transmission lines at 85 C
Current drive 24 mA at VCC = 3.0 V
74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Rev. 6 — 10 July 2012 Product data sheet
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 2 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Temperature range Package
Name Description Version
74ALVCH16373DL 40 C to +85 C SSOP48 plastic shrink small outline package; 48 leads;
body width 7.5 mm SOT370-1
74ALVCH16373DGG 40 Cto+85C TSSOP48 plastic thin shrink small outline package;
48 leads; body width 6.1 mm SOT362-1
Fig 1. Logic symbol
001aam007
1Q0
1Q1
1OE 2OE
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1LE
47
46
48 25
44
43
41
40
38
37
2
3
1
5
6
8
9
11
12
24
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
36
35
33
32
30
29
27
26
13
14
16
17
19
20
22
23
2LE
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 3 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Fig 2. IEC logic symbol
001aam009
47 3D 1Q01D0 2
1
46 1Q11D1 3
44 1Q21D2 5
43 1Q31D3
11EN1OE 48 C11LE 24 2EN2OE 25 C42LE
6
41 1Q41D4 8
40 1Q51D5 9
38 1Q61D6 11
37 1Q71D7 12
36 2Q02D0 13
35 2Q12D1 14
33 2Q22D2 16
32 2Q32D3 17
30 2Q42D4 19
29 2Q52D5 20
27 2Q62D6 22
26 2Q72D7 23
4D 2
Fig 3. Bus hold circuit
to internal circuit
mna705
VCC
data input
Fig 4. Logic diag ram
001aam010
LELE
to 7 other channels
D
LATCH
1
Q1D0
1LE
1OE
1Q0
LELE
to 7 other channels
D
LATCH
9
Q2D0
2LE
2OE
2Q0
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 4 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
Fig 5. Pin configuratio n
74ALVCH16373
1OE 1LE
1Q0 1D0
1Q1 1D1
GND GND
1Q2 1D2
1Q3 1D3
VCC VCC
1Q4 1D4
1Q5 1D5
GND GND
1Q6 1D6
1Q7 1D7
2Q0 2D0
2Q1 2D1
GND GND
2Q2 2D2
2Q3 2D3
VCC VCC
2Q4 2D4
2Q5 2D5
GND GND
2Q6 2D6
2Q7 2D7
2OE 2LE
001aam008
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 5 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
5.2 Pin description
6. Functional description
6.1 Function table
[1] H = HIGH voltage level;
L = LOW voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH LE transition;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH LE transition;
Z = high-impedance OFF-state.
Table 2. Pin description
Symbol Pin Description
1OE, 2OE 1, 24 output enable input (active LOW)
1Q0 to 1Q7 2, 3, 5, 6, 8, 9, 11, 12 data outputs
2Q0 to 2Q7 13, 14, 16, 17, 19, 20, 22, 23 data outputs
GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)
VCC 7, 18, 31, 42 positive supply voltage
1D0 to 1D7 47, 46, 44, 43, 41, 40, 38, 37 data inputs
2D0 to 2D7 36, 35, 33, 32, 30, 29, 27, 26 data inputs
1LE, 2LE 48, 25 latch enable input (active HIGH)
Table 3. Function table[1]
Inputs Internal latches Outputs nQn Operating mode
nOE nLE nDn
L H L L L enable and read register
(transparent mode)
LHHH H
L L l L L latch and read register
(hold mode)
LLhH H
H L l L Z latch register and disable outputs
HLhH Z
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 6 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] Above 55 C the value of Ptot derates linearly with 11.3 mW/K.
[3] Above 55 C the value of Ptot derates linearly with 8 mW/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +4.6 V
IIK input clampi n g cu rre nt VI<0V 50 - mA
VIinput voltage control inputs [1] 0.5 +4.6 V
data inputs [1] 0.5 VCC +0.5 V
IOK output clamping current VO>V
CC or VO<0V - 50 mA
VOoutput voltage [1] 0.5 VCC +0.5 V
IOoutput current VO=0V toV
CC -50 mA
ICC supply cur ren t - 100 mA
IGND ground current 100 - mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation Tamb =40 C to +125 C
SSOP48 package [2] -850mW
TSSOP48 package [3] -600mW
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage maximum speed performance
CL= 30 pF 2.3 - 2.7 V
CL= 50 pF 3.0 - 3.6 V
low voltage applications 1.2 - 3.6 V
VIinput voltage data inputs 0 - VCC V
control inputs 0 - 5.5 V
VOoutput voltage 0 - VCC V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VCC = 2.3 V to 3.0 V 0 - 20 ns/V
VCC = 3.0 V to 3.6 V 0 - 10 ns/V
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 7 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb = 40 C to +85 C
VIH HIGH-level input
voltage VCC = 1.2 V VCC --V
VCC = 1.8 V 0.7VCC 0.9 - V
VCC = 2.3 V to 2.7 V 1.7 1.2 - V
VCC = 2.7 V to 3.6 V 2.0 1.5 - V
VIL LOW-level input
voltage VCC = 1.2 V - - 0 V
VCC = 1.8 V - 0.9 0.2VCC V
VCC = 2.3 V to 2.7 V - 1.2 0.7 V
VCC = 2.7 V to 3.6 V - 1.5 0.8 V
VOH HIGH-level outp ut
voltage VI=V
IH or VIL
IO=100 A; VCC = 1.8 V to 3.6 V VCC 0.2 VCC -V
IO=6mA; V
CC = 1.8 V VCC 0.4 VCC 0.1 - V
IO=6mA; V
CC = 2.3 V VCC 0.3 VCC 0.08 - V
IO=12 mA; VCC = 2.3 V VCC 0.5 VCC 0.17 - V
IO=12 mA; VCC = 2.7 V VCC 0.5 VCC 0.14 - V
IO=18 mA; VCC = 2.3 V VCC 0.6 VCC 0.26 - V
IO=24 mA; VCC = 3.0 V VCC 1.0 VCC 0.28 - V
VOL LOW-level output
voltage VI=V
IH or VIL
IO= 100 A; VCC = 1.8 V to 3.6 V - 0 0.20 V
IO= 6 mA; VCC = 1.8 V - 0.09 0.30 V
IO=6mA; V
CC = 2.3 V - 0.07 0.20 V
IO=12mA; V
CC = 2.3 V - 0.15 0.40 V
IO=12mA; V
CC = 2.7 V - 0.14 0.40 V
IO= 18 mA; VCC = 2.3 V - 0.23 0.60 V
IO=24mA; V
CC = 3.0 V - 0.27 0.55 V
IIinput leakage current VCC = 1.8 V to 3.6 V
control input; VI= 5.5 V or GND - 0.1 5 A
data input; VI=V
CC or GND - 0.1 5 A
IOZ OFF-state output
current VI=V
IH or VIL; VO=V
CC or GND
VCC = 1.8 V to 2.7 V - 0.1 5 A
VCC = 2.7 V to 3.6 V - 0.1 10 A
ILIZ OFF-state input
leakage current VI=V
CC or GND
VCC = 1.8 V to 2.7 V - 0.1 10 A
VCC = 3.6 V - 0.1 15 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC = 1.8 V to 2.7 V - 0.2 40 A
VCC = 2.7 V to 3.6 V - 0.2 40 A
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 8 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
[1] All typical values are measured at Tamb =25C.
[2] Valid for data inputs of bus hold parts only.
10. Dynamic characteristics
ICC additional supply
current VI=V
CC 0.6 V; IO=0A;
VCC = 2.7 V to 3.6 V
per control input - 5 500 A
per data I/O input - 150 750 A
IBHL bus hold LOW current VCC = 2.3 V; VI=0.7V [2] 45 - - A
VCC = 3.0 V; VI=0.8V [2] 75 150 - A
IBHH bus hold HIGH current VCC = 2.3 V; VI=1.7V [2] 45 - - A
VCC = 3.0 V; VI=2.0V [2] 75 175 - A
IBHLO bus hold LOW
overdrive current VCC = 2.7 V [2] 300 - - A
VCC = 3.6 V [2] 450 - - A
IBHHO bus hold HIGH
overdrive current VCC = 2.7 V [2] 300 - - A
VCC = 3.6 V [2] 450 - - A
CIinput capacitance - 5.0 - pF
Table 6. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Table 7. Dynamic characteristics
At recommended operating conditions. Volt ages are referenced to GND (ground = 0 V); test circuit Figure 10.
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb = 40 C to +85 C
tpd propagation delay nDn to nQn; see Figure 6 [2]
VCC = 1.2 V - 8.8 - ns
VCC = 1.8 V 1.5 3.2 5.7 ns
VCC = 2.3 V to 2.7 V [3] 1.0 2.1 3.9 ns
VCC = 2.7 V 1.0 2.3 3.7 ns
VCC = 3.0 V to 3.6 V [4] 1.0 2.1 3.3 ns
nLE to nQn; see Figure 7 [2]
VCC = 1.2 V - 7.4 - ns
VCC = 1.8 V 1.5 3.4 5.9 ns
VCC = 2.3 V to 2.7 V [3] 1.0 2.2 3.9 ns
VCC = 2.7 V 1.0 2.2 3.5 ns
VCC = 3.0 V to 3.6 V [4] 1.0 2.2 3.2 ns
ten enable time nOE to nQn; see Figure 8 [2]
VCC = 1.2 V - 8.9 - ns
VCC = 1.8 V 1.5 4.0 7.3 ns
VCC = 2.3 V to 2.7 V [3] 1.0 2.6 5.2 ns
VCC = 2.7 V 1.0 2.9 4.9 ns
VCC = 3.0 V to 3.6 V [4] 1.0 2.3 4.2 ns
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 9 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
[1] All typical values are measured at Tamb =25C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
[3] Typical values are measured at VCC = 2.5 V.
[4] Typical values are measured at VCC = 3.3 V.
[5] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz; fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = number of inputs switching;
(CLVCC2fo) = sum of the outputs.
tdis disable time nOE to nQn; see Figure 8 [2]
VCC = 1.2 V - 8.9 - ns
VCC = 1.8 V 1.5 3.2 5.6 ns
VCC = 2.3 V to 2.7 V [3] 1.0 2.2 4.1 ns
VCC = 2.7 V 1.0 3.1 4.7 ns
VCC = 3.0 V to 3.6 V [4] 1.0 2.8 4.1 ns
tWpulse width nLE HIGH; see Figure 7
VCC = 1.8 V 3.5 1.0 - ns
VCC = 2.3 V to 2.7 V [3] 3.0 1.0 - ns
VCC = 2.7 V 3.0 1.0 - ns
VCC = 3.0 V to 3.6 V [4] 2.5 1.0 - ns
tsu set-up time nDn to nLE; see Figure 9
VCC = 1.8 V 1.0 0.1 - ns
VCC = 2.3 V to 2.7 V [3] 1.0 0.1 - ns
VCC = 2.7 V 1.0 0.1 - ns
VCC = 3.0 V to 3.6 V [4] 1.0 0.0 - ns
thhold time nDn to nLE; see Figure 9
VCC = 1.8 V 1.2 0.1 - ns
VCC = 2.3 V to 2.7 V [3] 1.5 0.2 - ns
VCC = 2.7 V 1.5 0.4 - ns
VCC = 3.0 V to 3.6 V [4] 1.2 0.2 - ns
CPD power dissipation
capacitance per flip-flop; VI=GNDtoV
CC [5]
outputs enabled - 16 - pF
outputs disabled - 10 - pF
Table 7. Dynamic characteristics …continued
At recommended operating conditions. Volt ages are referenced to GND (ground = 0 V); test circuit Figure 10.
Symbol Parameter Conditions Min Typ[1] Max Unit
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 10 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
11. Waveforms
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig 6. Propagation delay, input (nDn) to data output (nQn)
001aam011
nDn input
nQn output
t
PHL
t
PLH
GND
V
I
V
M
V
M
V
M
V
M
V
OH
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig 7. Propagation delay, latch enable input (nLE) to data output (nQn), and pulse width
001aam012
V
I
t
W
t
PHL
V
M
V
M
V
M
GND
V
OH
V
OL
nLE input
nQn output
t
PLH
V
M
V
M
Measurement points are given in Table 8.
VOL and VOH are typical output levels that occur with the output load.
Fig 8. 3-state enable and disable time s
001aal795
t
PLZ
t
PHZ
outputs
disabled outputs
enabled
V
Y
V
X
outputs
enabled
nQn output
LOW-to-OFF
OFF-to-LOW
nQn output
HIGH-to-OFF
OFF-to-HIGH
nOE input
V
I
V
OL
V
OH
V
CC
V
M
V
M
GND
GND
t
PZL
t
PZH
V
M
V
M
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 11 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Data setup and hold times for input (nDn) to input (nLE)
Table 8. Measurement points
Supply voltage Input Output
VCC VIVMVMVXVY
2.3 V to 2.7 V and < 2.3 V VCC 0.5 VCC 0.5 VCC VOL + 0.15 V VOH 0.15 V
2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH 0.3 V
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 12 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
12. Test information
Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 10. Lo a d circuit for measuring switching time s
VEXT
VCC
VIVO
mna616
DUT
CL
RT
RL
RL
G
Table 9. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLH, tPHL tPLZ, tPZL tPHZ, tPZH
2.3 V to 2.7 V and
< 2.3 V VCC 2.0 ns 30 pF 500 open 2 VCC GND
2.7 V 2.7 V 2.5 ns 50 pF 5 00 open 2 VCC GND
3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open 2 VCC GND
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 13 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
13. Package outline
Fig 11. Package outline SOT370-1 (SSOP48)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 14 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Fig 12. Package outline SOT362-1 (TSSOP48)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 15 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
14. Abbreviations
15. Revision history
Table 10. Abbreviation s
Acronym Description
CMOS Complementary Metal-Oxide Semiconducto r
DUT Device Under Test
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Cha nge notice Supersedes
74ALVCH16373 v.6 20120710 Product data sheet - 74ALVCH16373 v.5
Modifications: •Table 8 corrected (errata).
74ALVCH16373 v.5 20111117 Product data sheet - 74ALVCH16373 v.4
Modifications: •Legal pages updated.
74ALVCH16373 v.4 20100531 Product data sheet - 74ALVCH16373 v.3
74ALVCH16373 v.3 19990920 Product specification - 74ALVCH16373 v.2
74ALVCH16373 v.2 19980629 Product specification - 74ALVCH16373 v.1
74ALVCH16373 v.1 19970321 Product specification - -
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 16 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sh eet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those descri bed in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, bre ach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semi conductors’ aggreg ate and cumulative li ability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and with out
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applicat ions where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s app lications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74ALVCH16373 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 10 July 2012 17 of 18
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is a utomotive qualified,
the product is not suitable for automotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-En glish (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74ALVCH16373
2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 10 July 2012
Document identi fier: 74ALVCH16373
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Functional description . . . . . . . . . . . . . . . . . . . 5
6.1 Function table. . . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
12 Test information. . . . . . . . . . . . . . . . . . . . . . . . 12
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 15
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 15
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
17 Contact information. . . . . . . . . . . . . . . . . . . . . 17
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18