UG-234 EVAL-ADM3053EBZ User Guide
Rev. A | Page 4 of 10
OVERLAPPING STITCHING CAPACITOR
The evaluation board implements an embedded stitching
capacitor structure. A printed circuit board (PCB) embedded
stitching capacitor is created when two metal planes in a PCB
overlap each other and are separated by dielectric material. This
overlap is formed by extending the internal reference planes
from the primary and secondary layers across the area that is
used for creepage on the PCB surface. This capacitor provides a
return path for high frequency common-mode noise currents
across the isolation gap. The overlapping area is 24.9 mm ×
6.3 mm, the distance between overlapping layers is ~0.7 mm;
therefore, the plate capacitor is around 8.9 pF. For full details on
the layout and implementation of embedded stitching capacitors,
see the AN-0971 Application Note, Recommendations for
Control of Radiated Emissions with isoPower Devices.
PCB LAYOUT RECCOMENDATIONS
The ADM3053 evaluation board reduces emissions generated
by the high frequency switching elements used by the isoPower
technology to transfer power through the integrated isolated
dc-to-dc power supply. The layout of the evaluation board is
generated using guidelines similar to those in the AN-1349
Application Note, PCB Implementation Guidelines to Minimize
Radiated Emissions on the ADM2582E/ADM2587E RS-485/
RS-422 Transceivers.
To pass EN55022 Class B on a 4-layer PCB, the following layout
guidelines are recommended:
Best practice decoupling on the PCB per the ADM3053
data sheet.
Place ferrite beads between the PCB trace/plane connections
and the ADM3053 VISOOUT pin (Pin 12) and GND2 pins
(Pin 11 and Pin 13).
Do not connect the VISOOUT pin to a power plane; connect
between the VISOOUT pin and the VISOIN pin using a PCB
trace. Ensure VISOOUT (Pin 12) is connected first through
the L1 ferrite before connecting to VISOIN (Pin 19), as shown
in Figure 4.
An embedded stitching capacitor between the GND1 PCB
plane and GND2 Pin 11 and Pin 13 (inside L2 ferrite)
using internal layers of the PCB planes as highlighted in
the area around U1 in Figure 4 (see the Overlapping
Stitching Capacitor section).
The following additional notes apply to the PCB layout; refer to
the schematic and artwork in Figure 7 to Figure 13.
Ensure that GND2 (Pin 13) is connected to GND2 (Pin 11)
on the inside (device side) of the C7 100 nF capacitor.
Ensure that the C7 capacitor is connected between VISOOUT
(Pin 12) and GND2 (Pin 11) on the device side of the L1
and L2 ferrite beads.
Ensure that GND2 (Pin 16) is connected to the main bus
side PCB ground plane outside of the L2 ferrite, as shown
in Figure 4.
Ensure that there is a keep out area in the PCB layout
around the L1 and L2 ferrites (no PCB planes under or
alongside L1 and L2).
09833-004
Figure 4. Layout Notes for EVAL-ADM3053EBZ
Locate the power delivery circuit in close proximity to the
ADM3053 device, to ensure that the VCC trace is as short as
possible. The EVAL-ADM3053EBZ PCB has a power
delivery circuit located at the bottom of the PCB with a
short trace from the ADP667ARZ regulator output (U3) to
VCC (Pin 8). This layout example minimizes the loop area
in which high frequency current can flow. An increase in
the loop area results in an increase in the emissions levels.
EN55022 RADIATED EMISSIONS TEST RESULTS
The EVAL-ADM3053EBZ evaluation board is tested and
certified to pass EN55022 Class B with a 2.48 dB μV/m margin.
EN55022 certification documents for the EVAL-ADM3053EBZ
evaluation board is available to users upon request from Analog
Devices. Table 2 provides a summary of the results. All EN55022
radiated emissions tests are performed with the PCB schematic
and layout as described in Figure 7 to Figure 13.
The EVAL-ADM3053EBZ evaluation boards are configured and
tested with 5.0 V power supplied to the ADM3053 VIO pin and
VCC pin, with the power supplied from the ADP667ARZ
regulator output. The ADP667ARZ regulator input is supplied
from a standard 9 V battery. Testing is performed with an active
500 kbps clock on the TXD pin supplied by an on-board oscillator
fitted to U2. The ADM3053 CAN bus pins are loaded with a 60 Ω
termination resistor (per a double terminated bus). Measurements
are carried out in an anechoic chamber at 10 m from 30 MHz to
3 GHz. Figure 5 and Figure 6 show the results of the peak
horizontal and vertical scans, and Table 2 shows the tabulated
quasi-peak (QP) results.