Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
Description
The Atmel® | SMART SAM3S8/SD8 series is a member of a family of Flash
microcontrollers based on the high performance 32-bit ARM® Cortex®-M3 RISC
processor. It operates at a maximum speed of 64 MHz and features 512 Kbyte s of
Flash (dual plane on SAM3SD8) and 64 Kbytes of SRAM. The peripheral set
includes a Full Speed USB Device port with embedded transceiver, a High Speed
MCI for SDIO/SD/MMC, an External Bus Interface featuring a Static Memory
Controller providing connection to SRAM, PSRAM, NOR Flash, LCD Module and
NAND Flash, 2(3) USARTs (3 on SAM3SD8C), 2 UART s, 2 TWIs, 3 SPIs, an I 2S,
as well as a PWM timer, two 3-channel general-purpose 16-bit timers (with
stepper motor and quadrature decoder logic support), an RTC, a 12-bit ADC, a
12-bit DAC and an analog comparator.
The SAM3S8/SD8 se ries is ready for capacitive touch thanks to the QTouch®
library, offering an easy way to implement buttons, wheels and sliders.
The SAM3S8/SD8 device is a medium range general purpose microcontroller with
the best ratio in terms of reduced power consumption, processing power and
peripheral set. This enables the SAM3S8/SD8 to sustain a wide range of
applications including consumer, industrial control, and PC peripherals.
It operates from 1.62V to 3.6V and is available in 64- and 100-pin QFP, 64-pin
QFN, and 100-pin BGA packages.
The SAM3S8/SD8 series is the ideal migration path from the SAM7S series for
applications that require more p erformance. The SAM3S8/SD8 series is pin-to-pin
compatible with the SAM7S series.
SAM3S8 / SAM3SD8
Atmel | SMART ARM-based Flash MCU
DATASHEET
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
2
Features
Core
ARM Cortex-M3 revision 2.0 running at up to 64 MHz
Memory Protection Unit (MPU)
Thumb®-2 instruction set
Pin-to-pin compatible with AT91SAM7S legacy products (64-pin versions), SAM3S4/2/1 products
Memories
512 Kbytes Single Plane (SAM3S8) embedded Flash, 128-bit wide access, memory accelerator
512 Kbytes Dual Plane (SAM3SD8) embedded Flash, 128-bit wide access, memory accelerator
64 Kbytes embedded SRAM
16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support
System
Embedded voltage regulator for single supply operation
Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low-power
32.768 kHz for RTC or device clock
RTC with Gregorian and Persian Calendar mode, waveform generation in low-power modes
RTC clock calibration circuitry for 32.768 kHz crystal frequency compensation
High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup.
In-application trimming access for frequency adjustment
Slow Clock Internal RC oscillator as permanent low-power mode device clock
Two PLLs up to 130 MHz for device clock and for USB
Temperature Sensor
Up to 24 peripheral DMA (PDC) channels
Low Power Modes
Sleep and Backup modes, down to < 2 µA in Backup mode
Ultra low-power RTC
Peripherals
USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints. On-Chip Transceiver
Up to 3 USARTs with ISO7816, IrDA®, RS-485, SPI, Manchester and Modem Mode
Two 2-wire UARTs
Up to 2 Two Wire Interface (I2C compatible), 1 SPI, 1 Serial Synchronous Controller (I2S), 1 High Speed
Multimedia Card Interface (SDIO/SD Card/MMC)
Two 3-channel 16-bit Timer Counters with capture, waveform, compare and PWM mode, Quadrature Decoder
Logic and 2-bit Gray Up/Down Counter for Stepper Motor
4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor
Control
32-bit Real-time Timer and RTC with calendar and alarm features
Up to 15-channel, 1Msps ADC with differential input mode and programmable gain stage and auto calibration
One 2-channel 12-bit 1Msps DAC
One Analog Comparator with flexible input selection, Selectable input hysteresis
32-bit Cyclic Redundancy Check Calculation Unit (CRCCU)
Register Write Protection
3
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
I/O
Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-
die Series Resistor Termination
Three 32-bit Parallel Input/Output Controllers, Peripheral DMA assisted Parallel Capture Mode
Packages
100-lead LQFP (14 x 14 mm, pitch 0.5 mm)
100-ball TFBGA (9 x 9 mm, pitch 0.8 mm)
64-lead LQFP (10 x 10 mm, pitch 0.5 mm)
64-lead QFN (9 x 9 mm, pitch 0.5 mm)
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
4
1. Configuration Summary
The SAM3S8/SD8 series devices differ in memory size, package and features. Table 1-1 summarizes the
configurat ion s of th e de vice fam ily.
Notes: 1. Full Modem support on USART1.
2. One channel is reserved for internal temperature sensor.
3. Three TC channels are reserved for internal use.
Table 1-1. Configuration Summary
Feature SAM3S8B SAM3S8C SAM3SD8B SAM3SD8C
Flash 512 Kbytes 512 Kbytes 512 Kbytes 512 Kbytes
SRAM 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
Package LQFP64
QFN64 LQFP100
TFBGA100 LQFP64
QFN64 LQFP100
TFBGA100
Number of PIOs 47 79 47 79
12-bit ADC 11 channel s (2) 16 channels(2) 11 channels(2) 16 channels(2)
12-bit DAC 2 channels 2 channels 2 channels 2 channels
Timer Counter
Channels 6(3) 66
(3) 6
PDC Channels 22 22 24 24
USART/UART 2/2(1) 2/2(1) 2/2(1) 3/2(1)
HSMCI 1 port/4 bits 1 port/4 bits 1 port/4 bits 1 port/4 bits
External Bus Interface 8-bit data,
4 chip selects,
24-bit address 8-bit data,
4 chip selects,
24-bit address
5
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
2. Block Diagram
Figure 2-1. SAM3S8/SD8 100-pin version Block Diagram
PLLA
System Controller
WDT
RTT
Osc 32 kHz
SUPC
RSTC
8 GPBR
3–20 MHz
Osc
POR
RTC
RC 32 kHz
SM
RC Osc
12/8/4 MHz
I/D S
MPU
3-layer AHB Bus Matrix fmax 64 MHz
USART2
(SAM3SD8 only)
ADC Ch.
PLLB
PMC
PIOA / PIOB / PIOC
WKUPx
PIO
External Bus
Interface
D[7:0]
PIODC[7:0]
A[0:23]
A21/NANDALE
A22/NANDCLE
NCS0
NCS1
NCS2
NCS3
NRD
NWE
NANDOE
NANDWE
NWAIT
High Speed MCI
DATRG PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
DAC0
DAC1
Timer Counter 1
Timer Counter 0
TC[3..5]
TC[0..2]
TIOA[3:5]
TIOB[3:5]
TCLK[3:5]
AD[0..14]
RXD1
TXD1
USART1
USART0
UART1
UART0
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
NAND Flash
Logic
TWCK0
TWD0
TWD1
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
RXD2
TXD2
SCK2
RTS2
CTS2
TWCK1
ADVREF
TIOB[0:2]
TCLK[0:2]
PWMH[0:3]
PWML[0:3]
PWMFI0
ADTRG
TIOA[0:2]
TST
PCK0–PCK2
XIN
NRST
VDDCORE
XOUT
RTCOUT0
RTCOUT1
XIN32
XOUT32
ERASE
VDDPLL
VDDIO
12-bit DAC
Temp. Sensor
PWM
12-bit ADC
TWI0
TWI1
SPI
SSC
PIO
Static Memory
Controller
Analog
Comparator
CRC Unit
Peripheral
Bridge
2668
bytes
FIFO
USB 2.0
Full
Speed
Transceiver
NPCS0
PIODCCLK
PIODCEN1
PIODCEN2
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
MCDA[0..3]
MCCDA
MCCK
TF
TK
TD
RD
RK
RF
DDP
DDM
ADVREF
ROM
16 Kbytes
SRAM
64 Kbytes
512 Kbytes Flash
SAM3S8 Single Bank
SAM3SD8 Dual Bank
Flash
Unique
Identifier
TDI
TDO
TMS/SWDIO
TCK/SWCLK
JTAGSEL
Voltage
Regulator
VDDIN
VDDOUT
Cortex M-3 Processor
f
max
64 MHz
In-Circuit Emulator
JTAG & Serial Wire
24-bit
SysTick Counter
NVIC
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
6
Figure 2-2. SAM3S8/SD8 64-pin version Block Diagram
PLLA
System Controller
WDT
RTT
Osc 32 kHz
SUPC
RSTC
8 GPBR
3–20 MHz
Osc
POR
RTC
RC 32 kHz
SM
RC Osc
12/8/4 MHz
I/D S
MPU
3-layer AHB Bus Matrix fmax 64 MHz
ADC Ch.
PLLB
PMC
PIOA / PIOB
PIODC[7:0]
High Speed MCI
DATRG PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
PDC
DAC0
DAC1
Timer Counter 0
TC[0..2]
AD[0..14]
RXD1
TXD1
USART1
USART0
UART1
UART0
SCK1
RTS1
CTS1
DSR1
DTR1
RI1
DCD1
TWCK0
TWD0
TWD1
URXD0
UTXD0
URXD1
UTXD1
RXD0
TXD0
SCK0
RTS0
CTS0
TWCK1
ADVREF
TIOB[0:2]
TCLK[0:2]
PWMH[0:3]
PWML[0:3]
PWMFI0
ADTRG
TIOA[0:2]
TST
PCK0–PCK2
XIN
NRST
VDDCORE
XOUT
RTCOUT0
RTCOUT1
XIN32
XOUT32
ERASE
VDDPLL
VDDIO
12-bit DAC
Temp. Sensor
PWM
12-bit ADC
TWI0
TWI1
SPI
SSC
PIO
Analog
Comparator
CRC Unit
Peripheral
Bridge
2668
bytes
FIFO
USB 2.0
Full
Speed
Transceiver
NPCS0
PIODCCLK
PIODCEN1
PIODCEN2
NPCS1
NPCS2
NPCS3
MISO
MOSI
SPCK
MCDA[0..3]
MCCDA
MCCK
TF
TK
TD
RD
RK
RF
DDP
DDM
ADVREF
ROM
16 Kbytes
SRAM
64 Kbytes
512 Kbytes Flash
SAM3S8 Single Bank
SAM3SD8 Dual Bank
Flash
Unique
Identifier
TDI
TDO
TMS/SWDIO
TCK/SWCLK
JTAGSEL
Voltage
Regulator
VDDIN
VDDOUT
Cortex M-3 Processor
f
max
64 MHz
In-Circuit Emulator
JTAG & Serial Wire
24-bit
SysTick Counter
PIO
PIO
WKUPx
NVIC
7
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
3. Signal Description
Table 3-1 gives details on signal names classified by peripheral.
Table 3-1. Signal Description List
Signal Name Function Type Active
Level Voltage
reference Comments
Power Supplies
VDDIO Peripherals I/O Lines and USB
transceiver Power Supply Power 1.62V to 3.6V
VDDIN Voltage Regulator Input, ADC, DAC
and Analog Comparator Power Supply Power 1.8V to 3.6V(4)
VDDOUT Voltage Regulator Output Power 1.8V Output
VDDPLL Oscill ator and PLL Powe r Supply Power 1.62 V to 1.95V
VDDCORE Power the core, the embedded
memories and the peripherals Power 1.62V to 1.95V
GND Ground Ground
Supply Controller - SUPC
WKUPx Wake Up input pins Input VDDIO
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
Clocks, Osc illators and PLLs
XIN Main Oscillator Input Input
VDDIO
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input
XOUT32 Slow Clock Oscillator Output Output
PCK0–PCK2 Programmable Clock Output Output
Reset State:
- PIO Input
- Internal Pull-up enabled
- Schmitt Trigger enabled(1)
Real Time Clock - RTC
RTCOUT0 Programmable RTC waveform output Output
VDDIO
Reset State:
- PIO Input
- Internal Pull-up disabled
- Schmitt Trigger enabled(1)
RTCOUT1 Programmable RTC waveform output Output
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
8
Serial Wire/JTAG Debug Port - SWJ-DP
TCK/SWCLK Test Clock/Serial Wire Clock Input
VDDIO
Reset State:
- SWJ-DP Mode
- Internal pull-up disabled(5)
- Schmitt Trigger enabled(1)
TDI Test Data In Input
TDO/TRACESWO Test Data Out / Trace Asynchronous
Data Out Output
TMS/SWDIO Test Mode Select /Serial Wire
Input/Output Input / I/O
JTAGSEL JTAG Selection Input High Permanent Internal pull-
down
Flash Memory
ERASE Flash and NVM Configuration Bits
Erase Command Input High VDDIO
Reset State:
- Erase Input
- Internal pull-down
enabled
- Schmitt Trigger enabled(1)
Reset/Test
NRST Synchronous Microcontroller Reset I/O Low VDDIO Permanent Internal pull-up
TST Test Select Input Permanent Internal pull-
down
Universal Asynchronous Receiver Transceiver - UARTx
URXDx UART Receive Data Input
UTXDx UART T ransmit Data Output
PIO Controller - PIOA - PIOB - PIOC
PA0–PA31 Parallel IO Controller A I/O
VDDIO
Reset State:
- PIO or System IOs(2)
- Internal pull-up enabled
- Schmitt Trigger enabled(1)
PB0–PB14 Parallel IO Controller B I/O
PC0–PC31 Parallel IO Controller C I/O
PIO Controller - Parallel Capture Mode
PIODC0–PIODC7 Parallel Capture Mode Data Input
VDDIOPIODCCLK Parallel Capture Mode Clock Input
PIODCEN1–2 Parallel Capture Mode Enable Input
External Bus Interface
D0–D7 Data Bus I/O
A0–A23 Address Bus Output
NWAIT External Wait Signal Input Low
Static Memory Controller - SMC
NCS0–NCS3 Chip Select Lines Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
reference Comments
9
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
NAND Flash Logic
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
High Speed Multimedia Card Interface - HSMCI
MCCK Multimedia Card Clock I/O
MCCDA Multimedia Card Slot A Command I/O
MCDA0–MCDA3 Multimedia Card Slot A Data I/O
Universal Synchronous Asynchronous Receiver Transmitter - USARTx
SCKx USARTx Serial Clock I/O
TXDx USARTx Transmit Data I/O
RXDx USARTx Receive Data Input
RTSx USARTx Request To Send Output
CTSx USARTx Clear To Send Input
DTR1 USAR T1 Data Terminal Ready I/O
DSR1 USART1 Dat a Set Ready Input
DCD1 USAR T1 Data Carrier Detect Output
RI1 USART1 Ring Indicator Input
Synchronous Seri al Controller - SSC
TD SSC T ransmit Data Output
RD SSC Receive Data Input
TK SSC Transmit Clock I/O
RK SSC Receive Clock I/O
TF SSC Transmit Frame Syn c I/O
RF SSC Receive Frame Sync I/O
Timer/Counter - TC
TCLKx TC Channel x External Clock Input Input
TIOAx TC Channel x I/O Line A I/O
TIOBx TC Channel x I/O Line B I/O
Pulse Width Modulation Controller - PWMC
PWMHx PWM Waveform Output High for
channel x Output
PWMLx PWM Waveform Output Low for
channel x Output
Only output in
complementary mode
when dead time insertion is
enabled.
PWMFI0 PWM Fault Input Input
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
reference Comments
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
10
Note: 1. Schmitt Triggers can be disabled through PIO registers.
2. Some PIO lines are shared with System I/Os.
3. Refer to USB Section of the product Electrical Characteristics for informati on on Pull-down value in USB Mode.
4. See “Typical Powering Schematics” Section for restrictions on voltage range of Analog Cells.
5. TDO pin is set in input mode when the Cortex-M3 Core is not in debug mode. Thus the internal pull-up corresponding to this
PIO line must be enabled to avoid current consumption due to floating input.
Serial Peripheral Interface - SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
SPCK SPI Serial Clock I/O
SPI_NPCS0 SPI Peripheral Chip Select 0 I/O Low
SPI_NPCS1–
SPI_NPCS3 SPI Peripheral Chip Select Output Low
Two-Wire Interface - TWI
TWDx TWIx Two-wire Serial Data I/O
TWCKx TWIx Two-wire Serial Clock I/O
Analog
ADVREF ADC, DAC and Analog Comparator
Reference Analog
12-bit Analog-to-Digit al Converter - ADC
AD0–AD14 Analog Inputs Analog, Digital
ADTRG ADC Trigger Input VDDIO
12-bit Digital-to-Analog Converter - DAC
DAC0–DAC1 Analog output Analog, Digital
DACTRG DAC T rigger Input VDDIO
Fast Flash Programming Interf ace - FFPI
PGMEN0–
PGMEN2 Programming Enabling Input VDDIO
PGMM0–PGMM3 Programming Mode Input
VDDIO
PGMD0–PGMD15 Programming Data I/O
PGMRDY Programming Ready Output High
PGMNVALID Data Direction Output Low
PGMNOE Pr og ra mmi n g R ead Input Low
PGMCK Programming Clock Input
PGMNCMD Programming Command Input Low
USB Full Speed Device
DDM USB Full Speed Data - Analog, Digital VDDIO Reset State:
- USB Mode
- Internal Pull-down(3)
DDP USB Full Speed Data +
Table 3-1. Signal Description List (Continued)
Signal Name Function Type Active
Level Voltage
reference Comments
11
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
4. Package and Pinout
SAM3S8/SD8 devices are pin-to-pin compatible with AT91SAM7S legacy products for 64-pin version.
Furthermore, SAM3S8/SD8 products have new functionalities referenced in italic in Table 4-1, Table 4-3.
4.1 SAM3S8C/8DC Package and Pinout
4.1.1 100-Lead LQFP Package Outline
Figure 4-1. Orientation of the 100-lead LQFP Package
4.1.2 100-ball TFBGA Package Outline
The 100-ball TFBGA packag e has a 0.8 mm ball pitch and respects Gre en Standards. The package dime nsions
are 9 x 9 x 1.1 mm. Figure 4-2 shows the orientation of the 100-ball TFBGA package.
Figure 4-2. Orientation of the 100-ball TFBGA Package
125
26
50
5175
76
100
1
3
4
5
6
7
8
9
10
2
ABCDEFGHJK
TOP VIEW
BALL A1
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
12
4.1.3 100-Lead LQFP Pinout
Table 4-1. SAM3S8C/SD8C 100-lead LQFP pino ut
1 ADVREF 26 GND 51 TDI/PB4 76 TDO/TRACESWO/PB5
2 GND 27 VDDIO 52 PA6/PGMNOE 77 JTAGSEL
3 PB0/AD4 28 PA16/PGMD4 53 PA5/PGMRDY 78 PC18
4 PC29/AD13 29 PC7 54 PC28 79 TMS/SWDIO/PB6
5 PB1/AD5 30 PA15/PGMD3 55 PA4/PGMNCMD 80 PC19
6 PC30/AD14 31 PA14/PGMD2 56 VDDCORE 81 PA31
7 PB2/AD6 32 PC6 57 PA27/PGMD15 82 PC20
8 PC31 33 PA13/PGMD1 58 PC8 83 TCK/SWCLK/PB7
9 PB3/AD7 34 PA24/PGMD12 59 PA28 84 PC21
10 VDDIN 35 PC5 60 NRST 85 VDDCORE
11 VDDOUT 36 VDDCORE 61 TST 86 PC22
12 PA17/PGMD5/AD0 37 PC4 62 PC9 87 ERASE/PB12
13 PC26 38 PA25/PGMD13 63 PA29 88 DDM/PB10
14 PA18/PGMD6/AD1 39 PA26/PGMD14 64 PA30 89 DDP/PB11
15 PA21/PGMD9/AD8 40 PC3 65 PC10 90 PC23
16 VDDCORE 41 PA12/PGMD0 66 PA3 91 VDDIO
17 PC27 42 PA11/PGMM3 67 PA2/PGMEN2 92 PC24
18 PA19/PGMD7/AD2 43 PC2 68 PC11 93 PB13/DAC0
19 PC15/AD11 44 PA10/PGMM2 69 VDDIO 94 PC25
20 PA22/PGMD10/AD9 45 GND 70 GND 95 GND
21 PC13/AD10 46 PA9/PGMM1 71 PC14 96 PB8/XOUT
22 PA23/PGMD11 47 PC1 72 PA1/PGMEN1 97 PB9/PGMCK/XIN
23 PC12/AD12 48 PA8/XOUT32/PGMM0 73 PC16 98 VDDIO
24 PA20/PGMD8/AD3 49 PA7/XIN32/PGMNVALID 74 PA0/PGMEN0 99 PB14/DAC1
25 PC0 50 VDDIO 75 PC17 100 VDDPLL
13
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
4.1.4 100-Ball TFBGA Pinout
Table 4-2. SAM3S8C/SD8C 100-ball TFBGA pinout
A1 PB1/AD5 C6 TCK/SWCLK/PB7 F1 PA18/PGMD6/AD1 H6 PC4
A2 PC29 C7 PC16 F2 PC26 H7 PA11/PGMM3
A3 VDDIO C8 PA1/PGMEN1 F3 VDDOUT H8 PC1
A4 PB9/PGMCK/XIN C9 PC17 F4 GND H9 PA6/PGMNOE
A5 PB8/XOUT C10 PA0/PGMEN0 F5 VDDIO H10 TDI/PB4
A6 PB13/DAC0 D1 PB3/AD7 F6 PA27/PGMD15 J1 PC15/AD11
A7 DDP/PB11 D2 PB0/AD4 F7 PC8 J2 PC0
A8 DDM/PB10 D3 PC24 F8 PA28 J3 PA16/PGMD4
A9 TMS/SWDIO/PB6 D4 PC22 F9 TST J4 PC6
A10 JTAGSEL D5 GND F10 PC9 J5 PA24/PGMD12
B1 PC30 D6 GND G1 PA21/PGMD9/AD8 J6 PA25/PGMD13
B2 ADVREF D7 VDDCORE G2 PC27 J7 PA10/PGMM2
B3 GNDANA D8 PA2/PGMEN2 G3 PA15/PGMD3 J8 GND
B4 PB14/DAC1 D9 PC11 G4 VDDCORE J9 VDDCORE
B5 PC21 D10 PC14 G5 VDDCORE J10 VDDIO
B6 PC20 E1 PA17/PGMD5/AD0 G6 PA26/PGMD14 K1 PA22/PGMD10/AD9
B7 PA31 E2 PC31 G7 PA12/PGMD0 K2 PC13/AD10
B8 PC19 E3 VDDIN G8 PC28 K3 PC12/AD12
B9 PC18 E4 GND G9 PA4/PGMNCMD K4 PA20/PGMD8/AD3
B10 TDO/TRACESWO/PB5 E5 GND G10 PA5/PGMRDY K5 PC5
C1 PB2/AD6 E6 NRST H1 PA19/PGMD7/AD2 K6 PC3
C2 VDDPLL E7 PA29/AD13 H2 PA23/PGMD11 K7 PC2
C3 PC25 E8 PA30/AD14 H3 PC7 K8 PA9/PGMM1
C4 PC23 E9 PC10 H4 PA14/PGMD2 K9 PA8/XOUT32/PGMM0
C5 ERASE/PB12 E10 PA3 H5 PA13/PGMD1 K10 PA7/XIN32/PGMNVALID
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
14
4.2 SAM3S8B/D8B Package and Pinout
4.2.1 64-Lead LQFP Package Outline
Figure 4-3. Orientation of the 64-lead LQFP Package
4.2.2 64-lead QFN Package Outline
Figure 4-4. Orientation of the 64-lead QFN Package
33
49
48
32
17
16
1
64
1
16 17 3233
48
4964
T OP VIEW
15
SAM3S8 / SAM3SD8 [DATASHEET]
Atmel-11090B-ATARM-SAM3S8-SAM3SD8-Datasheet_18-Dec-14
4.2.3 64-Lead LQFP and QFN Pinout
Note: The bottom pad of the QFN package must be connected to ground.
Table 4-3. 64-pin SAM3S8B/D8B pinout
1 ADVREF 17 GND 33 TDI/PB4 49 TDO/TRACESWO/PB5
2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL
3 PB0/AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS/SWDIO/PB6
4 PB1/AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31
5 PB2/AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK/SWCLK/PB7
6 PB3/AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE
7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE/PB12
8 VDDOUT 24 VDDCORE 40 TST 56 DDM/PB10
9 PA17/PGMD5/AD0 25 PA25/PGMD13 41 PA29 57 DDP/PB11
10 PA18/PGMD6/AD1 26 PA26/PGMD14 42 PA30 58 VDDIO
11 PA21/PGMD9/AD8 27 PA12/PGMD0 43 PA3 59 PB13/DAC0
12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND
13 PA19/PGMD7/AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT/PB8
14 PA22/PGMD10/AD9 30 PA9/PGMM1 46 GND 62 XIN/PGMCK/PB9
15 PA23/PGMD11 31 PA8/XOUT32/PGMM0 47 PA1/PGMEN1 63 PB14/DAC1
16 PA20/PGMD8/AD3 32 PA7/XIN32/PGMNVALID 48 PA0/PGMEN0 64 VDDPLL
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5. Power Considerations
5.1 Power Supplies
The SAM3S8/SD8 has several types of power supply pins:
VDDCORE pins: Power the core, the embedded memories and the peripherals. Voltage ranges from 1.62V
to 1.95V.
VDDIO pins: Power the Peripherals I/O lines (Input/Output Buffers), USB transceiver, Backup part, 32 kHz
crystal oscillator and oscillator pads. Voltage ranges from 1.62V to 3.6V.
VDDIN pin: V o ltage Regulator Inpu t, ADC, DAC and Analog Comp arator Power Supply. Voltag e ranges from
1.8V to 3.6V.
VDDPLL pin: Powers the PLLA, PLLB, the Fast RC and the 3 to 20 MHz oscillator. Voltage ranges from
1.62V to 1.95V.
5.2 Power-up Considerations
5.2.1 VDDIO Versus VDDCORE
VDDIO must always be higher than or equal to VDDCORE.
VDDIO must reach its minimum operating voltage (1.62 V) before VDDCORE has reached the following
thresholds:
the minimum VT+ of the core power supply brownout detector (1.36 V)
the minimum value of tRST (100 µs)
If VDDCORE rises at the same time as VDDIO, the VDDIO rising slope must be higher than or equal to 5 V/ms.
If VDDCORE is powered by the internal regulator, all power-up considerations are met.
Figure 5-1. VDDCORE and VDDIO Constraints at Startup
Supply (V)
Time (t)
t
RST
VDDIO
VT+
VDDCORE
VDDIO(min)
VDDCORE(min)
Core supply POR output
SLCK
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5.2.2 VDDIO Versus VDDIN
At power-up, VDDIO needs to reac h 0.6 V before VDDIN reaches 1.0 V.
VDDIO voltage needs to be equal to or below (VDDIN voltage + 0.5 V).
5.3 Voltage Regulator
The SAM3S8/SD8 embeds a voltage regulator that is managed by the Supply Controller.
This internal regulator is designed to supply the internal core of SAM3S8/SD8. It features two operating modes:
In Normal mode, the voltage regulator consumes less tha n 700 µA st atic cu rrent a nd dra ws 80 mA of output
current. Internal adaptive biasing adjusts the regulator quiescent curre nt depending on the required load
current. In Wait Mode quiescent current is only 7 µA.
In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT) is driven
internally to GND. The default output voltage is 1.80 V and the start-up time to reach Norm al mod e is less
than 100 µs.
For adequate input and output power supply decoupling/bypassing, refer to Table 41-3 ”1.8V Voltage Regulator
Characteristics” in Section 41. “SAM3S8/SD8 Electrical Characteristics”.
5.4 Typical Powering Schematics
The SAM3S8/SD8 supports a 1.62–3.6 V single supply mode. The internal regulator input is connected to the
source and its output feeds VDDCORE. Figure 5-2 shows the power schematics.
As VDDIN powers the voltage regulator, the ADC, DAC and the analog comparator, when the user does not want
to use the embedded voltag e regulator, it can be disabled by software via the SUPC (note that this is different from
Backup mode).
Figure 5-2. Single Supply
Note: Restrictions
For USB, VDDIO needs to be greater than 3.0 V.
For ADC, VDDIN needs to be greater than 2.0 V.
For DAC, VDDIN needs to be greater than 2.4 V.
For Analog Comparator, VDDIN needs to be greater than 2.0 V.
Main Supply
(1.8–3.6 V) ADC, DAC,
Analog Comp.
USB
Transceivers
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDIO
VDDPLL
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Figure 5-3. Core Externally Supplied
Note: Restrictions
For USB, VDDIO needs to be greater than 3.0 V.
For ADC, VDDIN needs to be greater than 2.0 V.
For DAC, VDDIN needs to be greater than 2.4 V.
For Analog Comparator, VDDIN needs to be greater than 2.0 V.
Figure 5-4 provides an example of the powering scheme when using a backup battery. Since the PIO state is
preserved when in Backup mode , any free PIO line can be used to switch off the external regulator by driving the
PIO line at low level (PIO is input, pull-up enabled after backup reset). External wake- up of the system can be from
a push button or any signal. See Section 5.7 “Wake-up Sources” for further details.
Figure 5-4. Backup Battery
Note: Restrictions
For ADC, VDDIN needs to be greater than 2.0 V.
For DAC, VDDIN needs to be greater than 2.4 V.
For Analog Comparator, VDDIN needs to be greater than 2.0 V.
Main Supply
(1.62–3.6 V)
Can be the
same supply
VDDCORE Supply
(1.62–1.95 V)
ADC, DAC, Analog
Comparator Supply
(2.0–3.6 V)
ADC, DAC,
Analog Comp.
USB
Transceivers
VDDIN
Voltage
Regulator
VDDOUT
VDDCORE
VDDIO
VDDPLL
ADC, DAC,
Analog Comp.
USB
Transceivers
VDDIN
Voltage
Regulator
3.3V
LDO
Backup
Battery +
-
ON/OFF
IN OUT VDDOUT
Main Supply
VDDCORE
VDDIO
VDDPLL
PIOx (Output)
WKUPx
External wakeup signal
Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the
main supply when the system is put inbackup mode.
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5.5 Active Mode
Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal
oscillator or the PLLA. The power m anagement controller can be used to adapt the frequency a nd to disable the
peripheral clocks.
5.6 Low-power Modes
The various low-power modes of the SAM3S8/SD8 are described below.
5.6.1 Backup Mode
The purpose of Backup mode is to achieve the lowest power consumption possible in a system which is
performing periodic wake-ups to perform tasks but not requiring fast startup time (< 0.1 ms). Total current
consumption is 1.5 µA typical.
The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz oscillator (RC or
crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are
off.
Backup mode is based on the Cortex-M3 deep sleep mode with the voltage regulator disabled.
The SAM3S8/SD8 can be awakened from this mode through pins WKUP0–15, the supply monitor (SM), the RTT
or RTC wake-up event.
Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the Cortex-M3 System Control
Register set to 1. (See the power management description in Section 10. “ARM Cortex-M3 Processor”.)
Exit from Backup mode happens if one of the following enable wake up events occurs:
Level transition, configurable debouncing on pins WKUPEN0–15
Supply Monitor alarm
RTC alarm
RTT alarm
5.6.2 Wait Mode
The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a
powered state for a startup time of less than 10 µs. Current Consumption in Wait m ode is typically 20 µA (total
current consumption) if the internal voltage regulator is used or 12 µA if an external regulator is used.
In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and
memories power supplies are still powered. From this mode, a fast start up is available.
This mode is entered via Wait for Event (WFE) instructions with LPM = 1 (Lo w Power Mode bit in PMC Fast
Startup Mode Register (PMC_FSMR)). The Cortex-M3 is able to handle external events or internal events in order
to wake-up the core ( WFE). Th is is do ne by config ur ing th e exte rnal lin es WKUP0–1 5 a s fast star tup wake-up pins
(refer to Section 5.8 “Fast Startup”). RTC or RTT Alarm and USB wake-up events can be used to wake up the CPU
(exit from WFE).
Entering Wait Mode:
Select the 4/8/12 MHz fast RC oscillator as Main Clock
Set the LPM bit in the PMC_FSMR
Execute the Wait-For-Event (WFE) instruction of the processor
Note: Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN bit and the effective
entry in Wait mode. Depe nding on the user application, waiting for MOSCRCEN bit to be cleared is recommended to
ensure that the core will not execute undesired instructions.
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5.6.3 Sleep Mode
The purpose of sleep mode is to optimize p ower consumption of the dev ice versus response time . In this mode,
only the core clock is stoppe d. The peripheral clocks can be e nabled. The current consump tion in this mode is
application dependent.
This mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with LPM = 0 in
PMC_FSMR.
The processor can be awakened from an interrupt if WFI instruction of the Cortex M3 is used, or from an event if
the WFE instruction is used to enter this mode.
5.6.4 Low Power Mode Summary Table
The modes d etailed a bove are the ma in low-powe r modes . Each par t can be set to on or off sepa rately a nd wake
up sources can be individually configured. Table 5-1 shows a summary of the configurations of the low-power
modes.
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Notes: 1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12 MHz fast RC
oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time taken for wake up until the first
instruction is fetched.
2. The external loads on PIOs are not taken into account in the calculation.
3. Supply Monitor current consumption is not included.
4. Total Current consumption.
5. Total current consumption (without using internal voltage regulator) / Total current consumption (using internal voltage regulator).
6. Depends on MCK frequency.
7. In this mode the core is supplied and not clocked but some peripherals can be clocked.
Table 5-1. Low-power Mode Configuration Summary
Mode
SUPC, 32 kHz
Osc., RTC, RTT,
GPBRs, POR
(Backup Region) Regulator
Core
Memory
Peripherals Mode Entry Potential Wake-up
Sources Core at
Wake Up
PIO State
while in Low
Power Mode PIO State
at Wake Up
Consumption
(2)
(3) Wake-up
Time(1)
Backup ON OFF OFF
(Not
powered)
WFE +
SLEEPDEEP bit = 1
WKUP0–15 pins
SM alarm
RTC alarm
RTT alarm
Reset Previous state
saved
PIOA &
PIOB &
PIOC
Inputs with
pull ups
< 2 µA typ(4) < 0.1 ms
Wait ON ON Powered
(Not
clocked)
WFE +
SLEEPDEEP bit = 0
+ LPM bit = 1
Any Event from: Fast
startup through
WKUP0–15 pins
RTC alarm
RTT alarm
USB wake-up
Clocked
back Previous state
saved Unchanged 12 µA/20 µA(5) < 10 µs
Sleep ON ON Powered(7)
(Not
clocked)
WFE or WFI +
SLEEPDEEP bit = 0
+ LPM bit = 0
Entry mode = WFI
Interrupt Only
Entry mode = WFE Any
Enabled Interrupt and/or
Any Event from: Fast
start-up through
WKUP0–15 pins
RTC alarm
RTT alarm
USB wake-up
Clocked
back Previous state
saved Unchanged (6) (6)