[AK4384]
MS0176-E-02 2010/09
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GENERAL DESCRIPTION
The AK4384 offers the perfect mix for cost and performance based audio systems. Using AKM's multi bit
architecture for its modulator the AK4384 delivers a wide dynamic range while preserving linearity for
improved THD+N performance. The AK4384 integrates a combination of SCF and CTF filters increasing
performance for systems with excessive clock jitter. The 24 Bit word length and 192kHz sampling rate
make this part ideal for a wide range of applications including DVD-Audio. The AK4384 is offered in a
space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
SCF with High Tolerance to Clock Jitter
2nd order Analog LPF
Single Ended Output Buffer
Digital de-emphasis for 32k, 44.1k and 48kHz sampling
Soft mute
Digital Attenuator (Linear 256 steps)
I/F format: 24-Bit MSB justified, 24/20/16-Bit LSB justified or I2S
Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -94dB
Dynamic Range: 106dB
Power supply: 4.5 to 5.5V
Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
LRC
K
BIC
K
SDTI
Audio
Data
Interface
MCLK
PDN
ΔΣ
Modulator AOUTL
8X
Interpolator SCF
LPF
AOUT
R
V
DD
V
SS
V
COM
De-emphasis
Control
P/S
µP
Interface
Clock
Divider
SMUTE/CSN
ACKS/CCL
K
DIF0/CDTI
ΔΣ
Modulator
8X
Interpolator
DZF
R
DZFL
SCF
LPF
ATT
ATT
106dB 192kHz 24-Bit 2ch ΔΣ DAC
AK4384
[AK4384]
MS0176-E-02 2010/09
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■ Ordering Guide
AK4384ET -20 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AK4384VT -40 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD4384 Evaluation Board for AK4384
■ Pin Layout
1
MCLK
LRCK
BICK
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
Top
View
2
3
4
5
6
7
8
DZFL
DZFR
VSS
VDD
VCOM
A
OUTL
A
OUTR
P/S
16
15
14
13
12
11
10
9
PDN
SDTI
PIN/FUNCTION
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK I Audio Serial Data Clock Pin
3 SDTI I Audio Serial Data Input Pin
4 LRCK I L/R Clock Pin
5 PDN I Power-Down Mode Pin
When at “L”, the AK4384 is in the power-down mode and is held in reset. The
The AK4384 must be reset once upon power-up.
SMUTE I Soft Mute Pin in parallel mode
“H”: Enable, “L”: Disable
6
CSN I Chip Select Pin in serial mode
ACKS I Auto Setting Mode Pin in parallel mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
7
CCLK I Control Data Clock Pin in serial mode
DIF0 I Audio Data Interface Format Pin in parallel mode 8 CDTI I Control Data Input Pin in serial mode
9 P/S I Parallel/Serial Select Pin (Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
10 AOUTR O Rch Analog Output Pin
11 AOUTL O Lch Analog Output Pin
12 VCOM O Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a
10μF electrolytic cap.
13 VSS - Ground Pin
14 VDD - Power Supply Pin
15 DZFR O Rch Data Zero Input Detect Pin
16 DZFL O Lch Data Zero Input Detect Pin
Note: All input pins except pull-up pin should not be left floating.
[AK4384]
MS0176-E-02 2010/09
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ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter Symbol min max Units
Power Supply VDD -0.3 6.0 V
Input Current (any pins except for supplies) IIN - ±10 mA
Input Voltage VIND -0.3 VDD+0.3 V
AK4384ET Ta -20 85
°C
Ambient Operating Temperature
(Powered applied) AK4384VT Ta -40 85
°C
Storage Temperature Tstg -65 150 °C
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supply VDD 4.5 5.0 5.5 V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
[AK4384]
MS0176-E-02 2010/09
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ANALOG CHARACTERISTICS
(Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; unless otherwise specified)
Parameter min typ max Units
Resolution 24 Bits
Dynamic Characteristics (Note 3)
fs=44.1kHz
BW=20kHz 0dBFS
-60dBFS -94
-42 -84
- dB
dB
fs=96kHz
BW=40kHz 0dBFS
-60dBFS -92
-39 -
- dB
dB
THD+N
fs=192kHz
BW=40kHz 0dBFS
-60dBFS -92
-39 -
- dB
dB
Dynamic Range (-60dBFS with A-weighted) (Note 4) 100 106 dB
S/N (A-weighted) (Note 5) 100 106 dB
Interchannel Isolation (1kHz) 90 100 dB
Interchannel Gain Mismatch 0.2 0.5 dB
DC Accuracy
Gain Drift 100 - ppm/°C
Output Voltage (Note 6) 3.15 3.40 3.65 Vpp
Load Resistance (Note 7) 5 kΩ
Power Supplies
Power Supply Current (VDD)
Normal Operation (PDN = “H”, fs≤96kHz)
Normal Operation (PDN = “H”, fs=192kHz)
Power-Down Mode (PDN = “L”) (Note 8)
17
20
10
27
32
100
mA
mA
µA
Notes: 3. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
4. 100dB at 16bit data.
5. S/N does not depend on input bit length.
6. Full-scale voltage (0dB). Output voltage scales with the voltage of VREF,
AOUT (typ.@0dB) = 3.4Vpp × VDD/5.
7. For AC-load.
8. All digital inputs including clock pins (MCLK, BICK and LRCK) are held VDD or VSS.
[AK4384]
MS0176-E-02 2010/09
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SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD = 4.5 ∼ 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “0”)
Parameter Symbol min typ max Units
Digital filter
Passband ±0.05dB (Note 9)
-6.0dB PB 0
-
22.05 20.0
- kHz
kHz
Stopband (Note 9) SB 24.1 kHz
Passband Ripple PR ± 0.02 dB
Stopband Attenuation SA 54 dB
Group Delay (Note 10) GD - 19.3 - 1/fs
Digital Filter + LPF
Frequency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.1kHz
fs=96kHz
fs=192kHz
FR
FR
FR
-
-
-
± 0.03
± 0.03
± 0.03
-
-
-
dB
dB
dB
Notes: 9. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; VDD = 4.5 ~ 5.5V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)
Parameter Symbol min typ max Units
Digital Filter
Passband ±0.04dB (Note 11)
-3.0dB PB
0
-
18.2 8.1
- kHz
kHz
Stopband (Note 11) SB 39.2 kHz
Passband Ripple PR ± 0.005 dB
Stopband Attenuation SA 72 dB
Group Delay (Note 10) GD - 19.3 - 1/fs
Digital Filter + LPF
Frequency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.kHz
fs=96kHz
fs=192kHz
FR
FR
FR
-
-
-
+0.02/-5
+0.02/-4
+0.02/-5
-
-
-
dB
dB
dB
Note: 11. The passband and stopband frequencies scale with fs.
For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
DC CHARACTERISTICS
(Ta=25°C; VDD=4.5 ∼ 5.5V)
Parameter Symbol min typ max Units
High-Level Input Voltage
Low-Level Input Voltage VIH
VIL 2.2
- -
- -
0.8 V
V
High-Level Output Voltage (Iout=-80µA)
Low-Level Output Voltage (Iout=80µA) VOH
VOL VDD-0.4
- - -
0.4 V
V
Input Leakage Current (Note 12) Iin - - ± 10 µA
Note: 12. P/S pin has internal pull-up device, normally 100kΩ.
[AK4384]
MS0176-E-02 2010/09
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SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=4.5 ∼ 5.5V)
Parameter Symbol min typ max Units
Master Clock Frequency
Duty Cycle fCLK
dCLK 2.048
40 11.2896
36.864
60 MHz
%
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
8
60
120
45
48
96
192
55
kHz
kHz
kHz
%
Audio Interface Timing
BICK Period
Normal Speed Mode
Double/Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK rising to LRCK Edge (Note 13)
LRCK Edge to BICK rising (Note 13)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fs
1/64fs
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
200
80
80
40
40
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width (Note 14)
tPD
150
ns
Notes: 13. BICK rising edge must not occur at the same time as LRCK edge.
14. The AK4384 can be reset by bringing PDN= “L”.
[AK4384]
MS0176-E-02 2010/09
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■ Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Serial Interface Timing
[AK4384]
MS0176-E-02 2010/09
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tCSS
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
C1 C0 R/W A4
tCCKL tCCKH
tCDS tCDH
WRITE Command Input Timing
CSN
VIH
CCLK VIL
VIH
CDTI VIL
VIH
VIL
D3 D2 D1 D0
tCSW
tCSH
WRITE Data Input Timing
tPD
VIL
PDN
Power-down Timing
[AK4384]
MS0176-E-02 2010/09
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OPERATION OVERVIEW
■ System Clock
The external clocks, which are required t o operate the AK4384, are MCLK, LRCK and BICK. The mast er clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma m odulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~4).After exiting reset (PDN = “↑”), the AK4384 is in Auto Setting Mode. In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes
the appropriate frequency (Table 6), it is not necessary to set DFS0 /1.
In parallel mode, the sampling speed can be set by ACKS pin. The internal DFS0 andDFS1 bits are fixed to “0”.
Therefore, when ACKS pin is “L”, the AK4384 operates in Normal Speed Mode. The AK4384 operates in Auto Setting
Mode at ACKS = “H”. In parallel mode, the AK4384 does not support 128fs and 192fs of Double Speed Mode.
All external clocks (M CLK,BICK and LRCK) should always be present whenever t he AK4384 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4384 may draw excess current and m ay fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4384 should be reset by PDN=
“L” after threse clocks are provided. If the external clocks are not present, the AK4384 should be in the power-down
mode (PDN= “L”). After exiting reset at power-up etc., the AK4384 is in the power-down mode until MCLK and LRCK
are input.
DFS1 DFS0 Sampling Rate (fs)
0 0 Normal Speed Mode 8kHz~48kHz Default
0 1 Double Speed Mode 60kHz~96kHz
1 0 Quad Speed Mode 120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK MCLK BICK
fs 256fs 384fs 512fs 768fs 1152fs 64fs
32.0kHz 8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 36.8640MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz N/A 2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz N/A 3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK MCLK BICK
fs 128fs 192fs 256fs 384fs 64fs
88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz
96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
[AK4384]
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LRCK MCLK BICK
fs 128fs 192fs 64fs
176.4kHz 22.5792MHz 33.8688MHz 11.2896MHz
192.0kHz 24.5760MHz 36.8640MHz 12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MCLK Sampling Speed
512fs 768fs Normal
256fs 384fs Double
128fs 192fs Quad
Table 5. Sampling Speed (Auto Setting Mode: Default)
LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
Sampling
Speed
32.0kHz - - - - 16.3840 24.5760 36.8640
44.1kHz - - - - 22.5792 33.8688 -
48.0kHz - - - - 24.5760 36.8640 -
Normal
88.2kHz - - 22.5792 33.8688 - - -
96.0kHz - - 24.5760 36.8640 - - - Double
176.4kHz 22.5792 33.8688 - - - - -
192.0kHz 24.5760 36.8640 - - - - - Quad
Table 6. System Clock Example (Auto Setting Mode)
■ Audio Serial Interface Format
Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-2 as shown in Table 7 can select five serial
data modes. In all modes the serial data is MSB-first, 2’s compliment format and is latched on the rising edge of BICK.
Mode 2 can be used for 16/20 MSB justified formats by zeroing the unused LSBs.
Mode DIF2 DIF1 DIF0 SDTI Format BICK Figure
0 0 0 0 16bit LSB Justified ≥32fs Figure 1
1 0 0 1 20bit LSB Justified ≥40fs Figure 2
2 0 1 0 24bit MSB Justified ≥48fs Figure 3 Default
3 0 1 1 24bit I2S Compatible ≥48fs Figure 4
4 1 0 0 24bit LSB Justified ≥48fs Figure 2
Table 7. Audio Data Formats (Serial mode)
Mode DIF0 SDTI Format BICK Figure
2 0 24bit MSB Justified ≥48fs Figure 3
3 1 24bit I2S Compatible ≥48fs Figure 4
Table 8. Audio Data Formats (Parallel mode)
[AK4384]
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SDTI
BICK
LRCK
SDTI 15 14 6 5 4
BICK
0 1 10 11 12 13 14 15 0 1 10 11 12 13 14 15 0 1
3 2 1 0 15 14
(
32fs
)
(
64fs
)
014
115 16 17 31 0 1 14 15 16 17 31 0 1
15 14 0 15 14 0
Mode 0 Don’t care Don’t care
15:MSB, 0:LSB
Mode 0 15 14 6 5 4 3 2 1 0
Lch Data Rch Data
Figure 1. Mode 0 Timing
SDTI
LRCK
BICK
(
64fs
)
091 10 11 12 31 0 1 9 10 11 12 31 0 1
19 0 19 0
Mode 1 Don’t care Don’t care
19:MSB, 0:LSB
SDTI
Mode 4 23:MSB, 0:LSB
20 19 0 20 19 0
Don’t care Don’t care
22 21 22 21
Lch Data Rch Data
8
23 23
8
Figure 2. Mode 1,4 Timing
LRCK
BICK
(
64fs
)
SDTI
0221 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care23
Lch Data Rch Data
23 30 2222423 30
22 1 0 Don’t care
23 2223
Figure 3. Mode 2 Timing
[AK4384]
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LRCK
BICK
(
64fs
)
SDTI
031 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 10Don’t care
23
Lch Data Rch Data
23 25 322423 25
22 1 0Don’t care23 23
Figure 4. Mode 3 Timing
■ De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs) and is enabled or disabled
with DEM0 and DEM1. In case of double speed and quad speed mode, the digital de-emphasis filter is always off.
DEM1 DEM0 Mode
0 0 44.1kHz
0 1 OFF
Default
1 0 48kHz
1 1 32kHz
Table 9. De-emphasis Filter Control (Normal Speed Mode)
■ Output Volume
The AK4384 includes channel independent digital output volumes (ATT) wi th 256 levels at li near step including MUTE.
These volumes are in front of the DAC and can attenuate the input data from 0dB to –48dB and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition
time of 1 level and all 256 levels is shown in Table 10.
Transition Time
Sampling Speed 1 Level 255 to 0
Normal Speed Mode 4LRCK 1020LRCK
Double Speed Mode 8LRCK 2040LRCK
Quad Speed Mode 16LRCK 4080LRCK
Table 10. ATT Transition Time
[AK4384]
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■ Zero Detection
The AK4384 has channel-independent zeros detect function. When the input data at each channel is continuously zeros
for 8192 LRCK cycles, DZF pin of each channel goes to “H”. DZF pin of each channel imme di ately goes to “L” if input
data of each channel is not zero after going DZF “H”. If RSTN bit is “0”, DZF pins of both channels go to “H”. DZF pin
of both channels go to “L” at 2~3/ fs after RSTN bit returns to “1”. If DZFM bit is set to “1”, DZF pins of both channel s go
to “H” only when the input data at both channels are cont inuously zeros for 8192 LR CK cycles. Zero detect function can
be disabled by DZFE bit. In this case, DZF pins of both channels are always “L”. DZFB bit can invert the polarity of DZF
pin.
■ Soft Mute Operation
Soft mute operation is performed at digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated by
-∞ during ATT_DATA×ATT transition time (Table 10) from the current ATT level. When the SMUTE bit is returned to
“0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during ATT_DATA×ATT
transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is
discontinued and returned to ATT level by the same cycle. The soft mute is effective for changing the signal source
without stopping the signal transmission.
SMUTE bit
A
ttenuation
DZF pin
ATT Level
-∞
A
OUT
8192/fs
GD GD
(1)
(2)
(3)
(4)
(1)
Notes:
(1) ATT_DATA×ATT transition time (Table 10). For exam ple, in Normal Speed Mode, this time is 1020LRCK cycl es
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the att enuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zeros for 8192 LRCK cycles, DZF pin of each channel goes to
“H”. DZF pin immediately goes to “L” if input data are not zero after going DZF “H”.
Figure 5. Soft Mute and Zero Detection
[AK4384]
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■ System Reset
The AK4384 should be reset once by bringing PDN= “L” upon power-up. The AK4384 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4384 is in the
power-down mode until MCLK and LRCK are input.
■ Power-down
The AK4384 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 6 shows an example of the system timing at the power-down and power-up.
Normal Op eration
Internal
State
PDN
Power-down Normal Operation
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, LRCK, BICK
(1) (3)
(6)
DZFL/DZFR
External
MUTE (5)
(3) (1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN = “L”).
Figure 6. Power-down/up Sequence Example
[AK4384]
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■ Reset Function
When RSTN=0, DAC is powered down but the in ternal register values are not initialized. The analog outputs go to
VCOM voltage and DZFL/DZFR pins go to “H”. Figure 7 shows the example of reset by RSTN bit.
Internal
State
RSTN bit
Digital Block Power-down Normal Operat i o n
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1) (3)
DZF
(3) (1)
(2)
Normal Operation
2/fs(5)
Internal
RSTN bit
2~3/fs (6)3~4/fs (6)
Don’t care
(4)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage (VDD/2).
(3) Click noise occurs at t he edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0 ”, and 2~3/fs from RSTN bit “1” to the
internal RSTN “1”.
Figure 7. Reset Sequence Example
[AK4384]
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■ Mode Control Interface
Some function of the AK4384 can be controlled by pins (parallel control mode) shown in Table 11. The serial control
interface is enabled by the P/S pin = “L”. Internal registers may be written by 3-wire µP interface pins, CSN, CCLK and
CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”,
Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). AK4384 latches the data on the
rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN “↑”. The
clock speed of CCLK is 5MHz (max).
Function Parallel mode Serial mode
Double sampling mode at 128/192fs X O
De-emphasis X O
SMUTE O O
Zero Detection X O
16/20/24bit LSB justified format X O
Table 11. . Function list (O: available, X: not available)
PDN = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4384 should be reset
by PDN= “L”. The internal timing circuit is reset by RSTN bit, but the registers are not in itialized.
CDTI
CCLK
CSN
C1
012345678 9 10 11 12 13 14 15
D4D5D6D7A1A2A3A4R/WC0 A0 D0D1D2D3
C1-C0: Chip Address (Fixed to “01”)
R/W: READ/WRITE (Fixed to “1”, Write on ly)
A4-A0: Register Address
D7-D0: Control Data
Figure 8. Control I/F Timing
*The AK4384 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4384 is in the power down mode (PDN = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
■ Register Map
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN
01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE
02H Control 3 0 0 0 INVL INVR DZFB 0 0
03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
Notes:
For addresses from 05H to 1FH, data must not be written.
When PDN pin go es “L”, the registers are initialized to their default valu es.
When RSTN bit g oes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
[AK4384]
MS0176-E-02 2010/09
- 17 -
■ Register Definitions
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
00H Control 1 ACKS 0 0 DIF2 DIF1 DIF0 PW RSTN
default 1 0 0 0 1 0 1 1
RSTN: Internal timing reset control
0: Reset. All registers are not initialized.
1: Normal Operation
When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit.
PW: Power down control
0: Power down. All registers are no t initialized.
1: Normal Operation
DIF2-0: Audio data interface formats (see Table 7)
Initial: “010”, Mode 2
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0
are ignored. When this bit is “0”, DFS1-0 set the sampling speed mode.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
01H Control 2 DZFE DZFM SLOW DFS1 DFS0 DEM1 DEM0 SMUTE
default 0 0 0 0 0 0 1 0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (see Table 9)
Initial: “01”, OFF
DFS1-0: Sampling speed control
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise
occurs.
SLOW: Slow Roll-off Filter Enab le
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
DZFE: Data Zero Detect Enable
0: Disable
1: Enable
Zero detect function can be disabled by DZFE bi t “0”. In this case, the DZF pins of both channels are
always “L”.
[AK4384]
MS0176-E-02 2010/09
- 18 -
DZFM: Data Zero Detect Mode
0: Channel Separated Mode
1: Channel ANDed Mode
If the DZFM bit is set to “1”, the DZF pins of both channels go to “H” only when the input data at bot h
channels are continuously zeros for 8192 LRCK cycles.
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
02H Control 3 0 0 0 INVL INVR DZFB 0 0
default 0 0 0 0 0 0 0 0
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
INVR: Inverting Lch Output Polarity
0: Normal Output
1: Inverted Output
INVL: Inverting Rch Output Polarity
0: Normal Output
1: Inverted Output
Addr Register Name D7 D6 D5 D4 D3 D2 D1 D0
03H Lch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
04H Rch ATT ATT7 ATT6 ATT5 ATT4 ATT3 ATT2 ATT1 ATT0
default 1 1 1 1 1 1 1 1
ATT = 20 log
10 (ATT_DATA / 255) [dB]
00H: Mute
[AK4384]
MS0176-E-02 2010/09
- 19 -
SYSTEM DESIGN
Figure 9 and 10 show the system connection diagram. An evaluation board (AKD4384) is available in order to allow an
easy study on the layout of a surrounding circuit.
MCLK 1
BICK 2
SDTI
3
LRCK
4
PDN
5
SMUTE
6
A
CKS
7
DIF0
8
DZFL 16
DZFR 15
VDD 14
VSS 13
VCOM 12
AOUTL 11
AOUTR 10
P/S 9
Master Clock
Mode
Setting
AK4384
fs
24bit Audi o Data
Reset & Power down
64fs
10u
0.1u +
Rch O u t
Lch Out
Analog Gr ound Digit al G r ound
Lch
MUTE
Rch
MUTE
A
nalog
Supply 5V
+
10u
Figure 9. Typical Connection Diagram (Parallel Mode)
MCLK 1
BICK 2
SDTI
3
LRCK
4
PDN
5
CSN
6
CCLK
7
CDTI
8
DZFL 16
DZFR 15
VDD 14
VSS 13
VCOM 12
AOUTL 11
AOUTR 10
P/S 9
Master Clock
Micro-
controller
AK4384
fs
24bit Audi o Data
Reset & Power down
64fs
10u
0.1u +
Rch O u t
Lch Out
Analog Gr ound Digit al G r ound
Lch
MUTE
Rch
MUTE
A
nalog
Supply 5V
+
10u
Figure 10. Typical Connection Diagram (Serial Mode)
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-up pin should not be left floating.
[AK4384]
MS0176-E-02 2010/09
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1. Grounding and Power Supply Decoupling
VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling
capacitor, especially 0.1μF ceramic capacitor for high frequency should be placed as near to VDD as possible. The
differential Voltage between VDD and VSS pins set the analog output range.
2. Analog Outputs
The analog outputs are single-ended and centered around the VCOM voltage. The output signal range is typically
3.40Vpp (typ@VDD=5V). The phase of the analog outputs can be inverted channel independently by INVL/INVR bits.
The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the delta-sigma
modulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and a negative
full scale for 800000H (@24bit). The ideal output is VCOM voltage for 000000H (@24bit).
DC offsets on analog outputs are elim inated by AC coupling since anal og outputs have DC offsets of VCOM + a few mV.
Figure 11 shows an example of the external LPF with 2Vrms output.
820p
3.3k
1.5k 1.8k
820p
+Vop
2.2k
-Vop
AOUT 22u
fc=111.8kHz, Q=0.714, g=-0.04dB at 40kHz
Analog
Out
10k
Figure 11. External 2nd order LPF Circuit Example (using op-amp with dual power supplies)
[AK4384]
MS0176-E-02 2010/09
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PACKAGE
0-10°
Detail A
Seating Plane 0.10
0.17±0.05
0.22±0.1 0.65
*5.0±0.1 1.1 (max)
A
1 8
9 16
16pin TSSOP (Unit: mm)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13 M
■ Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder(Pb free) plate
[AK4384]
MS0176-E-02 2010/09
- 22 -
MARKING (AK4384VT)
AKM
4384VT
XX YYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4384VT
4) Asahi Kasei Logo
[AK4384]
MS0176-E-02 2010/09
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MARKING (AK4384ET)
AKM
4384ET
XX YYY
5) Pin #1 indication
6) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
7) Marketing Code : 4384ET
8) Asahi Kasei Logo
[AK4384]
MS0176-E-02 2010/09
- 24 -
REVISION HISTORY
Date (YY/MM/DD) Revision Reason Page Contents
02/09/11 00 First Edition
2 Ordering Guide
AK4384ET was added.
06/01/11 01 Spec Addition
23 MARKING
AK4384ET was added.
10/09/28 02 Specification
Change 21 PACKAGE
The package dimension was changed.
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application exampl es of the sem iconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assum es no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any p atent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulati ons of the country of export pertaini ng to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Repr esentative Director of AKM. As used h ere:
Note1) A critical com ponent is one whose failure to function or perform m ay reasonably be expected to resul t,
whether directly or indirectly, i n the loss of the safety or effect iveness of the device or system containi ng it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or ma intenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
