October 1987
Revised January 1999
CD4015BC Dual 4-Bit Static Shift Register
© 1999 Fairchild Semicond uctor Corpor ation DS005948.prf www.fairchildsemi .com
CD4015BC
Dual 4-Bit Static Shift Register
General Descript ion
The CD4015BC contains two identical, 4-stage, serial-
input/parallel-output registers with independent “Data”,
“Clock,” and “Reset” inputs. The logic level present at the
input of each stage is transferred to the output of that stage
at each positive-going clock transition. A logic high on the
“Reset” input resets all four stages covered by that input.
All inputs are protected from static discharge by a series
resistor and diode clamps to VDD and VSS.
Features
■Wide supply voltage range: 3.0V to 18V
■High noise immunity: 0.45 VDD (typ.)
■Low power TTL: Fan out of 2 driving 74L
compatibility: or 1 driving 74LS
■Medium speed operation: 8 MHz (typ.) clock rate
■Fully static design: @VDD − VSS = 10V
Applications
• Serial-input/parallel-output data queueing
• Serial to parallel data conversion
• General purpose register
Ordering Code:
Devices also available in Tape and R eel. Spec if y by appendin g t he suffix let t er “X” to the ordering code.
Connection Diagram
Pin Assignm ents for DIP and SOIC
Truth Table
X = Don't Care Case
Note 1: Level Change
Order Number Package Number Package Description
CD4015BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
CD4015BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
CL
(Note 1) DRQ
1Qn
000Q
n−1
101Q
n−1
X0Q
1Qn(No change)
XX100
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CD4015BC
Logic Diagrams
Terminal N o. 16 = VDD
Terminal N o. 8 = GND
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CD4015BC
Absolute Maximum Ratings(Note 2)
(Note 3) Recommended Operating
Conditions
Note 2: “Absolute Ma ximum Rating s” are tho se value s beyond which the
safety of the device cannot be guaranteed; they are not meant to imply that
the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and “Electrical Characteristics” provide con-
ditions for act ual device ope rat ion.
Note 3: VSS = 0V unles s ot herwise specified.
DC Electrical Characteristics (Note 3)
Note 4: IOH and IOL are tes t ed one ou tp ut at a ti m e.
DC Supply Voltage (VDD)−0.5 to +18 VDC
Input Voltage (VIN)−0.5 to VDD +0.5 VDC
Storage Temperature Range (TS)−65°C to +150°C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (TL)
(Soldering, 10 seconds) 260 °C
DC Supply Voltage (VDD)+3 to +15 VDC
Input Voltage (VIN) 0 to VDD VDC
Operating Temperature Range (TA)−40°C to +85°C
Symbol Parameter Conditions −40°C+25°C+85°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent De vice VDD = 5V, VIN = VDD or VSS 20 0.005 20 150 µA
Current VDD = 10V, VIN = VDD or VSS 40 0.010 40 300 µA
VDD = 15V, VIN = VDD or VSS 80 0.015 80 600 µA
VOL LOW Level VDD = 5V 0.05 0 0.05 0.05 V
Output Voltage VDD = 10V 0.05 0 0.05 0.05 V
VDD = 15V 0.05 0 0.05 0.05 V
VOH HIGH Level VDD = 5V 4.95 4.95 5 4.95 V
Output Voltage VDD = 10V 9.95 9.95 10 9.95 V
VDD = 15V 14.95 14.95 15 14.95 V
VIL LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 2.25 1.5 1.5 V
Input Voltage VDD = 10V, VO = 1.0V or 9.0V 3.0 4.50 3.0 3.0 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 6.75 4.0 4.0 V
VIH HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 2.75 3.5 V
Input Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 5.50 7.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 8.25 11.0 V
IOL LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
Current (Note 4) VDD = 10V, VO = 0.5V 1.3 1.1 2.25 0.9 mA
VDD = 15V, VO = 1.5V 3.6 3.0 8.8 2.4 mA
IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
Current (Note 4) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.25 −0.9 mA
VDD = 15V, VO = 13.5V −3.6 −3.0 −8.8 −2.4 mA
IIN Input Current VDD = 15V, VIN = 0V −0.3 −10−5−0.3 −1.0 µA
VDD = 15V, VIN = 15V 0.3 10−50.3 1.0 µA
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CD4015BC
AC Electrical Characteristics (Note 5)
TA= 25°C, C L= 50 pF, RL= 200k, tr = tf = 20 ns, unless otherwise specified
Note 5: AC Parameters are guaranteed by DC cor related test ing.
Symbol Parameter Conditions Min Typ Max Units
CLOCK OPERATION
tPHL, tPLH Propagation Delay Time VDD = 5V 230 350 ns
VDD = 10V 80 160 ns
VDD = 15V 60 120 ns
tTHL, tTLH Transition Time VDD = 5V 100 200 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
tWL, tWM Minimum Clock VDD = 5V 160 250 ns
Pulse-Width VDD = 10V 60 110 ns
VDD = 15V 50 85 ns
trCL, tfCL Clock Rise and VDD = 5V 15 µs
Fall Time VDD = 10V 15 µs
VDD = 15V 15 µs
tSU Minimum Data VDD = 5V 50 100 µs
Set-Up Time VDD = 10V 20 40 µs
VDD = 15V 15 30 µs
fCL Maximum C lock VDD = 5V 2 3.5 MHz
Frequency VDD = 10V 4.5 8 MHz
VDD = 15V 6 11 MHz
CIN Input Capacitance Clock Input 7.5 10 pF
Other Inputs 5 7.5 pF
RESET OPERATION
tPHL(R) Propagation Delay Time VDD = 5V 200 400 ns
VDD = 10V 100 200 ns
VDD = 15V 80 160 ns
tWH(R) Minimum Reset VDD = 5V 135 250 ns
Pulse Width VDD = 10V 40 80 ns
VDD = 15V 30 60 ns
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CD4015BC
Physical Dimensions in ches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
F airchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
CD4015BC Dual 4-Bit Static Shift Register
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or sys tem s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A criti cal comp onent in any comp onent of a l ife suppor t
device or system whose failure to perform can be rea-
sonably expected to cau se the failure of the li fe support
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Packag e Num be r N16E
