NB3N2304NZMNR4G - ON Semiconductor

October, 2009 − Rev. 6

1Publication Order Number:

NB3N2304NZ/D

NB3N2304NZ

3.3V 1:4 Clock Fanout

Buffer

Description

The NB3N2304NZ is a low skew 1−to 4 clock fanout buffer,

designed for high speed clock distribution such as in PCI−X

applications. The NB3N2304NZ guarantees low output−to−output

skew. Optimal design, layout and processing minimizes skew within a

device and from device−to−device.

The Output Enable (OE) pin forces the outputs LOW when LOW.

Features

•Input/Output Clock Frequency up to 140 MHz

•Low Skew Outputs (100 ps)

•Output Enable

•Operating Range: VDD = 3.0 V to 3.6 V

•Ideal for PCI−X and networking clocks

•Packaged in 8−pin TSSOP, 4.4 mm x 3 mm

•Industrial Temperature Range

•These are Pb−Free Devices*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

TSSOP−8

DT SUFFIX

CASE 948S

MARKING

DIAGRAM*

http://onsemi.com

*For additional marking information, refer to

Application Note AND8002/D.

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

Figure 1. Simplified Logic Diagram

40N

YWW

A = Assembly Location

Y = Year

WW = Work Week

M= Date Code

G= Pb−Free Package

DFN8

MN SUFFIX

CASE 506AA

6O M

NB3N2304NZ

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Figure 2. Block Diagram Figure 3. NB3N2304NZ Package Pinout (Top View)

Logic

Control

VDD

GND

Table 1. PIN DESCRIPTION

Pin #

Name Type Description

1 IN LVCMOS/LVTTL Input Clock Input

2 OE LVCMOS/LVTTL Input Output Enable for the clock outputs. Outputs are enabled when forced HIGH. Outputs

are forced to logic LOW when OE is forced LOW.

3 Q1 LVCMOS/LVTTL Output Clock Output 1

4 GND Power Negative Supply Voltage; Connect to Ground, 0 V

5 Q2 (LV)CMOS/(LV)TTL Input Clock Output 2

6 VDD Power Positive Supply Voltage (3.0 V to 3.6 V)

7 Q3 (LV)CMOS/(LV)TTL Output Clock Output 3

8 Q4 (LV)CMOS/(LV)TTL Input Clock Output 4

−EP Thermal Exposed Pad (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit.

Electrically connect to the most negative supply (GND) or leave unconnected, floating

open.

Table 2. OE, OUTPUT ENABLE FUNCTION TABLE

Inputs Outputs

IN OE

L L L

H L L

L H L

H H H

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Table 3. ATTRIBUTES

Characteristics Value

ESD Protection Human Body Model

Machine Model

> 2kV

> 200 V

Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)

TSSOP−8

DFN−8

Level 3

Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−O @ 0.125 in

Transistor Count 480 Devices

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

Table 4. MAXIMUM RATINGS

Symbol Parameter Condition 1 Condition 2 Rating Unit

VDD Positive Power Supply GND = 0 V VDD + 0.5V V

VIInput Voltage GND – 0.5 v

VI v VDD + 0.5

TAOperating Temperature Range, Industrial w −40 to v +85 °C

Tstg Storage Temperature Range −65 to +150 °C

qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm

500 lfpm

0 lfpm

500 lfpm

TSSOP−8

DFN−8

143

103

129

°C/W

TSOL Wave Solder Pb−Free (Note 2) 265 °C

qJC Thermal Resistance (Junction−to−Case) (Note 2) DFN8 35 to 40 °C/W

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)

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Table 5. DC CHARACTERISTICS VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C

Symbol Characteristic Min Typ Max Unit

IDD Power Supply Current @ 66.66 MHz, Unloaded Outputs 12 25 mA

VOH Output HIGH Voltage − IOH = −24 mA

−IOH = −12 mA

2.0

2.4

VOL Output LOW Voltage −IOL = 24 mA

−IOL = 12 mA

0.8

0.55

VIH Input HIGH Voltage, IN and OE (Note 3) 2.0 V

VIL Input LOW Voltage, IN and OE (Note 3) 0.8 V

IIH Input HIGH Current, VIN = VDD −50 50 mA

IIL Input LOW Current, VIN = 0 V −100 100 mA

CIN Input Capacitance, IN, OE 5 7 pF

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

3. IN input has a threshold voltage of VDD/2.

Table 6. AC CHARACTERISTICS VDD = 3.0 V to 3.6 V, GND = 0 V, TA = −40°C to +85°C (Note 4) (Figure 4)

Symbol Characteristic Min Typ Max Unit

fin Input Clock Frequency DC 140 MHz

tDCskew Duty Cycle Skew = t2 ÷ t1 (Figure 4) Measured at 1.5 V 40 50 60 %

tr/tf Output Rise and Fall Times; 0.8 V to 2.0 V CL = 25 pF

CL = 10 pF

0.9

0.6

1.5 ns

tpd Propagation Delay, IN−to−Qn (Note 5) 2.5 3.5 5 ns

tskew Output−to−Output Skew; (Note 5) 100 ps

tpu Powerup Time for VDD to Reach Minimum Specified Voltage 0.05 50 ms

NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit

board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared

operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit

values are applied individually under normal operating conditions and not valid simultaneously.

4. All outputs loaded equally with CL = 25 pF to GND. Duty cycle out = duty in. A 0.01 mF decoupling capacitor should be connected between

VDD and GND.

5. Measured on rising edges at VDD B 2; all outputs with equal loading.

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Figure 4. Switching Waveforms

Duty Cycle Timing

All Outputs Rise/Fall Time

Output−Output Skew

Input−Output Propagation Delay

1.5 V

2.0 V

0.8 V 0.8 V

2.0 V

1.5 V1.5 V 1.5 V

3.3 V

0 V

OUTPUT

INPUT

OUTPUT

trtf

tSKEW

VDD/2

tpd

ORDERING INFORMATION

Device Package Shipping†

NB3N2304NZDTG TSSOP−8

(Pb−Free)

100 Units / Rail

NB3N2304NZDTR2G TSSOP−8

(Pb−Free)

2500 / Tape & Reel

NB3N2304NZMNR4G* DFN8

(Pb−Free)

1000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*Contact a sales representative.

NB3N2304NZ

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PACKAGE DIMENSIONS

TSSOP−8

CASE 948S−01

ISSUE C

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B4.30 4.50 0.169 0.177

C--- 1.10 --- 0.043

D0.05 0.15 0.002 0.006

F0.50 0.70 0.020 0.028

G0.65 BSC 0.026 BSC

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH

OR GATE BURRS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

____

SEATING

PLANE

PIN 1

DETAIL E

2X L/2

−U−

U0.20 (0.008) TS

0.10 (0.004) V S

0.076 (0.003)

−T−

−V−

−W−

8x REFK

IDENT

K0.19 0.30 0.007 0.012

U0.20 (0.008) T

DETAIL E

0.25 (0.010)

ÉÉÉÉ

ÇÇÇ

JJ1

SECTION N−N

J0.09 0.20 0.004 0.008

K1 0.19 0.25 0.007 0.010

J1 0.09 0.16 0.004 0.006

NB3N2304NZ

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PACKAGE DIMENSIONS

DFN8

CASE 506AA−01

ISSUE D

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994 .

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b APPLIES TO PLATED

TERMINAL AND IS MEASURED BETWEEN

0.25 AND 0.30 MM FROM TERMINAL.

4. COPLANARITY APPLIES TO THE EXPOSED

PAD AS WELL AS THE TERMINALS.

ÇÇÇÇ

C0.10

PIN ONE

2 X

REFERENCE

2 X

TOP VIEW

SIDE VIEW

BOTTOM VIEW

(A3)

C0.10

C0.08

8 X

SEATING

PLANE

e/2 e

8 X

NOTE 3

8 X 0.10 C

0.05 C

ABB

DIM MIN MAX

MILLIMETERS

A0.80 1.00

A1 0.00 0.05

A3 0.20 REF

b0.20 0.30

D2.00 BSC

D2 1.10 1.30

E2.00 BSC

E2 0.70 0.90

e0.50 BSC

K0.20 −−−

L0.25 0.35

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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Phone: 421 33 790 2910

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Phone: 81−3−5773−3850

NB3N2304NZ/D

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