© 2010 Semtech Corporation
POWER MANAGEMENT
1
SC202
3.5MHz, 500mA Step-down
Regulator with Integrated Inductor
Features
Input Voltage — 2.9V to 5.5V
Output Voltage — 0.8V to 3.3V
Output current capability — 500mA
Internal inductor
15 programmable output voltages
High light-load eciency via automatic PSAVE mode
Fast transient response
Temperature range — -40 to +85°C
Oscillator frequency — 3.5MHz
100% duty cycle capability
Quiescent current — 38µA typ
Shutdown current — 0.1µA typ
Internal soft-start
Over-voltage protection
Current limit and short circuit protection
Over-temperature protection
Under-voltage lockout
Floating control pin protection
MLPQ-13 — 2.5 x 3.0 x 1.0 (mm) package
Lead-free and halogen-free
WEEE and RoHS compliant
Applications
Point of load regulation
Smart phones and cellular phones
MP3/personal media players
Personal navigation devices
Digital cameras
Single Li-ion cell or 3 NiMH/NiCd cell devices
Devices with 3.3V or 5V internal power rails
Description
The SC202 is a high eciency 500mA step-down regula-
tor that includes an integrated inductor inside the
package. The input voltage range makes it ideal for
battery operated applications with space limitations. The
SC202 also includes fteen programmable output voltage
settings that can be selected using the four control pins,
eliminating the need for external feedback resistors. The
output voltage can be xed to a single setting or dynami-
cally switched between dierent levels. Pulling all four
control pins low disables the output.
The SC202 operates at a xed 3.5MHz switching frequency
in normal PWM (Pulse-Width Modulation) mode. A vari-
able frequency PSAVE (power-save) mode is used to
optimize eciency at light loads for each output setting.
Built-in hysteresis prevents chattering between the two
modes.
The SC202 provides several protection features to safe-
guard the device under stressed conditions. These
include short circuit protection, over-temperature protec-
tion, under-voltage lockout, and soft-start to control
in-rush current. These features, coupled with the small
2.5 x 3.0 x 1.0 (mm) package, make the SC202 a versatile
device ideal for step-down regulation in products needing
high eciency and a small PCB footprint.
SC202
IN
CTL3
CTL2
CTL1
CTL0
SNS
OUT
GND
V
OUT
0.8V to 3.3V
VIN
2.9V to 5.5V
COUT
10µF
CIN
4.7µF
Control Logic
Lines
LX NC
Typical Application Circuit
June 30, 2010
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
2
Pin Conguration
Marking Information
Ordering Information
Device Package
SC202MLTRT(1)(2) MLPQ-13 — 2.5 x 3.0
SC202EVB Evaluation Board
Notes:
(1) Available in tape and reel only. A reel contains 3,000 devices.
(2) Lead-free packaging only. Device is WEEE and RoHS compliant
and halogen-free.
TOP VIEW
1
2
3
4
5
6
7 8
9
10
11
12
13
LX
LX
LX
OUT
OUT
OUT
GND
IN
CTL2CTL1
CTL0
CTL3
SNS
MLPQ-13; 2.5 x 3.0, 13 LEAD
θJA = 58°C/W
Table 1 – Output Voltage Settings
CTL3 CTL2 CTL1 CTL0 Vout
0 0 0 0 Shutdown
0 0 0 1 0.80
0 0 1 0 1.00
0 0 1 1 1.20
0 1 0 0 1.40
0 1 0 1 1.50
0 1 1 0 1.60
0 1 1 1 1.80
1 0 0 0 1.85
1 0 0 1 1.90
1 0 1 0 2.00
1 0 1 1 2.20
1 1 0 0 2.50
1 1 0 1 2.80
1 1 1 0 3.00
1 1 1 1 3.30
yyww = Date Code
xxxx = Semtech Lot Number
202
yyww
xxxx
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
3
Exceeding the above specications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specied in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114-B.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB per JESD51 standards.
Absolute Maximum Ratings
IN (V) ...................................... -0.3 to +6.0
LX Voltage (V) ............................-1.0 to VIN + 0.5
Other Pins (V) ............................-0.3 to VIN + 0.3
Output Short Circuit to GND . . . . . . . . . . . . . . . . Continuous
ESD Protection Level(1) (kV) ............................ 2
Recommended Operating Conditions
Input Voltage Range (V) . . . . . . . . . . . . . . . . . . . . . +2.9 to +5.5
Operating Temperature Range (°C) . . . . . . . . . . -40 to +85
Thermal Information
Thermal Resistance, Junction to Ambient(2) (°C/W) . . . . . 58
Junction Temperature Range (°C) . . . . . . . . . . . -40 to +150
Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150
Unless otherwise specied: VIN= 3.6V, CIN= 4.7µF, COUT=10µF, VOUT=1.8V, TJ(MAX)=125°C, TA= -40 to +85 °C. Typical values are TA=+25 °C
Parameter Symbol Condition Min Typ Max Units
Output Voltage Range VOUT 0.8 3.3 (1) V
Output Voltage Tolerance VOUT_TOL
IOUT = 200mA -2.0 2.0
%
PSAVE mode 1.5
Line Regulation ΔVLINEREG 2.9 ≤ VIN ≤ 5.5V, IOUT = 200mA 0.3 %/V
Load Regulation ΔVLOADREG 200mA ≤ IOUT ≤ 500mA -1 %/A
Output Current Capability IOUT 500 mA
Current Limit Threshold ILIMIT 800 1300 mA
Foldback Current Limit IFB_LIM ILOAD > ILIMIT 150 mA
Under-Voltage Lockout VUVLO
Rising VIN 2.9 V
Hysteresis 200 mV
Quiescent Current IQNo switching, IOUT = 0mA 38 60 µA
Shutdown Current ISD VCTL 0-3= 0V 0.1 1.0 µA
Output Leakage Current IOUT Into OUT pin 0.1 1.0 µA
High Side Switch Resistance(2) RDSON_P IOUT= 100mA 250
mΩ
Low Side Switch Resistance(3) RDSON_N IOUT= 100mA 350
Electrical Characteristics
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
4
Parameter Symbol Condition Min Typ Max Units
Switching Frequency fSW 2.8 3.5 4.2 MHz
Soft-Start tSS VOUT = 90% of nal value 100 500 µs
Thermal Shutdown TOT Rising temperature 160 °C
Thermal Shutdown Hysteresis THYST 20 °C
Logic Inputs - CTL0, CTL1, CTL2, and CTL3
Input High Voltage VIH 1.2 V
Input Low Voltage VIL 0.4 V
Input High Current IIH VCTL 0-3= VIN -2.0 5.0 µA
Input Low Current IIL VCTL 0-3= GND -2.0 2.0 µA
Notes
(1) Maximum output voltage is limited to VIN if the input is less than 3.3V.
(2) Measured from IN to LX.
(3) Measured from LX to GND.
Electrical Characteristics (continued)
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
5
Typical Characteristics
Eciency vs. IOUT (TA = -40°C)
Load Current (mA)
Efficiency (%)
V
OUT
= 1V, 1.8V, 2.8V, and 3.3V
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
3.3V
2.8V
1.8V
1V
Eciency vs. IOUT (TA = 25°C)
Load Current (mA)
Efficiency (%)
V
OUT
= 1V, 1.8V, 2.8V, and 3.3V
0
10
20
30
40
50
60
70
80
90
100
0.1 110 100 1000
3.3V
2.8V
1.8V
1V
Eciency vs. IOUT (TA = 85°C)
Load Current (mA)
Efficiency (%)
V
OUT
= 1V, 1.8V, 2.8V, and 3.3V
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
1V
3.3V
2.8V
1.8V
V
OUT
(V)
Efficiency (%)
4.2V
5.0V
65
70
75
80
85
90
95
100
0.5 1.0 1.5 2.0 2.5 3.0 3.5
3.6V
I
OUT
= 200mA, V
IN
= 3.6V, 4.2V, and 5.0V
Efficiency (%)
4.2V
5.0V
65
70
75
80
85
90
95
100
0.5 1.0 1.5 2.0 2.5 3.0 3.5
V
OUT
(V)
3.6V
I
OUT
= 200mA, V
IN
= 3.6V, 4.2V, and 5.0V
VOUT (V)
Efficiency (%)
4.2V
65
70
75
80
85
90
95
100
0.5 1.0 1.5 2.0 2.5 3.0 3.5
5.0V
3.6V
IOUT = 200mA, VIN = 3.6V, 4.2V, and 5.0V
VIN = 4.0V for VOUT = 3.3V, VIN = 3.6V for all others. CIN = 4.7µF, COUT = 10µF, TA = 25°C unless otherwise noted.
Eciency vs. VOUT (TA = -40°C)
Eciency vs. VOUT (TA = 25°C)
Eciency vs. VOUT (TA = 85°C)
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
6
VIN = 4.0V for VOUT = 3.3V, VIN = 3.6V for all others. CIN = 4.7µF, COUT = 10µF, TA = 25°C unless otherwise noted.
Frequency vs. Temperature
Temperature (°C)
Frequency (MHz)
1.0V
3.3V
3
3.1
3.2
3.3
3.4
3.5
3.6
-40 -20 0 20 40 60 80 100
2.8V
1.8V
VOUT = 1V, 1.8V, 2.8V, and 3.3V
Load Regulation (VOUT = 1.8V)
Load Current (mA)
Output Voltage (V)
1.77
1.78
1.79
1.80
1.81
1.82
1.83
0 100 200 300 400 500
25°C
85°C
-40°C
-40
°C
VIN (V)
VOUT (V)
IOUT = 200mA
25°C
85°C
1.77
1.78
1.79
1.80
1.81
1.82
1.83
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Line Regulation (VOUT =1.8V)
V
IN
(V)
Efficiency (%)
I
OUT
= 200mA
-40°C
25°C
85°C
76
79
82
85
88
91
2.5 3.0 3.5 4.0 4.5 5.0 5.5
Eciency vs. VIN (VOUT =1.8V)
Typical Characteristics (continued)
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
7
Typical Characteristics (continued)
Light Load Switching — VOUT = 1.8V
Time (400ns/div)
VLX (5V/div)
VOUT (50mV/div)
ILX (200mA/div)
Light Load Switching — VOUT = 1.0V
Time (400ns/div)
VLX (5V/div)
VOUT (50mV/div)
ILX (200mA/div)
Light Load Switching — VOUT = 2.8V
Time (400ns/div)
VLX (5V/div)
VOUT (50mV/div)
ILX (200mA/div)
Light Load Switching — VOUT = 3.3V
Time (400ns/div)
VLX (5V/div)
VOUT (50mV/div)
ILX (200mA/div)
Heavy Load Switching — VOUT = 1.0V
Time (200ns/div)
ILX (200mA/div)
VOUT (50mV/div)
VLX (5V/div)
Heavy Load Switching — VOUT = 1.8V
Time (200ns/div)
ILX (200mA/div)
VOUT (50mV/div)
VLX (5V/div)
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
8
Typical Characteristics (continued)
Heavy Load Switching — VOUT = 2.8V
Time (200ns/div)
ILX (200mA/div)
VOUT (50mV/div)
VLX (5V/div)
Heavy Load Switching — VOUT = 3.3V
Time (200ns/div)
ILX (200mA/div)
VOUT (50mV/div)
VLX (5V/div)
Heavy Load Soft-start
Time (40μs/div)
VOUT (1.0V/div)
IIN (200mA/div)
ILX (500mA/div)
Light Load Soft-start
Time (40μs/div)
Vout (1.0V/div)
IIN (200mA/div)
ILX (500mA/div)
Load Transient Response — 25 to 90mA
Time (20μs/div)
ILX (200mA/div)
VOUT (50mV/div)
ILOAD (50mA/div)
Load Transient Response — 25 to 500mA
Time (20μs/div)
ILX (500mA/div)
VOUT (100mV/div)
ILOAD (500mA/div)
ILOAD = 10mA
ILOAD = 500mA
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
9
Typical Characteristics (continued)
Load Transient Response — 200 to 500mA
Time (20μs/div)
ILX (500mA/div)
VOUT (100mV/div)
ILOAD (500mA/div)
Line Transient Response — PWM
Time (400μs/div)
ILX (200mA/div)
VOUT (50mV/div)
VIN (500mV/div)
VID Transient Response — PWM
Time (20μs/div)
VCTL2 (2V/div)
VOUT (500mV/div)
ILX (500mA/div)
1.2V to 1.8V transition
VID Transient Response — PSAVE
Time (20μs/div)
VCTL2 (2V/div)
VOUT (500mV/div)
ILX (500mA/div)
1.2V to 1.8V transition
Line Transient Response — PSAVE
Time (400μs/div)
ILX (200mA/div)
VOUT (50mV/div)
VIN (500mV/div)
Shutdown Transient Response
Time (20μs/div)
ILX (500mA/div)
VOUT (2V/div)
VCTL3-0 (2V/div)
4.0V to 3.5V using Li-Ion battery 4.0V to 3.5V using Li-Ion battery
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
10
Pin Descriptions
Pin Pin Name Pin Function
1, 2, 3 LX Switching node sense pin — for test purposes only.
4 SNS Output sense pin — connect to output capacitor for proper sensing of output voltage.
5 CTL3 Control bit 3 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at
reset that is removed when CTL3 is pulled above the logic high threshold.
6 CTL0 Control bit 0 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at
reset that is removed when CTL0 is pulled above the logic high threshold.
7 CTL1 Control bit 1 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at
reset that is removed when CTL1 is pulled above the logic high threshold.
8 CTL2Control bit 2 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at
reset that is removed when CTL2 is pulled above the logic high threshold.
9 IN Input power supply pin — connect a bypass capacitor from this pin to GND.
10 GND Ground reference and power ground for the SC202.
11, 12, 13 OUT Regulator output pin — connect a 10µF ceramic capacitor to this pin for proper ltering.
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
11
Block Diagram
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
12
General Description
The SC202 is a synchronous step-down PWM (Pulse Width
Modulated) DC-DC regulator utilizing a 3.5MHz xed-fre-
quency voltage-mode architecture and an internal 1µH
inductor. The device is designed to operate in xed-fre-
quency PWM mode and enter PSAVE (power save) mode
utilizing pulse frequency modulation under light load
conditions to maximize eciency. Two capacitors are the
only external components required — one for input
decoupling and one for output filtering. The output
voltage is programmable, eliminating the need for exter-
nal programming resistors. Loop compensation is also
internal, eliminating the need for external components to
control stability.
Programmable Output Voltage
The SC202 has 15 xed output voltage levels which can be
individually selected by programming the CTL control
pins (CTL3-0 — see Table 1 on page 2 for settings). The
device is disabled whenever all four CTL pins are pulled
low and enabled whenever at least one of the CTL pins is
pulled high. This conguration eliminates the need for a
dedicated enable pin. Each CTL pin is internally pulled
down via 1MΩ if VIN is below 1.5V or if the voltage on the
control pin is below the input high voltage. This ensures
that the output is disabled when power is applied if there
are no inputs to the CTL pins. Each weak pull-down is dis-
abled whenever its pin is pulled high and remains disabled
until all CTL pins are pulled low.
The output voltage can be set using dierent approaches.
If a static output voltage is required, the CTL pins can be
tied to either IN or GND to set the desired voltage when-
ever power is applied at IN. If enable control is required,
each CTL pin can be tied to either GND or to a micropro-
cessor I/O line to create the desired control code whenever
the control signal is forced high. This approach is equiva-
lent to using the CTL pins collectively as a single enable
pin. A third option is to connect each of the four CTL pins
to individual microprocessor I/O lines. Any of the 15
output voltages can be programmed using this approach.
If only two output voltages are needed, the CTL pins can
be combined in a way that will reduce the number of I/O
lines to 1, 2, or 3, depending on the control code for each
desired voltage. Other CTL pins could be hard-wired to
GND or IN. This option allows dynamic voltage adjust-
ment for systems that reduce the supply voltage when
entering sleep states. Note that applying all zeros to the
CTL pins when changing the output voltage will tempo-
rarily disable the device, so it is important to avoid this
combination when dynamically changing levels.
Adjustable Output Voltage Selection
If an output voltage other than one of the 15 program-
mable settings is needed, an external resistor divider
network can be added to the SC202 to adjust the output
voltage setting. This network scales the output based on
the resistor ratio and the programmed output setting.
The resistor values can be determined using the
equation
1FBSNS
2FB
2FB1FB
SETOUT RI
R
RR
VV u
»
¼
º
«
¬
ª
u
where VOUT is the desired output voltage, VSET is the voltage
setting selected by the CTL pins, RFB1 is the resistor
between the output capacitor and the SNS pin, RFB2 is the
resistor between the SNS pin and ground, and ISNS is the
leakage current into the SNS pin during normal opera-
tion. The current into the SNS pin is typically 1µA, so the
last term of the equation can be neglected if the current
through RFB2 is much larger than 1µA. Selecting a resistor
value of 10kΩ or lower will simplify the design. If ISNS is
neglected and RFB2 is xed, RFB1 can be determined using
the equation
SET
SETOUT
2FB1FB V
VV
RR
u
Inserting resistance in the feedback loop will adversely
aect the system’s transient performance if feed-forward
capacitance is not included in the circuit. The circuit in
Figure 1 illustrates how the resistor divider and feed-
forward capacitor can be added to the SC202 schematic.
The value of feed-forward capacitance needed can be
determined using the equation
5.0VVVR
5.0VV
104C
SETSETOUT1FB
2
OUTSET
6
FF
uu
Applications Information
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
13
V
OUT
SC202
IN
CTL3
CTL2
CTL1
CTL0
SNS
OUT
GND
V
IN
C
OUT
C
IN
Enable
C
FF
R
FB1
R
FB2
Figure 1 – Application Circuit with External Resistors
To simplify the design, it is recommended to program the
output setting to 1.0V, use resistor values smaller than
10kΩ, and include a feed-forward capacitance calculated
with the previous equation. If the output voltage is set to
1.0V, the previous equation reduces to
1VR
5.0V
108C
OUT1FB
2
OUT
6
FF
uu
Example:
An output voltage of 1.3V is desired, but this is not a pro-
grammable option. What external component values for
Figure 1 are needed?
Solution: To keep the circuit simple, set RFB2 to 10kΩ so
current into the SNS pin can be neglected and set the
CTL3-0 pins to 0010 (1.0V setting). The necessary compo-
nent values for this situation are
:
u k3
V
VV
RR
SET
SETOUT
2FB1FB
nF69.5
1VR
5.0V
108C
OUT1FB
2
OUT
6
FF
uu
PWM Operation
Normal PWM operation occurs when the output load
current exceeds the PSAVE threshold. In this mode, the
PMOS high side switch is activated with the duty cycle
required to produce the output voltage programmed by
the CTL pins. An internal synchronous NMOS rectifier
eliminates the need for an external Schottky diode on the
LX pin. The duty cycle (percentage of time PMOS is
active) increases as VIN decreases to maintain output
voltage regulation. As the input voltage approaches the
programmed output voltage, the duty cycle approaches
100% (PMOS always on) and the device enters a pass-
through mode until the input voltage increases or the
load decreases enough to allow PWM switching to
resume.
Power Save Mode Operation
When the load current decreases below the PSAVE
threshold, PWM switching stops and the device auto-
matically enters PSAVE mode. This threshold varies
depending on the input voltage and output voltage
setting, optimizing eciency for all possible load currents
in PWM or PSAVE mode. While in PSAVE mode, output
voltage regulation is controlled by a series of switching
bursts. During a burst, the inductor current is limited to a
peak value which controls the on-time of the PMOS
switch. After reaching this peak, the PMOS switch is dis-
abled and the inductor current decreases to near 0mA.
Switching bursts continue until the output voltage climbs
to VOUT +2.5% or until the PSAVE current limit is reached.
Switching is then stopped to eliminate switching losses,
enhancing overall eciency. Switching resumes when
the output voltage reaches the lower threshold of VOUT
and continues until the upper threshold again is reached.
Note that the output voltage is regulated hysteretically
while in PSAVE mode between VOUT and VOUT + 2.5%. The
period and duty cycle while in PSAVE mode are solely
determined by VIN and VOUT until PWM mode resumes. This
can result in the switching frequency being much lower
than the PWM mode frequency.
If the output load current increases enough to cause VOUT
to decrease below the PSAVE exit threshold (VOUT -2%),
the device automatically exits PSAVE and operates in
continuous PWM mode. Note that the PSAVE high and
low threshold levels are both set at or above VOUT to mini-
mize undershoot when the SC202 exits PSAVE. Figure 2
illustrates the transitions from PWM mode to PSAVE
mode and back to PWM mode.
Applications Information (continued)
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
14
V
OUT
-2%
V
OUT
V
OUT
+2.5%
Load
Demand
(I
OUT
)
BURST
OFF
V
LX
Time
PWM Mode at
Medium/High
Load
PSAVE Mode at
Light Load
PWM Mode at
Medium/High
Load
PSAVE
EXIT
Figure 2 — Transitions Between PWM and PSAVE Modes
Protection Features
The SC202 provides the following protection features:
Soft-Start Operation
Over-Voltage Protection
Current Limit
Thermal Shutdown
Under-Voltage Lockout
Soft-Start
The soft-start sequence is activated after a transition from
an all zeros CTL code to a non-zero CTL code enables the
device. At start-up, the PMOS current limit is stepped
through four levels: 25%, 40%, 60%, and 100%. Each step
is maintained for 60μs following an internal reference start
up of 20μs, resulting in a total nominal start-up period of
260μs. If VOUT reaches 90% of the target within the rst 2
steps, the device continues in PSAVE mode at the end of
soft-start; otherwise, it goes into PWM mode. Note the
VOUT ripple in PSAVE mode can be larger than the ripple in
PWM mode.
•
•
•
•
•
Applications Information (continued)
Over-Voltage Protection
Over-voltage protection ensures the output voltage does
not rise to a level that could damage its load. When VOUT
exceeds the regulation voltage by 15%, the PWM drive is
disabled. Switching does not resume until VOUT has fallen
below the regulation voltage by 2%.
Current Limit
The SC202 switching stage is protected by a current limit
function. If the output load exceeds the PMOS current
limit for 32 consecutive switching cycles, the device enters
fold-back current limit mode and the output current is
limited to approximately 150mA. Under these conditions,
the output voltage will be the product of IFB-LIM and the load
resistance. The load must fall below IFB-LIM for the device to
exit fold-back current limit mode. This function makes the
device capable of sustaining an indenite short circuit on
its output under fault conditions.
Thermal Shutdown
The SC202 has a thermal shutdown feature to protect the
device if the junction temperature exceeds 160°C. During
thermal shutdown, the PMOS and NMOS switches are
both disabled, tri-stating the LX output. When the junc-
tion temperature drops by the hysteresis value (20°C), the
device goes through the soft-start process and resumes
normal operation.
Under-Voltage Lockout
UVLO (Under-Voltage Lockout) activates when the supply
voltage drops below the falling UVLO threshold. This pre-
vents the device from entering an ambiguous state in
which regulation cannot be maintained. Hysteresis of
approximately 200mV is included to prevent chattering
near the threshold.
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
15
COUT Selection
The internal voltage loop compensation in the SC202
limits the minimum output capacitor value to 10μF. This
is due to its inuence on the the loop crossover frequency,
phase margin, and gain margin. Increasing the output
capacitor above this minimum value will reduce the cross-
over frequency and provide greater phase margin.
Capacitors with X7R or X5R ceramic dielectric are recom-
mended for their low ESR and superior temperature and
voltage characteristics. Y5V capacitors should not be used
as their temperature coecients make them unsuitable
for this application.
In addition to ensuring stability, the output capacitor
serves other important functions. This capacitor deter-
mines the output voltage ripple — as capacitance
increases, ripple voltage decreases. It also supplies current
during a large load step for a few switching cycles until
the control loop responds (typically 3 switching cycles).
Once the loop responds, regulation is restored and the
desired output is reached. During the period prior to PWM
operation resuming, the relationship between output
voltage and output capacitance can be approximated
using the equation
fV
I3
C
DROOP
LOAD
OUT u
'u
This equation can be used to approximate the minimum
output capacitance needed to ensure voltage does not
droop below an acceptable level. For example, a load step
from 50mA to 400mA requiring droop less than 50mV
would require the minimum output capacitance to be
F0.6
105.305.0
4.03
C6
OUT P
uu
u
In this example, using a standard 10µF capacitor would be
adequate to keep voltage droop less than the desired
limit. Note that if the voltage droop limit were decreased
from 50mV to 25mV, the output capacitance would need
to be increased to at least 12µF (twice as much capaci-
tance for half the droop). Capacitance will decrease from
the nominal value when a ceramic capacitor is biased with
a DC current, so it is important to select a capacitor whose
Applications Information (continued)
Manufacturer/Part No. L
(μH)
DCR
Max
(Ω)
Rated
Current
(A)
L at Rated
Current
(μH)
Dimensions
LxWxH
(mm)
Murata
LQM2HPN1R0 1±20% 0.13 1.5 0.78 2.5x2.0x1.2
Murata
LQH3NPN1R0 1±20% 0.07 1.7 0.78 3.0x3.0x1.5
Coilcraft
LPO4815 1±20% 0.036 1.9 0.8 4.8x4.8x1.5
Coilcraft
LPS3010 1±20% 0.085 1.6 0.7 3.0x3.0x1.0
shielded
FDK
MIPWT3226D1R5 1.5±30% 0.09 1.2 0.9 3.2x2.6x0.8
FDK
MIPF2520D1R5 1.5±30% 0.07 1.5 0.9 3.2x2.6x0.8
Tayo Yuden
CKP32161R5M 1.5±20% 0.13 1 0.5 3.2x1.6x0.8
value exceeds the necessary capacitance value at the pro-
grammed output voltage. Check the manufacturer’s
capacitance vs. DC voltage graphs when selecting an
output capacitor to ensure the capacitance will be
adequate.
Table 2 lists the manufacturers of recommended output
capacitor options.
Table 2 — Recommended Output Capacitors
Manufacturer
Part Nunber
Value
(μF) Type
Rated
Voltage
(VDC)
Dimensions
LxWxH (mm)
Case Size
Murata
GRM188R60J106ME47D 10±20% X5R 6.3 1.6x0.8x0.8
0603
Murata
GRM21BR60J106K 10±10% X5R 6.3 2.0x1.25x1.25
0805
Taiyo Yuden
JMK107BJ106MA-T 10±20% X5R 6.3 1.6x0.8x0.8
0603
TDK
C1608X5R0J106MT 10±20% X5R 6.3 1.6x0.8x0.8
0603
CIN Selection
The SC202 input source current will appear as a DC supply
current with a triangular ripple imposed on it. To prevent
large input voltage ripple, a low ESR ceramic capacitor is
required. A minimum value of 4.7μF should be used. It is
important to consider the DC voltage coecient charac-
teristics when determining the actual required value. For
example, a 10μF, 6.3V, X5R ceramic capacitor with 5V DC
applied may exhibit a capacitance as low as 4.5μF. The
value of required input capacitance is estimated by deter-
mining the acceptable input ripple voltage and calculating
the minimum value required for CIN using the equation
fESR
I
V
V
V
1
V
V
C
OUT
IN
OUT
IN
OUT
IN
¸
¸
¹
·
¨
¨
©
§
'
¸
¸
¹
·
¨
¨
©
§
The input voltage ripple is at maximum level when the
input voltage is twice the output voltage (50% duty cycle
scenario).
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
16
Applications Information (continued)
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the PMOS switch.
Low ESR/ESL X5R ceramic capacitors are recommended
for this function. To minimize stray inductance, the capaci-
tor should be placed as closely as possible to the IN and
GND pins. Table 3 lists recommended input capacitor
options from dierent manufacturers.
Table 3 — Recommended Input Capacitors
Manufacturer
Part Nunber
Value
(μF) Type
Rated
Voltage
(VDC)
Dimensions
LxWxH (mm)
Case Size
Murata
GRM188R60J475K 4.7±10% X5R 6.3 1.6x0.8x0.8
0603
Murata
GRM188R60J106K 10±10% X5R 6.3 1.6x0.8x0.8
0603
Taiyo Yuden
JMK107BJ475KA4.7±10% X5R 6.3 1.6x0.8x0.8
0603
TDK
C1608X5R0J475KT 4.7±10% X5R 6.3 1.6x0.8x0.8
0603
PCB Layout Considerations
The layout diagram in Figure 3 shows a recommended
PCB top-layer for the SC202 and supporting components.
Specied layout rules must be followed since the layout is
critical for achieving the performance specified in the
Electrical Characteristics table. Poor layout can degrade
the performance of the DC-DC converter and can contrib-
ute to EMI problems, ground bounce, and resistive voltage
losses. Poor regulation and instability can also result.
The following guidelines are recommended for designing
a PCB layout:
CIN should be placed as close to the IN and GND pins
as possible. This capacitor provides a low impedance
loop for the pulsed currents present at the buck
converter’s input. Use short wide traces to minimize
trace impedance. This will also minimize EMI and
input voltage ripple by localizing the high frequency
current pulses.
COUT should be connected as closely as possible to the
OUT pin.
1.
2.
Use a ground plane referenced to the GND pin. Use
several vias to connect to the component side ground
to further reduce noise and interference on sensitive
circuit nodes.
Route the output voltage feedback/sense trace
(connected to the SNS pin) away from the LX node
as shown in Figure 3 to minimize noise and magnetic
interference.
Minimize the resistance from the OUT and GND pins
to the load. This will reduce errors in DC regulation
due to voltage drops in the traces.
The two smaller exposed pads on this package should
not be connected to any traces. The area beneath
these two pads must be kept clear so that they do
not make electrical contact with any traces, including
ground.
CIN
CTL2
CTL0
CTL1
CTL3
LX
(no
connection
needed)
SNSGND
IN
OUT
3.8mm
3.5mm
SC202
These pads should not
be electrically
connected to the PCB.
COUT
Figure 3 — Recommended PCB Layout
3.
4.
5.
6.
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
17
2.502.40 2.60
NOTES:
0.08
13
0.60
-
0.00
0.80
0.750.70
-
0.05
1.00
(0.20)
-
-
0.10
1.17
2.90
1.27 1.32
3.00 3.10
0.40 BSC
0.40 0.45 0.50
COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
2.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
1.
DIMENSIONS
e
bbb
aaa
A1
A2
D1
E1
DIM
N
L
E
D
A
MILLIMETERS
MAXMIN NOM
b 0.15 0.20 0.25
SEATING
PLANE
bbb C A B
aaa C
C
PIN 1
INDICATOR
(LASER MARK)
D
E
B
A
A1
A
A2
Lx7
0.355
0.30 x 45°
CHAMFER
e
0.238
E1
SEE DETAIL A
C
L
C
L
0.363
0.684
0.157
0.312
2X 0.200
2X 0.110
8X 0.025
DETAIL A
SCALE: 4/1
1.30
1
2
N
0.800 E/2
0.265
D1
0.95
0.25
D/2
e
bxN
C
L
L
C
2X
Outline Drawing — MLPQ-13
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
SC202
18
Land Pattern — MLPQ-13
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
NOTES:
2.
DIM
X
Y
H
K
P
G
MILLIMETERS
0.20
0.80
1.27
0.40
0.75
1.50
DIMENSIONS
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3.10
Z
LAND PATTERNS ( SOLDER PADS) NOT REQUIRED FOR SMALLER EXPOSED PADS.
3.
1.
G
2X 0.110
2X 0.200
8X 0.025
SMALL EXPOSED PADS LOCATION
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
4. DO NOT PLACE EXPOSED TRACES OR VIAS UNDER SMALLER EXPOSED PADS.
0.80
P1
0.157
0.312
0.265
H
0.684
0.363
P1
P
0.355
1.55
CC
L
CC
L
(P)
0.55
.250
K
X
0.238
Z
(P)
(3.10)
1.30
Y
2X
NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
Contact Information
SC202
19
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NOT RECOMMENDED FOR NEW DESIGN
NOT RECOMMENDED
FOR NEW DESIGN