Dual 600 MHz, 50 mW
Current Feedback Amplifier
Data Sheet
AD8002
Rev. E Document Feedback
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FEATURES
Excellent video specifications (RL = 150 Ω, G = +2)
Gain flatness: 0.1 dB to 60 MHz
Differential gain error: 0.01%
Differential phase error: 0.02°
Low power
Maximum power supply current (50 mW): 5.0 mA/amp
High speed and fast settling
−3 dB bandwidth (G = +1): 600 MHz
−3 dB bandwidth (G = +2): 500 MHz
Slew rate: 1200 V/µs
Settling time to 0.1%: 16 ns
Low distortion
THD at fC = 5 MHz: −65 dBc
Third-order intercept at f1 = 10 MHz: 33 dBm
SFDR at f = 5 MHz: −66 dB
Crosstalk at f = 5 MHz: −60 dB
High output drive
Over 70 mA output current
Drives up to eight back terminated 75 Ω loads (four
loads/side) while maintaining good differential
gain/phase performance (0.01%/0.17°)
Available in 8-lead SOIC and MSOP packages
APPLICATIONS
Analog-to-digital drivers
Video line drivers
Differential line drivers
Professional cameras
Video switchers
Special effects
RF receivers
GENERAL DESCRIPTION
The AD8002 is a dual, low power, high speed amplifier
designed to operate on ±5 V supplies. The AD8002 features
unique transimpedance linearization circuitry, which allows the
AD8002 to drive video loads with excellent differential gain
and phase performance on only 50 mW of power per amplifier.
The AD8002 is a current feedback amplifier and features gain
flatness of 0.1 dB to 60 MHz while offering differential gain and
phase error of 0.01% and 0.02°, which makes the AD8002 ideal
for professional video electronics such as cameras and video
switchers. Additionally, the low distortion and fast settling of
the AD8002 make it ideal for buffer high speed analog-to-
digital converters (ADCs).
PIN CONNECTION BLOCK DIAGRAM
OUT1
–IN1
+IN1
V–
V+
OUT2
–IN2
+IN2
01044-001
1
2
3
4
8
7
6
5
AD8002
Figure 1.
The AD8002 offers a low power of 5.0 mA/amp maximum
(VS = ±5 V) and can run on a single 12 V power supply, yet is
capable of delivering over 70 mA of load current. It is offered
in 8-lead SOIC and MSOP packages. These features make this
amplifier ideal for portable and battery-powered applications
where size and power are critical.
The bandwidth of 600 MHz along with 1200 V/µs of slew rate
make the AD8002 useful in many general-purpose high speed
applications where dual power supplies of up to ±6 V and single
supplies from 6 V to 12 V are needed. The AD8002 is available
in the industrial temperature range of −40°C to +85°C.
01044-003
G = +2
1V STEP
SIDE 1
200mV
SIDE 2
5ns
Figure 2. 1 V Step Response, G = +1
AD8002 Data Sheet
Rev. E | Page 2 of 21
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Pin Connection Block Diagram ..................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Maximum Power Dissipation ..................................................... 5
ESD Caution .................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Test Circuits ..................................................................................... 13
Theory of Operation ...................................................................... 14
Choice of Feedback and Gain Resistors .................................. 14
Printed Circuit Board (PCB) Layout Considerations ........... 14
Power Supply Bypassing ............................................................ 14
DC Errors and Noise.................................................................. 14
Driving Capacitive Loads .......................................................... 15
Communications ........................................................................ 15
Operation as a Video Line Driver ............................................ 15
Driving ADCs ............................................................................. 16
Single-Ended-to-Differential Driver Using an AD8002 ....... 16
Applications Information .............................................................. 18
Layout Considerations ............................................................... 18
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
8/15—Rev. D to Rev. E
Updated Format .................................................................. Universal
Deleted 8-Lead Plastic DIP ............................................... Universal
Changes to Features Section............................................................ 1
Deleted Figure 1; Renumbered Sequentially ................................. 1
Changes to Table 1 ............................................................................ 3
Change to Figure 3 ........................................................................... 5
Added Pin Configurations and Function Descriptions Section,
Figure 4, Figure 5, and Table 3; Renumbered Sequentially ......... 6
Change to Figure 10 ......................................................................... 7
Change to Figure 16 ......................................................................... 8
Change to Figure ............................................................................... 9
Change to Figure 34 ....................................................................... 11
Change to Figure 32 ....................................................................... 11
Added Test Circuits Section and Figure 42 to Figure 47 ........... 13
Change to Theory of Operation Section ..................................... 14
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
4/01—Rev. C to Rev. D
Max Ratings Changed ...................................................................... 3
Data Sheet AD8002
Rev. E | Page 3 of 21
SPECIFICATIONS
At TA = 25°C, VS = ±5 V, RL = 100 Ω, RC1 = 75 Ω, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
R Package G = +2, RF = 681 Ω 500 MHz
G = +1, RF = 953 Ω 600 MHz
RM Package G = +2, RF = 681 Ω 500 MHz
G = +1, RF = 1 kΩ 600 MHz
Bandwidth for 0.1 dB Flatness
R Package G = +2, RF = 681 Ω 90 MHz
RM Package G = +2, RF = 681 Ω 60 MHz
Slew Rate G = +2, VOUT = 2 V step 700 V/µs
G = −1, VOUT = 2 V step 1200 V/µs
Settling Time to 0.1% G = +2, VOUT = 2 V step 16 ns
Rise and Fall Time G = +2, VOUT = 2 V step, RF = 750 Ω 2.4 ns
NOISE/HARMONIC PERFORMANCE
Total Harmonic Distortion (THD) fC = 5 MHz, VOUT = 2 V p-p, G = +2, RL = 100 Ω −65 dBc
Crosstalk (Output to Output) f = 5 MHz, G = +2 −60 dB
Input Voltage Noise f = 10 kHz, RC = 0 Ω 2.0 nV/√Hz
Input Current Noise f = 10 kHz, +IN1,+IN2 2.0 pA/√Hz
f = 10 kHz, −IN1, −IN2 18 pA/√Hz
Differential Gain Error NTSC, G = +2, RL = 150 Ω 0.01 %
Differential Phase Error
NTSC, G = +2, R
L
= 150 Ω
Degrees
Third-Order Intercept f1= 10 MHz 33 dBm
1 dB Gain Compression f = 10 MHz 14 dBm
Spurious-Free Dynamic Range (SFDR) f = 5 MHz −66 dB
DC PERFORMANCE
Input Offset Voltage 2.0 6 mV
TMIN to TMAX 2.0 9 mV
Offset Drift 10 µV/°C
Input Bias Current (−IN1, −IN2) −25 +5.0 +25 µA
TMIN to TMAX −35 +35 µA
Input Bias Current (+IN1, +IN2) −6.0 +3.0 +6.0 µA
TMIN to TMAX −10 +10 µA
Open-Loop Transresistance VOUT = ±2.5 V 250 900 kΩ
TMIN to TMAX 175 kΩ
INPUT CHARACTERISTICS
Input Resistance +IN1, +IN2 10 MΩ
−IN1, −IN2 50 Ω
Input Capacitance +IN1, +IN2 1.5 pF
Input Common-Mode Voltage Range ±3.2 V
Common-Mode Rejection Ratio
Offset Voltage VCM = ±2.5 V 49 54 dB
Input Current (−IN1, −IN2) VCM = ±2.5 V, TMIN to TMAX 0.3 1.0 µA/V
Input Current (+IN1, +IN2) VCM = ±2.5 V, TMIN to TMAX 0.2 0.9 µA/V
OUTPUT CHARACTERISTICS
Output Voltage Swing RL = 150 Ω ±2.7 ±3.1 V
Output Current
2
mA
Short-Circuit Current2 85 110 mA
AD8002 Data Sheet
Rev. E | Page 4 of 21
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Operating Range ±3.0 ±6.0 V
Quiescent Current/Both Amplifiers TMIN to TMAX 10.0 11.5 mA
Power Supply Rejection Ratio +VS = +4 V to +6 V, −VS = −5 V 60 75 dB
−V
S
= −4 V to −6 V, +V
S
= +5 V
49
dB
Input Current (−IN1, −IN2) TMIN to TMAX 0.5 2.5 µA/V
Input Current (+IN1, +IN2) TMIN to TMAX 0.1 0.5 µA/V
1 RC is recommended to reduce peaking and minimize input reflections at frequencies above 300 MHz. However, RC is not required.
2 Output current is limited by the maximum power dissipation in the package. See Figure 3.
Data Sheet AD8002
Rev. E | Page 5 of 21
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage 13.2 V
Internal Power Dissipation1
SOIC (R) 0.9 W
MSOP (RM) 0.6 W
Input Common-Mode Voltage ±VS
Differential Input Voltage ±1.2 V
Output Short-Circuit Duration Observe power
derating curves
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering 10 sec) 300°C
1 Specification is for device in free air:
8-lead SOIC: θJA = 155°C/W.
8-lead MSOP: θJA = 200°C/W.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD8002 is limited by the associated rise in junction temper-
ature. The maximum safe junction temperature for plastic
encapsulated devices is determined by the glass transition
temperature of the plastic, approximately 150°C. Exceeding
this limit temporarily may cause a shift in parametric perfor-
mance due to a change in the stresses exerted on the die by
the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure.
Although the AD8002 is internally short-circuit protected, this
may not be sufficient to guarantee that the maximum junction
temperature (150°C) is not exceeded under all conditions.
To ensure proper operation, it is necessary to observe the
maximum power derating curves.
2.0
0
– 0805
1.5
0.5
–40
1.0
010–10–20–30 20 30 40 50 60 70 90
MAXIMUM POWER DISSIPATIO N (W)
AMBI E NT TE M P E RATURE ( °C)
8-L E AD S O IC PACKAGE
T
J
= 150° C
8-LEAD MSOP
PACKAGE
01044-004
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
AD8002 Data Sheet
Rev. E | Page 6 of 21
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
OUT1
1
–IN1
2
+IN1
3
V–
4
V+
8
OUT2
7
–IN2
6
+IN2
5
01044-100
AD8002
(No t t o Scal e)
TOP VIEW
Figure 4. 8-Lead SOIC
1
2
3
4
–IN1
+IN1
V–
OUT1
8
7
6
5
OUT2
–IN2
+IN2
V+
01044-101
AD8002
(Not t o Scale)
TOP VIEW
Figure 5. 8-Lead MSOP
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1 OUT1 Output 1
2 −IN1 Inverting Input 1
3 +IN1 Noninverting Input 1
4 V− VEE or Negative Supply
5
+IN2
Noninverting Input 2
6 −IN2 Inverting Input 2
7 OUT2 Output 2
8 V+ VCC or Positive Supply
Data Sheet AD8002
Rev. E | Page 7 of 21
TYPICAL PERFORMANCE CHARACTERISTICS
01044-005
G = +1
100mV ST E P
SIDE 1
20mV
SIDE 2
5ns
Figure 6. 100 mV Step Response, G = +1
01044-006
G = +1
1V STEP
SIDE 1
20mV
SIDE 2
5ns
Figure 7. 1 V Step Response, G = +1
01044-007
G = +2
100mV ST E P
SIDE 1
20mV
SIDE 2
5ns
Figure 8. 100 mV Step Response, G = +2
01044-008
G = +2
100mV ST E P
SIDE 1
20mV
SIDE 2
5ns
Figure 9. 1 V Step Response, G = +2
1G0M11M 100M
0
–0.5
–0.1
–0.2
–0.3
–0.4
0.1
1
–4
–9
–5
–6
–7
–8
–3
–2
–1
0
NORMALIZED FLATNESS (dB)
FRE Q UE NCY ( Hz )
NORM ALIZED FREQUENCY RE S P ONSE ( dB)
SIDE 1
SIDE 2
SIDE 1
SIDE 2
G = +2
R
L
= 100Ω
V
IN
= 50mV
01044-009
Figure 10. Frequency Response and Flatness, G = +2 (See Figure 41)
FRE Q UE NCY ( Hz )
–50
–60
DISTORTION (dBc)
–110 100M
01044-010
10k 100k 1M 10M
–70
–80
–100
–90
SECO ND HARM ONI C
THIRD HARMO NIC
G = +2
RL= 100Ω
Figure 11. Distortion vs. Frequency, G = +2, RL = 100 Ω
AD8002 Data Sheet
Rev. E | Page 8 of 21
FRE Q UE NCY ( Hz )
–60
–70
DISTORTION (dBc)
–120 100M
01044-011
10k 100k 1M 10M
–80
–90
–110
–100
G = +2
R
L
= 1kΩ
V
OUT
= 2V p-p
SECO ND HARM ONI C
THIRD HARMO NIC
Figure 12. Distortion vs. Frequency, G = +2, RL = 1 kΩ
–70
–60
–100
–90
–80
OUTPUT SIDE 1
OUTPUT SIDE 2
CROSS TAL K ( dB)
–50
–40
–30
–20
–110
–120
FRE Q UE NCY ( Hz )
100M100k 1M 10M
G = +2
R
F
= 750Ω
R
L
= 100Ω
V
S
= ±5. 0V
V
IN
= –4dBV
01044-012
Figure 13. Crosstalk (Output to Output) vs. Frequency
01044-013
SIDE 1
SIDE 2
5ns
SIDE 1: V
IN
= 0V; 8mV /DI V RTO
SIDE 2: 1V S TEP RTO ; 400mV /DI V
G = +2
R
F
= 750Ω
R
C
= 75Ω
R
L
= 100Ω
Figure 14. Pulse Crosstalk, Worst Case, 1 V Step
0.02
0.06
0.02
12345678910 11
0.04
–0.02
0.08
–0.01
0
0.01
IRE
DIFFERENTIAL GAIN
(%)
DIFFE RE NTI AL PHAS E
(Degrees)
0
2 BACK TE RM INATE D
LOADS (75Ω)
1 BACK TE RM INATE D
LOAD (150Ω)
2 BACK TE RM INATE D
LOADS (75Ω)
G = +2
NTSC
R
F
= 750Ω
1 BACK TE RM INATE D
LOAD (150Ω)
01044-014
Figure 15. Differential Gain and Differential Phase (per Amplifier)
–2
–1
–4
–3
0
1
2
–5
–6 1G10M 100M1M FREQUENCY ( Hz )
GAI N (V)
SIDE 1
SIDE 2
G = +1
R
F
= 953Ω
R
L
= 100Ω
V
IN
= 50mV
01044-015
Figure 16. Gain vs. Frequency Response, G = +1 (See Figure 42)
–40
–70
–100
–80
–90
–60
–50
100M100k 10M1M10k FREQUENCY ( Hz )
DISTORTION (dBc)
G = +1
RL= 100Ω
VOUT = 2V p-p
01044-016
SECO ND HARM ONI C
THI RD HARMONIC
Figure 17. Distortion vs. Frequency, G = +1, RL = 100 Ω
Data Sheet AD8002
Rev. E | Page 9 of 21
FRE Q UE NCY ( Hz )
–40
–50
DISTORTION (dBc)
–110 100M
01044-017
10k 100k 1M 10M
–70
–80
–100
–60
–90
G = +1
RL= 1kΩ
SECO ND HARM ONI C
THIRD HARMO NIC
Figure 18. Distortion vs. Frequency, G = +1, RL = 1 kΩ
0
–3
–27
–18
–21
–24
–15
–12
–9
–6
–3
–18
–21
–15
–12
–9
–6
INPUT LEVEL (d BV)
FRE Q UE NCY ( Hz )
6
3
0
OUTPUT LEVEL (d BV)
1M 10M 100M 500M
G = +2
R
F
= 681Ω
V
S
= ±5V
R
L
= 100Ω
01044-018
Figure 19. Large Signal Frequency Response, G = +2
9
6
–21
–12
–15
–18
3
–9
–6
–3
0
INPUT/OUTPUT LEVEL (dBV)
FRE Q UE NCY ( Hz )
1M 10M 100M 500M
G = +1
R
F
= 1.21Ω
R
L
= 100Ω
01044-019
Figure 20. Large Signal Frequency Response, G = +1 (See Figure 43)
25
10
–51M
0
5
15
20
FRE Q UE NCY ( Hz )
GAI N (dB)
1G100M10M
45
30
35
40
G = + 100
G = +10
R
L
= 100Ω
R
F
= 1000Ω
R
F
= 499Ω
V
S
= ±5. 0V
01044-020
Figure 21. Frequency Response, G = +10, G = +100
01044-021
OUTPUT
ERROR,
(0.05%/DIV)
INPUT
10ns400mV
G = +2
2V STEP
RF= 750Ω
RC= 75Ω
Figure 22. Short Term Settling Time
3.4
2.5 125
2.7
2.6
–35–55
2.8
2.9
3.0
3.1
3.2
3.3
105856545255–15JUNCT IO N TEM P E RATURE ( °C)
OUTPUT SWING (V)
R
L
= 150Ω
R
L
= 50Ω
V
S
= ±5V
+V
OUT
+V
OUT
|–V
OUT
|
|–V
OUT
|
V
S
= ±5V
01044-022
Figure 23. Output Swing vs. Junction Temperature
AD8002 Data Sheet
Rev. E | Page 10 of 21
5
–3
–1
–2
1
0
2
3
4
125–35–55 105856545255–15JUNCT IO N TEM P E RATURE ( °C)
INPUT BI AS CURRE NT (µA)
–IN
+IN
01044-023
Figure 24. Input Bias Current vs. Junction Temperature
01044-024
ERROR,
(0.05%/DIV)
INPUT
2µs400mV
G = +2
2V STEP
RC= 75Ω
RF= 750Ω
RL= 100Ω
OUTPUT
Figure 25. Long Term Settling Time
4
–3
0
–2
–1
3
1
2
JUNCTION TEM P E RATURE ( °C)
INPUT OFFSET VOLTAGE (mV)
DEVICE 1
DEVICE 2
DEVICE 3
125–35–55 105856545255–15
01044-025
Figure 26. Input Offset Voltage vs. Junction Temperature
11.5
9.0
10.5
9.5
10.0
125–35–55 105856545255–15
11.0
JUNCTION TEM P E RATURE ( °C)
TOTAL SUP P LY CURRE NT (mA)
V
S
= 5V
01044-026
Figure 27. Total Supply Current vs. Junction Temperature
120
75
85
80
90
95
100
105
110
115
JUNCTI ON T E M P E RATURE ( °C)
SHORT-CIRCUI T CURRENT ( mA)
|SINK I
SC
|
SOURCE I
SC
70
125–35–55 105856545255–15
01044-027
Figure 28. Short-Circuit Current vs. Junction Temperature
100
10
110 100 100k
10k1k
FRE Q UE NCY ( Hz )
100
10
1
NOISE VOLTAGE (nV/√Hz)
NOISE CURRENT ( pA/√Hz)
INVE RTI NG CURRENT V
S
= ±5V
NONI NV E RTI NG CURRENT V
S
= ±5V
VOLTAGE NOISE V
S
= ±5V
01044-028
Figure 29. Noise Voltage vs. Frequency
Data Sheet AD8002
Rev. E | Page 11 of 21
–48
–56
–54
–55
–52
–53
–51
–50
–49
CMRR (dB)
–CMRR
+CMRR
JUNCTION TEM P E RATURE ( °C)
125–35–55 105856545255–15
01044-029
Figure 30. Common-Mode Rejection Ratio (CMRR) vs. Junction Temperature
FRE Q UE NCY ( Hz )
1
1G100k10k 100M
10M1M
10
100
0.01
0.1
OUTPUT RE S ISTANCE (Ω)
R
bT
= 50Ω
R
bT
= 0Ω
G = +2
R
F
= 750Ω
R
C
= 75Ω
V
S
= ±5. 0V
POWER = 0dBm
(223. 6mV rms)
01044-030
Figure 31. Output Resistance vs. Frequency
1
–4
–9
G1M01M1 100M
–5
–6
–7
–8
–3
–2
–1
0
FREQUENCY ( Hz )
OUTPUT VOLTAGE (dB)
NORMALIZED FLATNESS (dB)
0
–0.1
–0.2
–0.3
0.1
0.2
–3dB BANDWIDTH
0.1dB FLAT NE S S
SIDE 1
SIDE 1
SIDE 2
SIDE 2
G = –1
R
L
= 100Ω
R
F
= 549Ω
V
S
= ±5. 0V
V
IN
= 50mV
01044-031
Figure 32. −3 dB Bandwidth vs. Frequency, G = −1
–50.0
–72.5
–67.5
–70.0
–65.0
–62.5
–60.0
–57.5
–55.0
–52.5
PSRR ( dB)
–75.0
–PSRR
+PSRR
2V SPAN
CURVES ARE FO R WO RS T-
CASE CO NDIT IO N WHERE
ONE SUPPLY IS VARIED
WHILE THE OTHER IS
HEL D CO NS TANT .
125–35–55 105856545255–15
JUNCTION TEM P E RATURE ( °C)
01044-032
Figure 33. Power Supply Rejection Ration (PSRR) vs. Junction Temperature
100M10M1M FRE Q UE NCY ( Hz )
–40
–30
CMRR (dB)
1G
–50
–60
–20
–10
0
01044-033
V
S
= ±5. 0V
R
L
= 100Ω
V
IN
= 200mV
SIDE 1
SIDE 2
Figure 34. CMRR vs. Frequency (See Figure 45)
01044-034
SIDE 1
400mV
SIDE 2
5ns
G = –1
RF= 576Ω
RG= 576Ω
RC= 50Ω
Figure 35. 2 V Step Response, G = −1
AD8002 Data Sheet
Rev. E | Page 12 of 21
01044-035
20mV 5ns
SIDE 1
SIDE 2
G = –1
RF= 576Ω
RG= 576Ω
RC= 50Ω
RL= 100Ω
Figure 36. 100 mV Step Response, G = −1
–20
–50
–40
–30
–10
FRE Q UE NCY ( Hz )
PSRR ( dB)
–90
60k 100k 1M 10M 100M
–80
–70
–60
400M
0
+PSRR
–PSRR
V
IN
= 200mV
G = +2
01044-036
Figure 37. PSRR vs. Frequency
01044-037
G = –2
2V STEP
R
F
= 549Ω
SIDE 1
SIDE 2
400mV 5ns
Figure 38. 2 V Step Response, G = −2
01044-038
G = –1
100mV ST E P
RF= 549Ω
SIDE 1
SIDE 2
20mV 5ns
Figure 39. 100 mV Step Response, G = −1
Data Sheet AD8002
Rev. E | Page 13 of 21
TEST CIRCUITS
PULSE
GENERATOR
953Ω
+5V
R
L
= 100Ω
–5V
50Ω
V
IN
0.1µF
0.1µF
10µF
10µF
tR
/
tF
= 250ps
75Ω AD8002
2
1
3
8
4
01044-039
Figure 40. Test Circuit, Gain = +1
75Ω
50Ω
50Ω
R
F
681Ω
681Ω
01044-041
Figure 41. Frequency Response and Flatness Test Circuit (See Figure 10)
75Ω
50Ω
953Ω
50Ω
01044-042
Figure 42. Frequency Response Test Circuit (See Figure 16)
75Ω
50Ω
50Ω
1.21kΩ
01044-043
Figure 43. Large Signal Frequency Response Test Circuit (See Figure 20)
PULSE
GENERATOR
750Ω
+5V
R
L
= 100Ω
–5V
50Ω
V
IN
0.1µF
0.1µF
10µF
10µF
tR
/
tF
= 250ps
75Ω
750Ω
AD8002
2
1
3
8
4
01044-040
Figure 44. Test Circuit, Gain = +2
604Ω
V
IN
154Ω 154Ω
604Ω
50Ω
57.6Ω
–5V
0.1µF
01044-044
Figure 45. CMRR Test Circuit (See Figure 34)
576Ω
54.9Ω
50Ω
50Ω
576Ω
01044-045
Figure 46. 100 mV Step Response, G = −1
274Ω
61.9Ω
50Ω
50Ω
549Ω
01044-046
Figure 47. 100 mV Step Response, G = −2
AD8002 Data Sheet
Rev. E | Page 14 of 21
THEORY OF OPERATION
An analysis of the AD8002 can put the operation in familiar
terms. The open-loop behavior of the AD8002 is expressed
as transimpedance, ΔVOUT/ΔI−INx, or TZ. The open-loop
transimpedance behaves just as the open-loop voltage gain
of a voltage feedback amplifier, that is, it has a large dc value
and decreases at roughly 6 dB/octave in frequency.
Because the value of RIN is proportional to 1/gm, the equivalent
voltage gain is just TZ × gm, where the gm in question is the
transconductance of the input stage. This results in a low open-
loop input impedance at the inverting input. Using this
amplifier as a follower with gain (see Figure 48) basic analysis
yields the following result:
R1RGsT
sT
G
V
V
IN
Z
Z
IN
OUT
+×+
×= )(
)(
where:
TZ(s) implies the transimpedance as a function of the frequency.
G = 1 + R1/R2.
RIN = 1/gm ≈ 50 Ω.
V
OUT
R1
R2
R
IN
V
IN
01044-047
Figure 48. Small Signal Schematic
Recognizing that G × RIN << R1 for low gains, the amplifier
can be seen to the first-order that the bandwidth for it is
independent of gain (G).
Considering that additional poles contribute excess phase at
high frequencies, there is a minimum feedback resistance below
which peaking or oscillation may result. This fact is used to
determine the optimum feedback resistance, RF. In practice,
parasitic capacitance at the inverting input terminal also adds
phase in the feedback loop; thus selecting an optimum value for
RF can be difficult.
Achieving and maintaining gain flatness of better than 0.1 dB
at frequencies above 10 MHz requires careful consideration of
several issues discussed in the following sections.
CHOICE OF FEEDBACK AND GAIN RESISTORS
The fine scale gain flatness varies to some extent with feedback
resistance. Therefore, it is recommended that as soon as
optimum resistor values are determined, use 1% tolerance
values if it is desired to maintain flatness over a wide range of
production lots. In addition, resistors of different construction
have different associated parasitic capacitance of the character-
ization. It is not recommended to use leaded components with
the AD8002.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
CONSIDERATIONS
As expected for a wideband amplifier, PCB parasitics can affect
the overall closed-loop performance. Of concern are stray
capacitances at the output and the inverting input nodes. If a
ground plane is to be used on the same side of the board as the
signal traces, leave a space (5 mm minimum) around the signal
lines to minimize coupling. Additionally, make signal lines
connecting the feedback and gain resistors short enough so that
their associated inductance does not cause high frequency gain
errors. Line lengths of less than 5 mm are recommended. If long
runs of coaxial cable are being driven, dispersion and loss must
be considered.
POWER SUPPLY BYPASSING
Adequate power supply bypassing can be critical when optimiz-
ing the performance of a high frequency circuit. Inductance in
the power supply leads can form resonant circuits that produce
peaking in the response of the amplifier. In addition, if large
current transients must be delivered to the load, bypass capaci-
tors (typically greater than 1 μF) are required to provide the best
settling time and lowest distortion. A parallel combination of
4.7 μF and 0.1 μF is recommended. Some brands of electrolytic
capacitors require a small series damping resistor ≈4.7 Ω for
optimum results.
DC ERRORS AND NOISE
There are three major noise and offset terms to consider in a
current feedback amplifier. For offset errors, refer to Equation 1.
For noise error, the terms are root-sum-squared to give a net
output error. In Figure 49, the terms are input offset (VIO), which
appears at the output multiplied by the noise gain of the circuit
(1 + RF/RI), noninverting input current (IBN × RN), also multiplied
by the noise gain, and the inverting input current, which when
divided between RF and RI and subsequently multiplied by the
noise gain, always appears at the output as IBN × RF.
The input voltage noise of the AD8002 is a low 2 nV/√Hz. At low
gains, though, the inverting input current noise times RF is the
dominant noise source. Careful layout and device matching
contribute to a better offset and drift specifications for the
AD8002.Use the typical performance curves in conjunction
with Equation 1 to predict the performance of the AD8002 in
any application.
FBI
I
F
NBN
I
F
IO
OUT RI
R
R
RI
R
R
V
V××
+××±
+×= 11
(1)
01044-048
R
F
R
I
R
N
I
BN
V
OUT
I
BI
Figure 49. Output Offset Voltage
Data Sheet AD8002
Rev. E | Page 15 of 21
DRIVING CAPACITIVE LOADS
The AD8002 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, the best
frequency response is obtained by the addition of a small series
resistance as shown in Figure 50.
909Ω
R
SERIES
R
L
500Ω
I
N
C
L
01044-049
Figure 50. Driving Capacitive Loads
Figure 51 shows the optimum value for RSERIES vs. capacitive
load (CL). It is worth noting that the frequency response of the
circuit when driving large capacitive loads is dominated by
the passive roll-off of RSERIES and CL.
40
00 5 10 15 20 25
30
10
20
R
SERIES
(V)
CL (pF)
01044-050
Figure 51. Recommended RSERIES vs. Capacitive Load
COMMUNICATIONS
Distortion is a key specification in communications applica-
tions. Intermodulation distortion (IMD) is a measure of the
ability of an amplifier to pass complex signals without the
generation of spurious harmonics. Third-order products are
usually the most problematic because several of them fall
near the fundamentals and do not lend themselves to filtering.
Theory predicts that the third-order harmonic distortion
components increase in power at three times the rate of the
fundamental tones. The specification of the third-order intercept
as the virtual point where fundamental and harmonic power
are equal is one standard measure of distortion performance.
Op amps used in closed-loop applications do not always obey
this simple theory. Figure 52 shows the AD8002 performance
summarized at a gain of +2. Here, the worst third-order
products are plotted vs. input power. The third-order intercept
of the AD8002 is 33 dBm at 10 MHz.
–80 3–7
–75
210–4 6–5 –2
–70
–65
–60
–55
–50
–45
–1
THIRD-O RDE R IMD ( dBc)
INPUT POW E R ( dBm)
–6 54–8 –3
2f
2
– f
1
G = +2
f
2
= 12MHz
f
1
= 10MHz
2f
1
– f
2
01044-051
Figure 52. Third-Order IMD vs. Input Power; f1 = 10 MHz, f2 = 12 MHz
OPERATION AS A VIDEO LINE DRIVER
The AD8002 has been designed to offer good performance as a
video line driver. The important specifications of differential
gain (0.01%) and differential phase (0.02°) meet the most
exacting HDTV demands for driving one video load with each
amplifier. The AD8002 also drives four back terminated loads
(two each), as shown in Figure 53, with equally impressive
performance (0.01%, 0.07°). Another important consideration
is isolation between loads in a multiple load application. The
AD8002 has more than 40 dB of isolation at 5 MHz when
driving two 75 Ω back terminated loads.
750Ω750Ω
75Ω
75Ω
75Ω
CABLE
75Ω
V
OUT
1
V
OUT
2
+V
S
–V
S
V
IN
0.1µF
4.7µF
1/2
AD8002 0.1µF
4.7µF
75Ω
CABLE
75Ω
75Ω
CABLE
75Ω
75Ω
V
OUT
3
V
OUT
4
75Ω
CABLE
75Ω
75Ω
1/2
AD8002
750Ω
750Ω
CABLE
75Ω
+
+
1
8
2
34
5
7
6
75Ω
01044-052
Figure 53. Video Line Driver
AD8002 Data Sheet
Rev. E | Page 16 of 21
DRIVING ADCs
The AD8002 is well suited for driving high speed analog-to-
digital converters, such as the AD9058. The AD9058 is a dual,
8-bit, 50 MSPS ADC. In Figure 55, the AD8002 drives the
inputs of the AD9058, which are configured for 0 V to 2 V
ranges. Bipolar input signals are buffered, amplified (−2×), and
offset (by 1.0 V) into the proper input range of the ADC. Using
the internal 2 V reference of the AD9058 connected to both
ADCs (as shown in Figure 55) reduces the number of external
components required to create a complete data acquisition
system. The 20 Ω resistors in series with the ADC inputs help
the ADCs drive the 10 pF ADC input capacitance. The AD8002
adds only 100 mW to the power consumption, while not
limiting the performance of the circuit.
SINGLE-ENDED-TO-DIFFERENTIAL DRIVER USING
AN AD8002
The two halves of an AD8002 can be configured to create a
single-ended-to-differential high speed driver with a −3 dB
bandwidth in excess of 200 MHz, as shown in Figure 54.
Although the individual op amps are each current feedback op
amps, the overall architecture yields a circuit with attributes
normally associated with voltage feedback amplifiers, yet offers
the speed advantages inherent in current feedback amplifiers. In
addition, the gain of the circuit can be changed by varying a
single resistor, RF, which is often not possible in a dual op amp
differential driver.
50Ω OUTPUT 1
50Ω OUTPUT 2
RG
511Ω
RF511Ω
CC = 0.5pF TO 1.5pF
1/2
AD8002
1/2
AD8002
OP AMP 1
OP AMP 2
VIN
RA
511Ω
RA
511Ω
511Ω
RB
511Ω
RB
01044-054
Figure 54. Differential Line Driver
0.1µF
+VS
–VS
20Ω
50Ω
1kΩ
18
17
16
15
14
13
12
11
–VREF
10pF
CLOCK
5, 9, 22,
24, 37, 41
4,19, 21 25, 27, 42 0.1µF
38
8
–VREF
6
+VINT
2
3+VREF
AIN
549Ω
274Ω
ANALOG
IN A
±0.5V
1.1kΩ
AD8597
43 +VREF
20kΩ
0.1µF
–2V
1.1kΩ
20kΩ
549Ω
ANALOG
IN B
±0.5V
274Ω
20Ω
0.1µF
40
COMP
1
AIN
ENCODE ENCODE
10 36
ENCODE 74ACT04
0.1µF
+5V
28
29
30
31
32
33
34
35
RZ1
RZ2
D0(LSB)
D7 (MSB)
D0 (LSB)
D7 (MSB) 7, 20,
26, 39 –5V
1N4001
AD9058
(J-LEAD)
RZ1, RZ2 = 2,000Ω SIP (8-PKG)
74ACT 273 74ACT 273
8
8
1/2
AD8002
1/2
AD8002
50Ω
50Ω
01044-053
Figure 55. AD8002 Driving a Dual ADC
Data Sheet AD8002
Rev. E | Page 17 of 21
The current feedback nature of the op amps, in addition to
enabling the wide bandwidth, provides an output drive of
more than 3 V p-p into a 20 Ω load for each output at 20 MHz.
Conversely, the voltage feedback nature provides symmetrical
high impedance inputs and allows the use of reactive
components in the feedback network.
The circuit consists of the two op amps, each configured as a
unity-gain follower by the 511 Ω RA feedback resistors between
the output and inverting input of each op amp. The output of
each op amp has a 511 Ω RB resistor to the inverting input of
the other op amp. Thus, each output drives the other op amp
through a unity-gain inverter configuration. By connecting
the two amplifiers as cross-coupled inverters, the outputs of the
amplifiers are freed to be equal and opposite, assuring zero
output common-mode voltage.
Using this circuit configuration, the common-mode signal of
the outputs is reduced. If one output increases slightly, the
negative input to the other op amp drives its output slightly
lower and thus preserves the symmetry of the complementary
outputs, which reduces the common-mode signal. The common-
mode output signal was measured as −50 dB at 1 MHz.
Looking at this configuration overall, there are two high
impedance inputs (the +IN1, +IN2 of each op amp), two
low impedance outputs, and a high open-loop gain. The two
noninverting inputs and the output of the Op Amp 2 structure
looks like a voltage feedback op amp having two symmetrical,
high impedance inputs and one output. The +IN1, +IN2 to
Op Amp 2 is the noninverting input (it has the same polarity as
OUT2) and the +IN1, +IN2 to Op Amp 1 is the inverting input
(opposite polarity of Output 2).
With a feedback resistor, RF, an input resistor, RG, and the
grounding of the +IN1, +IN2 of Op Amp 2, a feedback
amplifier is formed. This configuration is similar to a voltage
feedback amplifier in an inverting configuration if only OUT2
is considered. The addition of OUT1 makes the amplifier a
differential output.
The differential gain of this circuit is
+×=
B
A
G
F
R
R
R
R
G1
where:
RF/RG is the gain of the overall op amp configuration and is the
same as for an inverting op amp except for the polarity. If OUT1
is used as the output reference, the gain is positive.
1 + RA/RB is the noise gain of each individual op amp in its
noninverting configuration.
The resulting architecture offers several advantages. First, the
gain can be changed by changing a single resistor. Changing
either RF or RG changes the gain as in an inverting op amp
circuit. For most types of differential circuits, more than one
resistor must be changed to change gain and still maintain good
common-mode rejection (CMR).
Reactive elements can be used in the feedback network. This is
in contrast to current feedback amplifiers that restrict the use of
reactive elements in the feedback op amp. The circuit described
requires about 0.9 pF of capacitance in shunt across RF to optimize
peaking and realize a −3 dB bandwidth of more than 200 MHz.
The peaking exhibited by the circuit is very sensitive to the
value of this capacitor. Parasitics in the board layout on the
order of tenths of picofarads influences the frequency response
and the value required for the feedback capacitor, thus a good
layout is essential.
The shunt capacitor type selection is also critical. A good
microwave type chip capacitor with high Q was found to yield
best performance. The device selected for this circuit was a
Murata Erie MA280R9B.
The distortion was measured at 20 MHz with a 3 V p-p input
and a 100 Ω load on each output. For OUT1, the distortion is
−37 dBc and −41 dBc for the second and third harmonics,
respectively. For OUT2, the second harmonic is −35 dBc and
the third harmonic is −43 dBc.
6
–4
–14 1G10M1M 100M
–6
–8
–10
–12
–2
0
2
4
OUTPUT (dB)
FRE Q UE NCY ( Hz )
C
C
= 0.9pF
OUT+
OUT–
01044-055
Figure 56. Differential Driver Frequency Response
AD8002 Data Sheet
Rev. E | Page 18 of 21
APPLICATIONS INFORMATION
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8002 requires
careful attention to board layout and component selection.
Proper RF design techniques and low parasitic component
selection are mandatory.
Use a ground plane to cover all unused portions of the
component side of the board to provide a low impedance
ground path. Remove the ground plane from the area near
the input pins to reduce stray capacitance.
Use chip capacitors for supply bypassing (see Figure 58). Connect
one end to the ground plane and the other within ⅛ inch of
each power pin. Connect an additional large tantalum
electrolytic capacitor (4.7 µF to 10 µF) in parallel, but not
necessarily so close, to supply current for fast, large signal
changes at the output.
Locate the feedback resistor close to the inverting input pin
to keep the stray capacitance at this node to a minimum.
Capacitance variations of less than 1 pF at the inverting input
significantly affects high speed performance.
Use stripline design techniques for long signal traces (greater than
about 1 inch). Design these with a characteristic impedance of
50 Ω or 75 Ω and ensure they are properly terminated at each
end.
Table 4 and Table 5 show the recommended component values.
R
F
R
BT
IN
–V
S
+V
S
R
S
R
T
R
G
OUT
01044-056
Figure 57. Inverting Configuration
C1
0.1µF C3
10µF
C2
0.1µF C4
10µF
+V
S
–V
S
01044-057
Figure 58. Supply Bypassing
R
F
R
BT
IN
–V
S
+V
S
R
T
R
G
OUT
R
C
01044-058
Figure 59. Noninverting Configuration
Table 4. AD8002AR (SOIC) Recommended Component Values1
Component
Gain
Unit −10 −2 −1 +1 +2 +10 +100
R
F
499
499
549
953
681
499
1000
Ω
RG 49.9 249 549 N/A 681 54.9 10 Ω
RBT (Nominal) 49.9 49.9 49.9 49.9 49.9 49.9 49.9 Ω
RC2 N/A N/A N/A 75 75 0 0 Ω
RS 49.9 49.9 49.9 N/A N/A N/A N/A Ω
RT (Nominal) N/A 61.9 54.9 49.9 49.9 49.9 49.9 Ω
Small Signal Bandwidth 250 410 410 600 500 170 17 MHz
0.1 dB Flatness 50 100 100 35 90 24 3 MHz
1 N/A means not applicable
2 RC is recommended to reduce peaking, and minimizes input reflections at frequencies above 300 MHz. However, RC is not required.
Table 5. AD8002ARM (MSOP) Recommended Component Values1
Component
Gain
Unit −10 −2 −1 +1 +2 +10 +100
R
F
499
499
590
1000
681
499
1000
Ω
RG 49.9 249 590 N/A 681 54.9 10 Ω
RBT (Nominal) 49.9 49.9 49.9 49.9 49.9 49.9 49.9 Ω
RC2 N/A N/A N/A 75 75 0 0 Ω
RS 49.9 49.9 49.9 N/A N/A N/A N/A Ω
RT (Nominal) N/A 61.9 49.9 49.9 49.9 49.9 49.9 Ω
Small Signal Bandwidth 270 400 410 600 450 170 19 MHz
0.1 dB Flatness 60 100 100 35 70 35 3 MHz
1 N/A means not applicable
2 RC is recommended to reduce peaking, and minimizes input reflections at frequencies above 300 MHz. However, RC is not required.
Data Sheet AD8002
Rev. E | Page 19 of 21
01044-059
Figure 60. Inverter SOIC Board Layout (Silkscreen)
01044-060
Figure 61. Noninverter SOIC Board Layout (Silkscreen)
01044-061
Figure 62. Inverter MSOP Board Layout (Silkscreen)
01044-062
Figure 63. Noninverter MSOP Board Layout (Silkscreen)
01044-063
Figure 64. Inverter SOIC Board Layout (Component Layer)
01044-064
Figure 65. Noninverter SOIC Board Layout (Component Layer)
AD8002 Data Sheet
Rev. E | Page 20 of 21
01044-065
Figure 66. Inverter MSOP Board Layout (Component Layer)
01044-066
Figure 67. Noninverter MSOP Board Layout (Component Layer)
01044-067
Figure 68. Inverter SOIC Board Layout (Solder Side) (Looking Through the
Board)
01044-068
Figure 69. Noninverter SOIC Board Layout (Solder Side) (Looking Through
the Board)
01044-069
Figure 70. Inverter MSOP Board Layout (Solder Side) (Looking Through the
Board)
01044-070
Figure 71. Noninverter MSOP Board Layout (Solder Side) (Looking Through
the Board)
Data Sheet AD8002
Rev. E | Page 21 of 21
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLYAND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 72. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
COM P LI ANT TO JE DE C ST ANDARDS MO- 1 87-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BS C
0.40
0.25
1.10 M AX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 73. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding Code
AD8002ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD8002ARZ-R7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Reel R-8
AD8002ARMZ −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP] RM-8 HFA
AD8002ARMZ-REEL −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 13" Reel RM-8 HFA
AD8002ARMZ-REEL7 −40°C to +85°C 8-Lead Mini Small Outline Package [MSOP], 7" Reel RM-8 HFA
AD8002AR-EBZ Evaluation Board for 8-Lead SOIC
AD8002ARM-EBZ Evaluation Board for 8-Lead MSOP
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D01044-0-8/15(E)
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