RS08
Microcontrollers
freescale.com
MC9RS08KA2
MC9RS08KA1
Data Sheet
MC9RS08KA2
Rev. 4
12/2008
8-Bit RS08 Central Processor Unit (CPU)
• Simplified S08 instruction set with added
high-performance instructions
— LDA, STA, and CLR instructions
support the short addressing mode;
address $0000 to $001F can be
accessed via a single-byte instruction
— ADD, SUB, INC, and DEC instructions
support the tiny addressing mode;
address $0000 to $000F can be
accessed via a single-byte instruction
with reduced instruction cycle
— Shadow PC register instructions: SHA
and SLA
• Pending interrupt indication
• Index addressing via D[X] and X register
• Direct page access to the entire memory
map through paging window
Memory
• On-chip Flash EEPROM
— MC9RS08KA2: 2048 bytes
— MC9RS08KA1: 1024 bytes
• 63 bytes on-chip RAM
Power-Saving Modes
• Wait and stop
• Wakeup from power-saving modes using
real-time interrupt (RTI), KBI, or ACMP
Clock Source
•ICS — Trimmable 20-MHz internal clock
source
— Up to 10-MHz internal bus operation
— 0.2% trimmable resolution, 2%
deviation over temperature and voltage
range
System Protection
• Computer operating properly (COP) reset
running off bus-independent clock source
• Low-voltage detection with reset or stop
wakeup
Peripherals
•MTIM — 8-bit modulo timer
•ACMP — Analog comparator
— Full rail-to-rail supply operation
— Option to compare to fixed internal
bandgap reference voltage
— Can operate in stop mode
•KBI — Keyboard interrupt ports
— Three KBI ports in 6-pin package
— Five KBI ports in 8-pin package
Development Support
• Background debug system
• Breakpoint capability to allow single
breakpoint setting during in-circuit debug
Package Options
• 6-pin dual flat no lead (DFN) package
— T wo general-purpose input/output (I/O)
pins
— One general-purpose input pin
— One general-purpose output pin
• 8-pin plastic dual in-line pin (PDIP)
package
— Four general-purpose input/output
(I/O) pins
— One general-purpose input pin
— One general-purpose output pin
• 8-pin narrow body SOIC package
— Four general-purpose input/output
(I/O) pins
— One general-purpose input pin
— One general-purpose output pin
MC9RS08KA2 Features
MC9RS08KA2 Series Data Sheet, Rev. 4
4Freescale Semiconductor
MC9RS08KA2 Series Data Sheet
Covers: MC9RS08KA2
MC9RS08KA1
MC9RS08KA2
Rev. 4
12/2008
MC9RS08KA2 Series Data Sheet, Rev. 4
6Freescale Semiconductor
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will
be the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com
The following revision history table summarizes changes contained in this document.
Revision
Number Revision
Date Description of Changes
1.0 04/2006 Initial public release version
2 12/2006 Added MC9RS08KA1
3 09/2007
Corrected Instruction Set Summary LDX ,X row operand to read 0E 0F. Revised the
Analog Comparator Electrical Specifications including the ACMP Bandgap
ref erence v oltage v alues . Corrected a tra nsposition in the DFN dra wing no . Upda ted
the ICS Characteristic table in the Electricals Appendix to include the ICS factory
trim and reference the parameters tir_wu and tfll_wu that are discusse d in th e ICS
chapter.
4 12/2008 Revised Figure 1-2. Updated “How to Reach Us” information.
Changed the mechanical drawing of 6-pin DFN in the Appendix B, “Ordering
Information and M ech a nic al Drawings.”
This product incorporates SuperFlash® technology licensed from SST.
Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
© Freescale Semiconductor, Inc., 2006-2008. All rights reserved.
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 7
List of Chapters
Chapter Title Page
List of Chapters
Chapter 1 MC9RS08KA2 Series Device Overview .........................................15
Chapter 2 Pins and Connections.....................................................................17
Chapter 3 Modes of Operation.........................................................................21
Chapter 4 Memory.............................................................................................25
Chapter 5 Resets, Interrupts, and General System Control..........................35
Chapter 6 Parallel Input/Output Control .........................................................45
Chapter 7 Keyboard Interrupt (RS08KBIV1) ...................................................51
Chapter 8 Central Processor Unit (RS08CPUV1) ...........................................57
Chapter 9 Internal Clock Source (RS08ICSV1)...............................................75
Chapter 10 Analog Comparator (RS08ACMPV1)..............................................83
Chapter 11 Modulo Timer (RS08MTIMV1).........................................................89
Chapter 12 Development Support .....................................................................97
Appendix A Electrical Characteristics..............................................................109
Appendix B Ordering Information and Mechanical Drawings........................123
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 9
Chapter 1
MC9RS08KA2 Series Device Overview
1.1 Overview .........................................................................................................................................15
1.2 MCU Block Diagram ......................................................................................................................15
1.3 System Clock Distribution ..............................................................................................................16
Chapter 2
Pins and Connections
2.1 Introduction .....................................................................................................................................17
2.2 Device Pin Assignment ...................................................................................................................17
2.3 Recommended System Connections ...............................................................................................18
2.4 Pin Detail .........................................................................................................................................18
2.4.1 Power ..............................................................................................................................19
2.4.2 PTA2/KBIP2/TCLK/RESET/VPP ........................................................................................................ 19
2.4.3 PTA3/ACMPO/BKGD/MS ............................................................................................19
2.4.4 General-Purpose I/O and Peripheral Ports .....................................................................20
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................21
3.2 Features ...........................................................................................................................................21
3.3 Run Mode ........................................................................................................................................21
3.4 Active Background Mode ...............................................................................................................21
3.5 Wait Mode .......................................................................................................................................22
3.6 Stop Mode .......................................................................................................................................23
3.6.1 Active BDM Enabled in Stop Mode ..............................................................................24
3.6.2 LVD Enabled in Stop Mode ...........................................................................................24
Chapter 4
Memory
4.1 Memory Map ...................................................................................................................................25
4.2 Unimplemented Memory ................................................................................................................27
4.3 Indexed/Indirect Addressing ...........................................................................................................27
4.4 RAM and Register Addresses and Bit Assignments .......................................................................27
4.5 RAM ................................................................................................................................................29
4.6 Flash ................................................................................................................................................29
4.6.1 Features ...........................................................................................................................29
4.6.2 Flash Programming Procedure .......................................................................................30
4.6.3 Flash Mass Erase Operation ...........................................................................................30
Table of Contents
Section Number Title Page
MC9RS08KA2 Series Data Sheet, Rev. 4
10 Freescale Semiconductor
Section Number Title Page
4.6.4 Security ...........................................................................................................................31
4.7 Flash Registers and Control Bits .....................................................................................................32
4.7.1 Flash Options Register (FOPT and NVOPT) .................................................................32
4.7.2 Flash Control Register (FLCR) ......................................................................................33
4.8 Page Select Register (PAGESEL) ...................................................................................................33
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction .....................................................................................................................................35
5.2 Features ...........................................................................................................................................35
5.3 MCU Reset ......................................................................................................................................35
5.4 Computer Operating Properly (COP) Watchdog .............................................................................36
5.5 Interrupts .........................................................................................................................................36
5.6 Low-Voltage Detect (LVD) System ................................................................................................37
5.6.1 Power-On Reset Operation .............................................................................................37
5.6.2 LVD Reset Operation .....................................................................................................37
5.6.3 LVD Interrupt Operation ................................................................................................37
5.7 Real-Time Interrupt (RTI) ...............................................................................................................37
5.8 Reset, Interrupt, and System Control Registers and Control Bits ...................................................38
5.8.1 System Reset Status Register (SRS) ...............................................................................38
5.8.2 System Options Register (SOPT) ...................................................................................39
5.8.3 System Device Identification Register (SDIDH, SDIDL) .............................................40
5.8.4 System Real-Time Interrupt Status and Control Register (SRTISC) .............................41
5.8.5 System Power Management Status and Control 1 Register (SPMSC1) .........................43
5.8.6 System Interrupt Pending Register (SIP1) .....................................................................44
Chapter 6
Parallel Input/Output Control
6.1 Pin Behavior in Low-Power Modes ................................................................................................46
6.2 Parallel I/O Registers ......................................................................................................................46
6.2.1 Port A Registers ..............................................................................................................46
6.3 Pin Control Registers ......................................................................................................................47
6.3.1 Port A Pin Control Registers ..........................................................................................47
6.3.1.1 Internal Pulling Device Enable .......................................................................47
6.3.1.2 Pullup/Pulldown Control ................................................................................48
6.3.1.3 Output Slew Rate Control Enable ...................................................................48
Chapter 7
Keyboard Interrupt (RS08KBIV1)
7.1 Introduction .....................................................................................................................................51
7.1.1 Features ...........................................................................................................................51
7.1.2 Modes of Operation ........................................................................................................52
7.1.2.1 Operation in Wait Mode ..................................................................................52
7.1.2.2 Operation in Stop Mode ..................................................................................52
7.1.2.3 Operation in Active Background Mode ..........................................................52
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 11
Section Number Title Page
7.1.3 Block Diagram ................................................................................................................52
7.2 External Signal Description ............................................................................................................52
7.3 Register Definition ..........................................................................................................................53
7.3.1 KBI Status and Control Register (KBISC) .....................................................................53
7.3.2 KBI Pin Enable Register (KBIPE) .................................................................................54
7.3.3 KBI Edge Select Register (KBIES) ................................................................................54
7.4 Functional Description ....................................................................................................................55
7.4.1 Edge Only Sensitivity .....................................................................................................55
7.4.2 Edge and Level Sensitivity .............................................................................................55
7.4.3 KBI Pullup/Pulldown Device .........................................................................................55
7.4.4 KBI Initialization ............................................................................................................55
Chapter 8
Central Processor Unit (RS08CPUV1)
8.1 Introduction .....................................................................................................................................57
8.2 Programmer’s Model and CPU Registers .......................................................................................57
8.2.1 Accumulator (A) .............................................................................................................58
8.2.2 Program Counter (PC) ....................................................................................................59
8.2.3 Shadow Program Counter (SPC) ....................................................................................59
8.2.4 Condition Code Register (CCR) .....................................................................................59
8.2.5 Indexed Data Register (D[X]) ........................................................................................60
8.2.6 Index Register (X) ..........................................................................................................60
8.2.7 Page Select Register (PAGESEL) ..................................................................................61
8.3 Addressing Modes ...........................................................................................................................61
8.3.1 Inherent Addressing Mode (INH) ..................................................................................61
8.3.2 Relative Addressing Mode (REL) ..................................................................................61
8.3.3 Immediate Addressing Mode (IMM) .............................................................................62
8.3.4 Tiny Addressing Mode (TNY) .......................................................................................62
8.3.5 Short Addressing Mode (SRT) .......................................................................................63
8.3.6 Direct Addressing Mode (DIR) ......................................................................................63
8.3.7 Extended Addressing Mode (EXT) ................................................................................63
8.3.8 Indexed Addressing Mode (IX, Implemented by Pseudo Instructions) .........................63
8.4 Special Operations ...........................................................................................................................63
8.4.1 Reset Sequence ...............................................................................................................64
8.4.2 Interrupts .........................................................................................................................64
8.4.3 Wait and Stop Mode .......................................................................................................64
8.4.4 Active Background Mode ............................................................................................... 64
8.5 Summary Instruction Table .............................................................................................................65
MC9RS08KA2 Series Data Sheet, Rev. 4
12 Freescale Semiconductor
Section Number Title Page
Chapter 9
Internal Clock Source (RS08ICSV1)
9.1 Introduction .....................................................................................................................................75
9.1.1 Features ...........................................................................................................................76
9.1.2 Modes of Operation ........................................................................................................76
9.1.2.1 FLL Engaged Internal (FEI) ...........................................................................76
9.1.2.2 FLL Bypassed Internal (FBI) ..........................................................................76
9.1.2.3 FLL Bypassed Internal Low Power (FBILP) .................................................76
9.1.2.4 Stop (STOP) ....................................................................................................76
9.1.3 Block Diagram ................................................................................................................76
9.2 External Signal Description ............................................................................................................77
9.3 Register Definition ..........................................................................................................................77
9.3.1 ICS Control Register 1 (ICSC1) .....................................................................................77
9.3.2 ICS Control Register 2 (ICSC2) .....................................................................................78
9.3.3 ICS Trim Register (ICSTRM) ........................................................................................79
9.3.4 ICS Status and Control (ICSSC) ....................................................................................79
9.4 Functional Description ....................................................................................................................80
9.4.1 Operational Modes .........................................................................................................80
9.4.1.1 FLL Engaged Internal (FEI) ...........................................................................80
9.4.1.2 FLL Bypassed Internal (FBI) ..........................................................................80
9.4.1.3 FLL Bypassed Internal Low Power (FBILP) .................................................80
9.4.1.4 Stop .................................................................................................................81
9.4.2 Mode Switching ..............................................................................................................81
9.4.3 Bus Frequency Divider ...................................................................................................81
9.4.4 Low Power Bit Usage ..................................................................................................... 81
9.4.5 Internal Reference Clock ................................................................................................81
9.4.6 Fixed Frequency Clock ................................................................................................... 82
Chapter 10
Analog Comparator (RS08ACMPV1)
10.1 Introduction .....................................................................................................................................83
10.1.1 Features ...........................................................................................................................84
10.1.2 Modes of Operation ........................................................................................................84
10.1.2.1 Operation in Wait Mode ..................................................................................84
10.1.2.2 Operation in Stop Mode ..................................................................................84
10.1.2.3 Operation in Active Background Mode ..........................................................84
10.1.3 Block Diagram ................................................................................................................84
10.2 External Signal Description ............................................................................................................86
10.3 Register Definition ..........................................................................................................................86
10.3.1 ACMP Status and Control Register (ACMPSC) ............................................................86
10.4 Functional Description ....................................................................................................................87
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 13
Section Number Title Page
Chapter 11
Modulo Timer (RS08MTIMV1)
11.1 Introduction .....................................................................................................................................89
11.1.1 Features ...........................................................................................................................90
11.1.2 Modes of Operation ........................................................................................................90
11.1.2.1 Operation in Wait Mode ..................................................................................90
11.1.2.2 Operation in Stop Modes ................................................................................90
11.1.2.3 Operation in Active Background Mode ..........................................................90
11.1.3 Block Diagram ................................................................................................................91
11.2 External Signal Description ............................................................................................................91
11.3 Register Definition ..........................................................................................................................91
11.3.1 MTIM Status and Control Register (MTIMSC) .............................................................92
11.3.2 MTIM Clock Configuration Register (MTIMCLK) ......................................................93
11.3.3 MTIM Counter Register (MTIMCNT) ..........................................................................93
11.3.4 MTIM Modulo Register (MTIMMOD) .........................................................................94
11.4 Functional Description ....................................................................................................................95
11.4.1 MTIM Operation Example .............................................................................................96
Chapter 12
Development Support
12.1 Introduction .....................................................................................................................................97
12.2 Features ...........................................................................................................................................97
12.3 RS08 Background Debug Controller (BDC) ..................................................................................98
12.3.1 BKGD Pin Description ...................................................................................................99
12.3.2 Communication Details ..................................................................................................99
12.3.3 SYNC and Serial Communication Timeout .................................................................102
12.4 BDC Registers and Control Bits ...................................................................................................103
12.4.1 BDC Status and Control Register (BDCSCR) .............................................................103
12.4.2 BDC Breakpoint Match Register ..................................................................................104
12.5 RS08 BDC Commands ..................................................................................................................105
MC9RS08KA2 Series Data Sheet, Rev. 4
14 Freescale Semiconductor
Section Number Title Page
Appendix A
Electrical Characteristics
A.1 Introduction ...................................................................................................................................109
A.2 Absolute Maximum Ratings ..........................................................................................................109
A.3 Thermal Characteristics .................................................................................................................110
A.4 Electrostatic Discharge (ESD) Protection Characteristics ............................................................111
A.5 DC Characteristics .........................................................................................................................111
A.6 Supply Current Characteristics ......................................................................................................115
A.7 Analog Comparator (ACMP) Electricals ......................................................................................117
A.8 Internal Clock Source Characteristics ...........................................................................................117
A.9 AC Characteristics .........................................................................................................................118
A.9.1 Control Timing ...............................................................................................................118
A.10 FLASH Specifications ...................................................................................................................119
Appendix B
Ordering Information and Mechanical Drawings
B.1 Ordering Information ....................................................................................................................123
B.2 Mechanical Drawings ....................................................................................................................123
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 15
Chapter 1
MC9RS08KA2 Series Device Overview
1.1 Overview
The MC9RS08KA2 Series microcontroller unit (MCU) is an extremely low-cost, small pin count device
for home appliances, toys, and small geometry applications. This device is composed of standard on-chip
modules including, a very small and highly efficient RS08 CPU core, 63 bytes RAM, 2K bytes Flash, an
8-bit modulo timer, keyboard interrupt, and analog comparator. The device is available in small 6- and
8-pin packages.
1.2 MCU Block Diagram
The block diagram, Figure 1-1, shows the structure of the MC9RS08KA2 Series MCU.
Figure 1-1. MC9RS08KA2 Series Block Diagram
RS08 CORE
USER
FLASH
USER
RAM
— 63 BYTES
NOTES:
(1) Pins are software configurable with pullup/pulldown device if input port.
(2) Integrated pullup device enabled if reset enabled (RSTPE=1).
(3) These pins are not available in 6-pin package.
POWER AND
PTA
VSS
VDD
INTERNAL CLOCK
SOURCE
BDC
RS08 SYSTEM CONTROL
RTI
CPU
COP
WAKEUP LVD
RESET AND STOP WAKEUP
MODES OF OPERATION
POWER MANAGEMENT
5-BIT KEYBOARD
INTERRUPT MODULE
PTA0/KBIP0/ACMP+
(1)
PTA1/KBIP1/ACMP-
(1)
PTA2/KBIP2/TCLK/RESET/V
PP
(1),( 2)
PTA3/ACMPO/BKGD/MS
ANALOG COMPARATOR
MODULE
MODULO TIMER
MODULE
PTA4/KBIP4
(1),(3)
PTA5/KBIP5
(1), (3)
INTERNAL REGULATOR
(
KBI
)
5
TCLK
ACMP-
ACMP+
ACMPO
(
ICS
)
(
ACMP
)
(
MTIM
)
MC9RS08KA2 — 2048 BYTES
MC9RS08KA1 — 1024 BYTES
Chapter 1 MC9RS08KA2 Series Device Overview
MC9RS08KA2 Series Data Sheet, Rev. 4
16 Freescale Semiconductor
Table 1-1 provides the functional versions of the on-chip modules.
1.3 System Clock Distribution
Figure 1-2. System Clock Distribution Diagram
Figure 1-2 shows a simplified clock connection diagram for the MCU. The bus clock frequency is half of
the ICS output frequency and is used by all of the internal modules.
Table 1-1. Block Versions
Module Version
Analog Comparator (ACMP) 1
Keyboard Interrupt (KBI) 1
Modulo Timer (MTIM) 1
Internal Clock Source (ICS) 1
MTIM
BDC FLASH
ICS
BDCBDC
CPU
SYSTEM CONTROL LOGIC
RTI
RTICLKS
1-kHz
÷2
ICSOUT
ICSFFCLK
ICSIRCLK
FIXED CLOCK (XCLK)
BUS CLOCK
TCLK
COP
÷32
÷2SYNC
1The fixed cloc k (XCLK) is internally synchronized to the bus clock and must not exceed one half of the
bus clock frequency
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 17
Chapter 2
Pins and Connections
2.1 Introduction
This chapter describes signals that connect to package pins. It includes a pinout diagram, a table of signal
properties, and a detailed discussion of signals.
2.2 Device Pin Assignment
Figure 2-1 and Figure 2-3 show the pin assignments in the packages available for the MC9RS08KA2
Series.
Figure 2-1. MC9RS08KA2 Series in 6-Pin DFN
Figure 2-2. MC9RS08KA2 Series in 8-Pin PDIP
PTA2/KBIP2/TCLK/RESET/VPP
PTA3/ACMPO/BKGD/MS
VDD VSS
PTA0/KBIP0/ACMP+
1
2
3
6
5
4
PTA1/KBIP1/ACMP-
1
PTA2/KBIP2/TCLK/RESET/VPP
PTA3/ACMPO/BKGD/MS
VDD
VSS
PTA4/KBIP4
PTA1/KBIP1/ACMP-
PTA0/KBIP0/ACMP+
PTA5/KBIP5
2
3
4
8
7
6
5
Chapter 2 Pins and Connections
MC9RS08KA2 Series Data Sheet, Rev. 4
18 Freescale Semiconductor
Figure 2-3. MC9RS08KA2 Series in 8-Pin Narrow Body SOIC
2.3 Recommended System Connections
Figure 2-4 shows reference connection for background debug and Flash programming.
Figure 2-4. Reference System Connection Diagram
2.4 Pin Detail
This section provides a detailed description of system connections.
PTA2/KBIP2/TCLK/RESET/VPP
PTA3/ACMPO/BKGD/MS
VDD
VSS
PTA4/KBIP4
PTA1/KBIP1/ACMP-
PTA0/KBIP0/ACMP+
PTA5/KBIP5
1
2
3
4
8
7
6
5
CBUK
10 μF
CBY
0.1 μF
VDD
VDD
VDD
VSS
BKGD/MS
RESET/VPP
PTA0/KBIP0/ACMP+
PTA1/KBIP1/ACMP-
MC9RS08KA2
BACKGROUND
HEADER
PTA4/KBIP4 (Note 1)
PTA5/KBIP5 (Note 1)
NOTES:
1. This pin is not available in the 6-pin package.
Chapter 2 Pins and Connections
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 19
2.4.1 Power
VDD and VSS are the primary power supply pins for the MCU. This voltage source supplies power to all I/O
buffer circuitry and to an internal voltage regulator. The internal voltage regulator provides a regulated
lower-voltage source to the CPU and other internal circuitry of the MCU.
Typically, application systems have two separate capacitors across the power pins: a bulk electrolytic
capacitor , such as a 10-μF tantalum capacitor , to provide bulk char ge storage for the overall system, and a
bypass capacitor, such as a 0.1-μF ceramic capacitor, located as near to the MCU power pins as practical
to suppress high-frequency noise.
2.4.2 PTA2/KBIP2/TCLK/RESET/VPP
After a power-on reset (POR) into user mode, the PTA2/KBIP2/TCLK/RESET/VPP pin defaults to a
general-purpose input port pin, PTA2. Setting RSTPE in SOPT configures the pin to be the RESET input
pin. After configured as RESET, the pin will remain as RESET until the next POR. The RESET pin can
be used to reset the MCU from an external source when the pin is driven low . When enabled as the RESET
pin (RSTPE = 1), the internal pullup device is automatically enabled.
External VPP voltage (typically 12 V, see Section A.10, “FLASH Specifications”) is required on this pin
when performing Flash programming or erasing. The VPP connection is always connected to the internal
Flash module regardless of the pin function. To avoid over stressing the Flash, external VPP voltage must
be removed and voltage higher than VDD must be avoided when Flash programming or erasing is not
taking place.
NOTE
This pin does not contain a clamp diode to VDD and should not be driven
above VDD when Flash programming or erasing is not taking place.
2.4.3 PTA3/ACMPO/BKGD/MS
The background / mode select function is shared with an output-only pin on PTA3 pin and the optional
analog comparator output. While in reset, the pin functions as a mode select pin. Immediately after reset
rises, the pin functions as the background pin and can be used for background debug communication.
While functioning as a background / mode select pin, this pin has an internal pullup device enabled. T o use
as an output-only port, BKGDPE in SOPT must be cleared.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header , it can hold BKGD/MS low
during the power-on-reset, which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock equals the bus clock rate; therefore, no significant capacitance should connected to the BKGD/MS
pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
Chapter 2 Pins and Connections
MC9RS08KA2 Series Data Sheet, Rev. 4
20 Freescale Semiconductor
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.
2.4.4 General-Purpose I/O and Peripheral Ports
The remaining pins are shared among general-purpose I/O and on-chip peripheral functions such as timers
and analog comparator. Immediately after reset, all of these pins are configured as high-impedance
general-purpose inputs with internal pullup/pulldown devices disabled.
NOTE
To avoid extra current drain from floating input pins, the reset initialization
routine in the application program should either enable on-chip
pullup/pulldown devices or change the direction of unused pins to outputs.
Table 2-1. Pin Sharing Reference
Pin Name Direction Pullup/Pulldown1
1SWC is software-controlled pullup/pulldown resistor; the register is asso ciated with the respective port .
Alternative Functions2
2Alternative functions are listed lowest prio rity first. For example, GPIO is the lowest priority alte rnative function of the
PTA0 pin; ACMP+ is the highest priority alternative function of the PTA0 pin.
VDD —— Power
VSS — — Ground
PTA0 I/O SWC PTA0
KBIP0
ACMP+
General-purpose input/output (GPIO)
Keyboard interrupt (stop/wait wakeup only)
Analog compa rator input
PTA1 I/O SWC PTA1
KBIP1
ACMP-
General-purpose input/output (GPIO)
Keyboard interrupt (stop/wait wakeup only)
Analog comparator input
PTA2 I SWC4PTA2
KBIP2
TCLK
RESET
VPP
General-purpose input
Keyboard interrupt (stop/wait wakeup only)
Modulo timer clock source
Reset
VPP
PTA3 I/O3
3Output-only when configured as PTA3 function.
—4
4When PTA2 or PTA3 is configured as RESET or BKGD/MS, respectively, pullup is enabled. When VPP is attached,
pullup/pulldown is disabled automatically.
PTA3
ACMPO
BKGD
MS
General-purpose output
Analog comparator output
Background debug data
Mode select
PTA45
5This pin is not availab le in 6-pin package. Enabling either the pullup or pulldown device is recommended to prev ent extr a
current leakage from the floating input pin.
I/O SWC PTA4
KBIP4 General-purpose input/output (GPIO)
Keyboard interrupt (stop/wait wakeup only)
PTA55I/O SWC PTA5
KBIP5 General-purpose input/output (GPIO)
Keyboard interrupt (stop/wait wakeup only)
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 21
Chapter 3
Modes of Operation
3.1 Introduction
This chapter describes the operating modes of the MC9RS08KA2 Series are described in this chapter. It
also details entry into each mode, exit from each mode, and functionality while in each of the modes.
3.2 Features
• Active background mode for code development
• Wait mode:
— CPU shuts down to conserve power
— System clocks continue to run
— Full voltage regulation is maintained
• Stop mode:
— System clocks are stopped; voltage regulator in standby
— All internal circuits remain powered for fast recovery
3.3 Run Mode
This is the normal operating mode for the MC9RS08KA2 Series. This mode is selected when the
BKGD/MS pin is high at the rising edge of reset. In this mode, the CPU executes code from internal
memory with execution beginning at the address $3FFD. A JMP instruction (opcode $BC) with operand
located at $3FFE–$3FFF must be programmed for correct reset operation into the user application. The
operand defines the location at which the user program will start. Instead of using the vector fetching
process as in HC08/S08 families, the user program is responsible for performing a JMP instruction to
relocate the program counter to the correct user program start location.
3.4 Active Background Mode
The active background mode functions are managed through the background debug controller (BDC) in
the RS08 core. The BDC provides the means for analyzing MCU operation during software development.
Active background mode is entered in any of four ways:
• When the BKGD/MS pin is low during power-on-reset (POR) or immediately after issuing a
background debug force reset (BDC_RESET) command
• When a BACKGROUND command is received through the BKGD pin
• When a BGND instruction is executed
Chapter 3 Modes of Operation
MC9RS08KA2 Series Data Sheet, Rev. 4
22 Freescale Semiconductor
• When a BDC breakpoint is encountered
After active background mode is entered, the CPU is held in a suspended state waiting for serial
background commands rather than executing instructions from the user application program.
Background commands are of two types:
• Non-intrusive commands, defined as commands that can be issued while the user program is
running, can be issued through the BKGD pin while the MCU is in run mode. Non-intrusive
commands can also be executed when the MCU is in the active background mode. Non-intrusive
commands include:
— Memory access commands
— Memory-access-with-status commands
— BACKGROUND command
• Active background commands, which can be executed only while the MCU is in active background
mode, include commands to:
— Read or write CPU registers
— Trace one user program instruction at a time
— Leave active background mode to return to the user application program (GO)
Active background mode is used to program user application code into the Flash program memory before
the MCU is operated in run mode for the first time. When the MC9RS08KA2 Series is shipped from the
Freescale Semiconductor factory, the Flash program memory is usually erased so there is no program that
could be executed in run mode until the Flash memory is initially programmed. The active background
mode can also be used to erase and reprogram the Flash memory after it has been previously programmed.
For additional information about the active background mode, refer to the Development Support chapter
of this data sheet.
3.5 Wait Mode
Wait mode is entered by executing a WAIT instruction. Upon execution of the WAIT instruction, the CPU
enters a low-power state in which it is not clocked. The program counter (PC) is halted at the position
where the WAIT instruction is executed. When an interrupt request occurs:
1. MCU exits wait mode and resumes processing.
2. PC is incremented by one and fetches the next instruction to be processed.
It is the responsibility of the user program to probe the corresponding interrupt source that woke the MCU,
because no vector fetching process is involved.
While the MCU is in wait mode, not all background debug commands can be used. Only the
BACKGROUND command and memory-access-with-status commands are available when the MCU is in
wait mode. The memory-access-with-status commands do not allow memory access, but they report an
error indicating that the MCU is in either stop or wait mode. The BACKGROUND command can be used
to wake the MCU from wait mode and enter active background mode.
Chapter 3 Modes of Operation
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 23
Table 3-1 summarizes the behavior of the MCU in wait mode.
3.6 Stop Mode
Stop mode is entered upon execution of a STOP instruction when the STOPE bit in the system option
register is set. In stop mode, all internal clocks to the CPU and the modules are halted. If the ST OPE bit is
not set when the CPU executes a STOP instruction, the MCU will not enter stop mode and an illegal
opcode reset is forced.
Table 3-2 summarizes the behavior of the MCU in stop mode.
Upon entering stop mode, all of the clocks in the MCU are halted. The ICS is turned of f by default when
the IREFSTEN bit is cleared and the voltage regulator is put in standby. The states of all of the internal
registers and logic, as well as the RAM content, are maintained. The I/O pin states are held.
Exit from stop is done by asserting RESET, any asynchronous interrupt that has been enabled, or the
real-time interrupt. The asynchronous interrupts are the KBI pins, LVD interrupt, or the ACMP interrupt.
If stop is exited by asserting the RESET pin, the MCU will be reset and program execution starts at
location $3FFD. If exited by means of an asynchronous interrupt or real-time interrupt, the next instruction
after the location where the STOP instruction was executed will be executed accordingly. It is the
responsibility of the user program to probe for the corresponding interrupt source that woke the CPU.
A separate self-clocked source (≈1 kHz) for the real-time interrupt allows a wakeup from stop mode with
no external components. When RTIS = 000, the real-time interrupt function and the 1-kHz source are
disabled. Power consumption is lower when the 1-kHz source is disabled, but in that case, the real-time
interrupt cannot wake the MCU from stop.
The trimmed 32-kHz clock in the ICS module can also be enabled for the real-time interrupt to allow a
wakeup from stop mode with no external components. The 32-kHz clock reference is enabled by setting
Table 3-1. Wait Mode Behavior
Mode CPU Digital
Peripherals ICS ACMP Regulator I/O Pins RTI
Wait Standby Optionally on On Optionally
on On States held Optionally on
Table 3-2. Stop Mode Behavior
Mode CPU Digital
Peripherals ICS1
1ICS requires IREFSTEN = 1 and LVDE and LVDSE must be set to allow operation in stop.
ACMP2
2If bandgap reference is required, the LVDE and LVDSE bits in the SPMSC1 must both be set before entering
stop.
Regulator I/O Pins RTI3
3If the 32-kHz trimmed clock in the ICS module is selected as the clock source f or the RTI, LVDE and LVDSE bits
in the SPMSC1 must both be set before entering stop.
Stop Standby Standby Optionally
on Optionally
on Standby States held Optionally on
Chapter 3 Modes of Operation
MC9RS08KA2 Series Data Sheet, Rev. 4
24 Freescale Semiconductor
the IREFSTEN bit. For the ICS to run in stop, the LVDE and LVDSE bits in the SPMSC1 must both be
set before entering stop.
3.6.1 Active BDM Enabled in Stop Mode
Entry into active background mode from run mode is enabled if the ENBDM bit in BDCSCR is set. This
register is described in the Development Support chapter of this data sheet. If ENBDM is set when the CPU
executes a STOP instruction, the system clocks to the background debug logic remain active when the
MCU enters stop mode so background debug communication is still possible. In addition, the voltage
regulator does not enter its low-power standby state; it maintains full internal regulation.
Most background commands are not available in stop mode. The memory-access-with-status commands
do not allow memory access, but they report an error indicating that the MCU is in either stop or wait
mode. The BACKGROUND command can be used to wake the MCU from stop and enter active
background mode if the ENBDM bit is set. After active background mode is entered, all background
commands are available.
Table 3-3 summarizes the behavior of the MCU in stop when entry into the active background mode is
enabled.
3.6.2 LVD Enabled in Stop Mode
The LVD system is capable of generating either an interrupt or a reset when the supply voltage drops below
the LVD voltage. If the LVD is enabled in stop (LVDE and LVDSE bits in SPMSC1 both set) at the time
the CPU executes a STOP instruction, the voltage regulator remains active.
Table 3-4 summarizes the behavior of the MCU in stop when LVD reset is enabled.
Table 3-3. BDM Enabled Stop Mode Behavior
Mode CPU Digital
Peripherals ICS ACMP Regulator I/O Pins RTI
Stop Standby Standby On Optionally
on On States held Optionally on
Table 3-4. LVD Enab led Stop Mode Behavior
Mode CPU Digital
Peripherals ICS ACMP Regulator I/O Pins RTI
Stop Standby Standby Optionally
on Optionally
on On States held Optionally on
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 25
Chapter 4
Memory
4.1 Memory Map
The memory map of the MCU is divided into the following groups:
• Fast access RAM using tiny and short instructions ($0000–$000E1)
• Indirect data access D[X] ($000E)
• Index register X for D[X] ($000F)
• Frequently used peripheral registers ($0010–$001E)
• PAGESEL register ($001F)
• RAM ($0020–$004F)
• Paging window ($00C0–$00FF)
• Other peripheral registers ($0200–$023F)
• Nonvolatile memory
— MC9RS08KA2: $3800–$3FFF
— MC9RS08KA1: $3C00—$3FFF
1. Physical RAM in $000E can be ac cessed through the D[X] register when the content of the inde x register X is $0E.
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
26 Freescale Semiconductor
Figure 4-1. MC9RS08KA2 Series Memory Maps
D[X]
REGISTER X
FAST ACCESS RAM
14 BYTES
FREQUENTLY USED REGISTERS
HIGH PAGE REGISTERS
$000E
$000F
$0000
$000D
$0010
$001E
$0200
$023F
RAM
48 BYTES
$0020
$004F
PAGING WINDOW
$00C0
$00FF
FLASH
$3800
$3FFB
2044 BYTES
UNIMPLEMENTED
UNIMPLEMENTED
NVOPT
$3FFC
$3FFD
$3FFF
FLASH
PAGESEL
$001F
UNIMPLEMENTED
PAGE REGISTER
$00
$08 (reset value)
$E0
CONTENT
MC9RS08KA2 MC9RS08KA1
D[X]
REGISTER X
FAST ACCESS RAM
14 BYTES
FREQUENTLY USED REGISTERS
HIGH PAGE REGISTERS
$000E
$000F
$0000
$000D
$0010
$001E
$0200
$023F
RAM
48 BYTES
$0020
$004F
PAGING WINDOW
$00C0
$00FF
FLASH
$3C00
$3FFB 1020 BYTES
UNIMPLEMENTED
UNIMPLEMENTED
NVOPT
$3FFC
$3FFD
$3FFF
FLASH
PAGESEL
$001F
UNIMPLEMENTED
PAGE REGISTER
$00
$08 (reset value)
$F0
CONTENT
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 27
4.2 Unimplemented Memory
Attempting to access either data or an instruction at an unimplemented memory address will cause reset.
4.3 Inde xed/Indirect Addressing
Register D[X] and register X together perform the indirect data access. Register D[X] is mapped to address
$000E. Register X is located in address $000F. The 8-bit register X contains the address that is used when
register D[X] is accessed. Register X is cleared to zero upon reset. By programming register X, any
location on the first page ($0000–$00FF) can be read/written via register D[X]. Figure 4-2 shows the
relationship between D[X] and register X. For example, in HC08/S08 syntax lda ,x is comparable to lda
D[X] in RS08 coding when register X has been programmed with the index value.
The physical location of $000E is in RAM. Accessing the location through D[X] returns $000E RAM
content when register X contains $0E. The physical location of $000F is register X, itself. Reading the
location through D[X] returns register X content; writing to the location modifies register X.
Figure 4-2. Indirect Addressing Registers
4.4 RAM and Register Addresses and Bit Assignments
The fast access RAM area can be accessed by instructions using tiny, short, and direct addressing mode
instructions. For tiny addressing mode instructions, the operand is encoded along with the opcode to a
single byte.
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
28 Freescale Semiconductor
Frequently used registers can make use of the short addressing mode instructions for faster load, store, and
clear operations. For short addressing mode instructions, the operand is encoded along with the opcode to
a single byte. Table 4-1. Register Summary
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
$0000–
$000D Fast Access RAM
$000E D[X]1Bit 7654321Bit 0
$000F X Bit 7 6 5 4 3 2 1 Bit 0
$0010 PTAD 00 PTAD5 PTAD4 PTAD3 PTAD2 PTAD1 PTAD0
$0011 PTADD 00 PTADD5 PTADD4 00 PTADD1 PTADD0
$0012 Unimplemented — — — — — — — —
$0013 ACMPSC ACME ACBGS ACF ACIE ACO ACOPE ACMOD
$0014 ICSC1 0CLKS00000IREFSTEN
$0015 ICSC2 BDIV 00LP0 0 0
$0016 ICSTRM TRIM
$0017 ICSSC 0 0 0 0 0CLKST0FTRIM
$0018 MTIMSC TOF TOIE TRST TSTP 0 0 0 0
$0019 MTIMCLK 00CLKS PS
$001A MTIMCNT COUNT
$001B MTIMMOD MOD
$001C KBISC 0000 KBF KBACK KBIE KBIMOD
$001D KBIPE —— KBIPE5 KBIPE4 — KBIPE2 KBIPE1 KBIPE0
$001E KBIES —— KBEDG5 KBEDG4 — KBEDG2 KBEDG1 KBEDG0
$001F PAGESEL AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6
$0020–
$004F RAM
$0050–
$00BF Unimplemented — — — — — — — —
$00C0–
$00FF Paging Window
$0100–
$01FF Unimplemented — — — — — — — —
$0200 SRS POR PIN COP ILOP ILAD 0LVD0
$0201 SOPT COPE COPT STOPE 0 0 0 BKGDPE RSTPE
$0202 SIP1 ——— KBI ACMP MTIM RTI LVD
$0203 Unimplemented — — — — — — — —
$0204 Reserved — — — — — — — —
$0205 Unimplemented — — — — — — — —
$0206 SDIDH REV3 REV2 REV1 REV0 ID
$0207 SDIDL ID
$0208 SRTISC RTIF RTIACK RTICLKS RTIE 0RTIS
$0209 SPMSC1 LVDF LVDACK LVDIE LVDRE LVDSE LVDE 0BGBE
$020A Reserved — — — — — — — —
$020B Reserved — — — — — — — —
= Unimplemented or Reserved
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 29
4.5 RAM
The device includes two sections of static RAM. The locations from $0000 to $000D can be directly
accessed using the more efficient tiny addressing mode instructions and short addressing mode
instructions. Location $000E RAM can either be accessed through D[X] register when register X is $0E
or through the paging window location $00CE when PAGESEL register is $00. The second section of
RAM starts from $0020 to $004F, and it can be accessed using direct addressing mode instructions.
The RAM retains data when the MCU is in low-power wait and stop mode. RAM data is unaffected by
any reset provided that the supply voltage does not drop below the minimum value for RAM retention.
4.6 Flash
The Flash memory is intended primarily for program storage. In-circuit programming allows the operating
program to be loaded into the Flash memory after final assembly of the application product. It is possible
to program the entire array through the single-wire background debug interface. Because the device does
not include on-chip charge pump circuitry, external VPP is required for program and erase operations.
4.6.1 Features
Features of the Flash memory include:
$020C–
$020F Unimplemented — — — — — — — —
$0210 FOPT 0000000 SECD
$0211 FLCR 0000 HVEN MASS 0PGM
$0212–
$0213 Reserved — — — — — — — —
$0214–
$021F Unimplemented —
——
——
——
——
——
——
——
—
$0220 PTAPE 00 PTAPE5 PTAPE4 0 PTAPE2 PTAPE1 PTAPE0
$0221 PTAPUD 00 PTAPUD5 PTAPUD4 0 PTAPUD2 PTAPUD1 PTAPUD0
$0222 PTASE 00 PTASE5 PTASE4 PTASE3 0 PTASE1 PTASE0
$0223–
$023F Unimplemented — — — — — — — —
$3FF8 Reserved — — — — — — — —
$3FF9 Reserved — — — — — — — —
$3FFA2Reserved Reserved for Room Temperature ICS Trim
$3FFB2Reserved Reserved FTRIM
$3FFC NVOPT 0000000 SECD
1Physical RAM in $000E can be accessed through D[X] register when the conte nt of the index register X is $0E.
2If using the MCU untrimmed, $3FFA and $3FFB ma y be used by applications.
Table 4-1. Register Summary (continued)
Address Register Name Bit 7 6 5 4 3 2 1 Bit 0
= Unimplemented or Reserved
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
30 Freescale Semiconductor
• Up to 1000 program/erase cycles at typical voltage and temperature
• Security feature for Flash
4.6.2 Flash Programming Procedure
Programming of Flash memory is done on a row basis. A row consists of 64 consecutive bytes starting
from addresses $3X00, $3X40, $3X80, or $3XC0. Use the following procedure to program a row of Flash
memory:
1. Apply external VPP.
2. Set the PGM bit. This configures the memory for program operation and enables the latching of
address and data for programming.
3. Write any data to any Flash location, via the high page accessing window $00C0–$00FF, within
the address range of the row to be programmed. (Prior to the data writing operation, the PAGESEL
register must be configured correctly to map the high page accessing window to the corresponding
Flash row).
4. Wait for a time, tnvs.
5. Set the HVEN bit.
6. Wait for a time, tpgs.
7. Write data to the Flash location to be programmed.
8. Wait for a time, tprog.
9. Repeat steps 7 and 8 until all bytes within the row are programmed.
10. Clear the PGM bit.
11. Wait for a time, tnvh.
12. Clear the HVEN bit.
13. After time, trcv, the memory can be accessed in read mode again.
14. Remove external VPP.
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Flash memory cannot be programmed or erased by software code executed
from Flash locations. To program or erase Flash, commands must be
executed from RAM or BDC commands. User code should not enter wait or
stop during erase or program sequence.
These operations must be performed in the order shown; other unrelated
operations may occur between the steps.
4.6.3 Flash Mass Erase Operation
Use the following procedure to mass erase the entire Flash memory:
1. Apply external VPP.
2. Set the MASS bit in the Flash control register.
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 31
3. W rite any data to any Flash location, via the high page accessing window $00C0–$00FF. (Prior to
the data writing operation, the PAGESEL register must be configured correctly to map the high
page accessing window to the any Flash locations).
4. Wait for a time, tnvs.
5. Set the HVEN bit.
6. Wait for a time tme.
7. Clear the MASS bit.
8. Wait for a time, tnvh1.
9. Clear the HVEN bit.
10. After time, trcv, the memory can be accessed in read mode again.
11. Remove external VPP.
NOTE
Flash memory cannot be programmed or erased by software code executed
from Flash locations. To program or erase Flash, commands must be
executed from RAM or BDC commands. User code should not enter wait or
stop during an erase or program sequence.
These operations must be performed in the order shown, but other unrelated
operations may occur between the steps.
4.6.4 Security
The MC9RS08KA2 Series includes circuitry to help prevent unauthorized access to the contents of Flash
memory . When security is engaged, Flash is considered a secure resource. The RAM, direct-page registers,
and background debug controller are considered unsecured resources. Attempts to access a secure memory
location through the background debug interface, or whenever BKGDPE is set, are blocked (reads return
all 0s).
Security is engaged or disengaged based on the state of a nonvolatile register bit (SECD) in the FOPT
register. During reset, the contents of the nonvolatile location NVOPT are copied from Flash into the
working FOPT register in high-page register space. A user engages s ecurity by programming the NVOPT
location, which can be done at the same time the Flash memory is programmed. Notice the erased state
(SECD = 1) makes the MCU unsecure. When SECD in NVOPT is programmed (SECD = 0), next time
the device is reset via POR, internal reset, or external reset, security is engaged. In order to disengage
security, mass erase must be performed via BDM commands and followed by any reset.
The separate background debug controller can still be used for registers and RAM access. Flash mass erase
is possible by writing to the Flash control register that follows the Flash mass erase procedure listed in
Section 4.6.3, “Flash Mass Erase Operation,” via BDM commands.
Security can always be disengaged through the background debug interface by following these steps:
1. Mass erase Flash via background BDM commands or RAM loaded program.
2. Perform reset and the device will boot up with security disengaged.
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
32 Freescale Semiconductor
NOTE
When the device boots up to normal operating mode, where MS pin is high
during reset, with SECD programmed (SECD = 0), Flash security is
engaged. BKGDPE is reset to 0, and all BDM communication is blocked,
and background debug is not allowed.
4.7 Flash Registers and Control Bits
The Flash module has a nonvolatile register, NVOPT ($3FFC), in Flash memory which is copied into the
corresponding control register, FOPT ($0210), at reset.
4.7.1 Flash Options Register (FOPT and NVOPT)
During reset, the contents of the nonvolatile location NVOPT is copied from Flash into FOPT. Bits 7
through 1 are not used and always read 0. This register may be read at any time, but writes have no meaning
or effect. To change the value in this register, erase and reprogram the NVOPT location in Flash memory
as usual and then issue a new MCU reset.
76543210
R0000000SECD
W
Reset This register is loaded from nonvolatile location NVOPT during reset.
= Unimplemented or Reserved
Figure 4-3. Flash Options Register (FOPT)
Table 4-2. FOPT Field Descriptions
Field Description
0
SECD Security State Code — This bit field determines the security state of the MCU . When the MCU is secured, the
contents of Flash memory cannot be accessed by instr uctions from any unsecured source including the
background debug interface; refer to Section 4.6.4, “Security”.
0 Security engaged.
1 Security disengaged.
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
Freescale Semiconductor 33
4.7.2 Flash Control Register (FLCR)
4.8 Page Select Register (PAGESEL)
There is a 64-byte window ($00C0–$00FF) in the direct-page reserved for paging access. Programming
the page select register determines the corresponding 64-byte block on the memory map for direct-page
access. For example, when the PAGESEL register is programmed with value $08, the high page registers
($0200–$023F) can be accessed through the paging window ($00C0–$00FF) via direct addressing mode
instructions.
76543210
R0000
HVEN MASS 0PGM1
W
Reset00000000
= Unimplemented or Reserved
Figure 4-4. Flash Control Register (FLCR)
Table 4-3. FLCR Field Descriptions
Field Description
3
HVEN High Voltage Enable — This read/write bit enables high voltages to the Flash array f or prog ram and erase
operations. HVEN can be set only if either PGM = 1 or MASS = 1 and the proper sequence for program or erase
is followed.
0 High voltage disabled to array.
1 High voltage enabled to array.
2
MASS Mass Erase Control Bit — This read/write bit configures the memory for mass erase operation.
0 Mass erase operation not selected.
1 Mass erase operation selected.
0
PGM1
1When Flash secur ity is engag ed, writing to PGM bit has no effect. As a result, Flash programming is not allowed.
Program Control Bit — This read/write bit configures the memory for progr am oper ation. PGM is interlocked
with the MASS bit such that both bits cannot be equal to 1 or set to 1 at the same time.
0 Prog ram operation not selected.
1 Program operation selected.
76543210
RAD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6
W
Reset00001000
Figure 4-5. Page Select Register (PAGESEL)
Table 4-4. PAGESEL Field Descriptions
Field Description
7:0
AD[13:6] P age Selector— These bits define the address line bit 6 to bit 13, which determines the 64-byte bloc k boundary
of the memory block accessed via the direct page window. See Figure 4-6 and Table 4-5.
Chapter 4 Memory
MC9RS08KA2 Series Data Sheet, Rev. 4
34 Freescale Semiconductor
Table 4-5 shows the memory block to be accessed through paging window ($00C0–$00FF).
NOTE
Physical location $0000-$000E is RAM. Physical location $000F is register
X. D[X] register is mapped to address $000E only. The physical RAM in
$000E can be accessing through D[X] register when X register is either $0E
or $CE with PAGESEL is $00.
When PAGESEL register is $00, paging window is mapped to the first page
($00-$3F). Paged location $00C0–$00CE is mapped to physical location
$0000-$000E, i.e., RAM. Paged location $00CF is mapped to register X.
Therefore, accessing address $CE returns the physical RAM content in
$000E, accessing address $000E returns D[X] register content.
14-bit memory address
Start address of memory block selected 000000
AD[13:6]
Figure 4-6. Memory Block Boundary Selector
Table 4-5. Paging Window for $00C0–$00FF
Page Memory Address
$00 $0000–$003F
$01 $0040–$007F
$02 $0080–$00BF
$03 $00C0–$00FF
$04 $0100–$013F
.
.
.
.
.
.
$FE $3F80–$3FBF
$FF $3FC0–$3FFF