Features
•Sensitivity: -162 dBm indoor (tracking mode)
• Interfaces:
– UART and I²C ports
– Configurable digital I/O timepulse
– EXTINT input for wakeup
• NMEA protocol
• Assisted GNSS:
– Predictive autonomous
– Predictive server-based
– Real-time server-based
• Compatible with SPC5
• LNA and SAW filter on the RF path
• SMA female antenna connector
• Battery holder
• Highly compact design: 70 x 65 mm
• Operating supply voltage: 3.3 - 5 V
• Ambient temperature: -40/+85 °C
• Part of the AutoDevKit™ initiative
• RoHS and WEEE compliant
Description
The AEK-COM-GNSST31 evaluation board is based on the certified Teseo-LIV3F
global navigation satellite system (GNSS) module with embedded TeseoIII single die
standalone positioning receiver IC.
The tiny, affordable, and easy-to use module guarantees superior accuracy and
reduced time to first fix (TTFF) thanks to the on-board 26 MHz temperature
compensated crystal oscillator (TCXO) and dedicated 32 KHz real-time clock (RTC)
oscillator.
The evaluation package is used in conjunction with the X-CUBE-GNSS1 firmware to
provide the necessary acquisition, tracking, navigation and data output functionality
without external memory support.
The AEK-COM-GNSST31 evaluation board can be readily connected with an SPC5
MCU for automotive application development as part of the AutoDevKit™ initiative.
Product summary
GNSS evaluation
board based on
Teseo-LIV3F for
SPC5 microcontrollers
AEK-COM-
GNSST31
Tiny GNSS module Teseo-LIV3F
Code generator, quick
resource configurator
and Eclipse
development
environment for SPC5
MCUs
SPC5-STUDIO
AutoDevKit library
plugin for SPC5-
STUDIO
STSW-
AUTODEVKIT
Global navigation
satellite system
software expansion
for STM32Cube
X-CUBE-GNSS1
Applications
Tracking
Smart City
GNSS/GPS
Mobility Services
GNSS evaluation board based on Teseo-LIV3F for SPC5 microcontrollers
AEK-COM-GNSST31
Data brief
DB4131 - Rev 1 - February 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
1Block diagram
Figure 1. AEK-COM-GNSST31 block diagram
AEK-COM-GNSST31
Block diagram
DB4131 - Rev 1 page 2/7
2Schematic diagrams
Figure 2. AEK-COM-GNSST31 schematic diagram (1 of 3)
HEADER1x2
AGND
J3
GND
20
NC/PF6
{Default}
HEADER1x2
22
Arduino
PB8
CN10
NM
11
PB1
CN9
VIN
TX
VDD
J2
PA0
PPS
7
1
1
20
PPS
PA12
31
1
1
HEADER1x2
D1/RX
19
PC10
J12
1
1
CN5
D0/TX
SYS_WAKEUP
21
PA13 PA11
Arduino
SYS_RESETn
PC14
22
PA1
10
D3/PWM
PC3
16
JR9
SHUNT 2.54 mm.
GND
D13/SCK
30
E5V
22
Closed
Open
26
GND
D9/PWM
HEADER1x2
19
NC/PF4
D6/PWM
38
27
16
PB11/NC
HEADER1x2
37
28
3
9
IOREF
910
26
1
J10
17
D7
38
1
2
3
4
5
6
31
30
D6/PWM
D11/MOSI/PWM
28
PA4
PD2
1
1
29
JR11
SHUNT 2.54 mm.
J4
PA15
VLCD/VBAT
29
Pass-Through:
Male on Bottom - Female on Top
Pass-Through:
Male on Bottom - Female on Top
Pass-Through:
Male on Bottom - Female on Top
Pass-Through:
Male on Bottom - Female on Top
GND
9
8
7
6
5
4
3
2
1
PH1/PF1/PD1
PC13
2
CN8
24
78
D8
37
35
8
RX
PH0/PF0/PD0
I2C_DATA
PC2
22
IOREF
PC9
Closed
HEADER1x2
22
23
1
1
Closed
PD8
PA14
27
D9/PWM
HEADER1x2
23
D15/SCL
PC8
D7
D10/CS/PWM
4
Pass-Through:
Female on Bottom - Male on Top Pass-Through:
Female on Bottom - Male on Top
CN7
12
NM
D4
10
J11
HEADER1x2
ST morpho
Closed
BOOT0
IOREF
18
GND
24
22
J9
1
1
17
AVDD
1
1
25
PC0
36
D5/PWM
1
2
3
4
5
6
7
8
34
5
PC1
PC6
PB9
PC15
D14/SDA
PB13
RESET
PC5
HEADER1x2
36
J6
15
+VCC_IO
11
D8
+3V3
+5V
1
1
PB0
I2C_CLOCK
PB2
HEADER1x2
Open
Open
HEADER1x2
22
21
D1/RX
JR13
SHUNT 2.54 mm.
Closed
1
35
22
Open
6
1
1
PB15
32
22
14
PB14
33
PB12
NC/PF7
Open
8
7
6
5
4
3
2
1
SYS_WAKEUP
22
Closed
22
+3V3
5
J13
22
D13/SCK
GND
34
4
1
1
J5
D12/MISO
RX
14
1
1
22
2
J8
15
HEADER1x2
PB7
13
NC/PF5
Open
CN6
PC12
Arduino
12
PC4
JR12
SHUNT 2.54 mm.
25
TX
D0/TX
D2
Arduino
IOREF
1
1
33
32
6
JR4
SHUNT 2.54 mm.
J7
+3V3
{Default}
{Default}
{Default}
{Default}
{Default}
3
D2
D2
22
13
D4
18
U5V
JR3
SHUNT 2.54 mm.
PC11
Bypass
4
1uF 16V
Gnd
7
C29
3
1
33n
Vin
U9
C27
6
N.C.
Vout
Vinh
LDS3985PU33R
2
+5V
Gnd
5
2u2F-16V-0603
C26
R35
SMD0603
SMD0603
10R
SMD0603
R37
N.M. SMD0603
+3V3
N.M.
SMD0603
R36
+VCC_IO
C28
2.2uF 16V
SMD0603
R38
0R0
SMD0603
IOREF
SMD0402
8
2
1
CN11
4
3
6
9
+5V
5
7
+3V3
D8
D2
D7
N.C.
D14/SDA
D15/SCL
ST morpho
SX side DX side
A0
A1
A2
A3
A4
A5
D15/SCL
D14/SDA
PA5
PA6
PA7
PB6
PC7
PA9
PA8
PB10
PB4
PB5
PB3
PA10
PA2
PA3
R39
SMD0603
N.M.
DB4131 - Rev 1 page 3/7
AEK-COM-GNSST31
Schematic diagrams
Figure 3. AEK-COM-GNSST31 schematic diagram (2 of 3)
Closed
VCC_RF
HEADER1x2
GND
AntOFF
13
A
3
1
GND
GND
R2
2K1
Closed
+VCC_IO
1
1
R1
Vant
U8
SN74LV1T126
R9
1k5
NM
IOREF
D2
GND
Red_LED
GND
3
RF_IN
C20
10nF
NM
R8
330R
AntOFF
B4
IOREF
SDA2
16
JR14
SHUNT 2.54 mm.
J15
VCC_RF
14
GND
GND
2
HEADER1x2
+VCC_IO
+VCC_IO
J14
UART_TX
GND
R10
330R
U6
TXB0101DCK
R32 0R0
C16
1µF
Vant
A
2
D3
OE 5
RESETn
GND
GND
GND
VccA
1
GND
A2
4
GND
GND
2
I2C_CLOCK
R2
C13 100nF
SYS_WAKEUP
GND
U1Teseo-LIV3F (SPGNSS-LIV3F)
R33
10K
I2C_DATA
R1
200k NM
C14 100pF
1PPS 4
C24
1µF
R11
0R
Vcc 5
VccB 7Reserved1
15
I2C_CLOCK
GND
GND
U5
TXB0101DCK
PPS
WAKEUP
TX
R30200k
IOREF PPS
A1
5
GND
2
GND
U7
TXB0101DCK
2
GND 1
Vbatt 6
+VCC_IO
22
C23
4.7µF
B1 8
A
3
RESETn
Battery
VccA
3
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0603
SMD0603
SMD0603
SMD0603
SMD0603
SMD0402
SMD0402
SMD0603
SMD0603
SMD0603
SMD0603
SMD0603
SMD0603
SMD0603
VSSOP
SMD0402
SMD0402
SMD0603
SMD0402
SYS_RESETn
RESETn
I2C_SDA
GND
I2C_SCL
WAKEUP
VccA
1
R31
200k NM
3
IOREF
GND
PPS
C19
1µF
Wake-Up 5
SCL2
17
GND
C21
1µF
RX
U4
TXS0102
VccB 6
GND_RF
10
R34
2K1
UART_TX
B4
I2C_DATA
+VCC_IO
+VBatt
JR15
SHUNT 2.54 mm.
OE 1
+VCC_IO
SYS_WAKEUP
OE 6
Q1
MUN2214T1G
AntOFF
UART_RX
VCC 8
VccB 6
C18
1µF
D1
BAT20J
C22
1µF
22
RX 3
Reserved2
18
OE 5
C12
4.7µF
C11
1µF
GND
+VBatt
RESETn 9
RF_IN
11
A
3
GND
C10
1µF
UART_RX
B2 1
VccB 6
GND
VL1
BATTERY HOLDER (CR2032)
GNSS Module
RX
+VCC_IO
RESETn
GND
VCC_IO 7
SYS_RESETn
I2C_SCL
GND
TX 2
1
1
RF_IN
IOREF
B4
Green_LED
GND_RF
12
RESETn
GND
Y4
+VCC_IO
OE 5
I2C_SDA
TX
GND
VCC_RF
TP1
C17
10nF
GND
2
VccA
1
C15
1µF
size SC70
DB4131 - Rev 1 page 4/7
AEK-COM-GNSST31
Schematic diagrams
Figure 4. AEK-COM-GNSST31 schematic diagram (3 of 3)
AI
5
GND
C1
1nF
4
R17
0R
NM
OC
3
L2
56nH
GND
AntOFF
C7
1µF
U2
BGA824N6
PON
GND
Vant
VCCGND-RF
VCC_RF
L1
6.8nH
R21
100k
RF_IN
GND
D4
ESDARF02-1BU2CK
GND
U3
TPS22943
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0603
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0402
SMD0805 SMD0805
SMD0402
C2
120pF
RF In Section
R25 0R0
NM
R29
3R
NM
R15
0R
A0 3
Ant_In
4
6
2
GND
R24
10K
SMD0402
2
R18
0R
NM
Vin 5
GND
C5
3.9pF
NM
R23 0R0
R28 0R0 NM
ON 4
R26 0R0
1
VCC_RF
GND
2
C3
120pF
GND
GND
GND
R22
0R
NM
C9
56pF
1
5
Vout
1
3
R20
0R
GND
CN1
SMA
C8
2.2µF
Z1
B4327
Current_L R27 0R0
DB4131 - Rev 1 page 5/7
AEK-COM-GNSST31
Schematic diagrams
Revision history
Table 1. Document revision history
Date Version Changes
03-Feb-2020 1 Initial release.
AEK-COM-GNSST31
DB4131 - Rev 1 page 6/7
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© 2020 STMicroelectronics – All rights reserved
AEK-COM-GNSST31
DB4131 - Rev 1 page 7/7
