SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com FEATURES * * * * * * * * * * * TI-OPCTM Circuitry Limits Ringing on Unevenly Loaded Backplanes OECTM Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels LVTTL Interfaces Are 5-V Tolerant Medium-Drive GTLP Outputs (50 mA) LVTTL Outputs (-24 mA/24 mA) GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on A-Port Data Inputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) SCES284E - OCTOBER 1999 - REVISED APRIL 2005 DGV, DW, OR PW PACKAGE (TOP VIEW) OE VCC A1 A2 A3 A4 GND A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 DIR VREF B1 B2 B3 B4 GND B5 B6 B7 B8 GND DESCRIPTION/ORDERING INFORMATION The SN74GTLPH306 is a medium-drive, 8-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OECTM circuitry, and TI-OPCTM circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 . GTLP is the Texas Instruments (TITM) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH306 is given only at the preferred higher-noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI-OPC, OEC, TI are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2005, Texas Instruments Incorporated SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E - OCTOBER 1999 - REVISED APRIL 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION PACKAGE (1) TA (1) TOP-SIDE MARKING Tube SN74GTLPH306DW Tape and reel SN74GTLPH306DWR TSSOP - PW Tape and reel SN74GTLPH306PWR GH306 TVSOP - DGV Tape and reel SN74GTLPH306DGVR GH306 SOIC - DW -40C to 85C ORDERABLE PART NUMBER GTLPH306 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. <BR/> FUNCTIONAL DESCRIPTION The SN74GTLPH306 is an 8-bit bus transceiver and is designed for asynchronous communication between data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input. OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting. For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When OE is high, the outputs are in the high-impedance state. The data flow for B to A is similar to A to B, except OE and DIR are low. FUNCTION TABLE INPUTS 2 OUTPUT MODE X Z Isolation L B data to A port H A data to B port OE DIR H L L True transparent SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E - OCTOBER 1999 - REVISED APRIL 2005 LOGIC DIAGRAM (POSITIVE LOGIC) 24 DIR 1 OE A1 22 3 B1 23 VREF To Seven Other Channels Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC MIN MAX -0.5 4.6 A port and control inputs -0.5 7 B port and VREF -0.5 4.6 A port -0.5 7 B port -0.5 4.6 Supply voltage range VI Input voltage range (2) VO Voltage range applied to any output in the high-impedance or power-off state (2) IO Current into any output in the low state IO Current into any A port output in the high state (3) A port 48 B port 100 Continuous current through each VCC or GND UNIT V V V mA 48 mA 100 mA IIK Input clamp current VI < 0 -50 mA IOK Output clamp current VO < 0 -50 mA JA Tstg (1) (2) (3) (4) Package thermal impedance (4) Storage temperature range DGV package 86 DW package 46 PW package 88 -65 150 C/W C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. 3 SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E - OCTOBER 1999 - REVISED APRIL 2005 Recommended Operating Conditions (1) (2) (3) (4) VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage VIL Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current t/v Input transition rise or fall rate t/VCC Power-up ramp rate TA Operating free-air temperature (1) (2) (3) (4) 4 MIN NOM MAX UNIT V 3.15 3.3 3.45 GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 B port VTT Except B port B port Except B port VCC 5.5 VREF + 0.05 VREF - 0.05 Except B port V V V 2 B port V 0.8 V -18 mA A port -24 mA A port 24 B port 50 Outputs enabled 10 ns/V s/V 20 -40 mA 85 C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but generally, GND is connected first. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E - OCTOBER 1999 - REVISED APRIL 2005 Electrical Characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH A port VCC = 3.15 V, II = -18 mA VCC = 3.15 V to 3.45 V, IOH = -100 A VCC - 0.2 IOH = -12 mA 2.4 IOH = -24 mA 2 VCC = 3.15 V VCC = 3.15 V to 3.45 V, A port VOL B port A-port and control inputs II (2) MIN TYP (1) MAX TEST CONDITIONS VCC = 3.15 V VCC = 3.15 V -1.2 IOL = 100 A 0.2 IOL = 12 mA 0.4 IOL = 24 mA 0.5 IOL = 40 mA 0.4 IOL = 50 mA 0.55 V 5 VI = 5.5 V B port V V VI = 0 or VCC VCC = 3.45 V UNIT 20 VI = 0 to 1.5 V A 5 IBHL (3) A port VCC = 3.15 V, VI = 0.8 V 75 A IBHH (4) A port VCC = 3.15 V, VI = 2 V -75 A IBHLO (5) A port VCC = 3.45 V, VI = 0 to VCC 500 A (6) A port VCC = 3.45 V, VI = 0 to VCC -500 IBHHO ICC A or B port ICC Ci Cio (1) (2) (3) (4) (5) (6) (7) VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND, VI (B port) = VTT or GND A Outputs high 20 Outputs low 20 Outputs disabled 20 VCC = 3.45 V, One A-port or control input at VCC - 0.6 V, Other A-port or control inputs at VCC or GND (7) mA 1.5 mA pF Control inputs VI = 3.15 V or 0 4.5 5 A port VO = 3.15 V or 0 7.5 9 B port VO = 1.5 V or 0 7.5 9 pF All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter II includes the off-state output leakage current. The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. An external driver must source at least IBHLO to switch this node from low to high. An external driver must sink at least IBHHO to switch this node from high to low. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Hot-Insertion Specifications for A Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS VCC = 0, VI or VO = 0 to 5.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, MIN MAX UNIT 10 A OE = 0 30 A OE = 0 30 A MAX UNIT Hot-Insertion Specifications for B Port over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS VCC = 0, VI or VO = 0 to 1.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 1.5 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 1.5 V, MIN 10 A OE = 0 30 A OE = 0 30 A 5 SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E - OCTOBER 1999 - REVISED APRIL 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER tPLH tPHL ten tdis tr A B OE B MIN TYP (1) MAX 1 7.5 1 7.5 1 8 1 8 UNIT ns ns Rise time, B outputs (20% to 80%) 2.2 ns tf Fall time, B outputs (80% to 20%) 2.1 ns Rise time, A outputs (10% to 90%) 4.1 ns tf Fall time, A outputs (90% to 10%) 3.3 ns tPHL ten tdis 6 TO (OUTPUT) tr tPLH (1) FROM (INPUT) B A OE A All typical values are at VCC = 3.3 V, TA = 25C. 1 7 1 7 1 8 1 8 ns ns SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E - OCTOBER 1999 - REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 500 From Output Under Test S1 1.5 V 6V Open GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 25 From Output Under Test CL = 30 pF (see Note A) S1 Open 6V GND Test Point LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR A OUTPUTS 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1V Output 1V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1V 0V tPLH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH VOH Output 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 1.5 V tPZL 1.5 V 1V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) tPHZ VOH 1.5 V VOH - 0.3 V 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 7 SN74GTLPH306 8-BIT LVTTL-TO-GTLP BUS TRANSCEIVER www.ti.com SCES284E - OCTOBER 1999 - REVISED APRIL 2005 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 1.5 V 1.5 V 0.25" ZO = 70 2" Conn. Conn. 1" 1" Conn. 1" 2" 0.25" 38 38 1.5 V 19 From Output Under Test Conn. LL = 19 nH 1" Test Point CL = 9 pF Rcvr Rcvr Rcvr Slot 2 Slot 9 Slot 10 Drvr Slot 1 Figure 3. Medium-Drive RLC Network Figure 2. Medium-Drive Test Backplane Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3) PARAMETER tPLH tPHL ten tdis (1) 8 FROM (INPUT) TO (OUTPUT) A B OE B TYP (1) 3.6 4.1 4.4 4.6 UNIT ns ns tr Rise time, B outputs (20% to 80%) 1.2 ns tf Fall time, B outputs (80% to 20%) 2.2 ns All typical values are at VCC = 3.3 V, TA = 25C. All values are derived from TI-SPICE models. PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74GTLPH306DGVRE4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74GTLPH306DGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306DGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306DWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306PW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306PWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306PWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306PWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306PWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLPH306PWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74GTLPH306DGVR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TVSOP DGV 24 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74GTLPH306DWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74GTLPH306PWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74GTLPH306DGVR TVSOP DGV 24 2000 346.0 346.0 29.0 SN74GTLPH306DWR SOIC DW 24 2000 346.0 346.0 41.0 SN74GTLPH306PWR TSSOP PW 24 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C - FEBRUARY 1996 - REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0-8 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. 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