Vishay Siliconix
Si9122E
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
www.vishay.com
1
500-kHz Half-Bridge DC/DC Controller
with Integrated Secondary Synchronous Rectification Drivers
DESCRIPTION
Si9122E is a half-bridge controller IC ideally suited to fixed
telecom applications where high efficiency is required at low
output voltages (e.g. < 3.3 V). Designed to operate within the
fixed telecom voltage range of 36 V to 75 V, the IC is capable
of controlling and driving both the low and high-side switching
devices of a half bridge circuit and also controlling the
switching devices on the secondary side of the bridge. Due
to the very low on-resistance of the secondary MOSFETs, a
significant increase in conversion efficiency can be achieved
as compared with conventional Schottky diodes. Control of
the secondary devices is by means of a pulse transformer
and a pair of inverters. Such a system has efficiencies well in
excess of 90 % even for low output voltages.
On-chip control of the dead time delays between the primary
and secondary synchronous signals keep efficiencies high
and prevent shorting of the power transformer. An external
resistor sets the oscillator frequency from 200 kHz to
500 kHz.
Si9122E has advanced current monitoring and control
circuitry which allow the user to set the maximum current in
the primary circuit. Such a feature acts as protection against
output shorting and also provides constant current into large
capacitive loads during start-up or when paralleling power
supplies. Current sensing is by means of a sense resistor on
the low-side primary device.
FEATURES
• 92 % primary/secondary duty cycle
• 135 °C over temperature protection
• Compatible with ETSI 300 132-2
• 28 V to 75 V input voltage range
• Integrated ± 1 A half bridge primary drivers
• Secondary synchronous rectifier control signals with
programmable deadtime delay
• Voltage mode control
• Voltage feedforward compensation
• High voltage pre-regulator operates during start-up
• Current sensing on low-side primary device
• Frequency foldback eliminates constant current tail
• Advanced maximum current control during start-up and
shorted load
• Low input voltage detection
• Programmable soft-start function
APPLICATIONS
• Network cards
• Power supply modules
• Distributed power systems
• Intermediate bus converter
• Brick converter
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Figure 1.
BST
DH
LX
DL
CS2
CS1
EP
C
L_CONT
P
M O C _ G
E
R
V
N
I
V
C C
V
INDET
S S
V
F E R
R
C S O
M
B
B
D
N
G
D
N
G
P
Si9122E
36 V to 75 V
Synchronous
Rectifiers
V
CC
-
+
V
REF
Error
Amplifier
Opto Isolator
V
OUT
+
-
1 V to 12 V Typ.
SR
H
SR
L
RoHS
COMPLIANT
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Document Number: 73866
S-80112-Rev. D, 21-Jan-08
Vishay Siliconix
Si9122E
TECHNICAL DESCRIPTION
Si9122E is a voltage mode controller for the half-bridge
topology. With 100 V depletion mode MOSFET, the Si9122E
is capable of powering directly from the high voltage bus to
VCC through an external PNP pass transistor, or may be
powered through an external regulator directly through the
VCC pin. With PWM control, Si9122E provides peak
efficiency throughout the entire line and load range. In order
to simplify the design of efficient secondary synchronous
rectification circuitry, the Si9122E provides intelligent gate
drive signals to control the secondary MOSFETs. With
independent gate drive signals from the controller,
transformer design is no longer limited by the gate to source
rating of the secondary-side MOSFETs. Si9122E provides
constant VGS voltage, independent of the line voltage to
minimize the gate charge loss as well as conduction loss.
To prevent shoot-through current or transformer shorting,
adjustable Break-Before-Make (BBM) time is incorporated
into the IC and is programmed by an external precision
resistor.
Si9122E is assembled in lead (Pb)-free TSSOP-20 and
MLP65-20 packages. To satisfy stringent ambient
temperature requirements, Si9122E is rated to handle the
industrial temperature range of - 40 °C to 85 °C. When a
situation arises which results in a rapid increase in primary
(or secondary) current such as output shorted or start-up
with a large output capacitor, control of the PWM generator
is handed over to the current loop. Monitoring of the load
current is by means of an external current sense resistor in
the source of the primary low-side switch. With the lower
OTP set at 135 °C , the DNF20 package improves the
thermal headroom.
Figure 2.
V
REF
-
+
Pre-Regulator
-
+
-
+
REG_COMP
V
INDET
V
REF
V
IN
+
–
Error Amplifier
132 k
EP
–
+
PWM
Comparator
SS
–
+
CS2
CS1
Over Current Protection
GND
V
UVLO
V
UV
V
SD
V
CC
Duty Cycle
Control
C
L_CONT
Driver
Control
and
Timing
BBM
OTP
OSC
R
OSC
V
FF
Ramp
SR
L
SR
H
PGND
DL
DH
SYNC
Driver Low
SYNC
Driver High
Low-Side
Driver
High-Side
Primary
Driver
Int
BST
LX
Si9122E
Peak DET
V
REF
2
60 k
I
SS
8.8 V
550 mV
20 µA
8 V
9.1 V
V
CC
V
CC
V
CC
Primary
ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND = 0 V
Parameter Limit Unit
VIN (Continuous) 80
V
VIN (100 ms) 100
VCC 14.5
VBST
Continuous 95
100 ms 113.2
VLX 100
VBST - VLX 15
VREF
, ROSC - 0.3 to VCC + 0.3
Logic Inputs - 0.3 to VCC + 0.3
Analog Inputs - 0.3 to VCC + 0.3
HV Pre-Regulator Input Current Continuous 5 mA
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
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Vishay Siliconix
Si9122E
Notes:
a. Device mounted on JEDEC compliant 1S2P test board.
b. Derate 14 mW/°C above 25 °C.
c. Derate 26 mW/°C above 25 °C.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Parameter Limit Unit
Storage Temperature - 65 to 150 °C
Operating Junction Temperature 150
Power DissipationaTSSOP-20b
MLP65-20c
850
2500 mW
Thermal Impedance (θJA)TSSOP-20
MLP65-20
75
38 °C/W
RECOMMENDED OPERATING RANGE All voltages referenced to GND = 0 V
Parameter Limit Unit
VIN 36 to 75 V
VCC 10.5 to 13.2
CVCC ≥ 4.7 µF
fOSC 200 to 500 kHz
ROSC 30 to 72 kΩ
RBBM 22 to 50
CREF 0.1 µF
CBOOST 0.1
Analog Inputs 0 to VCC - 2 V
Digital Inputs 0 to VCC
Reference Voltage Output Current 0.1 to 2.5 mA
ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND = 0 V
SPECIFICATIONSa
Parameter Symbol
Test Conditions
Unless Otherwise Specified
fNOM = 500 kHz, VIN = 75 V
VINDET = 7.5 V; 10.5 V ≤ VCC ≤ 13.2 V
Limits
- 40 to 85 °C
Unit Min.b Typ.c Max.b
Reference (3.3 V)
Output Voltage VREF VCC = 12 V, 25 °C Load = 0 mA 3.2 3.3 3.4 V
Short Circuit Current ISREF VREF = 0 V - 50 mA
Load Regulation dVr/dir IREF = 0 to - 2.5 mA - 30 - 75 mV
Power Supply Rejection PSRR at 100 Hz 60 dB
Oscillator
Accuracy (1 % ROSC)ROSC = 30 kΩ, fNOM = 500 kHz - 20 20 %
Max FrequencygFMAX ROSC = 22.6 kΩ400 500 600 kHz
Foldback FrequencydFFOBK fNOM = 500 kHz, VCS2 - VCS1 > 150 mV 100
Error Amplifier
Input Bias Current IBIAS VEP = 0 V - 40 - 15 µA
Gain AV- 2.2 V/V
Bandwidth BW 5 MHz
Power Supply Rejection PSRR at 110 Hz 60 dB
Slew State SR 0.5 V/µs
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Document Number: 73866
S-80112-Rev. D, 21-Jan-08
Vishay Siliconix
Si9122E
Parameter Symbol
Test Conditions
Unless Otherwise Specified
fNOM = 500 kHz, VIN = 75 V
VINDET = 7.5 V; 10.5 V ≤ VCC ≤ 13.2 V
Limits
- 40 to 85 °C
Unit Min.b Typ.c Max.b
Current Sense Amplifier
Input Voltage CM Range VCM VCS1 - GND, VCS2 - GND ± 150 mV
Current Sense Amplifier
Input Amplifier Gain AVOL 17.5 dB
Input Amplifier Bandwidth BW 5 MHz
Input Amplifier Offset Voltage VOS ± 5 mV
CL_CONT Current ICL_CONT
dVCS = 0 120 µA
dVCS = 100 mV 0
dVCS = 100 mV > 2 mA
Lower Current Limit Threshold VTLCL
IPD = IPU - ICL_CONT = 0 100
mV
Upper Current Limit Threshold VTHCL IPD > 2 mA 150
Hysteresis IPU < 500 µA- 50
CL_CONT Clamp Level CL_CONT IPU = 500 µA0.6 1.5 V
PWM Operation
Duty Cycle
DMAX fOSC = 500 kHz, 25 °C
VINDET = 4.8 V, VIN = 48 V
VEP = 0 V Primary 88
91
94 %
Secondary
90
93
95 %
DMIN
VEP = 1.75 V < 17
VCS2 - VCS1 > 150 mV 3
Pre-Regulator
Input Voltage + VIN IIN = 10 µA36 75 V
Input Leakage Current ILKG VIN = 75 V, VCC > VREG 10 µA
Regulator Bias Current IREG1 VIN = 75 V, VINDET < VSD 86 200
IREG2 VIN = 75 V, VINDET > VREF 814mA
Regulator_Comp ISOURCE VCC = 12 V - 29 - 19 - 9 µA
ISINK 50 82 110
Pre-Regulator drive Capability ISTART VCC < VREG 20 mA
VCC Pre-Regulator Turn Off
Threshold Voltage
VREG1 VINDET > VREF
7.4 9.1 10.4
V
TA = 25 °C 8.5 9.1 9.7
VREG2 VINDET = 0 V 9.2
Undervoltage Lockout VUVLO VCC Rising 7.15 8.8 9.8
TA = 25 °C 8.1 8.8 9.3
VULVO HysteresisfVUVLOHYS 0.5
Soft-Start
Soft-Start Current Output ISS Start-Up Condition 12 20 28 µA
Soft-Start Completion Voltage VSS_COMP Normal Operation 7.35 8.05 8.85 V
Shutdown
VINDET Shutdown VSD VINDET Rising 350 550 720 mV
VSD Hysteresis VINDET Falling 200
VINDET Input Threshold Protection
VINDET - VIN Under Voltage VUV VINDET Rising 3.13 3.3 3.46 V
VUV Hysteresis VINDET Falling 0.23 0.3 0.35
Over Temperature Voltages
Activating Temperature OTP_on TJ Increasing 135 °C
De-Activating Temperature OTP_off TJ Decreasing 113
SPECIFICATIONSa
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
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Vishay Siliconix
Si9122E
Notes:
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (- 40 °C to 85 °C).
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. FMIN when VCL_CONT at clamp level. Typical foldback frequency change + 20 %, - 30 % over temperature.
e. See Figure 3 for Break-Before-Make time definition.
f. VUVLO tracks VREG1 by a diode drop.
g. Guaranteed by design and characterization, not tested in production.
Parameter Symbol
Test Conditions
Unless Otherwise Specified
fNOM = 500 kHz, VIN = 75 V
VINDET = 7.5 V; 10.5 V ≤ VCC ≤ 13.2 V
Limits
- 40 to 85 °C
Unit Min.b Typ.c Max.b
Converter Supply Current (VCC)
Shutdown ICC1 Shutdown, VINDET = 0 V 50 350 µA
Converter Supply Current (VCC)
Switching Disabled ICC2 VINDET < VREF 4812
mA
Switching w/o Load ICC3 VINDET > VREF, fNOM = 500 kHZ 51015
Switching with CLOAD ICC4
VCC = 12 V, CDH = CDL = 3 nF
CSRH = CSRL = 0.3 nF 21
Output MOSFET DH Driver (High-Side)
Output High Voltage VOH Sourcing 10 mA
V
BST
- 0.3
V
Output Low Voltage VOL Sinking 10 mA VLX + 0.3
Boost Current IBST VLX = 48 V, VBST = VLX + VCC 1.3 1.9 2.7 mA
LX Current ILX VLX = 48 V, VBST = VLX + VCC - 1.3 - 0.7 - 0.4
Peak Output Source ISOURCE VCC = 10.5 V - 1.0 - 0.75 A
Peak Output Sink ISINK 0.75 1.0
Rise Time trCDH = 3 nF 35 ns
Fall Time tf35
Output MOSFET DL Driver (Low-Side)
Output High Voltage VOH Sourcing 10 mA VCC - 0.3 V
Output Low Voltage VOL Sinking 10 mA 0.3
Peak Output Source ISOURCE VCC = 10.5 V - 1.0 - 0.75 A
Peak Output Sink ISINK 0.75 1.0
Rise Time trCDH = 3 nF 35 ns
Fall Time tf35
Synchronous Rectifier (SRH, SRL) Drivers
Output High Voltage VOH Sourcing 10 mA VCC - 0.4 V
Output Low Voltage VOL Sinking 10 mA 0.4
Break-Before-Make Timee
tBBM1 TA = 25 °C, RBBM = 33 kΩ, VINDET = 4.8 V,
VEP = 0 V, VIN = 48 V
48
ns
tBBM2 9
tBBM3 TA = 25 °C, RBBM = 33 kΩ, BST= 60 V,
VINDET = 4.8 V, VEP = 0 V, VIN = 48 V = LX
24
tBBM4 18
Peak Output Source ISOURCE VCC = 10.5 V - 100 mA
Peak Output Sink ISINK 100
Rise Time trCDH = 3 nF 35 ns
Fall Time tf35
Voltage Mode
Error Amplifier td1DH Input to High-Side Switch Off < 200 ns
td2DL Input to Low-Side Switch Off < 200
Current Mode
Current Amplifier td3DH Input to High-Side Switch Off < 200 ns
td4DL Input to Low-Side Switch Off < 200
SPECIFICATIONSa
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Document Number: 73866
S-80112-Rev. D, 21-Jan-08
Vishay Siliconix
Si9122E
TIMING DIAGRAM FOR MOS DRIVERS
Figure 3.
GND
Time
V
CC
V
BST
V
MID
GND
V
CC
PWMPWMPWMPWM
SR
L
SR
L
DL DL
DH DH
DH DH
SR
H
SR
H
t
BBM1 t
BBM2 t
BBM3 t
BBM4
50 %
DH
LX
50 %
t
BBM3 t
BBM4
DH , LX
DH , LX
DH , LX
SR
H
SR
L
GND
GND
V
CC
V
MID
BST = LX + V
CC
t
BBM1 t
BBM2
V
CC
GND
SR
L
DL
GND
GND
V
CC
V
CC
V LX
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
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Vishay Siliconix
Si9122E
PIN CONFIGURATION
20
19
18
17
1
2
3
4
16
15
14
13
5
6
7
8
VINBST
REG_COMP DH
VCC LX
VREF DL
GNDPGND
ROSC SRH
EP SRL
VINDET SS
Si9122EDQ (TSSOP-20)
Top View
12
11
9
10
CS1 BBM
CS2 CL_CONT
Si9122EDLP (MLP65-20)
Top View
BST
DH
LX
DL
PGND
SRH
SRL
SS
BBM
CL_CONT
VIN
REG_COMP
VCC
VREF
GND
ROSC
EP
VINDET
CS1
CS2
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
ORDERING INFORMATION
Part Number Temperature Range Package
Si9122EDQ-T1-E3 - 40 °C to 85 °C TSSOP-20
Si9122EDLP-T1-E3 MLP65-20
Eval Board Temperature Range Board Type
Contact Factory - 10 °C to 70 °C Surface Mount and Thru-Hole
PIN DESCRIPTION
1VIN Input supply voltage for the start-up circuit
2 REG_COMP Control signal for an external pass transistor
3VCC Supply voltage for internal circuitry
4VREF 3.3 V reference
5 GND Ground
6ROSC External resistor connection to oscillator
7 EP Voltage control input
8VINDET
VIN under voltage detect and shutdown function input. Shuts down or disables switching when VINDET
falls below preset threshold voltages and provides the feed forward voltage.
9 CS1 Current limit amplifier negative input
10 CS2 Current limit amplifier positive input
11 CL_CONT Current limit compensation
12 BBM Programmable Break-Before-Make time connection to an external resistor to set time delay
13 SS Soft-Start control - external capacitor connection
14 SRLSignal transformer drive, sequenced with the primary side.
15 SRHSignal transformer drive, sequenced with the primary side
16 PGND Power ground
17 DL Low-side gate drive signal - primary
18 LX High-side source and transformer connection node
19 DH High-side gate drive signal - primary
20 BST Bootstrap voltage to drive the high-side n-channel MOSFET switch
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Document Number: 73866
S-80112-Rev. D, 21-Jan-08
Vishay Siliconix
Si9122E
DETAILED OPTION
Start-Up
When VINEXT rises above 0 V, the internal pre-regulator
begins to charge up the VCC capacitor. Current into the
external VCC capacitor is limited to typically 40 mA by the
internal DMOS device. When VCC exceeds the UVLO
voltage of 8.8 V a soft-start cycle of the switch mode supply
is initiated. The VCC supply continues to be charged by the
pre-regulator until VCC equals VREG. During this period,
between VUVLO and VREG, excessive load current will result
in VCC falling below VUVLO and stopping switch mode
operation. This situation is avoided by the hysteresis
between VREG and VUVLO and correct sizing of the VCC
capacitor, bootstrap capacitor and the soft-start capacitor.
The value of the VCC capacitor should therefore be chosen
to be capable of maintaining switch mode operation until the
required VCC current can be supplied from the external circuit
(e.g via a power transformer winding and zener regulator).
Feedback from the output of the switch mode supply charges
VCC above VREG and fully disconnects the pre-regulator,
isolating VCC from VIN. VCC is then maintained above VREG
for the duration of switch mode operation. In the event of an
over voltage condition on VCC, an internal voltage clamp
turns on at 14.5 V to shunt excessive current to GND.
Care needs to be taken if there is a delay prior to the external
circuit feeding back to the VCC supply. To prevent excessive
power dissipation within the IC it is advisable to use an
external PNP device. A pin has been incorporated on the IC,
(REG_COMP) to provide compensation when employing the
external device. In this case the VIN pin is connected to the
base of the PNP device and controls the current, while the
REG_COMP pin determines the frequency compensation of
the circuit. The value of the REG_COMP capacitor cannot be
too big, otherwise it will slow down the response of the
pre-regulator in the case that fault situations occur and
pre-regulator needs to be turned on again. To understand
the operation, please refer to figure 5.
Figure 4. Detailed Si9122E Block Diagram
Timer
+
–
132 k
EP
+
–
Bandgap
Reference
3.3 V
OSC
Loop
Control
135 °C Temp
Protection
High V oltage
Interface
V
SD V
UV V
UVLO
Logic
Clock OTP
V
REF
V
INDET
–
+
R
OSC
Oscillator
Clock
60 k
V
REF
/2 PWM
Generator
–
+
–
+
V
UV
V
SD
V
REF
550 mV
Logic
DH
BST
LX
High-Side
Primary
Driver
DL
SR
H
SR
L
PGND
Low-Side
Primary
Driver
Synchronous
Driver
(High)
Synchronous
Driver
(Low)
BBM
Current
Control Gain
100 mV
CS2
CS1
Blanking
C
L_CONT
V
CC
20 µA
Soft-Start
SS Enable
SS
Si9122E
8 V
–
+
–
+
VREG
9.1 V
V
CC V
IN
Pre-Regulator
VUVLO
8.8 V
9.1 V
V
CC
V
CC
VCC
G
ND
Voltage
Feedforward
Frequency
Foldback
C
L_CONT
12 V
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
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Vishay Siliconix
Si9122E
The soft-start circuit is designed for the dc-dc converter to
start-up in an orderly manner and reduce component
stresses on the Converter. This feature is programmable by
selecting an external CSS. An internal 20 µA current source
charges CSS from 0 V to the final clamped voltage of 8 V. In
the event of UVLO or shutdown, VSS will be held low (< 1 V)
disabling driver switching. To prevent oscillations, a longer
soft-start time may be needed for highly capacitive loads
and/or high peak output current applications.
Reference
The reference voltage of Si9122E is set at 3.3 V. The
reference voltage should be de-coupled externally with
0.1 µF capacitor. The VREF voltage is 0 V in shutdown mode
and has 50 mA source capability.
Voltage Mode PWM Operation
Under normal load conditions, the IC operates in voltage
mode and generates a fixed frequency pulse width
modulated signal to the drivers. Duty cycle is controlled over
a wide range to maintain output voltage under line and load
variation. Voltage feedforward is also included to take
account of variations in supply voltage VIN.
In the half-bridge topology requiring isolation between output
and input, the reference voltage and error amplifier must be
supplied externally, usually on the secondary side. The error
information is thus passed to the power controller through an
opto-coupling device. This information is inverted, hence 0 V
represents the maximum duty cycle, while 2 V represents
minimum duty cycle. The error information enters the IC via
pin EP, and is passed to the PWM generator via an inverting
amplifier. The relationship between Duty cycle and VEP is
shown in the Typical Characteristic Graph, Duty Cycle vs.
VEP 25 °C , page 12. Voltage feedforward is implemented by
taking the attenuated VIN signal at VINDET and directly
modulating the duty cycle.
At start-up, i.e., once VCC is greater than VUVLO, switching is
initiated under soft-start control which increases primary
switch on-times linearly from DMIN to DMAX over the soft-start
period. Start-up from a VINDET power down is also initiated
under soft-start control.
Half Bridge and Synchronous Rectification Timing
Sequence
The PWM signal generated within the Si9122E controls the
low and high-side bridge drivers on alternative cycles. A
period of inactivity always results after initiation of the soft-
start cycle until the soft-start voltage reaches approximately
1.2 V and PWM controlled switching begins. The first bridge
driver to switch is always the low-side (DL), as this allows
charging of the high-side boost capacitor.
The timing and coordination of the drives to the primary and
secondary stages is very important and shown in figure 3. It
is essential to avoid the situation where both of the
secondary MOSFETs are on when either the high or the low-
side switch are active. In this situation the transformer would
effectively be presented with a short across the output. To
avoid this, a dedicated break-before-make circuit is included
which will generate non-overlapping waveforms for the
primary and the secondary drive signals. This is achieved by
a programmable timer which delays the on switching of the
primary driver relative to the off switching of the related
secondary and subsequently delays the on switching of the
secondary relative to the off switching of the related primary.
Typical variations of BBM times with respect to RBBM and
other operating parameters are shown on page 14 and 15.
Primary High- and Low-Side MOSFET Drivers
The drive voltage for the low-side MOSFET switch is
provided directly from VCC. The high-side MOSFET however
requires the gate voltage to be enhanced above VIN. This is
achieved by bootstrapping the VCC voltage onto the LX
voltage (the high-side MOSFET source). In order to provide
the bootstrapping an external diode and capacitor are
required as shown on the application schematic. The
capacitor will charge up after the low-side driver has turned
on. The switch gatedrive signals DH and DL are shown in
figure 3.
Secondary MOSFET Drivers
The secondary side MOSFETs are driven from the Si9122E
via a center tapped pulse transformer and inverter drivers.
The waveforms from SRH and SRL are shown in figure 3. Of
importance is the relative voltage between SRH and SRL, i.e.
that which is presented across the primary of the pulse
transformer. When both potentials of SRL and SRH are equal
then by the action of the inverting drivers both secondary
MOSFETs are turned on.
Oscillator
The oscillator is designed to operate at a nominal frequency
of 500 kHz. The 500 kHz operating frequency allows the
converter to minimize the inductor and capacitor size,
improving the power density of the converter. The oscillator
and therefore the switching frequency is programmable by
attaching a resistor to the ROSC pin. Under overload
conditions the oscillator frequency is reduced by the current
overload protection to enable a constant current to be
maintained into a low impedance circuit.
Current Limit
Current mode control providing constant current operation is
achieved by monitoring the differential voltage VCS between
the CS1 and CS2 pins, which are connected to a current
sense resistor on the primary low-side MOSFET. In the
absence of an overcurrent condition, VCS is less than lower
current limit threshold VTLCL (typical 100 mV); CL_CONT is
pulled up linearly via the 120 µA current source (IPU) and
both DL and DH switch at half the oscillator set frequency.
When a moderate overcurrent condition occurs (VTLCL < VCS
< VTHCL), the CL_CONT capacitor will be discharged at a rate
that is proportional to VCS - 100 mV by the IPD current
source. Both driver outputs are in frequency fold-back mode
and the switching frequency becomes roughly 20 % of
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Document Number: 73866
S-80112-Rev. D, 21-Jan-08
Vishay Siliconix
Si9122E
normal switching frequency. When a severe overcurrent
condition occurs (VTHCL < VCS), the NMOS discharges
CL_CONT capacitor immediately at 2 mA rate and the
CL_CONT voltage will be clamped to 1.2 V disabling both DL
and DH outputs.
Before VCS reaches severe overcurrent condition, a lowering
of the CL_CONT voltage results in PWM control of the output
drive being taken over by the current limit control loop
through CL_CONT. Current control initially reduces the
switching duty cycle toward the minimum the chip can reach
(DMIN). If this duty cycle reduction still cannot lower the load
current, then the switching frequency will start to fold back to
minimum 1/5 of the nominal frequency. This prevents the
on-time of the primary drivers from being reduced to below
100 ns and avoids current tails. If VCS > VTHCL, the switching
will then stop.
With constant current mode control and frequency foldback,
protection of the MOSFET switches is increased. The
converter reverts to voltage mode operation immediately
when the primary current falls below the limit level, and
CL_CONT capacitor is charged up and clamped to 6.5 V. The
soft-start function does not apply during current limit period,
as this would constitute hiccup mode operation.
VIN Voltage Monitor - VINDET
The chip provides a means of sensing the voltage of VIN, and
withholding operation of the output drivers until a minimum
voltage of VREF (3.3 V, 300 mV hysteresis), is achieved. This
is achieved by choosing an appropriate resistive tap between
the ground and VIN, and comparing this voltage with the
reference voltage. When the applied voltage is greater than
VREF, the output drivers are activated as normal. VINDET also
provides the input to the voltage feedforward function.
However, if the divided voltage applied to the VINDET pin is
greater than VCC - 0.3 V, the high-side driver, DH, will stop
switching until the voltage drops below VCC - 0.3 V. Thus, the
resistive tap on the VIN divider must be set to accommodate
the normal VCC operating voltage to avoid this condition.
Alternatively, a zener clamp diode from VINDET to GND may
also be used.
Shutdown Mode
If VINDET is forced below the lower VSD threshold, the device
will enter SHUTDOWN mode. This powers down all
unnecessary functions of the controller, ensures that the
primary switches are off, and results in a low level current
demand from the VIN or VCC supplies.
Figure 5. High-Voltage Pre-Regulator Circuit
CVCC
0.5 µF
CEXT
2 nF
GND
VCC
PNP Ext
REG_COMP
VREF
VIN
VINEXT
HVDMOS
14.5 V
REXT
12 V
Auxillary
VCC
Figure 6. Current Limit Circuit
-
+ GM
C
EXT
+
- AV A
V 150 mV
-
+ GM
Peak Detect
Blank
CS1
CS2
I
PD
0 to 240 µA (nom)
I
PU
120 µA (nom)
AV
V
OFFSET
OSC
C
L_CLAMP
R
EXT
C
L_CONT
A
V 100 mV
V
CC
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
www.vishay.com
11
Vishay Siliconix
Si9122E
REDUCTION OF BBM2, 4 AT HIGHER fOSC
The start of a switching period is defined as the turning point
of the oscillator, marked in Figure 7 as A, with the end of a
switching period marked as B. For a half bridge, two
switching periods are required for both the primary high-side
and low-side drivers to operate as shown in Figure 3. For a
given oscillator frequency there is a finite time in which all
events from equation (1) have to occur. These are tdt dead-
time duration which is a function of VEP, tpd1 is the
propagation delay from the PWM to SRL (or SRH ) output
going low, tBBM1 (or tBBM3) rise delay, DL (or DH) primary
driver on-time, tpd2 is the propagation delay from PWM to DL
(or DH) output going low and tBBM2(or tBBM4) fall delay.
Figure 7 shows the switching cycle for the low side primary
driver and associated synchronous driver and equation (1)
shows the switching time components.
At 500 kHz and maximum duty tpd2 is typically 60 ns.
Tswitch = 1/2tdt + tpd1+ tSRLOFF + 1/2tdt - tpd2- tBBM2 (1)
The Si9122E has an improved primary and secondary duty
cycles with typical maximum secondary duty at 93.2 %.
Hence the dead-time is 6.8 % or 136 ns at 500 kHz. Half of
the dead-time is 68 ns and during this time tpd2 plus tBBM2
has to occur before the next transition point of the oscillator
cycle. RBBM contributes 1.2 ns/kΩ to tBBM2; with 33 kΩ this
amounts to 40 ns. If tBBM2 is set beyond the transition point,
SRL will be forced high due to logic conditions and a
reduction in the set tBBM2 will be determined by the half dead-
time minus tpd2 and will be independent of the RBBM value as
shown in figure 8.
Note: this applies to tBBM4 as well.
To mitigate the decrease in set tBBM2 and tBBM4, the
following criteria must be met. The set tBBM2 plus its
associated tpd2 must not exceed 3.4 % of the oscillator
period. The typical tBBM2 and tBBM4 delays are provided in
figure 9 to facilitate setting these delays for a given frequency
with RBBM of 33 kΩ.
tBBM2 + tpd2 < 3.4 % of oscillator period (2)
tBBM4 + tpd4 < 3.4 % of oscillator period (3)
It is critical to avoid the condition where the sum of tBBM2(set)
and tpd2 is greater than 6.8 % of oscillator period whereby the
correct sequence of logic signals cannot be guaranteed.
Figure 7. Components of a Low-Side Switching Period
DL
SR
V
EP
1.2 V
Tpd1
BBM1
T
p
d2
BBM2
MAX
½ deadtime ½ deadtime
Transition
point
A
B
L
Figure 8. Components of a Low-Side Switching Period with
Maximum Duty and Limited BBM2
Figure 9. Reduction in BBM2 and BBM4
Si9122E BBM vs. FOSC, VIN = 50 V, VCC = 10 V,
BST = 60 V, LX = 50 V, VEP = 0 V
Transition
point
DL
SR
1.2 V
T
p
d1
BBM1
T
p
d2
Set BBM2
Actual
BBM2
A
B
L
0
10
20
30
40
50
60
150 200 250 300 350 400 450 500
Fosc
(kHz)
Delay (ns)
BBM2
BBM4
www.vishay.com
12
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
Vishay Siliconix
Si9122E
TYPICAL CHARACTERISTICS
F
OSC
vs. R
OSC
at V
CC
= 12 V
VREG vs. Temperature, VIN = 48 V
ISS vs. Temperature
200
300
400
500
600
20 30 40 50 60 70 80
ROSC (k )
)zHk(F CSO
)
V
(
V
GER
Temperature (°C)
7.5
8.0
8.5
9.0
9.5
10.0
- 50 - 25 0 25 50 75 100 125 150
VINDET VREF
TC = - 11 mV/C
15
17
19
21
23
25
- 50 - 25 0 25 50 75 100 125
Temperature (°C)
VCC = 13 V
VCC = 10 V
VCC = 12 V
)A
u(I
1SS
VREF vs. Temperature, VCC = 12 V
SRL, SRH Duty Cycle vs. VEP
VSS vs. Temperature, V = 12 V
3.270
3.275
3.280
3.285
3.290
3.295
3.300
- 50 - 25 0 25 50 75 100
Temperature (°C)
)V(V
FER
0
10
20
30
40
50
60
70
80
90
100
0.0 0.5 1.0 1.5 2.0
VEP (V)
)%( elcy
C ytu
D
3.6 V = VINDET
VCC = 12 V
7.2 V
4.8 V
7.90
7.95
8.00
8.05
8.10
8.15
8.20
- 50 - 25 0 25 50 75 100 125 150
Temperature (°C)
)
V
(VSS
TC = + 1.25 mV/C
VINDET VREF
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
www.vishay.com
13
Vishay Siliconix
Si9122E
TYPICAL CHARACTERISTICS
IREG2 vs. Temperature, VCC = 12 V
DH, DL ISOURCE vs. VOH
SRL, SRH ISOURCE vs. VOH
5
6
7
8
9
10
11
- 50 - 25 0 25 50 75 100
I2GER )Am(
Temperature (°C)
0
50
100
150
200
250
0 200 400 600 800
VOH (mV)
IEC
R
UOS )
Am(
VCC = 12 V
0
5
10
15
20
25
30
35
0 200 400 600 800
VOH (mV)
IECRUO
S)
A
m(
VCC = 12 V
ICC3 vs. Temperature VCC = 12 V
DH, DL ISINK vs. VOL
SRL, SRH ISINK vs. VOL
7
8
9
10
11
12
13
- 50 - 25 0 25 50 75 100
Temperature (°C)
I3CC )Am(
0
50
100
150
200
250
0 200 400 600 800
VCC = 12 V
IK
N
IS )A
m
(
VOL (mV)
0
5
10
15
20
25
30
35
0 200 400 600 800
VOL (mV)
IKNIS )Am
(
VCC = 12 V
www.vishay.com
14
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
Vishay Siliconix
Si9122E
TYPICAL CHARACTERISTICS
tBBM vs. RBBM, VEP = 0 V, VLX = 48 V, BST = 60 V,
VINDET = 4.8 V, fOSC < 200 kHZ
tBBM1, 2 vs. Temperature, VEP = 0 V, fOSC < 200 kHz
tBBM3, 4 vs. Temperature, VEP = 0 V, fosc < 200 kHz
20
30
40
50
60
70
80
90
100
25 30 35 40 45
tMBB )sn(
RBBM (k )
VCC = 12 VtBBM1
tBBM2
tBBM3
tBBM4
30
40
50
60
70
80
- 50 - 25 0 25 50 75 100 125
V = 0 V
RBBM = 33 k
t,1MBB2
)sn
(
Temperature (°C)
tBBM1, VCC = 13 V
tBBM1, VCC = 10 V
tBBM2, VCC = 13 V
tBBM2, VCC = 10 V
tBBM1, VCC = 12 V
tBBM2, VCC = 12 V
EP
30
35
40
45
50
55
60
65
70
- 50 - 25 0 25 50 75 100 125
t , 3 M B B 4 ) s n (
Temperature (°C)
t
BBM4, V
CC
= 13 V
t
BBM4, V
CC
= 12 V
t
BBM4, V
CC
= 10 V
t
BBM3, V
CC
= 13 V
t
BBM3, V
CC
= 10 V
V
EP
= 0 V
R
BBM
= 33 k
t
BBM3, V
CC
= 12 V
fosc < 200 kHz
tBBM vs. RBBM, VEP = 1.65 V, VLX = 48 V, BST = 60 V,
VINDET = 4.8 V
tBBM1, 2 vs. Temperature, VEP = 1.65 V
tBBM3, 4 vs. Temperature, VEP = 1.65 V
15
25
35
45
55
65
25 30 35 40 45
tMBB )sn(
RBBM (k )
VCC = 12 VtBBM1
tBBM2
tBBM3
tBBM4
30
35
40
45
50
55
60
- 50 - 25 0 25 50 75 100 125
t
,1
M
B
B2
)sn
(
V
EP
= 1.65 V
R
BBM
= 33 k
t
BBM1,
V
CC
= 12 V
t
BBM1,
V
CC
= 10 V
t
BBM2,
V
CC
= 13 V
t
BBM2,
V
CC
= 12 V
t
BBM2,
V
CC
= 10 V
t
BBM1,
V
CC
= 13 V
Temperature (°C)
20
30
40
50
60
70
80
- 50 - 25 0 25 50 75 100 125
t,3M
B
B4)sn(
tBBM4, VCC = 13 V
tBBM4, VCC = 12 V
tBBM4, VCC = 10 V
tBBM3, VCC = 13 V
tBBM3, VCC = 10 V
VEP = 1.65 V
RBBM = 33 k
tBBM3, VCC = 12 V
Temperature (°C)
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
www.vishay.com
15
Vishay Siliconix
Si9122E
TYPICAL CHARACTERISTICS
tBBM1, 2 vs. VCC vs. VINDET, fOSC < 200 kHz
tBBM3, 4 vs. VCC vs. VINDET, fOSC < 200 kHz
IOUT vs. RLOAD (VIN = 72 V)
30
40
50
60
70
80
3.5 4.5 5.5 6.5 7.5
t,1MBB2
)sn(
VINDET (V)
VEP = 0 V
tBBM1, VCC = 13 V
tBBM1, VCC = 10 V
tBBM2, VCC = 13 V
tBBM2, VCC = 12 V
tBBM2, VCC = 10 V
tBBM1, VCC = 12 V
30
40
50
60
70
80
3.5 4.5 5.5 6.5 7.5
VINDET (V)
t
,
3
M
BB4
)
sn
(
VEP = 0 V
tBBM4, VCC = 13 V
tBBM4, VCC = 12 V
tBBM4, VCC = 10 V
tBBM3, VCC = 13 V
tBBM3, VCC = 10 VtBBM3, VCC = 12 V
LX = 48 V, BST = 60 V
0
10
20
30
40
50
60
0.0 0.2 0.4 0.6 0.81.0
V
.%
e
lcy
C yt
uD
,I TUO
RLOAD ()
D%
Frequency
IOUT
TUO
VOUT
0
100
200
300
400
500
)z
Hk
(
yc
ne
u
qe
r
F
tBBM1, 2 vs. VCC vs. VINDET
tBBM3, 4 vs. VCC vs. VINDET
VROSC, FOSC, and Duty Cycle vs. VCL_CONT
35
40
45
50
55
3.5 4.5 5.5 6.5 7.5
t,1MBB2
)sn(
VINDET (V)
VEP = 1.65 V
tBBM1, VCC = 13 V
tBBM1, VCC = 12 V
tBBM1, VCC = 10 V
tBBM2, VCC = 13 V
tBBM2, VCC = 10 V
tBBM2, VCC = 12 V
30
35
40
45
50
55
60
65
3.5 4.5 5.5 6.5 7.5
VINDET (V)
t,
3
M
BB4
)sn(
VEP = 1.65 V
tBBM4, VCC = 13 V
tBBM4, VCC = 12 V
tBBM4, VCC = 10 V
tBBM3, VCC = 12 V
tBBM3, VCC = 10 VtBBM3, VCC = 13 V
LX = 48 V, BST = 60 V
0
5
10
15
20
25
30
35
40
45
50
12345
VC (V)
D%
Frequency
VR
)z
Hk
(
yc
n
eu
qerF
0
200
300
400
500
DDL
DSR
100
VCSOR F ,)
V( CSO Hzk
(
)
%
(
elcy
C
ytu
D
,
)
L
OSC
L_CONT
www.vishay.com
16
Document Number: 73866
S-80112-Rev. D, 21-Jan-08
Vishay Siliconix
Si9122E
TYPICAL WAVEFORMS
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?73866.
Figure 10. Foldback Mode, RL = 0.02 Ω
Figure 12. VCC Ramp-Up
Figure 14. Effective BBM - Measured On Secondary
SR 10 V/div
I
OUT
5 A /div
DL 10 V/div
CS2 50 mV/div
2 µs/div
L
VIN 2 V/div
VCC 2 V/div
2 ms/div
LX 20 V/div
SR 2 V/div
SR 2 V/div
500 ns/div
H
L
Figure 11. Normal Mode, RL = 0.1 Ω
Figure 13. Overload Recovery
Figure 15. Drive Waveforms
SR 10 V/div
DL 5 V/div
CS2 5 V/div
I
OUT
5 A /div
2 µs/div
L
VCL 2 V/div
VEP 2 V/div
IOUT 10 A/div
VOUT 2 V/div
200 µs/div
DH 5 V/div
SR 5 V/div
DL 5 V/div
SR 5 V/div
500 ns/div
L
H
1.00
SEATING
PLANE
1.00 DIA.
D
B
E
E/2
4X
0.20 C A−BD
0.20 H A−BD
2X N/2 TIPS
1.00
1.00 A
N
123
SEE
DETAIL ‘A’
C
L
BB
c
e/2
X X = A and B
LEAD SIDES
TOP VIEW
H
C
aaa C
A1
A2
A
MCbbb A−B D 9
0.05C
b
e
D
SIDE VIEW
DETAIL ‘A’
(SCALE: 30/1)
(VIEW ROTATED 90_ C.W.)
(14_)
H
(14_)
6
+
+
L
(∝)
0.25
PARTING
LINE
END VIEW
E1
Package Information
Vishay Siliconix
Document Number: 72818
28-Jan-04
www.vishay.com
1
TSSOP: 20-LEAD (POWER IC ONLY)
MILLIMETERS
Dim Min Nom Max
A— — 1.10
A10.05 — 0.15
A20.85 0.90 0.95
aaa 0.076
b0.19 −0.30
b1 0.19 0.22 0.25
bbb 0.10
c0.09 −0.20
c1 0.09 0.127 0.16
D6.50 BSC
E6.40 BSC
E14.30 4.40 4.50
e0.65 BSC
L0.50 0.60 0.70
N20
P4.2
P13.0
∝0_— 8_
ECN: S-40082—Rev. A, 02-Feb-04
DWG: 5923
Index Area
D/2 E/2
E
D
E/2
D/2
-A-
-B-
SEATING
PLANE
A3
A1
A
C0.08
Cccc//
NX
BOTTOM VIEW
TOP VIEW
SIDE VIEW
Caaa 2x
Caaa 2x
-C-
Index Area
D/2 E/2
NXb
NXL
2.00
Detail D D2/2
D2
E2/2
E2
NXb
Abbb MB C
55
e/2
e
Terminal Tip Terminal Tip
e
# IDENTIFIER TYPE A
EVEN TERMINAL SIDE ODD TERMINAL SIDE
Chamber
DETAIL B
Package Information
Vishay Siliconix
Document Number: 73182
15-Oct-04
www.vishay.com
1
PowerPAKr MLP65-18/20 (POWER IC ONLY)
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
2. All dimensions are in millimeters. All angels are in degrees.
3. N is the total number of terminals.
4. The terminal #1 identifier and terminal numbering convention shall conform to JEDEC publication 95 SSP-022. Details of terminal #1 identifier are optional,
but must be located within the zone indicated. A dot can be marked on the top side by pin 1 to indicate orientation.
5. ND and NE refer to the number of terminals on the D and E side respectively.
6. Depopulation is possible in a symmetrical fashion.
7. NJR refers to NON JEDEC REGISTERED.
8. Dimension “b” applies to metalized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has optional radius on
the other end of the terminal, the dimension “b” should not be measured in that radius area.
9. Coplanarity applies to the exposed heat slug as well as the terminal.
10. The 45_ chamfer dimension C’ is located by pin 1 on the bottom side of the package.
Package Information
Vishay Siliconix
www.vishay.com
2Document Number: 73182
15-Oct-04
PowerPAK MLP65-18/20 (POWER IC ONLY)
N = 18/20 PITCH: 0.5 mm, BODY SIZE: 6.00 x 5.00
MILLIMETERS* INCHES
Dim Min Nom Max Min Nom Max Notes
A 0.80 0.90 1.00 0.031 0.035 0.039 1, 2
A1 0.00 0.02 0.05 0.000 0.001 0.002 1, 2
A2 0.00 0.65 1.00 0.000 0.003 0.004 1, 2
A3 0.20 REF 0.008 REF
aaa −0.15 − − 0.006 −
b 0.18 0.25 0.30 0.007 0.010 0.012 8
bbb −0.10 − − 0.004 −
C’ −0.225 − − 0.009 −4, 10
ccc −0.10 − − 0.004 −
D6.00 BSC 0.236 BSC 1, 2
D2 4.00 4.15 4.25 0.157 1.63 0.167 1, 2
E5.00 BSC 0.197 BSC 1, 2
E2 3.00 3.15 3.25 0.118 0.124 0.128 1, 2
e−0.50 − − 0.020 −
L 0.45 0.55 0.65 0.018 0.022 0.026 1, 2
N18, 20 18, 20 1, 2
ND(18) 9 9 1, 2
NE(18) 0 0 1, 2
ND(20) 10 10 1, 2
NE(20) 0 0 1, 2
* Use millimeters as the primary measurement.
ECN: S-41946—Rev. A, 18-Oct-04
DWG: 5939
Legal Disclaimer Notice
www.vishay.com Vishay
Revision: 12-Mar-12 1Document Number: 91000
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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including but not limited to the warranty expressed therein.
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
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