________________General Description
The MAX1245 12-bit data-acquisition system combines
an 8-channel multiplexer, high-bandwidth track/hold, and
serial interface with high conversion speed and ultra-low
power consumption. It operates from a single +2.375V to
+3.3V supply, and its analog inputs are software config-
urable for unipolar/bipolar and single-ended/differential
operation.
The 4-wire serial interface directly connects to SPI™,
QSPI™, and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection to
TMS320-family digital signal processors. The MAX1245
works with an external reference, and uses either the
internal clock or an external serial-interface clock to
perform successive-approximation analog-to-digital
conversions.
This device provides a hard-wired SHDN pin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a
conversion. Accessing the serial interface powers up
the MAX1245, and the quick turn-on time allows it to be
shut down between conversions. This technique can
cut supply current to under 10µA at reduced sampling
rates.
The MAX1245 is available in a 20-pin DIP package and
an SSOP that occupies 30% less area than an 8-pin DIP.
For supply voltages from +2.7V to +5.25V, use the pin-
compatible MAX147.
________________________Applications
Portable Data Logging Medical Instruments
Battery-Powered Instruments Data Acquisition
____________________________Features
oSingle +2.375V to +3.3V Operation
o8-Channel Single-Ended or 4-Channel
Differential Analog Inputs
oLow Power: 0.8mA (100ksps)
10µA (1ksps)
1µA (power-down mode)
oInternal Track/Hold, 100kHz Sampling Rate
oSPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
oSoftware-Configurable Unipolar or Bipolar Inputs
o20-Pin DIP/SSOP Packages
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
TOP VIEW
DIP/SSOP
VDD
SCLK
CS
DIN
SSTRB
DOUT
DGND
AGND
VDD
VREFSHDN
COM
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
MAX1245
___________________Pin Configuration
VDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSS
SHDN
SSTRB
DOUT
DIN
SCLK
CS
COM
AGND
DGND
VDD
CH7
0.1µF
0.1µF
CH0
0V to
+2.048V
ANALOG
INPUTS
MAX1245
CPU
+2.5V
VREF
+2.048V
___________Typical Operating Circuit
19-1066; Rev 1; 11/09
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
________________Ordering Information
*
Contact factory for availability of alternate surface-mount packages.
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
PART* TEMP RANGE PIN-PACKAGE INL
(LSB)
MAX1245ACPP 0°C to +70°C 20 Plastic DIP ±1/2
MAX1245BCPP 0°C to +70°C 20 Plastic DIP ±1
MAX1245ACAP 0°C to +70°C 20 SSOP ±1/2
MAX1245BCAP 0°C to +70°C 20 SSOP ±1
MAX1245AEPP -40°C to +85°C 20 Plastic DIP ±1/2
MAX1245BEPP -40°C to +85°C 20 Plastic DIP ±1
MAX1245AEAP -40°C to +85°C 20 SSOP ±1/2
MAX1245BEAP -40°C to +85°C 20 SSOP ±1
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +2.375V to +3.3V, VCOM = 0V, fCLK = 1.5MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps),
VREF = 2.048V applied to VREF pin, TA= TMIN to TMAX, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND, DGND .............................................. -0.3V to +6V
AGND to DGND.................................................... -0.3V to +0.3V
CH0–CH7, COM to AGND, DGND ............ -0.3V to (VDD + 0.3V)
VREF to AGND........................................... -0.3V to (VDD + 0.3V)
Digital Inputs to DGND............................................ -0.3V to +6V
Digital Outputs to DGND ........................... -0.3V to (VDD + 0.3V)
Digital Output Sink Current .................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C) ......... 889mW
SSOP (derate 8.00mW/°C above +70°C) ................... 640mW
CERDIP (derate 11.11mW/°C above +70°C).............. 889mW
Operating Temperature Ranges
MAX1245_C_P ................................................... 0°C to +70°C
MAX1245_E_P ................................................ -40°C to +85°C
Storage Temperature Range ............................ -60°C to +150°C
Lead Temperature (soldering, 10sec) ............................ +300°C
8
µs
35 65
tCONV
Conversion Time (Note 5)
5.5 7.5
MHz1.0Full-Power Bandwidth
MHz2.25Small-Signal Bandwidth
dB-85Channel-to-Channel Crosstalk
dB76SFDRSpurious-Free Dynamic Range
dB-76THDTotal Harmonic Distortion
dB68SINADSignal-to-Noise + Distortion Ratio
LSB±0.2
Channel-to-Channel Offset
Matching
ppm/°C±0.25Gain Temperature Coefficient
±0.5
Bits12Resolution
LSBGain Error (Note 3) ±0.5 ±4
LSB
±1.0
INLRelative Accuracy (Note 2)
LSB±1DNL
LSB±0.5 ±4
UNITSMIN TYP MAXSYMBOLPARAMETER
External clock = 1.5MHz, 12 clocks/conversion
Internal clock, SHDN = VDD
Internal clock, SHDN = open
MAX1245A
-3dB rolloff
50kHz, 2Vp-p (Note 4)
Up to the 5th harmonic
MAX1245B
No missing codes over temperature
CONDITIONS
Differential Nonlinearity
ns40Aperture Delay
MHz
1.5
SHDN = open
ps<50Aperture Jitter
MHz
0.1 1.5
µs2.0tACQ
Track/Hold Acquisition Time External clock = 1.5MHz
0.225
Internal Clock Frequency SHDN = VDD
0 1.5
External Clock Frequency Data transfer only
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0Vp-p to 2.048Vp-p, 100ksps, 1.5MHz external clock, bipolar input mode)
CONVERSION RATE
Offset Error
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________________________________________________________________________________ 3
Multiplexer Leakage Current
pF15CIN
DIN, SCLK, CS Input Capacitance
µA±0.01 ±1IIN
DIN, SCLK, CS Input Leakage
V0.2VHYST
DIN, SCLK, CS Input Hysteresis
V0.8VINL
DIN, SCLK, CS Input Low Voltage
µA0.01 10Shutdown VREF Input Current
k18 25VREF Input Resistance
µA82 120VREF Input Current
V
1.0 VDD +
50mV
VREF Input Voltage Range
(Note 8)
pF16Input Capacitance
0 to VREF V
±VREF/2
Input Voltage Range, Single-
Ended and Differential (Note 6)
µA±0.01 ±1
UNITSMIN TYP MAXSYMBOLPARAMETER
(Note 7)
VIN = 0V or VDD
Unipolar, VCOM = 0V
VREF = 2.048V
Bipolar, VCOM = VREF/2
On/off leakage current, VIN = 0V or VDD
(Note 7)
CONDITIONS
V
VDD/2 VDD/2
- 0.3 + 0.3
VIM
SHDN Input Mid Voltage
µA±4.0IIN
SHDN Input Current
V0.4VINL
SHDN Input Low Voltage
VVDD - 0.4VINH
SHDN Input High Voltage
SHDN = 0V or VDD
nA±80
SHDN Maximum Allowed Leakage,
Mid Input
VVDD/2VFLT
SHDN Voltage, Open
SHDN = open
SHDN = open
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.375V to +3.3V, VCOM = 0V, fCLK = 1.5MHz, external clock (50% duty cycle), 15 clocks/conversion cycle (100ksps),
VREF = 2.048V applied to VREF pin, TA= TMIN to TMAX, unless otherwise noted.)
mV±0.3PSRSupply Rejection (Note 9)
mA0.8 1.3
IDD
Positive Supply Current
µA±0.01 ±10IL
Three-State Leakage Current
VVDD - 0.375VOH
Output Voltage High
V
0.5
VOL
Output Voltage Low 0.4
V2.375 3.3VDD
Positive Supply Voltage
pF15COUT
Three-State Output Capacitance
VDD = 2.375V to 3.3V, full-scale input,
external reference = 2.048V
Operating mode, full-scale input
CS = VDD (Note 7)
CS = VDD
ISOURCE =0.5mA
ISINK = 16mA
ISINK = 5mA
1.2 10Power-down
V2.0VINH
DIN, SCLK, CS Input High Voltage
ANALOG/COM INPUTS
EXTERNAL REFERENCE
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS
µA
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
4 _______________________________________________________________________________________
TIMING CHARACTERISTICS
(VDD = +2.375V to +3.3V, VCOM = 0V, TA= TMIN to TMAX, unless otherwise noted.)
Note 1: Tested at VDD = +2.375V; VCOM = 0V; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: External reference (VREF = +2.048V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7: Guaranteed by design. Not subject to production testing.
Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 9: Measured as |VFS(2.375V) - VFS(3.3V)|.
DIN to SCLK Setup
ns400tSTR
CS Rise to SSTRB Output Disable
ns240tSDV
CS Fall to SSTRB Output Enable
260tSSTRB
SCLK Fall to SSTRB ns
300tCL
SCLK Pulse Width Low
ns300SCLK Pulse Width High
ns0
CS to SCLK Rise Hold
ns200tCSS
CS to SCLK Rise Setup
ns400tTR
CS Rise to Output Disable
ns240tDV
CS Fall to Output Enable
tDO
SCLK Fall to Output Data Valid
ns0tDH
DIN to SCLK Hold
ns
µs2.0tACQ
Acquisition Time
0tSCK
SSTRB Rise to SCLK Rise
ns200tDS
UNITSMIN TYP MAXSYMBOL
Internal clock mode only (Note 7)
External clock mode only, Figure 2
External clock mode only, Figure 1
Figure 1
Figure 2
Figure 1
CONDITIONS
Figure 1 ns20 260
tCSH
tCH
__________________________________________Typical Operating Characteristics
(VDD = 2.5V, VREF = 2.048V, fCLK = 1.5MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
ns
1.25
2.375
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.00
VDD (V)
IDD (mA)
2.875
0.75
0.50
3.375
3.125
2.625
RL =
CODE = 101010100000
MAX1245-01
CLOAD = 50pF
CLOAD = 20pF
0.90
0.65
-55 -30 70
SUPPLY CURRENT
vs. TEMPERATURE
0.85
0.80
0.75
0.70
TEMPERATURE (
°C)
IDD (mA)
20 145120-5 45 95
MAX1245-02
RL =
CODE = 101010100000
0.50
0.00
INTEGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
V
DD (V)
INL (LSB)
MAX1245-03
2.375 2.875 3.3753.1252.625
PARAMETER
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________________________________________________________________________________
5
0.50
0
-55 -30 45
INTEGRAL NONLINEARITY
vs. TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
TEMPERATURE (˚C)
INL (LSB)
20-5 70 95 145120
MAX1245-04
VDD = 2.375V
0.50
0
OFFSET vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
V
DD (V)
OFFSET (LSB)
MAX1245-05
2.375 2.875 3.375
3.1252.625
0.50
0
-55 -30 45
OFFSET vs. TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
TEMPERATURE (˚C)
OFFSET (LSB)
20-5 70 14512095
MAX1245-06
0.50
0
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
V
DD (V)
OFFSET MATCHING (LSB)
MAX1245-07
2.375 2.875 3.375
3.1252.625
0.50
0
-55 -30 20
GAIN ERROR
vs. TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
TEMPERATURE (˚C)
GAIN ERROR (LSB)
-5 45 120 145
95
70
MAX1245-10
0.50
0
-55 -30 45
CHANNEL-TO-CHANNEL OFFSET MATCHING
vs. TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
TEMPERATURE (˚C)
OFFSET MATCHING (LSB)
20
-5 70 145120
95
MAX1245-08
0.50
0
GAIN ERROR
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
V
DD (V)
GAIN ERROR (LSB)
MAX1245-09
2.375 2.875 3.3753.1252.625
0.50
0
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. SUPPLY VOLTAGE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
V
DD (V)
GAIN MATCHING (LSB)
MAX1245-11
2.375 2.875 3.3753.125
2.625
0.50
0
-55 -30 20
CHANNEL-TO-CHANNEL GAIN MATCHING
vs. TEMPERATURE
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
TEMPERATURE (˚C)
GAIN MATCHING (LSB)
-5 45 1451209570
MAX1245-12
____________________________Typical Operating Characteristics (continued)
(VDD = 2.5V, VREF = 2.048V, fCLK = 1.5MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
6 _______________________________________________________________________________________
____________________________Typical Operating Characteristics (continued)
(VDD = 2.5V, VREF = 2.048V, fCLK = 1.5MHz, CLOAD = 20pF, TA = +25°C, unless otherwise noted.)
100
1000
0.1
0.1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
10
1
CONVERSIONS PER CHANNEL PER SECOND (Hz)
IDD (µA)
101 1k 10k100 100k
MAX1245-13
VDD = VREF = 2.5V
CODE = 101010100000
RL =
8 CHANNELS
1 CHANNEL
0.15
-0.25
0.25
04096
INTEGRAL NONLINEARITY
-0.20
0.20
0.10
-0.10
-0.15
INL (BITS)
0.05
0
-0.05
2048
DIGITAL CODE
20
-120
0
FFT PLOT
-100
0
-80
-40
-20
-60
10 20 30 40 50
AMPLITUDE (dB)
FREQUENCY (kHz)
fTONE = 10ksps
fSAMPLE = 100ksps
12.0
10.5
10.0
1 10 100
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
MAX1245-14
INPUT FREQUENCY (kHz)
EFFECTIVE NUMBER OF BITS
11.5
11.0
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________________________________________________________________________________ 7
NAME FUNCTION
1–8 CH0–CH7 Sampling Analog Inputs
9COM Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
PIN
10 SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1245 down to 10µA (max) supply current; oth-
erwise, the MAX1245 is fully operational. Letting SHDN be open sets the internal clock frequency to 1.5MHz.
Pulling SHDN high sets the internal clock frequency to 225kHz. See
Hardware Power-Down
section.
11 VREF External Reference Voltage Input for analog-to-digital conversion
15 DOUT Serial Data Output. Data is clocked out at the falling edge of SCLK. High impedance when CS is high.
14 DGND Digital Ground
13 AGND Analog Ground
12, 20 VDD Positive Supply Voltage
19 SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
18 CS Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
17 DIN Serial Data Input. Data is clocked in at the rising edge of SCLK.
16 SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1245 begins the A/D con-
version and goes high when the conversion is done. In external clock mode, SSTRB pulses high for
one clock period before the MSB decision. High impedance when CS is high (external clock mode).
______________________________________________________________Pin Description
VDD
6k
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
6k
DOUT
a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL
VDD
6k
DGND
DOUT
CLOAD
50pF
CLOAD
50pF
DGND
6k
DOUT
a) VOH to High-Z b) VOL to High-Z
Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
8 _______________________________________________________________________________________
_______________Detailed Description
The MAX1245 analog-to-digital converter (ADC) uses a
successive-approximation conversion technique and
input track/hold (T/H) circuitry to convert an analog sig-
nal to a 12-bit digital output. A flexible serial interface
provides easy interface to microprocessors (µPs). No
external hold capacitors are required. Figure 3 is a
block diagram of the MAX1245.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog compara-
tor is illustrated in the equivalent input circuit (Figure 4). In
single-ended mode, IN+ is internally switched to
CH0–CH7, and IN- is switched to COM. In differential
mode, IN+ and IN- are selected from the following pairs:
CH0/CH1, CH2/CH3, CH4/CH5, and CH6/CH7. Configure
the channels with Tables 2 and 3.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as the
positive input (IN+) charges capacitor CHOLD. The acqui-
sition interval spans three SCLK cycles and ends on the
falling SCLK edge after the last bit of the input control
word has been entered. At the end of the acquisition inter-
val, the T/H switch opens, retaining charge on CHOLD as a
sample of the signal at IN+.
The conversion interval begins with the input multiplexer
switching CHOLD from the positive input, IN+, to the
negative input, IN- (In single-ended mode, IN- is simply
COM). This unbalances node ZERO at the input of the
comparator. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node ZERO
to 0V within the limits of 12-bit resolution. This action is
equivalent to transferring a charge of 16pF x [(VIN+) -
(VIN-)] from CHOLD to the binary-weighted capacitive
DAC, which in turn forms a digital representation of the
analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by:
tACQ = 9 x (RS+ RIN) x 16pF
INPUT
SHIFT
REGISTER CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
T/H
ANALOG
INPUT
MUX
12-BIT
SAR
ADC
IN
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
CH0
CH1
CH3
CH2
CH7
CH6
CH5
CH4
COM
VREF
OUT
REF
CLOCK
1
2
3
4
5
6
7
8
10
11
9
15
16
17
18
19
MAX1245
CS
SHDN
12, 20
14
13
Figure 3. Block Diagram
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
12k
CHOLD
HOLD
12-BIT CAPACITIVE DAC
VREF
ZERO
COMPARATOR
+
16pF
SINGLE-ENDED MODE: IN+ = CHO–CH7, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4. Equivalent Input Circuit
MAX1245
0.1µF
2.048V
VDD
DGND
AGND
COM
CS
SCLK
DIN
DOUT
SSTRB
SHDN
+2.5V
N.C.
0.01µF
CH7
VREF
C1
0.1µF
0V TO
2.048V
ANALOG
INPUT
OSCILLOSCOPE
CH1 CH2 CH3 CH4
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
MAX1245
+2.5V
1.5MHz
OSCILLATOR
SCLK
SSTRB
DOUT*
Figure 5. Quick-Look Circuit
where RIN = 12k, RS= the source impedance of the
input signal, and tACQ is never less than 2.0µs. Note
that source impedances below 1kdo not significantly
affect the AC performance of the ADC. Higher source
impedances can be used if an input capacitor is con-
nected to the analog inputs, as shown in Figure 5. Note
that the input capacitor forms an RC filter with the input
source impedance, limiting the ADC’s signal bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to VDD and AGND, allow the channel input pins to
swing from AGND - 0.3V to VDD + 0.3V without dam-
age. However, for accurate conversions near full scale,
the inputs must not exceed VDD by more than 50mV or
be lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over two milliamperes, as excessive
current will degrade the conversion accuracy of the
on channel.
Quick Look
To quickly evaluate the MAX1245’s analog perfor-
mance, use the circuit of Figure 5. The MAX1245
requires a control byte to be written to DIN before each
conversion. Tying DIN to VDD feeds in control bytes of
$FF (HEX), which trigger single-ended unipolar conver-
sions on CH7 in external clock mode without powering
down between conversions. In external clock mode, the
SSTRB output pulses high for one clock period before
the most significant bit of the 12-bit conversion result is
shifted out of DOUT. Varying the analog input to CH7
alters the sequence of bits from DOUT. A total of 15
clock cycles is required per conversion. All transitions
of the SSTRB and DOUT outputs occur on the falling
edge of SCLK.
How to Start a Conversion
A conversion is started by clocking a control byte into
DIN. With CS low, each rising edge on SCLK clocks a
bit from DIN into the MAX1245’s internal shift register.
After CS falls, the first arriving logic “1” bit defines the
MSB of the control byte. Until this first “start” bit arrives,
any number of logic “0” bits can be clocked into DIN
with no effect. Table 1 shows the control-byte format.
The MAX1245 is compatible with MICROWIRE, SPI, and
QSPI devices. For SPI, select the correct clock polarity
and sampling edge in the SPI control registers: set
CPOL = 0 and CPHA = 0. MICROWIRE, SPI, and QSPI
all transmit a byte and receive a byte at the same time.
Using the
Typical Operating Circuit,
the simplest soft-
ware interface requires only three 8-bit transfers to
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
_______________________________________________________________________________________ 9
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
10 ______________________________________________________________________________________
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(MSB) (LSB)
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
BIT NAME DESCRIPTION
7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.
6 SEL2 These three bits select which of the eight channels are used for the conversion (Tables 2 and 3).
5 SEL1
4 SEL0
3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF/2 to +VREF/2.
2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
1 PD1 Selects clock and power-down modes.
0(LSB) PD0 PD1 PD0 Mode
0 0 Power-down (IQ= 1.2µA)
0 1 Unassigned
1 0 Internal clock mode
1 1 External clock mode
Table 1. Control-Byte Format
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
00 0 +
10 0 +
00 1 +
10 1 +
01 0 +
11 0 +
01 1 +–
11 1 +
Table 2. Channel Selection in Single-Ended Mode (SGL/DDIIFF= 1)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
00 0 +
00 1 +
01 0 +
01 1 +–
10 0 +
10 1 +
11 0 +
11 1 –+
Table 3. Channel Selection in Differential Mode (SGL/DDIIFF= 0)
perform a conversion (one 8-bit transfer to configure the
ADC, and two more 8-bit transfers to clock out the 12-bit
conversion result). See Figure 17 for MAX1245 QSPI
connections.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 1.5MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 HEX) and, simulta-
neously, receive byte RB2.
5) Transmit a byte of all zeros ($00 HEX) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
Figure 6 shows the timing for this sequence. Bytes RB2
and RB3 will contain the result of the conversion
padded with one leading zero and three trailing zeros.
The total conversion time is a function of the serial
clock frequency and the amount of idle time between
8-bit transfers. Make sure that the total conversion time
does not exceed 120µs, to avoid excessive T/H droop.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 14). For bipolar inputs, the output is two’s-com-
plement (Figure 15). Data is clocked out at the falling
edge of SCLK in MSB-first format.
Clock Modes
The MAX1245 may use either an external serial clock or
the internal clock to perform the successive-approxima-
tion conversion. In both clock modes, the external clock
shifts data in and out of the MAX1245. The T/H acquires
the input signal as the last three bits of the control byte
are clocked into DIN. Bits PD1 and PD0 of the control
byte program the clock mode. Figures 7–10 show the
timing characteristics common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
version. SSTRB pulses high for one clock period after
the control byte’s last bit. Successive-approximation bit
decisions are made and appear at DOUT on each of the
next 12 SCLK falling edges (Figure 6). SSTRB and
DOUT go into a high-impedance state when CS goes
high; after the next CS falling edge, SSTRB outputs a
logic low. Figure 8 shows the SSTRB timing in external
clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
______________________________________________________________________________________ 11
SSTRB
CS
SCLK
DIN
DOUT
14 8 12 16 20 24
START
SEL2 SEL1 SEL0 UNI/
BIP SGL/
DIF PD1 PD0
B11
MSB B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
LSB
ACQUISITION
(SCLK = 1.5MHz)
IDLE
FILLED WITH
ZEROS
IDLE
CONVERSION
tACQ
A/D STATE
RB1 RB2 RB3
2.0µs
Figure 6. 24-Clock External-Clock-Mode Conversion Timing (MICROWIRE and SPI Compatible, QSPI Compatible with fCLK
1.5MHz)
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
12 ______________________________________________________________________________________
Internal Clock
In internal clock mode, the MAX1245 generates its own
conversion clock internally. This frees the µP from the
burden of running the SAR conversion clock and allows
the conversion results to be read back at the proces-
sor’s convenience, at any clock rate from zero to
1.5MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB will be low for a maximum of 7.5µs (SHDN =
open), during which time SCLK should remain low for
best noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 9). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1245 and three-states DOUT, but it does not
adversely affect an internal clock-mode conversion
already in progress. When internal clock mode is
• • •
• • • • • •
• • •
tSDV
tSSTRB
PD0 CLOCKED IN
tSTR
SSTRB
SCLK
CS
tSSTRB
• • • • • •
Figure 8. External-Clock-Mode SSTRB Detailed Timing
• • •
• • •
• • •
• • •
CS
SCLK
DIN
DOUT
tCSH
tCSS tCL
tDS
tDH
tDV
tCH
tDO tTR
tCSH
Figure 7. Detailed Serial-Interface Timing
selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1245 at clock rates exceeding 1.5MHz, provid-
ed that the minimum acquisition time, tACQ, is kept
above 2.0µs.
Data Framing
The falling edge of CS does not start a conversion on
the MAX1245. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
SCLK, after the eighth bit of the control byte (the PD0
bit) is clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after VDD is applied.
OR
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
If CS is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nized as a start bit; the current conversion is terminated,
and a new one is started.
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
______________________________________________________________________________________ 13
SSTRB
CS
SCLK
DIN
DOUT
14 8 12 18 20 24
START
SEL2 SEL1 SEL0 UNI/
BIP
SGL/
DIF PD1 PD0
B11
MSB B10 B9 B2 B1 B0
LSB
FILLED WITH
ZEROS
IDLE
CONVERSION
7.5µs MAX
(SHDN = OPEN)
2 3 5 6 7 9 10 11 19 21 22 23
tCONV
ACQUISITION
(SCLK = 1.5MHz)
IDLE
A/D STATE 2.0µs
PD0 CLOCK IN
tSSTRB
tCSH
tCONV
tSCK
SSTRB • • •
SCLK • • •
DOUT • • •
tCSS
tDO
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS • • •
Figure 9. Internal Clock Mode Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing
The fastest the MAX1245 can run is 15 clocks per conver-
sion with CS held low between conversions. Figure 11a
shows the serial-interface timing necessary to perform a
conversion every 15 SCLK cycles in external clock mode.
If CS is low and SCLK is continuous, guarantee a start bit
by first clocking in 16 zeros.
Most microcontrollers require that conversions occur in
multiples of eight SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX1245. Figure 11b shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
__________ Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1245 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies have stabi-
lized, the internal reset time is 10µs, and no conver-
sions should be performed during this phase. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN will be interpreted as a start bit. Until a conversion
takes place, DOUT shifts out zeros.
Power-Down
The MAX1245’s automatic power-down mode can save
considerable power when operating at speeds below
the maximum sampling rate. Figure 13 shows the aver-
age supply current as a function of the sampling rate.
You can save power by placing the converter in a low-
current shutdown state between conversions.
Select power-down via bits 1 and 0 of the DIN control
byte with SHDN high (Tables 1 and 4). Pull SHDN low at
any time to shut down the converter completely. SHDN
overrides bits 1 and 0 of the control byte (Table 5).
Power-down mode turns off all chip functions that draw
quiescent current, reducing IDD typically to 1.2µA.
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 4, PD1 and PD0
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
14 ______________________________________________________________________________________
SCLK
DIN
DOUT
CS
S CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
SSTRB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONTROL BYTE 2S
18181
CS
SCLK
DIN
DOUT
S CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8
CONVERSION RESULT 1
• • •
• • •
• • •
• • •
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
______________________________________________________________________________________ 15
POWERED UP
HARDWARE
POWER-
DOWN POWERED UP
POWERED UP
12 DATA BITS 12 DATA BITS INVALID
DATA
VALID
DATA
EXTERNAL
EXTERNAL
SXXXXX11 S 00
XXXXX XX XXX
S11
SOFTWARE
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS SOFTWARE
POWER-DOWN
SOFTWARE
POWER-DOWN
POWERED UP
POWERED UP
DATA VALID DATA VALID
INTERNAL
SXXXXX10 S 00
XXXXX S
MODE
DOUT
DIN
CLOCK
MODE SETS INTERNAL
CLOCK MODE
SETS
POWER-DOWN
CONVERSION
CONVERSION
SSTRB
Figure 12a. Timing Diagram Power-Down Modes, External Clock
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
PD1 PD0 DEVICE MODE
1 1 External Clock
1 0 Internal Clock
0 1 Unassigned
0 0 Power-Down
SSHHDDNNDEVICE INTERNAL CLOCK
STATE MODE FREQUENCY
1 Enabled 225kHz
Open Enabled 1.5MHz
0 Power-Down N/A
Table 4. Software Power-Down and
Clock Mode
Table 5. Hard-Wired Power-Down and
Internal Clock Frequency
also specify the clock mode. When software shutdown is
asserted, the ADC continues to operate in the last speci-
fied clock mode until the conversion is complete. Then the
ADC powers down into a low quiescent-current state. In
internal clock mode, the interface remains active and con-
version results can be clocked out after the MAX1245 has
entered a software power-down.
The first logical 1 on DIN is interpreted as a start bit, and
powers up the MAX1245. Following the start bit, the data
input word or control byte also determines clock mode
and power-down states. For example, if the DIN word
contains PD1 = 1, the chip remains powered up. If PD0 =
PD1 = 0, a power-down resumes after one conversion.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down. Unlike the software power-down mode, the
conversion is not completed; it stops coincidentally with
SHDN being brought low. SHDN also controls the clock
frequency in internal clock mode. Letting SHDN be open
sets the internal clock frequency to 1.5MHz. When
returning to normal operation with SHDN open, there is a
tRC delay of approximately 2Mx CL, where CLis the
capacitive loading on the SHDN pin. Pulling SHDN high
sets the internal clock frequency to 225kHz. This feature
eases the settling-time requirement for the reference
voltage.
External Reference
An external reference is required for the MAX1245. The
reference voltage range is 1V to VDD.
At VREF, the input impedance is a minimum of 18kfor
DC currents. During a conversion, the reference must
be able to deliver up to 250µA DC load current and
have an output impedance of 10or less. If the refer-
ence has higher output impedance or is noisy, bypass
it close to the VREF pin with a 0.1µF capacitor.
Transfer Function
Table 6 shows the full-scale voltage ranges for unipolar
and bipolar modes using a 2.048V reference.
The external reference must have a temperature coefficient
of 4ppm/°C or less to achieve accuracy to within 1LSB over
the commercial temperature range of 0°C to +70°C.
Figure 14 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 15 shows the bipolar
input/output transfer function. Code transitions occur
halfway between successive-integer LSB values.
Output coding is binary, with 1LSB = 500µV (2.048V /
4096) for unipolar operation and 1LSB = 500µV
[(2.048V / 2 - -2.048V / 2) / 4096] for bipolar operation.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 16 shows the recommended system ground
connections. A single-point analog ground (“star”
ground point) should be established at AGND, sepa-
rate from the logic ground. Connect all other analog
grounds and DGND to the star ground. No other digital
system ground should be connected to this ground.
The ground return to the power supply for the star
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
16 ______________________________________________________________________________________
100
1000
0.1
0.1
AVERAGE SUPPLY CURRENT
vs. CONVERSION RATE
10
1
CONVERSIONS PER CHANNEL PER SECOND (Hz)
IDD (µA)
1011k10k100 100k
MAX1245-13
1 CHANNEL
8 CHANNELS
VDD = VREF = 2.5V
CODE = 101010100000
RL =
Figure 13. Average Supply Current vs. Conversion Rate
Table 6. Full Scale and Zero Scale
UNIPOLAR MODE BIPOLAR MODE
Full Scale Zero Scale Positive Zero Negative
Full Scale Scale Full Scale
VREF + COM COM VREF/2 COM -VREF/2
+ COM + COM
ground should be low impedance and as short as pos-
sible for noise-free operation.
High-frequency noise in the VDD power supply may
affect the high-speed comparator in the ADC. Bypass
the supply to the star ground with 0.1µF and 4.7µF
capacitors close to pin 20 of the MAX1245. Minimize
capacitor lead lengths for best supply-noise rejection. If
the +2.5V power supply is very noisy, a 10resistor
can be connected as a lowpass filter (Figure 16).
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
______________________________________________________________________________________ 17
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
123
0
(COM)
FS
FS - 3/2LSB
FS = VREF + COM
ZS = COM
INPUT VOLTAGE (LSBs)
1LSB = VREF
4096
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
- FS COM
INPUT VOLTAGE (LSBs)
OUTPUT CODE
ZS = COM
+FS - 1LSB
( VREF/2)
+ COM
FS = VREF
2
-FS = + COM
-VREF
2
1LSB = VREF
4096
Figure 14. Unipolar Transfer Function, Full Scale (FS) = VREF
+ COM, Zero Scale (ZS) = COM
Figure 15. Bipolar Transfer Function, Full Scale (FS) = VREF /
2 + COM, Zero Scale (ZS) = COM
+2.5V +2.5V GND
SUPPLIES
DGND+2.5VDGNDCOM
AGNDVDD
DIGITAL
CIRCUITRY
MAX1245
R* = 10
* OPTIONAL
Figure 16. Power-Supply Grounding Connection
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
18 ______________________________________________________________________________________
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
MAX1245 MC683XX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SHDN
VDD
SCLK
CS
DIN
SSTRB
DOUT
DGND
AGND
VDD
VREF
(POWER SUPPLIES)
SCK
PCS0
MOSI
MISO
CLOCK CONNECTIONS NOT SHOWN
0.1µF4.7µF
(GND)
0.1µF
ANALOG
INPUTS
+3V
+2.5V
+2.048V
Figure 17. MAX1245 QSPI Connections
High-Speed Digital Interfacing with QSPI
The MAX1245 can interface with QSPI using the circuit in
Figure 17 (fSCLK = 1.5MHz, CPOL = 0, CPHA = 0). This
QSPI circuit can be programmed to do a conversion on
each of the eight channels. The result is stored in memory
without taxing the CPU, since QSPI incorporates its own
micro-sequencer.
Because the maximum external clock frequency is
1.5MHz, the MAX1245 is QSPI compatible up to 1.5MHz.
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
______________________________________________________________________________________ 19
TMS320LC3x-to-MAX1245 Interface
Figure 18 shows an application circuit to interface the
MAX1245 to the TMS320 in external clock mode. The tim-
ing diagram for this interface circuit is shown in Figure 19.
Use the following steps to initiate a conversion in the
MAX1245 and to read the results:
1) The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
tied together with the MAX1245’s SCLK input.
2) The MAX1245’s CS pin is driven low by the TMS320’s
XF_ I/O port, to enable data to be clocked into the
MAX1245’s DIN.
3) An 8-bit word (1XXXXX11) should be written to the
MAX1245 to initiate a conversion and place the
device into external clock mode. Refer to Table 1 to
select the proper XXXXX bit values for your specific
application.
4) The MAX1245’s SSTRB output is monitored via the
TMS320’s FSR input. A falling edge on the SSTRB
output indicates that the conversion is in progress
and data is ready to be received from the
MAX1245.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 12-bit conversion result followed by four
trailing bits, which should be ignored.
6) Pull CS high to disable the MAX1245 until the next
conversion is initiated.
CS
SCLK
DIN
SSTRB
DOUT
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
MSB B10 B1 LSB HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 19. TMS320 Serial-Interface Timing Diagram
XF
CLKX
CLKR
DX
DR
FSR
CS
SCLK
DIN
DOUT
SSTRB
TMS320LC3x
MAX1245
Figure 18. MAX1245-to-TMS320 Serial Interface
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
20 ______________________________________________________________________________________
Chip Information
TRANSISTOR COUNT: 2554
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
20 PDIP A20-1 21-0056
20 SSOP P20-4 21-0043
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
21
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 6/96 Initial release.
1 11/09 Removed the dice package from the Ordering Information table. 1