Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES DECEMBER 1996
1996 Integrated Device Technology, Inc. DSC-2661/9
5.04 1
FEATURES:
• First-In/First-Out Dual-Port memory
• 2048 x 9 organization (IDT7203)
• 4096 x 9 organization (IDT7204)
• 8192 x 9 organization (IDT7205)
• 16384 x 9 organization (IDT7206)
• High-speed: 12ns access time
• Low power consumption
— Active: 770mW (max.)
— Power-down: 44mW (max.)
• Asynchronous and simultaneous read and write
• Fully expandable in both word depth and width
• Pin and functionally compatible with IDT720X family
• Status Flags: Empty, Half-Full, Full
• Retransmit capability
• High-performance CMOS technology
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing for #5962-88669 (IDT7203),
5962-89567 (IDT7203), and 5962-89568 (IDT7204) are
listed on this function
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
.
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
IDT7203
IDT7204
IDT7205
IDT7206
DESCRIPTION:
The IDT7203/7204/7205/7206 are dual-port memory buff-
ers with internal pointers that load and empty data on a first-
in/first-out basis. The device uses Full and Empty flags to
prevent data overflow and underflow and expansion logic to
allow for unlimited expansion capability in both word size and
depth.
Data is toggled in and out of the device through the use of
the Write (
W
) and Read (
R
) pins.
The devices 9-bit width provides a bit for a control or parity
at the user’s option. It also features a Retransmit (
RT
) capa-
bility that allows the read pointer to be reset to its initial position
when
RT
is pulsed LOW. A Half-Full Flag is available in the
single device and width expansion modes.
The IDT7203/7204/7205/7206 are fabricated using IDT’s
high-speed CMOS technology. They are designed for appli-
cations requiring asynchronous and simultaneous read/writes
in multiprocessing, rate buffering, and other applications.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9,
8192 x 9 and 16384 x 9
W
WRITE
CONTROL
READ
CONTROL
R
FLAG
LOGIC
EXPANSION
LOGIC
XI
WRITE
POINTER RAM ARRAY
2048 x 9
4096 x 9
8192 x 9
16384 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS DATA OUTPUTS
EF
FF
XO
/
HF
RS
FL
/
RT
0(D –D8)
0(Q –Q8)
2661 drw 01
FUNCTIONAL BLOCK DIAGRAM
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.04 2
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Commercial Military Unit
VTERM Terminal –0.5 to + 7.0 –0.5 to +7.0 V
Voltage with
Respect to
GND
TAOperating 0 to +70 –55 to +125 ° C
Temperature
TBIAS Temperature –55 to +125 –65 to +135 ° C
Under Bias
TSTG Storage –55 to + 125 –65 to +155 ° C
Temperature
IOUT DC Output 50 50 mA
Current
NOTE: 2661 tbl 01
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCCM Military Supply 4.5 5.0 5.5 V
Voltage
VCCC Commercial Supply 4.5 5.0 5.5 V
Voltage
GND Supply Voltage 0 0 0 V
VIH(1) Input High Voltage 2.0 — — V
Commercial
VIH(1) Input High Voltage 2.2 — — V
Military
VIL(1) Input Low Voltage — — 0.8 V
Commercial and
Military
NOTE: 2661 tbl 02
1. 1.5V undershoots are allowed for 10ns once per cycle.
5
6
7
8
9
10
11
12
13
FF
D
2
D
1
D
0
XI
Q
0
Q
1
GND
Q
2
1
2
3
4
14
Q
3
28
27
26
25
24
23
22
21
EF
XO/HF
Vcc
FL/RT
RS
20
19
18
17
16
15
D
3
D
8
W
Q
8
D
6
D
5
D
4
D
7
Q
5
Q
6
Q
7
Q
4
R
P28-1
P28-2
D28-1
D28-3
SO28-3
2661 drw 02a
DIP
TOP VIEW
NOTES:
1. The THINDIPs P28-2 and D28-3 are only available for the 7203/7204/
7205.
2. The small outline package SO28-3 is only available for the 7204.
3. Consult factory for CERPACK pinout.
PLCC/LCC
TOP VIEW
5
6
7
8
9
10
11
12
13
J32-1
&
L32-1
FF
D
2
D
1
D
0
XI
Q
0
Q
1
29
28
27
26
25
24
23
22
21
EF
XO
/
HF
D
6
D
7
NC
FL
/
RT
RS
Q
7
Q
6
14
15
16
17
18
19
20
4
3
2
132
31
30
INDEX
NC
Q
2
D
3
D
8
W
NC
Vcc
D
5
D
4
GND
Q
3
Q
8
NC
Q
5
Q
4
R
2661 drw 02b
5.04 3
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS FOR THE 7205 AND 7206
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
IDT7205/7206 IDT7205/7206
Commercial Military
tA = 15, 20, 25, 35, 50 ns tA = 20, 30, 50 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
ILI(1) Input Leakage Current (Any Input) –1 — 1 –1 — 1 µA
ILO(2) Output Leakage Current –10 — 10 –10 — 10 µA
VOH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — V
VOL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 V
ICC1(3) Active Power Supply Current — — 120(4) — — 150(4) mA
ICC2(3) Standby Current (
R
=
W
=
RS
=
FL
/
RT
=VIH)——12— —25mA
I
CC3(L)(3) Power Down Current (All Input = VCC - 0.2V) — — 8 — — 12 mA
DC ELECTRICAL CHARACTERISTICS FOR THE 7203 AND 7204
(Commercial: VCC = 5.0V±10%, TA = 0°C to +70°C; Military: VCC = 5.0V±10%, TA = –55°C to +125°C)
IDT7203/7204 IDT7203/7204
Commercial Military(1)
tA = 12, 15, 20, 25, 35, 50 ns tA = 20, 30, 40, 50, 65, 80, 120 ns
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit
ILI(2) Input Leakage Current (Any Input) –1 — 1 –1 — 1 µA
ILO(3) Output Leakage Current –10 — 10 –10 — 10 µA
VOH Output Logic “1” Voltage IOH = –2mA 2.4 — — 2.4 — — V
VOL Output Logic “0” Voltage IOL = 8mA — — 0.4 — — 0.4 V
ICC1(4) Active Power Supply Current — — 120(5) — — 150(5) mA
ICC2(4) Standby Current (
R
=
W
=
RS
=
FL
/
RT
=VIH)——12— —25mA
I
CC3(L)(4) Power Down Current (All Input = VCC - 0.2V) — — 2 — — 4 mA
ICC3(S)(4) Power Down Current (All Input = VCC - 0.2V) — — 8 — — 12 mA
NOTES: 2661 tbl 03
1. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. ICC measurements are made with outputs open (only capacitive loading).
5. Tested at f = 20MHz.
NOTES: 2661 tbl 04
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3. ICC measurements are made with outputs open (only capacitive loading).
4. Tested at f = 20MHz.
5.04 4
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Commercial Com'l & Mil. Com'l Military Com'l
7203S/L12 7203S/L15 7203S/L20 7203S/L25 7203S/L30 7203S/L35
7204S/L12 7204S/L15 7204S/L20 7204S/L25 7204S/L30 7204S/L35
7205L15 7205L20 7205L25 7205L30 7205L35
7206L15 7206L20 7206L25 7206L30 7206L35
Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fSShift Frequency — 50 — 40 — 33.3 — 28.5 — 25 — 22.2 MHz
tRC Read Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
tAAccess Time — 12 — 15 — 20 — 25 — 30 — 35 ns
tRR Read Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
tRPW Read Pulse Width(2) 12 — 15 — 20 — 25 — 30 — 35 — ns
tRLZ Read LOW to Data Bus LOW(3) 3—5—5 — 5—5—5—ns
t
WLZ Write HIGH to Data Bus Low-Z(3, 4) 3—5—5 — 5—5—10—ns
t
DV Data Valid from Read HIGH 5 — 5 — 5 — 5 — 5 — 5 — ns
tRHZ Read HIGH to Data Bus High-Z(3) — 12 — 15 — 15 — 18 — 20 — 20 ns
tWC Write Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
tWPW Write Pulse Width(2) 12 — 15 — 20 — 25 — 30 — 35 — ns
tWR Write Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
tDS Data Set-up Time 9 — 11 — 12 — 15 — 18 — 18 — ns
tDH Data Hold Time 0 — 0 — 0 — 0 — 0 — 0 — ns
tRSC Reset Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
tRS Reset Pulse Width(2) 12 — 15 — 20 — 25 — 30 — 35 — ns
tRSS Reset Set-up Time(3) 12 — 15 — 20 — 25 — 30 — 35 — ns
tRTR Reset Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
tRTC Retransmit Cycle Time 20 — 25 — 30 — 35 — 40 — 45 — ns
tRT Retransmit Pulse Width(2) 12 — 15 — 20 — 25 — 30 — 35 — ns
tRTS Retransmit Set-up Time(3) 12 — 15 — 20 — 25 — 30 — 35 — ns
tRSR Retransmit Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
tEFL Reset to
EF
LOW — 12 — 25 — 30 — 35 — 40 — 45 ns
tHFH, tFFH Reset to
HF
and
FF
HIGH — 17 — 25 — 30 — 35 — 40 — 45 ns
tRTF Retransmit LOW to Flags Valid — 20 — 25 — 30 — 35 — 40 — 45 ns
tREF Read LOW to
EF
LOW — 12 — 15 — 20 — 25 — 30 — 30 ns
tRFF Read HIGH to
FF
HIGH — 14 — 15 — 20 — 25 — 30 — 30 ns
tRPE Read Pulse Width after
EF
HIGH 12 — 15 — 20 — 25 — 30 — 35 — ns
tWEF Write HIGH to
EF
HIGH — 12 — 15 — 20 — 25 — 30 — 30 ns
tWFF Write LOW to
FF
LOW — 14 — 15 — 20 — 25 — 30 — 30 ns
tWHF Write LOW to
HF
Flag LOW — 17 — 25 — 30 — 35 — 40 — 45 ns
tRHF Read HIGH to
HF
Flag HIGH — 17 — 25 — 30 — 35 — 40 — 45 ns
tWPF Write Pulse Width after
FF
HIGH 12 — 15 — 20 — 25 — 30 — 35 — ns
tXOL Read/Write LOW to
XO
LOW — 12 — 15 — 20 — 25 — 30 — 35 ns
tXOH Read/Write HIGH to
XO
HIGH — 12 — 15 — 20 — 25 — 30 — 35 ns
tXI
XI
Pulse Width(2) 12 — 15 — 20 — 25 — 30 — 35 — ns
tXIR
XI
Recovery Time 8 — 10 — 10 — 10 — 10 — 10 — ns
tXIS
XI
Set-up Time 8 — 10 — 10 — 10 — 10 — 15 — ns
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: V CC = 5V ± 10%, TA = –55°C to +125°C)
NOTES: 2661 tbl 05
1. Timings referenced as in AC Test Conditions.
2. Pulse widths less than minimum are not allowed.
3. Values guaranteed by design, not currently tested.
4. Only applies to read data flow-through mode.
5.04 5
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Military Com'l & Mil. Military(2)
7203S/L40 7203S/L50 7203S/L65 7203S/L80 7203S/L120
7204S/L40 7204S/L50 7204S/L65 7204S/L80 7204S/L120
7205L50
7206L50
Symbol Parameters Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fSShift Frequency — 20 — 15 — 12.5 — 10 — 7 MHz
tRC Read Cycle Time 50 — 65 — 80 — 100 — 140 — n s
tAAccess Time — 40 — 50 — 65 — 80 — 120 ns
tRR Read Recovery Time 10 — 15 — 15 — 20 — 20 — n s
tRPW Read Pulse Width(3) 40 — 50 — 65 — 80 — 120 — ns
tRLZ Read LOW to Data Bus LOW(4) 5 — 10 — 10 — 10 — 10 — ns
tWLZ Write HIGH to Data Bus Low-Z(4, 5) 10 — 15 — 15 — 20 — 20 — ns
tDV Data Valid from Read HIGH 5 — 5 — 5 — 5 — 5 — ns
tRHZ Read HIGH to Data Bus High-Z(4) — 25 — 30 — 30 — 30 — 35 ns
tWC Write Cycle Time 50 — 65 — 80 — 100 — 140 — ns
tWPW Write Pulse Width(3) 40 — 50 — 65 — 80 — 120 — ns
tWR Write Recovery Time 10 — 15 — 15 — 20 — 20 — ns
tDS Data Set-up Time 20 — 30 — 30 — 40 — 40 — ns
tDH Data Hold Time 0 — 5 — 10 — 10 — 10 — ns
tRSC Reset Cycle Time 50 — 65 — 80 — 100 — 140 — ns
tRS Reset Pulse Width(3) 40 — 50 — 65 — 80 — 120 — ns
tRSS Reset Set-up Time(4) 40 — 50 — 65 — 80 — 120 — ns
tRSR Reset Recovery Time 10 — 15 — 15 — 20 — 20 — ns
tRTC Retransmit Cycle Time 50 — 65 — 80 — 100 — 140 — ns
tRT Retransmit Pulse Width(3) 40 — 50 — 65 — 80 — 120 — ns
tRTS Retransmit Set-up Time(4) 40 — 50 — 65 — 80 — 120 — ns
tRSR Retransmit Recovery Time 10 — 15 — 15 — 20 — 20 — ns
tEFL Reset to
EF
LOW — 50 — 65 — 80 — 100 — 140 ns
tHFH, tFFH Reset to
HF
and
FF
HIGH — 50 — 65 — 80 — 100 — 140 ns
tRTF Retransmit LOW to Flags Valid — 50 — 65 — 80 — 100 — 140 ns
tREF Read LOW to
EF
Flag LOW — 35 — 45 — 60 — 60 — 60 ns
tRFF Read HIGH to
FF
HIGH — 35 — 45 — 60 — 60 — 60 ns
tRPE Read Pulse Width after
EF
HIGH 40 — 50 — 65 — 80 — 120 — ns
tWEF Write HIGH to
EF
HIGH — 35 — 45 — 60 — 60 — 60 ns
tWFF Write LOW to
FF
LOW — 35 — 45 — 60 — 60 — 60 ns
tWHF Write LOW to
HF
LOW — 50 — 65 — 80 — 100 — 140 ns
tRHF Read HIGH to
HF
HIGH — 50 — 65 — 80 — 100 — 140 ns
tWPF Write Pulse Width after
FF
HIGH 40 — 50 — 65 — 80 — 120 — ns
tXOL Read/Write LOW to
XO
LOW — 40 — 50 — 65 — 80 — 120 ns
tXOH Read/Write HIGH to
XO
HIGH — 40 — 50 — 65 — 80 — 120 ns
tXI
XI
Pulse Width(3) 40 — 50 — 65 — 80 — 120 — ns
tXIR
XI
Recovery Time 10 — 10 — 10 — 10 — 10 — ns
tXIS
XI
Set-up Time 15 — 15 — 15 — 15 — 15 — ns
AC ELECTRICAL CHARACTERISTICS(1) (Continued)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: V CC = 5V ± 10%, TA = –55°C to +125°C)
NOTES: 2661 tbl 06
1. Timings referenced as in AC Test Conditions.
2. Speed grades 65, 80, and 120ns are only available in the ceramic DIP.
3. Pulse widths less than minimum are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
5.04 6
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
2661 tbl 07
CAPACITANCE(1) (TA = +25°C, f = 1.0 MHz)
Symbol Parameter Condition Max. Unit
CIN(1) Input Capacitance V IN = 0V 10 pF
COUT(1,2) Output Capacitance VOUT = 0V 10 pF
NOTES: 2661 tbl 08
1. This parameter is sampled and not 100% tested.
2. With output deselected.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure 1
SIGNAL DESCRIPTIONS
Inputs:
DATA IN (D0–D8) — Data inputs for 9-bit wide data.
Controls:
RESET (
RS
RS
) — Reset is accomplished whenever the Reset
(
RS
) input is taken to a LOW state. During reset, both internal
read and write pointers are set to the first location. A reset is
required after power-up before a write operation can take place.
Both the Read Enable (
R
R
) and Write Enable (
W
W
) inputs must
be in the HIGH state during the window shown in Figure 2
(i.e. tRSS before the rising edge of
RS
RS
) and should not
change until tRSR after the rising edge of
RS
RS
.
WRITE ENABLE (
W
W
) — A write cycle is initiated on the falling
edge of this input if the Full Flag (
FF
) is not set. Data set-up and
hold times must be adhered-to, with respect to the rising edge
of the Write Enable (
W
). Data is stored in the RAM array
sequentially and independently of any on-going read operation.
After half of the memory is filled, and at the falling edge of the
next write operation, the Half-Full Flag (
HF
) will be set to LOW,
and will remain set until the difference between the write pointer
and read pointer is less-than or equal to one-half of the total
memory of the device. The Half-Full Flag (
HF
) is reset by the
rising edge of the read operation.
To prevent data overflow, the Full Flag (
FF
) will go LOW on
the falling edge of the last write signal, which inhibits further write
operations. Upon the completion of a valid read operation, the
Full Flag (
FF
) will go HIGH after tRFF, allowing a new valid write
to begin. When the FIFO is full, the internal write pointer is
blocked from
W
, so external changes in
W
will not affect the FIFO
when it is full.
READ ENABLE (
R
R
) — A read cycle is initiated on the falling
edge of the Read Enable (
R
), provided the Empty Flag (
EF
) is not
set. The data is accessed on a First-In/First-Out basis, inde-
pendent of any ongoing write operations. After Read Enable (
R
)
goes HIGH, the Data Outputs (Q0 through Q8) will return to a
high-impedance condition until the next Read operation. When
all the data has been read from the FIFO, the Empty Flag (
EF
)
will go LOW, allowing the “final” read cycle but inhibiting further
read operations, with the data outputs remaining in a high-
impedance state. Once a valid write operation has been accom-
plished, the Empty Flag (
EF
) will go HIGH after tWEF and a valid
Read can then begin. When the FIFO is empty, the internal read
pointer is blocked from
R
so external changes will not affect the
FIFO when it is empty.
FIRST LOAD/RETRANSMIT (
FL
FL
/
RT
RT
) — This is a dual-
purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first device loaded (see
Operating Modes). The Single Device Mode is initiated by
grounding the Expansion In (
XI
).
The IDT7203/7204/7205/7206 can be made to retransmit
data when the Retransmit Enable Control (
RT
) input is pulsed
LOW. A retransmit operation will set the internal read pointer to
the first location and will not affect the write pointer. The status
of the Flags will change depending on the relative locations of
the read and write pointers. Read Enable (
R
) and Write Enable
(
W
) must be in the HIGH state during retransmit. This feature is
useful when less than 2048/4096/8192/16384 writes are per-
formed between resets. The retransmit feature is not compat-
ible with the Depth Expansion Mode.
EXPANSION IN (
XI
XI
) — This input is a dual-purpose pin.
Expansion In (
XI
) is grounded to indicate an operation in the
single device mode. Expansion In (
XI
) is connected to Expan-
sion Out (
XO
) of the previous device in the Depth Expansion or
Daisy-Chain Mode.
1.1KΩ
30pF*
680Ω
5V
D.U.T.
OR EQUIVALENT CIRCUIT
2661 drw 03
Figure 1. Output Load
*Includes jig and scope capacitances.
5.04 7
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Outputs:
FULL FLAG (
FF
FF
) — The Full Flag (
FF
) will go LOW, inhibiting
further write operations, when the device is full. If the read
pointer is not moved after Reset (
RS
), the Full Flag (
FF
) will go
LOW after 2048/4096/8192/16384 writes.
EMPTY FLAG (
EF
EF
) — The Empty Flag (
EF
) will go LOW,
inhibiting further read operations, when the read pointer is equal
to the write pointer, indicating that the device is empty.
EXPANSION OUT/HALF-FULL FLAG (
XO
XO
/
HF
HF
) — This is a
dual-purpose output. In the single device mode, when Expan-
sion In (
XI
) is grounded, this output acts as an indication of a half-
full memory.
After half of the memory is filled, and at the falling edge of the
next write operation, the Half-Full Flag (
HF
) will be set to LOW
Figure 2. Reset
Figure 3. Asynchronous Write and Read Operation
NOTE:
1.
W
and
R
= VIH around the rising edge of
RS
.
W
RS
R
EF
HF
,
FF
t
RSC
t
RS
t
RSS
t
RSS
t
RSR
t
EFL
t
HFH
, t
FFH
2661 drw 04
R
W
D
t
RC
t
A
t
WR
t
DS
DATA
0
–D
8
Q
0
–Q
8
t
DH
t
WPW
t
WC
VALID
t
RLZ
t
RHZ
t
DV
t
A
t
RR
t
RPW
IN
VALID
DATA
OUT
VALIDDATA
OUT
DATA
IN
VALID
2661 drw 05
and will remain set until the difference between the write pointer
and read pointer is less than or equal to one half of the total
memory of the device. The Half-Full Flag (
HF
) is then reset by
the rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (
XI
) is con-
nected to Expansion Out (
XO
) of the previous device. This
output acts as a signal to the next device in the Daisy Chain by
providing a pulse to the next device when the previous device
reaches the last location of memory. There will be an
XO
pulse
when the Write pointer reaches the last location of memory, and
an additional
XO
pulse when the Read pointer reaches the last
location of memory.
DATA OUTPUTS (Q0-Q8) — Q0-Q8 are data outputs for 9-
bit wide data. These outputs are in a high-impedance condition
whenever Read (
R
) is in a HIGH state.
5.04 8
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 4. Full FlagTiming From Last Write to First Read
NOTE:
1.
EF
,
FF
and
HF
may change status during Retransmit, but flags will be valid at tRTC.
Figure 6. Retransmit
Figure 5. Empty Flag Timing From Last Read to First Write
R
W
FF
tRFF
tWFF
FIRST READ
IGNORED
WRITE
LAST WRITE
2661 drw 06
W
R
EF
tWEF
tREF
FIRST WRITE
IGNORED
READ
LAST READ
DATA VALID
tA
OUT
2661 drw 07
t
RTC
t
RT
t
RTS
RT
W
,
R
HF
,
EF
,
FF
t
RTR
FLAG VALID
2661 drw 08
RTF
5.04 9
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse.
Figure 8. Minimum Timing for an Full Flag Coincident Write Pulse.
Figure 9. Half-Full Flag Timing
Figure 10. Expansion Out
W
R
HF
HALF-FULL OR LESS MORE THAN HALF-FULL HALF-FULL OR LESS
t
RHF
t
WHF
2661 drw 11
t
RFF
FF
R
W
t
WPF
2661 drw 10
W
R
XO
WRITE TO
LAST PHYSICAL
LOCATION
tXOL
tXOL tXOH
READ FROM
LAST PHYSICAL
LOCATION
tXOH
2661 drw 12
t
WEF
EF
W
R
t
RPE
2661 drw 09
5.04 10
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
OPERATING MODES:
Care must be taken to assure that the appropriate flag is
monitored by each system (i.e.
FF
is monitored on the device
where
W
is used;
EF
is monitored on the device where
R
is
used). For additional information, refer to Tech Note 8:
Oper-
ating FIFOs on Full and Empty Boundary Conditions
and
Tech Note 6:
Designing with FIFOs.
Single Device Mode
A single IDT7203/7204/7205/7206 may be used when the
application requirements are for 2048/4096/8192/16384 words
or less. The IDT7203/7204/7205/7206 is in a Single Device
Configuration when the Expansion In (
XI
) control input is
grounded (see Figure 12).
Depth Expansion
The IDT7203/7204/7205/7206 can easily be adapted to
applications when the requirements are for greater than 2048/
4096/8192/16384 words. Figure 14 demonstrates Depth Ex-
pansion using three IDT7203/7204/7205/7206s. Any depth
can be attained by adding additional IDT7203/7204/7205/
7206s. The IDT7203/7204/7205/7206 operates in the Depth
Expansion mode when the following conditions are met:
1. The first device must be designated by grounding the First
Load (
FL
) control input.
2. All other devices must have
FL
in the HIGH state.
3. The Expansion Out (
XO
) pin of each device must be tied to
the Expansion In (
XI
) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag
(
FF
) and Empty Flag (
EF
). This requires the ORing of all
EF
s and ORing of all
FF
s (i.e. all must be set to generate the
correct composite
FF
or
EF
). See Figure 14.
5. The Retransmit (
RT
) function and Half-Full Flag (
HF
) are
not available in the Depth Expansion Mode.
For additional information, refer to Tech Note 9:
Cascading
FIFOs or FIFO Modules.
USAGE MODES:
Width Expansion
Word width may be increased simply by connecting the
corresponding input control signals of multiple devices. Sta-
tus flags (
EF
,
FF
and
HF
) can be detected from any one device.
Figure 13 demonstrates an 18-bit word width by using two
IDT7203/7204/7205/7206s. Any word width can be attained
by adding additional IDT7203/7204/7205/7206s (Figure 13).
Bidirectional Operation
Applications which require data buffering between two
systems (each system capable of Read and Write operations)
can be achieved by pairing IDT7203/7204/7205/7206s as
shown in Figure 16. Both Depth Expansion and Width Expan-
sion may be used in this mode.
Data Flow-Through
Two types of flow-through modes are permitted, a read
flow-through and write flow-through mode. For the read flow-
through mode (Figure 17), the FIFO permits a reading of a
single word after writing one word of data into an empty FIFO.
The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of
W
, called the first write edge, and it remains on the bus
until the
R
line is raised from LOW-to-HIGH, after which the
bus would go into a three-state mode after tRHZ ns. The
EF
line
would have a pulse showing temporary deassertion and then
would be asserted.
In the write flow-through mode (Figure 18), the FIFO
permits the writing of a single word of data immediately after
reading one word of data from a full FIFO. The
R
line causes
the
FF
to be deasserted but the
W
line being LOW causes it to
be asserted again in anticipation of a new data word. On the
rising edge of
W
, the new word is loaded in the FIFO. The
W
line must be toggled when
FF
is not asserted to write new data
in the FIFO and to increment the write pointer.
Compound Expansion
The two expansion techniques described above can be
applied together in a straightforward manner to achieve large
FIFO arrays (see Figure 15).
W
R
XI
WRITE TO
FIRST PHYSICAL
LOCATION t
XIS
READ FROM
FIRST PHYSICAL
LOCATION
t
XIS
t
XI
t
XIR
2661 drw 11
Figure 11. Expansion In
5.04 11
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 12. Block Diagram of 2048 x 9/4096 x 9/8192 x 9/16384 x 9 FIFO Used in Single Device Mode
IDT
7203/
7204/
7205/
7206
XI XI
9
18
9
WRITE (
W
)
FULL FLAG (
FF
)
RESET (
RS
)
9918
HFHF
DATA (D)
IN
READ (
R
)
EMPTY FLAG (
EF
)
RETRANSMIT (
RT
)
DATA (Q)
OUT
IDT
7203/
7204/
7205/
7206
2661 drw 15
NOTE:
1. Flag detection is accomplished by monitoring the
FF
,
EF
and
HF
signals on either (any) device used in the width expansion configuration.
Do not connect any output signals together.
Figure 13. Block Diagram of 2048 x 18/4096 x 18/8192 x 18/16384 x 18 FIFO Memory Used in Width Expansion Mode
WRITE (
W
)
DATA IN (D)
FULL FLAG (
FF
)
RESET (
RS
)
9READ (
R
)
9DATA OUT (Q)
EMPTY FLAG (
EF
)
RETRANSMIT (
RT
)
EXPANSION IN (
XI
)
(
HF
)
IDT
7203/
7204/
7205/
7206
(HALF–FULL FLAG)
2661 drw 14
5.04 12
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I – RESET AND RETRANSMIT
SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE
Inputs Internal Status Outputs
Mode
RS
RS RT
RT XI
XI
Read Pointer Write Pointer
EF
EF FF
FF HF
HF
Reset 0 X 0 Location Zero Location Zero 0 1 1
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment
(1)
Increment
(1)
XXX
TABLE II – RESET AND FIRST LOAD
DEPTH EXPANSION/COMPOUND EXPANSION MODE
Inputs Internal Status Outputs
Mode
RS
RS FL
FL XI
XI
Read Pointer Write Pointer
EF
EF FF
FF
Reset First Device 0 0 (1) Location Zero Location Zero 0 1
Reset all Other Devices 0 1 (1) Location Zero Location Zero 0 1
Read/Write 1 X (1) X X X X
Figure 14. Block Diagram of 6149 x 9/12298 x 9/24596 x 9/49152 x 9 FIFO Memory (Depth Expansion)
NOTES: 2661 tbl 10
1.
XI
is connected to
XO
of previous device. See Figure 14.
2.
RS
= Reset Input,
FL/RT
= First Load/Retransmit,
EF
= Empty Flag Output,
FF
= Full Flag Output,
XI
= Expansion Input,
HF
= Half-Full Flag Output
NOTE: 2661 tbl 09
1. Pointer will Increment if flag is HIGH.
D
W
IDT
7203/
7204/
7205/
7206
FF EF
FL
XO
RS
FULL EMPTY
VCC
R
9
9
99
XI
9Q
FF EF
FL
XO
XI
FF EF
FL
XO
XI
IDT
7203/
7204/
7205/
7206
IDT
7203/
7204/
7205/
7206
2661 drw 16
5.04 13
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 17. Read Data Flow-Through Mode
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
R
,
W
,
RS
•••
•••D0–DN
D0-D8
D9-DN
D9-D17
D18 -DN
D(N-8)-DN
D(N-8)-DN
•••
Q0–Q8Q9–Q17
Q9–Q17Q0–Q8
Q(N-8) -QN
Q(N-8) -QN
IDT7203/
IDT7204/
IDT7205/
IDT7206
DEPTH
EXPANSION
BLOCK
IDT7203/
IDT7204/
IDT7205/
IDT7206
DEPTH
EXPANSION
BLOCK
IDT7203/
IDT7204/
IDT7205/
IDT7206
DEPTH
EXPANSION
BLOCK
2661 drw 17
Figure 16. Bidirectional FIFO Operation
IDT
7201A
R
B
EF
B
HF
B
W
A
FF
A
W
B
FF
B
SYSTEM A SYSTEM B
QB 0-8
DB 0-8QA 0-8
R
A
HF
A
EF
A
IDT
7203/
7204/
7205/
7206
DA 0-8
IDT
7203/
7204/
7205/
7206
2661 drw 18
W
DATA
R
tRPE
IN
EF
DATAOUT
tWLZ tWEF tAtREF
DATA VALIDOUT
2661 drw 19
5.04 14
IDT7203/7204/7205/7206 CMOS ASYNCHRONOUS FIFO
2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES
Figure 18. Write Data Flow-Through Mode
ORDERING INFORMATION
R
DATA
W
IN
FF
DATA OUT
tDS
tDH
tA
tWFF
tRFF
tWPF
DATA IN VALID
DATA OUT VALID
2661 drw 20
X
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
BMilitary (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
P
TP
D
TD
J
L
SO
Plastic DIP
Plastic THINDIP
Ceramic DIP
Ceramic THINDIP (all except 7206)
Plastic Leaded Chip Carrier
Leadless Chip Carrier (Military only)
Small Outline IC (7204 only)
12
15
20
25
30
35
40
50
65
80
120
Commercial 7203/04 Only
Commercial Only
Commercial Only
Military Only
Commercial Only
Military 7203/04 Only
Military 7203/04DB Only
XXXX
DeviceType
7203
7204
7205
7206
2048 x 9 FIFO
4096 x 9 FIFO
8192 x 9 FIFO
16384 x 9 FIFO
IDT
S
LStandard Power (7203/7204 only)
Low Power
Access Time (tA)
Speed in ns
2661 drw 21
