MOTOROLA Order this document by MCM81430/D SEMICONDUCTOR TECHNICAL DATA MCM81430 1M x 8 Bit Dynamic Random Access Module S PACKAGE SIMM MODULE CASE 839A-01 The MCM81430 is an 8M dynamic random access memory (DRAM) module organized as 1,048,576 x 8 bits. The module is a 30-lead single-in-line memory module (SIMM) consisting of two MCM54400AN DRAMs housed in a 20/26 J-lead small outline package (SOJ) and mounted on a substrate along with a 0.22 F (min) decoupling capacitor mounted adjacent to each DRAM. The MCM54400AN is a CMOS high-speed dynamic random access memory organized as 1,048,576 fourbit words and fabricated with CMOS silicon-gate process technology. * * * * * * * * * * * * * * * L PACKAGE SIP MODULE CASE 852A-02 Three-State Data Output Early-Write Common I/O Capability Fast Page Mode Capability TTL-Compatible Inputs and Outputs RAS-Only Refresh CAS Before RAS Refresh Hidden Refresh 1024 Cycle Refresh: 16 ms (Max) Consists of Two 4M DRAMs and Two 0.22 F (Min) Decoupling Capacitors Unlatched Data Out at Cycle End Allows Two Dimensional Chip Selection Fast Access Time (tRAC): MCM81430-60 = 60 ns (Max) MCM81430-70 = 70 ns (Max) Low Active Power Dissipation: MCM81430-60 = 1.32 W (Max) MCM81430-70 = 1.10 W (Max) Low Standby Power Dissipation: TTL Levels = 22 mW (Max) CMOS Levels = 11 mW (Max) CAS Control for Eight Common I/O Lines Available in Edge Connector (MCM81430S) or Pin Connector (MCM81430L) TOP VIEW PIN NAMES A0 - A9 . . . . . . . . . . . . . . Address Inputs DQ0 - DQ7 . . . . . . . . Data Input/Output CAS . . . . . . . . . Column Address Strobe RAS . . . . . . . . . . . . Row Address Strobe W . . . . . . . . . . . . . . . . . Read/Write Input VCC . . . . . . . . . . . . . . . . . . Power (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . No Connection Motorola, Inc. 1994 MOTOROLA DRAM REV 2 3/94 VCC (1) CAS (2) DQ0 (3) A0 (4) A1 (5) DQ1 (6) A2 (7) A3 (8) VSS (9) DQ2 (10) A4 (11) A5 (12) DQ3 (13) A6 (14) A7 (15) DQ4 (16) A8 (17) A9 (18) NC (19) DQ5 (20) W (21) VSS (22) DQ6 (23) NC (24) DQ7 (25) NC (26) RAS (27) NC (28) NC (29) VCC (30) MCM81430 1 FUNCTIONAL BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS (See Note) Rating Power Supply Voltage Symbol Value Unit VCC - 1 to + 7 V Vin, Vout - 1 to + 7 V Data Output Current per DQ Pin Iout 50 mA Power Dissipation PD 1.4 W Operating Temperature Range TA 0 to + 70 C Voltage Relative to VSS for Any Pin Except VCC This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. Storage Temperature Range Tstg - 55 to + 125 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MCM81430 2 MOTOROLA DRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (All voltages referenced to VSS) Parameter Symbol Min Typ Max Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 Logic High Voltage, All Inputs VIH 2.4 -- 6.5 V Logic Low Voltage, All Inputs VIL - 1.0 -- 0.8 V Symbol Min Max Unit Notes ICC1 -- -- 240 200 mA 1 VCC Power Supply Current (Standby) (RAS = CAS = VIH) ICC2 -- 4 mA VCC Power Supply Current During RAS Only Refresh Cycles MCM81430-60, tRC = 110 ns MCM81430-70, tRC = 130 ns ICC3 -- -- 240 200 VCC Power Supply Current During Fast Page Mode Cycle MCM81430-60, tPC = 45 ns MCM81430-70, tPC = 45 ns ICC4 -- -- 140 140 VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V) ICC5 -- 2 VCC Power Supply Current During CAS Before RAS Refresh Cycle MCM81430-60, tRC = 110 ns MCM81430-70, tRC = 130 ns ICC6 -- -- 240 200 Input Leakage Current (0 VSS Vin VCC) Ilkg(I) - 20 20 A Output Leakage Current (CAS at Logic 1, VSS Vout VCC) Ilkg(O) - 10 10 A Output High Voltage (IOH = - 5 mA) VOH 2.4 -- V Output Low Voltage (IOL = 4.2 mA) VOL -- 0.4 V Supply Voltage (Operating Voltage Range) DC CHARACTERISTICS AND SUPPLY CURRENTS Characteristic VCC Power Supply Current MCM81430-60, tRC = 110 ns MCM81430-70, tRC = 130 ns mA 1 mA 1, 2 mA mA 1 NOTES: 1. Current is a function of cycle rate and output loading; maximum current is measured at the fastest cycle rate with the output open. 2. Column address can be changed once or less while RAS = VIL and CAS = VIH. CAPACITANCE (f = 1.0 MHz, TA = 25C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested) Parameter Input Capacitance Input/Output Capacitance Symbol Max Unit A0 - A9, W, CAS, RAS Cin 24 pF DQ0 - DQ7 CI/O 17 pF NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I t/V. MOTOROLA DRAM MCM81430 3 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) READ AND WRITE CYCLES (See Notes 1, 2, 3, and 4) Symbol Parameter MCM81430-60 MCM81430-70 Std Alt Min Max Min Max Unit Notes Random Read or Write Cycle Time tRELREL tRC 110 -- 130 -- ns 5 Fast Page Mode Cycle Time tCELCEL tPC 45 -- 45 -- ns Access Time from RAS tRELQV tRAC -- 60 -- 70 ns 6, 7 Access Time from CAS tCELQV tCAC -- 20 -- 20 ns 6, 8 Access Time from Column Address tAVQV tAA -- 30 -- 35 ns 6, 9 Access Time from Precharge CAS tCEHQV tCPA -- 40 -- 40 ns 6 CAS to Output in Low-Z tCELQX tCLZ 0 -- 0 -- ns 6 Output Buffer and Turn-Off Delay tCEHQZ tOFF 0 20 0 20 ns 10 Transition Time (Rise and Fall) tT tT 3 50 3 50 ns RAS Precharge Time tREHREL tRP 40 -- 50 -- ns RAS Pulse Width tRELREH tRAS 60 10 k 70 10 k ns RAS Pulse Width (Fast Page Mode) tRELREH tRASP 60 200 k 70 200 k ns RAS Hold Time tCELREH tRSH 20 -- 20 -- ns CAS Hold Time tRELCEH tCSH 60 -- 70 -- ns CAS Precharge to RAS Hold Time tCEHREH tRHCP 40 -- 40 -- ns CAS Pulse Width tCELCEH tCAS 20 10 k 20 10 k ns RAS to CAS Delay Time tRELCEL tRCD 20 40 20 50 ns 11 tRELAV tRAD 15 30 15 35 ns 12 CAS to RAS Precharge Time tCEHREL tCRP 5 -- 5 -- ns CAS Precharge Time tCEHCEL tCP 10 -- 10 -- ns Row Address Setup Time tAVREL tASR 0 -- 0 -- ns Row Address Hold Time tRELAX tRAH 10 -- 10 -- ns Column Address Setup Time tAVCEL tASC 0 -- 0 -- ns Column Address Hold Time tCELAX tCAH 15 -- 15 -- ns RAS to Column Address Delay Time Column Address to RAS Lead Time tAVREH tRAL 30 -- 35 -- ns Read Command Setup Time tWHCEL tRCS 0 -- 0 -- ns NOTES: (continued) 11. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 12. An initial pause of 200 s is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed. 13. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 14. AC measurements tT = 5.0 ns. 15. The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (0C TA 70C) is ensured. 16. Measured with a current load equivalent to 2 TTL (- 200 A, + 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V and VOL = 0.8 V. 17. Assumes that tRCD tRCD (max). 18. Assumes that tRCD tRCD (max). 19. Assumes that tRAD tRAD (max). 10. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. t RAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max), then access time is controlled exclusively by tAA. MCM81430 4 MOTOROLA DRAM READ AND WRITE CYCLES (Continued) Symbol Parameter MCM81430-60 MCM81430-70 Std Alt Min Max Min Max Unit Notes Read Command Hold Time Referenced to CAS tCEHWX tRCH 0 -- 0 -- ns 13 Read Command Hold Time Referenced to RAS tREHWX tRRH 0 -- 0 -- ns 13 Write Command Hold Time Referenced to CAS tCELWH tWCH 10 -- 15 -- ns Write Command Pulse Width tWLWH tWP 10 -- 15 -- ns Write Command to RAS Lead Time tWLREH tRWL 20 -- 20 -- ns Write Command to CAS Lead Time tWLCEH tCWL 20 -- 20 -- ns Data in Setup Time tDVCEL tDS 0 -- 0 -- ns 14 Data in Hold Time tCELDX tDH 15 -- 15 -- ns 14 Refresh Period tRVRV tRFSH -- 16 -- 16 ms Write Command Setup Time tWLCEL tWCS 0 -- 0 -- ns 15 CAS to Write Delay tCELWL tCWD 50 -- 50 -- ns 15 RAS to Write Delay tRELWL tRWD 90 -- 100 -- ns 15 Column Address to Write Delay Time tAVWL tAWD 60 -- 65 -- ns 15 CAS Precharge to Write Delay Time (Page Mode) tCEHWL tCPWD 70 -- 70 -- ns 15 CAS Setup Time for CAS Before RAS Refresh tRELCEL tCSR 5 -- 5 -- ns CAS Hold Time for CAS Before RAS Refresh tRELCEH tCHR 15 -- 15 -- ns RAS Precharge to CAS Active Time tREHCEL tRPC 0 -- 0 -- ns CAS Precharge Time for CAS Before RAS Counter Time tCEHCEL tCPT 30 -- 40 -- ns Write Command Setup Time (Test Mode) tWLREL tWTS 10 -- 10 -- ns Write Command Hold Time (Test Mode) tRELWH tWTH 10 -- 10 -- ns Write to RAS Precharge Time (CAS Before RAS Refresh) tWHREL tWRP 10 -- 10 -- ns Write to RAS Hold Time (CAS Before RAS Refresh) tRELWL tWRH 10 -- 10 -- ns NOTES: 13. Either tRRH or tRCH must be satisfied for a read cycle. 14. These parameters are referenced to CAS leading edge in early write cycles. 15. tWCS is not a restrictive operating parameter. It is included in the data sheet as an electrical characteristic only; if tWCS t WCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. If this condition is not satisfied, the condition of the data out (at access time) is indeterminate. MOTOROLA DRAM MCM81430 5 READ CYCLE EARLY WRITE CYCLE MCM81430 6 MOTOROLA DRAM FAST PAGE MODE READ CYCLE FAST PAGE MODE EARLY WRITE CYCLE MOTOROLA DRAM MCM81430 7 RAS ONLY REFRESH CYCLE (W is Don't Care) CAS BEFORE RAS REFRESH CYCLE (A0 - A9 are Don't Care) MCM81430 8 MOTOROLA DRAM HIDDEN REFRESH CYCLE (READ) HIDDEN REFRESH CYCLE (EARLY WRITE) MOTOROLA DRAM MCM81430 9 CAS BEFORE RAS REFRESH COUNTER TEST CYCLE MCM81430 10 MOTOROLA DRAM DEVICE INITIALIZATION On power-up, an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight active cycles of the row address strobe (clock) to initialize all dynamic nodes within the module. During an extended inactive state (greater than 16 milliseconds with the device powered up), a wake up sequence of eight active cycles is necessary to ensure proper operation. ADDRESSING THE RAM The ten address pins on the device are time multiplexed at the beginning of a memory cycle by two clocks, row address strobe (RAS) and column address strobe (CAS), into two separate 10-bit address fields. A total of twenty address bits, ten rows and ten columns, will decode one of the 1,048,576 byte locations in the device. RAS active transition is followed by CAS active transition (active = VIL, tRCD minimum) for all read or write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the RAM. The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock enables the internal CAS line as soon as the row address hold time (tRAH) specification is met (and defines tRCD minimum). The multiplex window can be used to absorb skew delays in switching the address bus from row to column addresses and in generating the CAS clock. There are three other variations in addressing the module: RAS only refresh cycle, CAS before RAS refresh cycle, and page mode. All three are discussed in separate sections that follow. READ CYCLE The DRAM may be read with either a "normal" random read cycle or a page mode read cycle. The normal read cycle is outlined here, while the page mode cycle is discussed in a separate section. The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching the desired bit location. The write (W) input level must be high (VIH), tRCS (minimum) before the CAS active transition, to enable read mode. Both the RAS and CAS clocks trigger a sequence of events that are controlled by several delayed internal clocks. The internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex window. CAS controls read access time: CAS must be active before or at tRCD maximum to guarantee valid data out (DQ) at tRAC (access time from RAS active transition). If the tRCD maximum is exceeded, read access time is determined by the CAS clock active transition (tCAC). The RAS and CAS clocks must remain active for a minimum time of tRAS and tCAS, respectively, to complete the read cycle. W must remain high throughout the cycle, and for time tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of tRP to precharge the internal device circuitry for the next active cycle. DQ is valid, but not latched, as long as the CAS clock is active. When the CAS clock transitions to inactive, the output will switch to High Z (three-state) tOFF after the inactive transition. MOTOROLA DRAM WRITE CYCLE The user can write to the DRAM with either an early write or page mode early write cycle. Early write mode is discussed here, while page mode write operations are covered in a separate section. A write cycle begins as described in ADDRESSING THE RAM. Write mode is enabled by the transition of W to active (VIL). Early write mode is distinguished by the active transition of W, with respect to CAS. Minimum active time tRAS and tCAS, and precharge time tRP apply to write mode, as in the read mode. An early write cycle is characterized by W active transition at minimum time tWCS before CAS active transition. Data in (DQ) is referenced to CAS in an early write cycle. RAS and CAS clocks must stay active for tRWL and tCWL, respectively, after the start of the early write operation to complete the cycle. PAGE MODE CYCLES Page mode allows fast successive data operations at all 1024 column locations on a selected row of the module. Read access time in page mode (tCAC) is typically half the regular RAS clock access time, tRAC. Page mode operation consists of keeping RAS active while toggling CAS between VIH and VIL. The row is latched by RAS active transition, while each CAS active transition allows selection of a new column location on the row. A page mode cycle is initiated by a normal read or write cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for minimum tCP, while RAS remains low (VIL). The second CAS active transition while RAS is low initiates the first page mode cycle (tPC). Either a read or write operation can be performed in a page mode cycle, subject to the same conditions as in normal operation (previously described). These operations can be intermixed in consecutive page mode cycles and performed in any order. The maximum number of consecutive page mode cycles is limited by tRASP. Page mode operation is ended when RAS transitions to inactive, coincident with or following CAS inactive transition. REFRESH CYCLES The dynamic RAM design is based on capacitor charge storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the MCM81430 require refresh every 16 milliseconds. This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6 microseconds for the MCM81430. Burst refresh, a refresh of all 1024 rows consecutively, must be performed every 16 milliseconds. A normal read or write operation to the RAM will refresh all the bits associated with the particular row decoded. Three other methods of refresh, RAS-only refresh, CAS before RAS refresh, and hidden refresh are available on this device for greater system flexibility. RAS-Only Refresh RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high (VIH) throughout the cycle. An external counter is employed to ensure all rows are refreshed within the specified limit. MCM81430 11 The internal refresh counter of this device can be tested with a CAS before RAS refresh counter test. This refresh counter test is performed with read and write operations. During this test, the internal refresh counter generates the row address, while the external address supplies the column address. The entire array is refreshed after 1024 test cycles, as indicated by the check data written in each row. See CAS before RAS refresh counter test cycle timing diagram. The test can be performed only after a minimum of 8 CAS before RAS initialization cycles. The test procedure is as follows: CAS Before RAS Refresh CAS before RAS refresh is enabled by bringing CAS active before RAS. This clock order activates an internal refresh counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh cycle. The output buffer remains at the same state it was in during the previous cycle (hidden refresh). W must be inactive for time tWRP before and time tWRH after RAS active transition to prevent switching the device into a test mode cycle. Hidden Refresh 1. Write "0"s into all memory cells with normal write mode. 2. Select a column address, and read "0" out of the cell by performing CAS before RAS refresh counter test, read cycle. Repeat this operation 512 times. 3. Select a column address and write "1" into the cell by performing the CAS before RAS refresh counter test, write cycle. Repeat this operation 512 times. 4. Read "1"s (normal read mode), which were written at step 3. 5. Repeat steps 1 to 4 using complement data. Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the end of a read or write cycle, while RAS cycles inactive for tRP and back to active, starts the hidden refresh. This is essentially the execution of a CAS before RAS refresh from a cycle in progress (see Figure 1). W is subject to the same conditions with respect to RAS active transition (to prevent test mode cycle) as in CAS before RAS refresh. CAS BEFORE RAS REFRESH COUNTER TEST Figure 1. Hidden Refresh Cycle ORDERING INFORMATION (Order by Full Part Number) MCM 81430 X XX Motorola Memory Prefix Speed (60 = 60 ns, 70 = 70 ns) Part Number Package (S = SIMM, L = SIP) Full Part Numbers -- MCM81430S60 MCM81430S70 MCM81430 12 MCM81430L60 MCM81430L70 MOTOROLA DRAM PACKAGE DIMENSIONS S PACKAGE SIMM MODULE CASE 839A-01 "! ! " -Y- B ! % Q " A ! "! " " !! % " " ! #! " "&" V R -ZP M N P G U DETAIL X -D- S F E W "" & #!" & ! ! C % DETAIL X ' ! ' ! ! ' ' H L S ! F ' ' ' ' ' ' L PACKAGE SIP MODULE CASE 852A-02 COMPONENT AREA -X- "! A -Y- ! " ! % " B K -T C D 30 PL G " $ ! % ! L J 30 PL " $ ! % ! ' ' ' ' ! ' ! ! ' ! ! Motorola reserves the right to make changes without further notice to any products herein. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. MCM81430 14 *MCM81430/D* MCM81430/D MOTOROLA DRAM