CX24109-11Z,557 - NXP Semiconductors / Philips Semiconductors

CX24109

Digital Satellite Tuner

Rev. 01 — 13 November 2008 Product data sheet

Document information

Info Content

Keywords

Abstract

Product data sheet Rev. 01 — 13 November 2008 2

Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors CX24109

Digital Satellite Tuner

Ordering information

Type number Description Package

CX24109-11 Digital Satellite Tuner 48-pin eTQFP

CX24109-11Z

Revision history

Revision Date Description

01 20081113 First NXP version based on the Conexant 102031A data sheet.

Product data sheet Rev. 01 — 13 November 2008 3

NXP Semiconductors CX24109

Digital Satellite Tuner

General description

The CX24109 is a highly integrated, direct down-conversion satellite tuner intended for

high-volume digital video, audio, and data receivers. When combined with the CX24121

QPSK demodulator/FEC decoder, the chip set provides a complete broadband satellite

front-end solution capable of operating from 1–45 MSps in the most demanding satellite

environments. It is compatible with international standards such as DVB and DSS. The

highly integrated CX24109 reduces the tuner BOM cost and simplifies the RF layout.

Features

Zero-IF architecture eliminates the need for image reject filtering

Integrated LNA

Integrated LO with onboard VCO and synthesizer

Single +5 V supply

Reference oscillator output for demodulator

Applications

DBS set-top boxes

Commercial digital video, audio, and data receivers

Digital VCRs

Block diagram

Input

VGA1 VGA2

VGA1

VCA

VGA2

Variable Low

Pass Filter

I Channel

Output

Variable Low

Pass Filter

Q Channel

Output

VCO

Reference

Oscillator

Reference

to DEMOD

Programming

and Control

Lock

Detect

PLL

Dividers, Phase Detector,

and Charge Pump

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NXP Semiconductors CX24109

Digital Satellite Tuner

Product data sheet Rev. 01 — 13 November 2008 5

NXP Semiconductors CX24109

Digital Satellite Tuner

Contents

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.1 Pinout Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.2 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1.3 Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

1.4 Signal Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

1.5 AGC and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.6 Local Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.7 Programming Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.7.1 Gain Equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.7.2 Frequency Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.7.3 Recommended Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.1 AGC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.2 VCO Power Pin Ripple Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3 Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4 Example Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.5 Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3 Parametric Data and Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.1.1 Standard Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Legal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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NXP Semiconductors CX24109

Digital Satellite Tuner

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NXP Semiconductors CX24109

Digital Satellite Tuner

Figures

Fig. 1 CX24109 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Fig. 2 QPSK Demodulation Typical Application Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Fig. 3 Detailed Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Fig. 4 Serial Interface Programming Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Fig. 5 Programming Word Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Fig. 6 Simplified Application Schematic (Page 1 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Fig. 7 Simplified Application Schematic (Page 2 of 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Fig. 8 Reflection Coefficient at Input of CX24109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Fig. 9 Baseband Filter Gain vs. Frequency and FILTUNE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Fig. 10 Filter –3 dB Bandwidth vs. FILTUNE Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Fig. 11 Gain and IIP3 vs. AGC Voltage at 950 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Fig. 12 Gain and IIP3 vs. AGC Voltage at 2150 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Fig. 13 Gain and NF vs. AGC Voltage at 950 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Fig. 14 Gain and NF vs. AGC Voltage at 2150 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Fig. 15 Serial Programming Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Fig. 16 48-pin eTQFP Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Fig. 17 48-pin eTQFP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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NXP Semiconductors CX24109

Digital Satellite Tuner

Product data sheet Rev. 01 — 13 November 2008 9

NXP Semiconductors CX24109

Digital Satellite Tuner

Tables

Table 1. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 2. Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Programming Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4. Band Select Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 5. VGA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 6. VCA Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 7. PLL Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 8. Recommended AGC Programming Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 9. Recommended VCO Frequency vs. Charge Pump Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 10. Recommended Charge Pump Polarity and Reference Divider Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 12. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 13. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 14. AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 15. RF Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 16. Baseband Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Product data sheet Rev. 01 — 13 November 2008 10

NXP Semiconductors CX24109

Digital Satellite Tuner

Product data sheet Rev. 01 — 13 November 2008 11

CX24109

Chapter 1: Functional Description

Rev. 01 — 13 November 2008 Product data sheet

1.1 Pinout Information

1.2 Pin Description

Figure 1. CX24109 Pin Diagram

Table 1. Pin Description

Pin Name Pin No. I/O Description

RFIN 4 I RF input signal pin.

AGC 37 I AGC control input from the demodulator/FEC IC. It controls the gain of the RF attenuator

and both baseband amplifiers. Minimum gain occurs at minimum voltage. Input impedance

zin = 1 MΩ//20 pF..

FILTUNE 36 I Baseband filter control input from the demodulator/FEC IC.

Minimum BW occurs at minimum voltage. Zin = 17 kΩ//20 pF.

102031_002

VCC

GND

RFIN

RFGND

GND

DCIP

DCIN

DCQP

DCQN

TUNERES

FILTUNE

IOUTN

IOUTP

GND

QOUTN

QOUTP

GND

VCC

CLK

DATA

GND

VCC

GND

VCC

GND

VCC

GND

VCC

GND

VCC

AGC

VCC

GND

XTAL1

XTAL2

VCC

GND

LPFILT

GND

VCC

GND

CLKREFOUT

CX24109

Product data sheet Rev. 01 — 13 November 2008 12

NXP Semiconductors CX24109

Chapter 1: Functional Description

1.3 Application Overview

Several million Satellite Set-Top Boxes (STBs) are deployed in many different entertainment

networks around the world today. The standards for each network may vary a little but the

requirements for the tuner in the STB are essentially the same. Each receiver system in the

TUNERES 12 — Filter reference. A resistor to ground from this pin sets the reference current for the tunable

filter. See Figure 6 and Figure 7.

IOUTP, IOUTN 34, 35 O I channel output to the demodulator/FEC IC. Can be used balanced or single-ended. Zout

= 1 kΩ//10 pF.

QOUTP, QOUTN 31, 32 O Q channel output to the demodulator/FEC IC. Can be used balanced or single-ended. Zout

= 1 kΩ//10 pF.

DCIP, DCIN 8, 9 — I channel DC offset cancellation. A capacitor must be placed between these pins. See

Figure 6 and Figure 7.

DCQP, DCQN 10, 11 — Q channel DC offset cancellation. A capacitor must be placed between these pins. See

Figure 6 and Figure 7.

LPFILT 20 — Loop filter. A network with a capacitor in parallel with a series resistor and capacitor

connected from this pin to ground determines the loop filter bandwidth. See Figure 6 and

Figure 7.

CLKREFOUT 24 O Clock reference output. This pin provides the reference clock for the demodulator/FEC IC.

The maximum load allowed at this node is ZLOAD = 10 kΩ//20 pF.

XTAL1, XTAL2 16, 17 — Crystal inputs. A 10.111 MHz, series-resonant, fundamental crystal is placed between

these two pins to create the system clock. See Figure 6 and Figure 7.

CLK 28 I Serial bus clock signal.

EN 26 I Serial bus latch enable.

DATA 27 I Serial bus data pin.

LD 25 O The lock detect signal to the demodulator/FEC IC.

ZLOAD = 10 kΩ//20 pF. High is the locked state.

Table 2. Power Suppl y an d Ground Pins

Pin Name Pin No. I/O Description

VCC 1, 13, 18, 22,

29, 38, 40,

42, 44, 47

P +5 V power supply

GND 2, 3, 5, 6, 7,

14, 15, 19,

21, 23, 30,

33, 39, 41,

43, 45, 46, 48

P Ground

Table 1. Pin Description

Pin Name Pin No. I/O Description

Product data sheet Rev. 01 — 13 November 2008 13

NXP Semiconductors CX24109

Chapter 1: Functional Description

network requires an antenna, a Low Noise Block (LNB) downconverter, a drop cable, and an

STB. The LNB converts the satellite downlink frequency to an intermediate L-band frequency

where it is passed to the STB via the drop cable. The STB front end consists of a tune r and a

demodulator/FEC IC. The satellite tuner must tune to the L-band frequency, downconvert the

carrier, and separate it to baseband I and Q signals. The demodulator/FEC IC includes

QPSK Demodulation, carrier tracking, AGC control, bit timing, and the required FEC for a

given network service. Figure 2 illustrates a typical application block diagram for the

CX24109/CX24121 chip set in an STB front end.

1.4 Signal Path

The CX24109 is a highly integrated, direct-down conversion satellite tuner. It consists of an

LNA, variable RF attenuator, quadrature downconverter, variable IF gain amplifiers, variable

low-pass filters, VCO, and synthesizer. A detailed block diagram of the IC is illustrated in

Figure 3.

Figure 2. QPSK Demodulation Typical Application Block Diagram

RFIN

XTAL1

XTAL2

CLKREFOUT

LPFILT

CONTROL

XTAL_IN

Tuner_Clk

Tuner_Data

Tuner_En

IOUTP

IOUTN

QOUTN

QOUTP

AGC

FILTUNE

TUNERES

RS_DATA[7:0]

RS_CLK

RSCntl1

RSCntl2

I_N

Q_N

AGCV

FILTERV

MPEG

Processor

CX24109

RF Tuner IC

CX24121

Demod/FEC IC

Drop

Cable

Dish

Antenna

Tuner Control

LNB

102031_003

Product data sheet Rev. 01 — 13 November 2008 14

NXP Semiconductors CX24109

Chapter 1: Functional Description

Figure 3. Detailed Functional Block Diagram

90 Degree

Splitter and

Divide by

2 or 4

Voltage

Controlled

Oscillator

Variable Low

Pass Filter

VGA1

VCA

VGA2

AGC

Control

Charge

Pump

Divide by

10, 20, 40

Control

Interface

Divide

by 2

32/33

Prescaler

9 Bit

Counter

5 Bit

Counter

Phase

Detector

Lock

Detect

Crystal

Cell

RFIN

IOUTP

IOUTN

TUNERES

QOUTP

QOUTN

FILTUNE

LPFILT

AGC

XTAL1

XTAL2

CLKREFOUT

CLK

DATA

102031_004

Product data sheet Rev. 01 — 13 November 2008 15

NXP Semiconductors CX24109

Chapter 1: Functional Description

The L-band output from the LNB enters the IC through the RFIN pin and is immediately

amplified by the Voltage Controlled Attenuator block (VCA). The VCA functions as a variable

gain LNA. The noise figure and gain of the VCA are the dominant factors for the tuner’s noise

figure. The signal is then quadrature downconverted to I and Q baseband channels.

Additional amplifiers at baseband provide more variable gain for the AGC loop. Also at

baseband, variable low-pass filters provide anti-alias filtering and eliminate noise power from

adjacent carriers and spurious signals before they can impact the A/Ds in the demodulator

IC.

1.5 AGC and Control

The AGC functionality for the CX24109 is split between the RF and baseband sections, and

provides 80 dB of variable gain. The primary control for the AGC is an analog voltage from

the demodulator IC. Programmable adjustments to the slope and of fset of each variable gain

component in the tuner are available through the AGC control registers. Programming

information for the VGA and VCA is provided in Tables 4 and 5, respectively. The

recommended default values for the programmable control bits versus symbol rate are listed

in Table 8.

1.6 Local Oscillator

The local oscillator consists of a synthesizer and a VCO block, and is contained entirely

within the CX24109. The VCO block uses an innovative architecture that requires only a 5 V

source, eliminating the need for a 28 V power supply. It includes the required tank circuit.

The VCO block consists of a bank of eight oscillators operating at twice and four times the

input frequency with a continuous range from 2200 MHz to 4400 MHz. The VCOs overlap to

cover the frequency range from 950 MHz to 2150 MHz under all voltage, temperature, and

process variations. The VCO tuning range, combined with programmable ÷2 or ÷4 frequency

dividers, creates the continuous frequencies from 950 MHz to 2150 MHz for the local

oscillator. A simple tuning algorithm must be run by the host processor one time at power-up

to calibrate the VCO block. Conexant provides this program.

The synthesizer is also contained within the CX24109. It uses a 10.111 MHz reference

frequency and a reference divider, ÷R, to set the phase comparison frequency. Two

programming bits are used to configure the reference divider to divide by 10, 20, or 40, which

in turn sets the comparison frequency to 1.0111 MHz, 505 kHz, or 253 kHz, respectively. A

reference divider of 10 is recommended. The comparison frequency also determines the

frequency step size of the local oscillator. Another programmable divider is provided for the

VCO output. It consists of a 32/33 prescaler, a 9-bit N-counter (N-divider), a 5-bit A-counter

(A-divider), and a fixed ÷2 block. The programmable divider divides the VCO outpu t from its

highest frequency to the minimum phase comparison frequency. The programmable charge

pump includes output currents of 1 mA, 2 mA, 3 mA, and 4 mA. Programming information for

the synthesizer can be found in Table 7. The recommended values for charge pump current,

polarity, and referenced dividers are listed in Tables 9 and 10.

The typical loop filter bandwidth is set with external passive components and should be set

between 8 kHz and 15 kHz.

1.7 Programming Interface

A three-wire serial interface with Clock, Data, and Enable lines is used to program the

CX24109. All digital signals are CMOS-comp atible. The serial data carries the binary settings

for the programmable dividers, the VCO band select, the voltage-controlled attenuator, and

the voltage-controlled amplifiers. When the Enable line is low, data is shifted into an internal

shift register on the rising edge of the clock, and when the Enable line goes high, the stored

data is latched. The clock signal should be kept low when inactive. The maximum clock rate

is 1 MHz. Figure 4 illustrates the relationship between the Clock, Data, and Enable signals.

Product data sheet Rev. 01 — 13 November 2008 16

NXP Semiconductors CX24109

Chapter 1: Functional Description

The internal shift register in the CX24109 is 21 bit s long. When the data is latched into the IC,

the two MSBs act as control bits, and the lower 19 bits are the data bits as illustrated in

Figure 5. Data must be entered MSB first.

The control bits determine the functional block that is being programmed, while the data bits

contain the specific control information. Table 3 provides a detail mapping of the control and

data bits.

Figure 4. Serial Interface Programming Example

Figure 5. Programming W ord Config ura tio n

Table 3. Programming Bit Mapping (Sheet 1 of 2)

Programming Bit Mapping

MSB 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

LSB

Band Select

0 0RRRRR R RR

(1) RVR

(1) Band Select

VGA Programming

0 1 R VGA2 Offset VGA1 Offset

VCA Programming

1 0 R VCA Offset VCA Slope

PLL Programming

102031_005

. . .

Clock

Data

Enable

102031_006

d20 d19 d18 d17 d16 d15 d14 d13 d12 d11

Data Bits

d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0

Control

Bits

MSB LSB

Product data sheet Rev. 01 — 13 November 2008 17

NXP Semiconductors CX24109

Chapter 1: Functional Description

11÷R Divider P Charge

Pump

Current

MSB ÷ N Divider(2) LSB MSB ÷A Divider(2) LSB

GENERAL NOTES:

1. R means Reserved except for ÷R which means reference divider.

P means Charge Pump Polarity

V means VCO Divide Select

FOOTNOTES:

(1) These Reserved locations must be set to zero. All other Reserved location values do not matter.

(2) These Divide ratios are binary coded.

Table 3. Programming Bit Mapping (Sheet 2 of 2)

Programming Bit Mapping

Product data sheet Rev. 01 — 13 November 2008 18

NXP Semiconductors CX24109

Chapter 1: Functional Description

Table 4. Band Select Prog ra mming

Band Select

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Typical Receive

Frequency Range

(MHz)

VCO

Number VCO

Divider

01000000 950–1019 7 4

10000000 1019–1075 8 4

00000001 1075–1178 1 2

00000010 1178–1296 2 2

00000100 1296–1432 3 2

00001000 1432–1576 4 2

00010000 1576–1718 5 2

00100000 1718–1856 6 2

01000000 1856–2036 7 2

10000000 2036–2150 8 2

VCO Divide Select

Bit 9 Function

0÷4

1÷2

Product data sheet Rev. 01 — 13 November 2008 19

NXP Semiconductors CX24109

Chapter 1: Functional Description

Table 5. VGA Programming

VGA1 Offset

Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Offset in dB

111111110 –27.0

111111100 –28.5

111111000 –30.0

111110000 –31.5

111100000 –33.0

111000000 –34.5

110000000 –36.0

100000000 –37.5

000000000 –39.0

VGA2 Offset

Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Offset in dB

111111110 35

111111100 32

111111000 29

111110000 26

111100000 23

111000000 20

110000000 17

100000000 14

000000000 11

Product data sheet Rev. 01 — 13 November 2008 20

NXP Semiconductors CX24109

Chapter 1: Functional Description

Table 6. VCA Programming

VCA Slope

Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Slope in dB/V

000000001 47.0

000000011 49.5

000000111 52.0

000001111 54.5

000011111 57.0

000111111 59.5

001111111 62.0

011111111 64.5

111111111 67.0

VCA Offset

Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Offset in dB

000000001 90.00

000000011 94.25

000000111 98.50

000001111 102.75

000011111 107.00

000111111 111.25

001111111 115.50

011111111 119.75

111111111 124.00

Product data sheet Rev. 01 — 13 November 2008 21

NXP Semiconductors CX24109

Chapter 1: Functional Description

1.7.1 Gain Equations

The RF block voltage gain (GRF) is equal to the VCA gain + the mixer gain.

Table 7. P LL Programming

Charge Pump Current

Bit 15 Bit 14 Current (mA)

00 1

01 2

10 3

11 4

Charge Pump Polarity

Bit 16 Function

0Positive

1 Negative

Reference Dividers

Bit 18 Bit 17 Function

00 —

01 Reserved

10 Reserved

11 ÷10

GRF VAGC VCA Slope VCA Offset in dB()23+–×

where the maximum value of GRF is 23 dB, regardless of voltage

VGA1 voltage gain GVGA1

() is equal to

GVGA1 VAGC

=26×VGA1 Offset in dB()+

VGA2 voltage gain GVGA2

() is equal to

GVGA2 VGA2 Offset = in dB()

The total baseband voltage gain GBaseband

() is equal to

GBaseband G

VGA1

Filter GVGA2

G=VGA1 3G

VGA2

Product data sheet Rev. 01 — 13 November 2008 22

NXP Semiconductors CX24109

Chapter 1: Functional Description

1.7.2 Frequency Equations

The VCO frequency is determined by

Remember, the incoming receive frequency is always lower than the VCO frequency, such

that:

1.7.3 Recommended Default Values

NOTE: If A = 0, then N = N + 1

Table 8. Recommended AGC Programming Values

VCA and VGA Slope and Offset vs. Symbol Rate Condition

Symbol Rate VCA Slope

(dB/V) VCA Offset

(dB)(1) VGA1 Slope

(dB/V)(2) VGA1 Offset

(dB)

VGA2

Slope (dB/

V)(2)

VGA2 Offset

(dB)

FILTUNE

Voltage

(V)

1 to 5 MSps 52 98.5

(102.75) 26 –30 0 29 0.41

5 to 15 MSps 57 98.5

(107) 26 –33 0 17 0.90

15 to 45 MSps 59.5 98.5

(111.25) 26 –36 0 14 2.70

FOOTNOTES:

(1) There is an interaction between the offset and slope settings in the RF block, so the actual settings will be different from the theoretical

setting. Theoretical settings are given in parentheses.

(2) These values are for reference only. They are not programmable.

Table 9. Recommended VCO Frequency vs. Char ge Pump Current

VCO Frequency Charge Pump Current

Lower 50% VCO Frequency Range 2 mA

Upper 50% of VCO Frequency Range 3 mA

Table 10. Recommended Charge Pump Polarity and Refe rence Divider Values

Feature Specification

Charge Pump Polarity Negative

Reference Divider ÷10

FVCO = FCrystal R÷()NA32÷()+()32×2××

10.111 R÷()NA32÷()+()32×2××=

FReceive FVCO 2 ÷=or F

VCO 4÷

Product data sheet Rev. 01 — 13 November 2008 23

CX24109

Chapter 2: Applications

Rev. 01 — 13 November 2008 Product data sheet

2.1 AGC Input

To prevent excessive current draw, a 10 kΩ resistor on the AGC pin is recommended. See

Figure 6.

2.2 VCO Power Pin Ripple Requirement

Care must be taken to reduce the power supply ripple on pin 13 (VCO power supply) in order

to reduce phase noise. The power supply conditioning circuitry given in Figure 6 is suitable

for most circumstances.

2.3 Transmission Lines

Though the CX24109’s RF layout is simple, there are two transmission lines that must be

designed. The first transmission line is the LNB power line, which is located at the connector .

The second transmission line is between the connector and the RF IN pin. The input

transmission line must have a characteristic impedance of 75 Ω. The schematic gives

recommended dimensions assuming a two-layer FR-4 board.

2.4 Example Schematic

Figure 6 provides a simplified version of the CX24109/CX24121 reference design. For

complete and current reference design information, contact your local Conexant sales office.

Product data sheet Rev. 01 — 13 November 2008 24

NXP Semiconductors CX24109

Chapter 2: Applications

Figure 6. Simplified Application Schematic (Page 1 of 2)

102031_007

FOOTNOTE:

(1) Ground pins include: 2, 3, 5, 6, 7, 14, 15, 19, 21, 23, 30, 33, 39, 41, 43, 45, 46, and 48

GND (1)

W = 0.5 mm, L = 27 mm, H = 1.6 mm FR-4

W = 1.4 mm

L = 1.6 mm

H < 10 mm FR-4

75 ΩFILTUNE

I_OUTN

I_OUTP

Q_OUTN

Q_OUTP

AGC2_VCC

CLK

DATA

ATTEN_VCC2

RF_IN

RF_GND

DC_IP

DC_IN

DC_QP

TUNERES

VCO_VCC

XTA1

XTA2

OSC_VCC

LP_ILT

SYNTH_VCC

CKREF_OUT

ATTEN_VCC1

ATTEN_VCC3

MIX_VCC

FILT_VCC

AGC1_VCC

AGC

LNB_POWER

RF_IN F Connector

C104

C101

C103

33 p

C105

33 p

C106

33 p C107

0.01 µF

C108

33 p C109

1 n

C110

1 n

C111

0.047 µF

C112

0.047 µF

C114

1 n

C116

6.8 n

C117

10 n

R102

1.0 k

10.111

Series

C115

33 n

C113

0.047 µF

L103

BEAD

L102

BEAD

C118

100 u

5 V_RF

R105

8.2

C121

0.047 µF

C120

0.047 µF

C119

10 n

R101

1.2 k

47 p

3.3 pF

22 pF

CX24109

AGC

FILTUNE

I_OUT

Q_OUT

CLK

DATA

CLKREF

_OUT

Product data sheet Rev. 01 — 13 November 2008 25

NXP Semiconductors CX24109

Chapter 2: Applications

Figure 7. Simplified Application Schematic (Page 2 of 2)

102031_008

GND (1)

PWR (2)

TUNER_EN

TUNER_DATA

TUNER_CLK

AGCV

FILTERV

TEST_MODE

XTAL_IN

I_N

Q_N

I_P

Q_P

AD_VAA

AD_VDD

Iref

Vcm

AGC

FILTUNE

I_OUT

Q_OUT

CLK

DATA

CLKREF

_OUT

C204

0.1 u

C205

100 p

C206

100 p

C207

100 p C208

0.1 u

C209

0.1 u

C861

0.01 µF C863

0.01 µF

R203 300

R207 10 K

R208

300

R204 300

R205 300

R206

300

R306

R307

+3.3 V

64 56

CX24121

SER_CLK

SER_DATA

SER_CLK

SER_DATA

LNB

Control

To MPEG

Processor

FOOTNOTE:

(1) Ground Pins include: 4, 6, 8, 10, 15, 26, 30, 34, 50, 52, 62, 70, and 71.

(2) Core (1.8 V) power pins include: 7, 9, 14, 29, 49, and 69.

3.3 V power pins include: 25, 33, 51, and 61.

(3) RS_DATA includes RS_DATA0–RS_DATA7 pins 35, 31, 28, 27, 24, 23, 22, and 21.

RS_DATA(3)

RS_CLK

RSCntl1

Interrupt (RSSYNC)

RSCntl2

GPIO_1 (LNB_DC)

LNB_22K

C602

0.047 uF

C536

0.01 uF

R515

30.9 KΩ

C535

0.047 uF C532

0.01 uF

C534

0.01 uF

C533

0.01 uF

Product data sheet Rev. 01 — 13 November 2008 26

NXP Semiconductors CX24109

Chapter 2: Applications

2.5 Typical Performance Curves

Figure 8. Reflection Coefficient at Input of CX24109

102031_020

CX24109 S11

S11

Frequency (950.0 MHz to 2.200 GHz)

Freq = 950 MHz

plot_vs(S(1,1), freq) = –0.19 + j0.21

Impedance = 31.629 + j14.373

Freq = 1.20 GHz

plot_vs(S(1,1), freq) = 0.39/65.79

Impedance = 51.055 + j42.441

Freq = 2.15 GHz

plot_vs(S(1,1), freq) = 0.29/–2.11

Impedance = 89.855 – j2.055

Product data sheet Rev. 01 — 13 November 2008 27

NXP Semiconductors CX24109

Chapter 2: Applications

Figure 9. Baseband Filter Gain vs. Frequency and FILTUNE Voltage

Figure 10. Filter –3 dB Bandwidth vs. FILTUNE Voltage

–10

0 5 10 15 20 25

Frequency (MHz)

Gain (dB)

30 35 40 45

–20

–30

–40

–50

–60

–70

FILTUNE = 0.5 V

FILTUNE = 1.0 V

FILTUNE = 1.5 V

FILTUNE = 2.0 V

FILTUNE = 2.5 V

FILTUNE = 3.0 V

0 0.5 1 1.5

FILTUNE Voltage (V)

–3dB Bandwodth of Filter (MHz)

2 2.5 3

Product data sheet Rev. 01 — 13 November 2008 28

NXP Semiconductors CX24109

Chapter 2: Applications

Figure 11. Gain and IIP3 vs. AGC Voltage at 950 MHz

Figure 12. Gain and IIP3 vs. AGC Voltage at 2150 MHz

–5

–10

1 1.5 2

AGC Voltage (V)

Gain and IIIP3 (dB)

2.5 3

IIIP3

Gain

1.2 1.7 2.2

AGC Voltage (V)

Gain and IIIP3 (dB)

2.7 3.2

IIIP3

Gain

–5

–10

Product data sheet Rev. 01 — 13 November 2008 29

NXP Semiconductors CX24109

Chapter 2: Applications

Figure 13. Gain and NF vs. AGC Voltage at 950 MHz

Figure 14. Gain and NF vs. AGC Voltage at 2150 MHz

–5

1 1.21.1 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1

AGC Voltage (V)

Gain

Noise Figure

Gain and NF (dB)

2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2

–5

–10

1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1

AGC Voltage (V)

Gain and NF (dB)

Gain

Noise Figure

2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2

Product data sheet Rev. 01 — 13 November 2008 30

NXP Semiconductors CX24109

Chapter 2: Applications

Product data sheet Rev. 01 — 13 November 2008 31

CX24109

Chapter 3: Parametric Data and Specifications

Rev. 01 — 13 November 2008 Product data sheet

3.1 Electrical Specifications

3.1.1 Standard Operating Conditions

All specifications are valid under the operating conditions indicated in Tables 8, 9, 10, and

12.

Table 11. Absolute Maximum Ratings

Parameter Minimum Maximum Units

Supply V oltage –0.3 6 V

Input Voltage Range –0.3 Vcc +0.3 V

Storage Temperature –65 +150 °C

Junction Temperature — +150 °C

Table 12. Operating Conditions

Parameter Conditions Min Typ Max Units

Ambient Operating Temperature — 0 +25 +70 °C

Maximum Operating Junction Temperature — — — 125 °C

Supply Voltage — 4.75 5.0 5.25 V

Reference Oscillator Frequency Series resonant, fundamental — 10.111 — MHz

Reference Oscillator Frequency Stability Including temperature drift — — +100 ppm

Loop Filter Bandwidth — — 10 — kHz

Product data sheet Rev. 01 — 13 November 2008 32

NXP Semiconductors CX24109

Chapter 3: Parametric Data and Specifications

Table 13. DC Electrical Characteristics

Parameter Conditions Min Typ Max Units

Supply Current(1) — — 244 262 mA

Usable AGC Voltage Range, VAGC — 1.3 — 2.80 V

Impedance of AGC Input at DC — 1 — MΩ

AGC Current, IAGC ——— 0.4mA

Usable Filtune Voltage Range, VFiltune —0—3.0V

Impedance of Filtune Input at DC — 17 — kΩ

Thermal Resistance of Package θja(2) —42—°C/W

θjc — 8.7 — °C/W

FOOTNOTES:

(1) Using 15–45 MSps programming values (see Table 8), Vcc = 5.0 V, VAGC = 1.45 V, VFiltune = 2.7 V.

(2) Using a 2-layer CX24109/CX24121 reference design, where the package’s exposed paddle is connected to the printed circuit board ground plane

using thermal vias. The ground plane on the reference design is approximately 2-7/8 inches x 1-1/4 inches. Better thermal performance can be

obtained by increasing ground plane coverage or increasing the number of attached printed circuit board layers.

Table 14. AC Electrical Characteristics

Parameter Conditions Min Typ Max Units

Programming Clock Frequency — — — 1 MHz

Bus Timing Data Setup, tSU See Figure 15.—10—ns

Data Hold, tHD —10— ns

Enable Pulse

Width, tEW

1——μs

Clock to Enable,

tCE

—1—μs

Programming Lines:

Clock, Data, Enable VIH —2.1——V

VIL ———0.8V

IIH ———0.5mA

IIL — — — –0.5 mA

LD and CLKREFOUT VOH — 2.3 2.65 — V

VOL — — 0.9 1.125 V

Product data sheet Rev. 01 — 13 November 2008 33

NXP Semiconductors CX24109

Chapter 3: Parametric Data and Specifications

Figure 15. Serial Programming Example

Table 15. RF Electrical Characteristics (Sheet 1 of 3)

Parameter Conditions Min Typ Max Units

Tuning Frequency — 950 — 2150 MHz

Input Power , Single Tone(1) Depends on bandwidth of incoming signal

and C/I –81 — –23 dBm

Aggregate Input Power(1)(2) ———–7dBm

Input Impedance, Balanced(1) ZSOURCE = 75 Ω—75— Ω

Input VSWR(1) ——10—dB

Iout and Qout Output Voltage RLoad = 1kΩ—0.5—V

P-P

Maximum Conversion (Voltage) Gain VAGC=2.4 V, 1 MSps gain coefficients(1) 76 86 91 dB

Minimum Conversion (Voltage) Gain VAGC=1.45 V, 45 MSps gain coefficients(1) 8 18 23 dB

Noise Figure (NF)(1) (3) Pin = –43 dBm,

1–5 MSps gain coefficients(4) — 36 42 dB

Pin = –81 dBm,

1–5 MSps gain coefficients(5) —10.514 dB

Pin = –34.5 dBm,

5–15 MSps gain coefficients(6) —3542dB

Pin = –72 dBm,

5–15 MSps gain coefficients(7) —10.514 dB

Pin = –30 dBm,

15–45 MSps gain coefficients(8) —3545dB

Pin = –70 dBm,

15–45 MSps gain coefficients(9) —10.514 dB

102031_016

. . .

Clock

tHD

tsu

tce tew

Data

Enable

Product data sheet Rev. 01 — 13 November 2008 34

NXP Semiconductors CX24109

Chapter 3: Parametric Data and Specifications

IIP3 (Out-of-band)(1) (4) +(31 and 60) MHz, Pin = –42 dBm,

1–5 MSps gain coefficients(4) –2 4.0 — dBm

+(91 and 180) MHz, Pin = –42 dBm,

1–5 MSps gain coefficients(4) 5.5 9.4 — dBm

+(31 and 60) MHz, Pin = –81 dBm,

1–5 MSps gain coefficients –35 –25.0 — dBm

+(91 and 180) MHz, Pin = –81 dBm,

1–5 MSps gain coefficients(5) –39 –7.2 — dBm

+(31 and 60) MHz, Pin = –34.5 dBm,

5–15 MSps gain coefficients(6) 05.0—dBm

+(91 and 180) MHz, Pin = –34.5 dBm,

5–15 MSps gain coefficients(6) 5.5 9.8 — dBm

+(31 and 60) MHz, Pin = –72 dBm,

5–15 MSps gain coefficients(7) –35 –25.5 — dBm

+(91 and 180) MHz, Pin = –72 dBm,

5–15 MSps gain coefficients(7) –30 –6.5 — dBm

+(31 and 60) MHz, Pin = –30 dBm,

15–45 MSps gain coefficients(8) –2 5.5 — dBm

+(91 and 180) MHz, Pin = –30 dBm,

15–45 MSps gain coefficients(8) 5.7 10.5 — dBm

+(31 and 60) MHz, Pin = –70 dBm,

15–45 MSps gain coefficients(9) –35 –24.5 — dBm

+(91 and 180) MHz, Pin = –70 dBm,

15–45 MSps gain coefficients(9) –28 –6.5 — dBm

IIP3I (Inband) 1 MSps coefficients and VAGC = 1. 5 V(1) —–30—dBm

1 MSps coefficients and VAGC = 2.4 V(1) —–65—dBm

I/Q Phase Difference — — 3 13 +deg

I/Q Amplitude Ratio — — 1 3 +dB

LO Leakage 950 to 2150 MHz(1) —–80–70dBm

2LO-RF Rejection C/I = 10 dB VAGC = 1.5 V(1) –30 –45 — dB

2RF-LO Rejection C/I = 10 dB(1) –30 –50 — dB

Table 15. RF Electrical Characteristics (Sheet 2 of 3)

Parameter Conditions Min Typ Max Units

Product data sheet Rev. 01 — 13 November 2008 35

NXP Semiconductors CX24109

Chapter 3: Parametric Data and Specifications

VCO and Synthesizer

Reference Oscillator Phase Noise Measured at 400 Hz — –130 — dBc/Hz

Spurious At 1, 10.111, and 30 MHz offsets

with 2 mA charge pump and

10 kHz loop BW

–30 –45 — dBc

VCO Tuning Sensitivity — 100 — 330 MHz/V

LO Phase Noise at 950 MHz–1450 MHz 10 kHz offset — –75 — dBc/Hz

100 kHz offset — –97 — dBc/Hz

LO Phase Noise at 1450 MHz–2150 MHz 10 kHz offset — –69 — dBc/Hz

100 kHz offset — –94 — dBc/Hz

LO Phase Noise at 950 MHz–2150 MHz 10 kHz offset +100 kHz offset — — –158 dBc/Hz

Local Oscillator Settling Time All frequencies, VCOs and modes — 1 — ms

GENERAL NOTES:

1. Values in this table are valid under the operating conditions listed in Tables 8, 9, and 10, using a reference divider of 10, unless otherwise

stated.

FOOTNOTES:

(1) This measurement is made at RFIN of CX24109.

(2) Aggregate average power of 40 QPSK modulated carriers.

(3) All NF and IIP3 measurements/specifications are made by setting a specific input level for the desired symbol rate and adjusting the AGC

level to obtain the desired output level of 0.5 Vpp.

(4) This level is derived assuming –23 dBm is the maximum level of all other transponders and that the operating symbol rate is 1 MSps.

Assume C/I of 7 dB and a bandwidth scaling of 10 log (20 MHz / 1 MHz), thus, Pin = –23 dBm – 7 dB – 10 log (20 / 1) = –43 dBm.

(5) This level is derived from Pin = PTransponder – LPath + GAntenna + GLNBmin – LCable. Where the operating symbol rate is 1 MSps and

PTransponder is at a minimum. PTransponder = 10 log ((1E6 / 45E6) 10 (82 – 4) /10) = +61 dBm. Therefore, Pin = + 61 dBm – 205 dB + 38 dB +

45 dB – 20 dB = –81 dBm.

(6) This level is derived assuming –23 dBm is the maximum level of all other transponders and that the operating symbol rate is 7 MSps.

Assume C/I of 7 dB and a bandwidth scaling of 10 log (20 MHz / 7 MHz), thus, Pin = –23 dBm – 7 dB – 10 log 20 / 7 = –34.5 dBm.

(7) This level is derived from Pin = PTransponder – LPath + GAntenna + GLNBmin – LCable. Where the operating symbol rate is 7 MSps and

PTransponder = 10 log ((7E6 / 45E6) 10 (82–4)/10) = +70 dBm. Therefore, Pin = +70 dB – 205 dB + 38 dB + 45 dB – 20 dB = –72 dBm

(8) This level is derived assuming –23 dBm is the maximum level of all other transponders, an operating symbol rate of 20 MSps and a C/I of

7 dB.

(9) Assume a sym bol rate of 20 MSps.

Table 15. RF Electrical Characteristics (Sheet 3 of 3)

Parameter Conditions Min Typ Max Units

Product data sheet Rev. 01 — 13 November 2008 36

NXP Semiconductors CX24109

Chapter 3: Parametric Data and Specifications

3.2 Mechanical Specifications

Table 16. Baseband Frequency Response

Parameter Conditions Min Typ Max Units

Minimum Cutoff Frequency, F1 dB Measured at minimum VFiltune 1.4 — 2.6 MHz

Minimum Cutoff Frequency, F1 dB Measured at maximum VFiltune 27 — — MHz

Tuning Voltage Transfer Function 0 V < VFiltune < 3.0 V — 10.5 — MHz/V

Passband Ripple 0 < Freq < F1 dB ——1.0dB

Stopband Attenuation F > 2.6 × F1 dB 35 — — dB

Stopband Attenu atio n 5 × F1 dB < F < 2 GHz 45 — — dB

Figure 16. 48-pin eTQFP Land Pattern

5.070 REF. 4.570 REF.1.215 REF.

1.215 REF.

8.400 REF.

9.400 REF.

11 EQ SP @ 0.50 = 5.50

TYP

5.070 REF.

0.965 REF.

4.570 REF.

3x3 Array of

Thermal Vias

0.330 mm Dia.

Spacing TBD

Mask Opening

Thermal Vias Should be

Tinted Using 0.430 mm Dia.

Solder Mask

1.000

0.500

0.250

PWB Exposed Pad

LAND PATTERN - 48 ETQFP

PWB METALIZATION PATTERN PWB SOLDER MASK PATTERN

102031_017

Product data sheet Rev. 01 — 13 November 2008 37

NXP Semiconductors CX24109

Chapter 3: Parametric Data and Specifications

Figure 17. 48-pin eTQFP Package Diagram

102031_018

Pin #1

Ref. Mark

D1D1

Coplanarity

See Detail A

TOP VIEW

SIDE VIEW

BOTTOM VIEW

DETAIL A

e b

0.05

0.95

0.45

0.17

0.09

0.15

1.05

0.75

0.27

0.20

1.20 MAX

9.00 BSC

7.00 BSC

4.50 REF

1.00 REF

0.50 BSC

0.08 MAX

0.002

0.037

0.018

0.007

0.004

0.006

0.041

0.030

0.011

0.008

0.047 MAX

0.354 BSC

0.275 BSC

0.177 REF

0.039 REF

0.020 BSC

0.003 MAX

Millimeters

Min

Dimension Max Min Max

Inches

Product data sheet Rev. 01 — 13 November 2008 38

NXP Semiconductors CX24109

Chapter 3: Parametric Data and Specifications

Product data sheet Rev. 01 — 13 November 2008 39

NXP Semiconductors CX24109

Digital Satellite Tuner

Legal information

Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device (s) descri bed in this d ocument may have change d since this document was p ublished and may dif fer in case of multiple devices. The latest product st atus

information is available on the Internet at URL http://www.nxp.com.

Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sh eet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Disclaimers

General — In formation in this document is believed to be accurate and

reliable. However, NXP Semiconductors d oes not give an y represent ations or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and with out

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ra tings System of IEC 60134) may cause pe rmanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or inte llectual property rights.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data fro m the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

NXP Semiconductors CX24109

Digital Satellite Tuner

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 13 November 2008

Document identifier: CX24109_N_1

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.