1
FEATURES
>155.5 Mbps (77.7 MHz) switching rates
+340mV differential signaling
5 V power supply
Cold Spare LVDS inputs
TTL compatible outputs
Ultra low power CMOS technology
8.0ns maximum propagat ion delay
3.0ns maximum differential skew
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
Packaging options:
- 16-lead flatpack (dual in-line)
Standard Microcircuit Drawing 5962-95834
- QML Q and V compliant part
Compatible with IEEE 1596.3SCI LVDS
Compatible with ANSI/TIA/EIA 644-1996 L VDS Standard
INTRODUCTION
The UT54LVDSC032 Quad Receiver is a quad CMOS
differential line receiver designed for applications requiring
ultra low power dissipation and high data rates. The device is
designed to support data rates in excess of 155.5 Mbps (77.7
MHz) utilizing Low Voltage Differential Signaling (LVDS)
technology.
The UT54L VDSC032 accepts low voltage (340mV) differential
input signals and translates them to 5V TTL output levels. The
receiver supports a three-state function that may be used to
multiplex outputs. The receiver also suppo rts OPEN, shorted
and terminated (100 Ω) input fail-safe. Receiver output will be
HIGH for all fail-safe conditions.
The UT54LVDSC032 and companion quad line driver
UT54LVDS03 1 provides new alternatives to high power
pseudo-ECL devices for high speed point-to-point interface
applications.
All LVDS pins have Cold Spare buffers. These buffers will be
high impedance when V DD is tied to VSS.
+
R1
-
RIN1+
RIN1-
RIN2+
RIN2-
RIN3+
RIN3-
RIN4+
RIN4-
ROUT1
ROUT2
ROUT4
ROUT3
EN
EN
+
R2
-
+
R3
-
+
R4
-
Standard Products
UT54LVDSC032 Quad Receiver
Data Sheet
July 2, 2004
www.aeroflex.com/lvds
Figure 1. UT54LVDSC032 Quad Receiver Block Diagram
2
TRUTH TABLE
PIN DESCRIPTION
APPLICATIONS INFORMATION
The UT54L VDSC032 receiver’ s intended use is primarily in an
uncomplicated point-t o-poin t configuration as is shown in
Figure 3. This configuration provides a clean signaling
environment for quick edge rates of the drivers. The receiver is
connected to the driver through a balanced media which may
be a standard twisted pair cable, a parallel pair cable, or simply
PCB traces. Typically, the characteristic impedance of the
media is in the range of 100Ω. A termination resistor of 100Ω
should be selected to match the media and is located as close to
the receiver input pins as possible. The termination resistor
converts the current sourced by the driver into voltages that are
detected by the receiver. Other configurations are possible such
as a multi-receiver configuration, but the effects of a mid-stream
connector(s), cable stub(s), and other impedance
discontinuities, as well as ground shifting, noise margin limits,
and total termination loading must be taken into account.
The UT54LVDSC032 differential line receiver is capable of
detecting signals as low as 100mV, over a + 1V common-mode
range centered around +1.2V. This is related to the driver offset
voltage which is typically +1.2V. The driven signal is centered
around this voltage and may shift +1V around this center point.
The +1V shifting may be the result of a ground potential
difference between the driver’s ground reference and the
receiver’s ground reference, the common-mode effects of
coupled noise or a combination of the two. Both receiver input
pins should honor their specified operating input voltage range
of 0V to +2.4V (measured from each pin to ground).
Receiver Fail-Safe
Enables Input Output
EN EN RIN+ - RIN- ROUT
L H X Z
All other combinations
of ENABLE inputs VID > 0.1V H
VID < -0.1V L
Full Fail-safe
OPEN/SHORT or
Terminated
H
Pin No. Name Description
2, 6, 10, 14 RIN+ Non-inverting receiver input pin
1, 7, 9, 15 RIN- Inverting receiver input pin
3, 5, 1 1, 13 ROUT Receiver output pin
4EN Active high enable pin, OR-ed
with EN
12 EN Active low enable pin, OR-ed
with EN
16 VDD Power supply pin, +5V + 10%
8 VSS Ground pin
Figure 2. UT54LVDSC032 Pinout
UT54LVDSC032
Receiver
16
15
14
13
12
11
10
9
VDD
RIN4-
RIN4+
ROUT4
EN
ROUT3
RIN3+
RIN3-
1
RIN1-
2
RIN1+ 3
ROUT1
4
EN 5
ROUT2 6
RIN2+ 7
RIN2-
8
VSS
ENABLE
DATA
INPUT
1/4 UT54LVDS031
1/4 UT54LVDSC032
+
-DATA
OUTPUT
Figure 3. Point-to-Point Application
RT 100Ω
3
The UT54LVDSC32 receiver is a high gain, high speed device
that amplifies a small differential signal (20mV) to TTL logic
levels. Due to the high gain and tight threshold of the receiver,
care should be taken to prevent noise from appearing as a valid
signal.
The receiver’s internal fail-safe circuitry is designed to source/
sink a small amount of current, providing fail-safe protection (a
stable known state of HIGH output voltage) for floating,
terminated or shorted receiver inputs.
1. Open Input Pins. The UT54LVDSC032 is a quad
receiver device, and if an application requires only 1, 2
or 3 receivers, the unused channel(s) inputs should be
left OPEN. Do not tie unused receiver inputs to ground
or any other voltages. The input is biased by internal high
value pull up and pull down resistors to set the output to
a HIGH state. This internal circuitry will guarantee a
HIGH, stable output state for open inputs.
2. Terminated Input. If the driver is disconnected (cable
unplugged), or if the driver is in a three-state or power-
off condition, the receiver output will again be in a HIGH
state, even with the end of cable 100Ω termi nation
resistor across the input pins. The unplugged cable can
become a floating antenna which can pick up noise. If
the cable picks up more than 10mV of differential noise,
the receiver may see the noise as a valid signal and
switch. To insure that any noise is seen as common-mode
and not differential, a balanced interconnect should be
used. Twisted pair cable offers better balance than flat
ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts
the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output remains in
a HIGH state. Shorted input fail-safe is not supported
across the common-mode range of the device (VSS to
2.4V). It is only supported with inputs shorted and no
external common-mode voltage applied.
4
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only , and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
4. During cold spare, all pins except LVDS inputs shoul d no t excee d ±0. 3V.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.3V to 6.0V
VI/O4Voltage on any pin during operation
Voltage on L VDS inputs during cold spare
-0.3V to (VDD + 0.3V)
-0.3V to 6.0V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissi p a tion 1.25 W
TJMaximum junction temperature2+150°C
ΘJC Thermal resistance, junction-to-case310°C/W
IIDC input current ±10mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 4.5 to 5.5V
TCCase temperature range -55 to +125°C
VIN DC input voltage, receiver inputs
DC input voltage, logic inputs 2.4V
0 to VDD for EN, EN
5
DC ELECTRICAL CHARACTERISTICS 1(VDD = 5.0V +10%; -55°C < TC < +125°C)
Notes:
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed
maximum junction temperature specification.
3. Guaranteed by characterization.
4. Device tested at VCC = 5.5V only.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (TTL) 2.0 V
VIL Low-level input voltage (TTL) 0.8 V
VOL Low-level output voltage IOL = 2mA, VDD = 4.5V 0.3 V
VOH High-level output voltage IOH = -0.4mA, VDD = 4.5V 4.0 V
IIN Logic input leakage current Inputs, VIN = 0 and 2.4V, VCC = 5.5
Enables = EN/EN= 0 and 5.5V,
VCC = 5.5
-10
-10 +10
+10 µA
ICSIN Cold Spare Leakage LVDS Inputs VIN=5.5V, VDD=VSS -10 +10 µΑ
VTH3Differential Input High Threshold VCM = +1.2V +100 mV
VTL3Differential Input Low Threshold VCM = +1.2V -100 mV
IIReceiver input Current VIN = 2.4V -10 +10 µΑ
IOZ4Output Three-State Current Disabled, VOUT = 0 V or VDD -10 +10 µΑ
VCL Input clamp voltage ICL = +/-18mA -1.5 1.5 V
IOS3Output Short Circuit Current Enabled, VOUT = 0 V2-15 -130 mA
ICC4Loaded supply current receivers
enabled EN, EN = VDD or VSS
Inputs Open
11 mA
ICCZ4Loaded supply current receivers
disabled EN = VSS, EN = VDD
Inputs Open 11 mA
6
AC SWITCHING CHARACTERISTICS1, 2, 3, 4 (VDD = +5.0V + 10%, TA = -55 °C to +125 °C)
Notes:
1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the
inputs.
2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z0 = 50Ω, tr and tf (0% - 100%) < 1ns for RIN and tr and tf < 6ns for EN or EN.
3. CL includes probe and jig capacitance.
4. Guaranteed by characterization.
5. Chip to Chip Skew is defined as the difference between the minimum and max im um specified differential propagation delays.
SYMBOL PARAMETER MIN MAX UNIT
tPHLD Differential Propagation Delay High to Low
CL = 20pf (figures 4 and 5) 1.0 8.0 ns
tPLHD Differential Propagation Dela y Lo w to High
CL = 20pf (figures 4 and 5) 1.0 8.0 ns
tSKD Differential Skew (tPHLD - tPLHD) (figures 4 and 5) 03.0 ns
tSK14Channel-to-Channel Skew1 (figures 4 and 5) 03.0 ns
tSK24Chip-to-Chip Skew5 (figures 4 and 5) 7.0 ns
tTLH4Rise Time (figures 4 and 5) 2.0 ns
tTHL4Fall Time (figures 4 and 5) 2.0 ns
tPHZ4Disable Time High to Z (figures 6 and 7) 20 ns
tPLZ4Disable Time Low to Z (figures 6 and 7) 20 ns
tPZH4Enable Time Z to High (figures 6 and 7) 20 ns
tPZL4Enable Time Z to Low (figures 6 and 7) 20 ns
7
R
RIN+ ROUT
Receiver Enabled
Generator
50Ω
Figure 4. Receiver Propagation Delay and Transition Time Test Circuit or Equivalent Circuit
RIN-
50Ω
CL
RIN-
RIN+
ROUT
tPHLD
VOL
VOH
+1.1V
1.25V
+1.2V
tTHL
20%
80%
1.25V
20%
80%
tTLH
0V Differential
Figure 5. Receiver Propagation Delay and Transition Time Waveforms
tPLHD
VID = 200mV
+1.3V
8
Figure 6. Receiver Three-State Delay Test Circuit or Equivalent Circuit
RIN+
RIN-
EN VDD
2K
2K
20pf
EN when EN = VDD
EN when EN = VSS
Output when
VID = -100mV
Output when
VID = +100mV
tPHZ tPZH
0.5V 50%
VOH
VSS
VDD
0V
VDD
0V
VDD
1.25V
1.25V
1.25V
1.25V
0.5V
tPZL
tPLZ
Figure 7. Receiver Three-State Delay Waveform
50%
VOL
9
Notes:
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance to MIL-PRF-38535.
4. Package dimensions and symbols are similar to MIL-STD-183 5 variation F-5A.
5. Lead position and coplanarity are not measured.
6. ID mark symbol is vendor optio n.
7. With solder, increase maximum by 0.003.
Figure 8. 16-pin Ceramic Flatpack
PACKAGING
10
ORDERING INFORMATION
UT54LVDSC032 QUAD RECEIVER:
UT54LVDSC032- * * * * *
Device Type:
UT54LVDSC032 LVDS Receiver
Access T i me:
Not applicable
Package Type:
(U) = 16-lead Flatpack (dual-in-line)
Screening:
(C) = Military Temperature Range flow
(P) = Prototype flow
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per UTMC Manufacturing Flows Document. T ested at 25°C only . Lead f inish is GOLD ONLY. Radiation neither
tested nor guaranteed.
4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.
Radiation neither tested nor guaranteed.
11
UT54LVDSC032 QUAD RECEIVER: SMD
5962 - ** *
Federal Stock Class Designator: No Options
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
Drawing Number: 95834
Device Type
03 = LVDS Receiver
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Case Outline:
(X) = 16 lead Flatpack (dual-in-line)
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
**
95834
Notes:
1.Lead finish (A,C, or X) must be specifi ed.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
