LTC1871-7
1
18717fd
Typical applicaTion
FeaTures
applicaTions
DescripTion
High Input Voltage,
Current Mode Boost,
Flyback and SEPIC Controller
The LTC
®
1871-7 is a current mode, boost, flyback and
SEPIC controller optimized for driving 6V-rated MOSFETs
in high voltage applications. The LTC1871-7 works equally
well in low or high power applications and requires few
components to provide a complete power supply solution.
The switching frequency can be set with an external resistor
over a 50kHz to 1MHz range, and can be synchronized to
an external clock using the MODE/SYNC pin. Burst Mode
operation at light loads, a low minimum operating supply
voltage of 6V and a low shutdown quiescent current of
10µA make the LTC1871-7 well suited for battery-operated
systems. For applications requiring constant frequency
operation, Burst Mode operation can be defeated using
the MODE/SYNC pin. The LTC1871-7 is available in the
10-lead MSOP package.
PARAMETER LTC1871-7 LTC1871
INTVCC 7.0V 5.2V
INTVCC UV+5.6V 2.1V
INTVCC UV–4.6V 1.9V
Figure 1. Small, Nonisolated 12V Flyback Telecom Housekeeping Supply
n Optimized for High Input Voltage Applications
n Wide Chip Supply Voltage Range: 6V to 36V
n Internal 7V Low Dropout Voltage Regulator
Optimized for 6V-Rated MOSFETs
n Current Mode Control Provides Excellent
Transient Response
n High Maximum Duty Cycle (92% Typ)
n ±2% RUN Pin Threshold with 100mV Hysteresis
n ±1% Internal Voltage Reference
n Micropower Shutdown: IQ = 10µA
n Programmable Operating Frequency
(50kHz to 1MHz) with One External Resistor
n Synchronizable to an External Clock Up to 1.3 × fOSC
n User-Controlled Pulse Skip or Burst Mode
®
Operation
n Output Overvoltage Protection
n Can be Used in a No RSENSE™ Mode for VDS < 36V
n Small 10-Lead MSOP Package
n Telecom Power Supplies
n 42V Automotive Systems
n 24V Industrial Controls
n IP Phone Power Supplies
L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks
of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
RUN
ITH
FB
FREQ
MODE/SYNC
SENSE
VIN
INTVCC
GATE
GND
LTC1871-7
120k 4.7µF
X5R
2.2µF
100V
X7R
M1
FDC2512
0.12Ω
VIN
36V TO 72V
3.4k
2.2nF
26.7k
D3
10BQ060
47µF
16V
X5R
VOUT
12V
0.4A
604k
12.4k
T1
VP1-0076
100k
10Ω
Q1
FMMT625
D2
4148
D1
9.1V
110k 0.1µF
X5R
3:1
18717 F01
•
•
LTC1871-7
2
18717fd
pin conFiguraTionabsoluTe MaxiMuM raTings
VIN Voltage ............................................... – 0.3V to 36V
INTVCC Voltage ........................................... –0.3V to 9V
INTVCC Output Current...........................................50mA
GATE Voltage ........................... –0.3V to VINTVCC + 0.3V
ITH, FB Voltages ....................................... –0.3V to 2.7V
RUN Voltage................................................ –0.3V to 7V
MODE/SYNC Voltage ................................... –0.3V to 9V
FREQ Voltage ............................................ –0.3V to 1.5V
SENSE Pin Voltage .................................... –0.3V to 36V
Operating Temperature Range (Note 2)
LTC1871E-7 ..........................................–40°C to 85°C
LTC1871I-7 ......................................... –40°C to 125°C
Junction Temperature (Note 3) ............................. 125°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec) ................... 300°C
(Note 1)
1
2
3
4
5
RUN
ITH
FB
FREQ
MODE/
SYNC
10
9
8
7
6
SENSE
VIN
INTVCC
GATE
GND
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 120°C/W
orDer inForMaTion
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1871EMS-7#PBF LTC1871EMS-7#TRPBF LTG4 10-Lead Plastic MSOP –40°C to 85°C
LTC1871IMS-7#PBF LTC1871IMS-7#TRPBF LTBTR 10-Lead Plastic MSOP –40°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC1871EMS-7 LTC1871EMS-7#TR LTG4 10-Lead Plastic MSOP –40°C to 85°C
LTC1871IMS-7 LTC1871IMS-7#TR LTBTR 10-Lead Plastic MSOP –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
VIN(MIN) Minimum Input Voltage 6 V
I-Grade (Note 2) ●6 V
IQInput Voltage Supply Current (Note 4)
Continuous Mode VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V 550 1000 µA
VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V,
I-Grade (Note 2)
●600 1100 µA
Burst Mode Operation, No Load VMODE/SYNC = 0V, VITH = 0.2V (Note 5) 280 500 µA
VMODE/SYNC = 0V, VITH = 0.2V (Note 5),
I-Grade (Note 2)
●280 600 µA
Shutdown Mode VRUN = 0V 12 25 µA
VRUN = 0V, I-Grade (Note 2) ●12 25 µA
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 8V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified.
LTC1871-7
3
18717fd
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 8V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VRUN+Rising RUN Input Threshold Voltage 1.348 V
VRUN–Falling RUN Input Threshold Voltage
●
1.223
1.198
1.248 1.273
1.298
V
V
VRUN(HYST) RUN Pin Input Threshold Hysteresis 50 100 150 mV
I-Grade (Note 2) ●35 100 175 mV
IRUN RUN Input Current 5 60 nA
VFB Feedback Voltage VITH = 0.2V (Note 5)
●
1.218
1.212
1.230 1.242
1.248
V
V
VITH = 0.2V (Note 5), I-Grade (Note 2) ●1.205 1.255 V
IFB FB Pin Input Current VITH = 0.2V (Note 5) 18 60 nA
∆VFB
∆VIN
Line Regulation 6V ≤ VIN ≤ 30V 0.002 0.02 %/V
6V ≤ VIN ≤ 30V, I-Grade (Note 2) ●0.002 0.02 %/V
∆VFB
∆VITH
Load Regulation VMODE/SYNC = 0V, VITH = 0.5V to 0.9V (Note 5) ●–1 –0.1 %
VMODE/SYNC = 0V, VITH = 0.5V to 0.9V (Note 5)
I-Grade (Note 2)
●–1 –0.1 %
∆VFB(OV) ∆FB Pin, Overvoltage Lockout VFB(OV) – VFB(NOM) in Percent 2.5 6 10 %
gmError Amplifier Transconductance ITH Pin Load = ±5µA (Note 5) 600 µmho
VITH(BURST) Burst Mode Operation ITH Pin Voltage Falling ITH Voltage (Note 5) 0.3 V
VSENSE(MAX) Maximum Current Sense Input Threshold Duty Cycle < 20% 120 150 180 mV
Duty Cycle < 20%, I-Grade (Note 2) ●100 200 mV
ISENSE(ON) SENSE Pin Current (GATE High) VSENSE = 0V 35 70 µA
ISENSE(OFF) SENSE Pin Current (GATE Low) VSENSE = 30V 0.1 5 µA
Oscillator
fOSC Oscillator Frequency RFREQ = 80k 250 300 350 kHz
RFREQ = 80k, I-Grade (Note 2) ●250 300 350 kHz
Oscillator Frequency Range 50 1000 kHz
I-Grade (Note 2) ●50 1000 kHz
DMAX Maximum Duty Cycle 87 92 97 %
I-Grade (Note 2) ●87 92 98.5 %
fSYNC/fOSC Recommended Maximum Synchronized
Frequency Ratio
fOSC = 300kHz (Note 6) 1.25 1.30
fOSC = 300kHz (Note 6), I-Grade (Note 2) ●1.25 1.30
tSYNC(MIN) MODE/SYNC Minimum Input Pulse Width VSYNC = 0V to 5V 25 ns
tSYNC(MAX) MODE/SYNC Maximum Input Pulse Width VSYNC = 0V to 5V 0.8/fOSC ns
VIL(MODE) Low Level MODE/SYNC Input Voltage 0.3 V
I-Grade (Note 2) ●0.3 V
VIH(MODE) High Level MODE/SYNC Input Voltage 1.2 V
I-Grade (Note 2) ●1.2 V
RMODE/SYNC MODE/SYNC Input Pull-Down Resistance 50 kΩ
VFREQ Nominal FREQ Pin Voltage 0.62 V
Low Dropout Regulator
VINTVCC INTVCC Regulator Output Voltage VIN = 8V 6.5 7 7.5 V
VIN = 8V, I-Grade (Note 2) ●6.5 7 7.5 V
LTC1871-7
4
18717fd
FB Voltage vs Temp
FB Voltage Line Regulation
FB Pin Current vs Temperature
elecTrical characTerisTics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 8V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
UVLO INTVCC Undervoltage Lockout Threshold Rising INTVCC
Falling INTVCC
UVLO Hysteresis
5.6
4.6
1.0
V
V
V
∆VINTVCC
∆VIN1
INTVCC Regulator Line Regulation 8V ≤ VIN ≤ 15V 8 25 mV
∆VINTVCC
∆VIN2
INTVCC Regulator Line Regulation 15V ≤ VIN ≤ 30V 70 200 mV
VLDO(LOAD) INTVCC Load Regulation 0 ≤ IINTVCC ≤ 20mA, VIN = 8V –2 –0.2 %
VDROPOUT INTVCC Regulator Dropout Voltage VIN = 6V, INTVCC Load = 20mA 280 mV
GATE Driver
trGATE Driver Output Rise Time CL = 3300pF (Note 7) 17 100 ns
tfGATE Driver Output Fall Time CL = 3300pF (Note 7) 8 100 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC1871E-7 is guaranteed to meet performance specifications
from 0°C to 70°C junction temperature. Specifications over the –40°C
to 85°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LTC1871I-7 is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD • 120°C/W)
Note 4: The dynamic input supply current is higher due to power MOSFET
gate charging (QG • fOSC). See Applications Information.
Note 5: The LTC1871-7 is tested in a feedback loop that servos VFB to the
reference voltage with the ITH pin forced to a voltage between 0V and 1.4V
(the no load to full load operating voltage range for the ITH pin is 0.3V to
1.23V).
Note 6: In a synchronized application, the internal slope compensation
gain is increased by 25%. Synchronizing to a significantly higher ratio will
reduce the effective amount of slope compensation, which could result in
subharmonic oscillation for duty cycles greater than 50%.
Note 7: Rise and fall times are measured at 10% and 90% levels.
Typical perForMance characTerisTics
TEMPERATURE (°C)
–50
FB VOLTAGE (V)
1.23
1.24
150
18717 G01
1.22
1.21 050 100
–25 25 75 125
1.25
VIN (V)
0
1.229
FB VOLTAGE (V)
1.230
1.231
5 10 15 20
18717 G02
25 30 35
TEMPERATURE (°C)
–50
0
FB PIN CURRENT (nA)
10
20
30
40
60
–25 250 50 10075
18717 G03
125 150
50
LTC1871-7
5
18717fd
Typical perForMance characTerisTics
Shutdown Mode IQ vs VIN
Shutdown Mode IQ vs Temperature
Burst Mode IQ vs VIN
Burst Mode IQ vs Temperature
Dynamic IQ vs Frequency
Gate Drive Rise and
Fall Time vs CL
RUN Thresholds vs VIN
RUN Thresholds vs Temperature
RT vs Frequency
VIN (V)
0
0
SHUTDOWN MODE IQ (µA)
10
20
10 20 30 40
18717 G04
30
TEMPERATURE (°C)
–50
0
SHUTDOWN MODE IQ (µA)
5
10
15
20
–25 0 25 50
18717 G05
75 100 125 150
VIN = 8V
VIN (V)
0
0
BURST MODE I
Q
(µA)
100
200
300
400
600
10 20
18717 G06
30 40
500
TEMPERATURE (°C)
–50
0
Burst Mode IQ (µA)
200
500
050 75
18717 G07
100
400
300
–25 25 100 125 150
FREQUENCY (kHz)
0
0
IQ (mA)
2
6
8
10
800
18
18717 G08
4
400 1200
600
200 1000
12
14
16
CL = 3300pF
IQ(TOT) = 600µA + Qg • f
CL (pF)
0
0
TIME (ns)
10
20
30
40
60
2000 4000 6000 8000
18717 G09
10000 12000
50
RISE TIME
FALL TIME
VIN (V)
0
1.2
RUN THRESHOLDS (V)
1.3
1.4
10 20 30 40
18717 G10
1.5
TEMPERATURE (°C)
–50
RUN THRESHOLDS (V)
1.30
1.35
150
18717 G11
1.25
1.20 050 100
–25 25 75 125
1.40
FREQUENCY (kHz)
100
RT (kΩ)
300
1000
18717 G12
10
100
200 1000
900
800700600
500
400
0
LTC1871-7
6
18717fd
Typical perForMance characTerisTics
Frequency vs Temperature
Maximum Sense Threshold
vs Temperature
SENSE Pin Current vs Temperature
INTVCC Load Regulation
INTVCC Line Regulation
INTVCC Dropout Voltage
vs Current, Temperature
RUN (Pin 1): The RUN pin provides the user with an
accurate means for sensing the input voltage and pro-
gramming the start-up threshold for the converter. The
falling RUN pin threshold is nominally 1.248V and the
comparator has 100mV of hysteresis for noise immunity.
When the RUN pin is below this input threshold, the IC
is shut down and the VIN supply current is kept to a low
value (typ 10µA). The Absolute Maximum Rating for the
voltage on this pin is 7V.
ITH (Pin 2): Error Amplifier Compensation Pin. The current
comparator input threshold increases with this control
voltage. Nominal voltage range for this pin is 0V to 1.40V.
FB (Pin 3): Receives the feedback voltage from the external
resistor divider across the output. Nominal voltage for this
pin in regulation is 1.230V.
FREQ (Pin 4): A resistor from the FREQ pin to ground
programs the operating frequency of the chip. The nominal
voltage at the FREQ pin is 0.6V.
pin FuncTions
TEMPERATURE (°C)
–50
275
GATE FREQUENCY (kHz)
280
290
295
300
325
310
050 75
18717 G13
285
315
320
305
–25 25 100 125 150
TEMPERATURE (°C)
–50
140
MAX SENSE THRESHOLD (mV)
145
150
155
160
–25 0 25 50
18717 G14
75 100 125 150
TEMPERATURE (°C)
–50
25
SENSE PIN CURRENT (µA)
30
35
050 75
18717 G15
–25 25 100 125 150
GATE HIGH
VSENSE = 0V
0
INTVCC VOLTAGE (V)
7.0
30 50 80
18717 G16
6.9
6.8
10 20 40 60 70
VIN = 8V
VIN (V)
0
6.9
INTVCC VOLTAGE (V)
7.0
7.1
10 20 30 40
18717 G17
7.2
5 15 25 35
INTVCC LOAD (mA)
0
0
DROPOUT VOLTAGE (mV)
50
150
200
250
500
350
510
18717 G18
100
400
450
300
15 20
150°C
75°C
125°C
25°C
–50°C
0°C
LTC1871-7
7
18717fd
pin FuncTions
MODE/SYNC (Pin 5): This input controls the operating
mode of the converter and allows for synchronizing the
operating frequency to an external clock. If the MODE/
SYNC pin is connected to ground, Burst Mode operation
is enabled. If the MODE/SYNC pin is connected to INTVCC,
or if an external logic-level synchronization signal is ap-
plied to this input, Burst Mode operation is disabled and
the IC operates in a continuous mode.
GND (Pin 6): Ground Pin.
GATE (Pin 7): Gate Driver Output.
INTVCC (Pin 8): The Internal 7V Regulator Output. The
gate driver and control circuits are powered from this
voltage. Decouple this pin locally to the IC ground with a
minimum of 4.7µF low ESR tantalum or ceramic capacitor.
This 7V regulator has an undervoltage lockout circuit with
5.6V and 4.6V rising and falling thresholds, respectively.
VIN (Pin 9): Main Supply Pin. Must be closely decoupled
to ground.
SENSE (Pin 10): The Current Sense Input for the Control
Loop. Connect this pin to a resistor in the source of the
power MOSFET. Alternatively, the SENSE pin may be con-
nected to the drain of the power MOSFET, in applications
where the maximum VDS is less than 36V. Internal leading
edge blanking is provided for both sensing methods.
block DiagraM
–
+
–
+
+
1.230V
85mV OV 50k
EA
UV
TO
START-UP
CONTROL
BURST
COMPARATOR
S
R
Q
LOGIC
PWM LATCH
CURRENT
COMPARATOR
0.30V
1.230V
7V
–
+
5.6V UP
4.6V DOWN
1.230V SLOPE
1.230V
ILOOP
FB
ITH
–
+
gm
3
MODE/SYNC
5
FREQ
4
2
INTVCC
8LDO
V-TO-I
OSCV-TO-I
SLOPE
COMPENSATION
BIAS AND
START-UP
CONTROL
VIN
BIAS VREF
IOSC
RLOOP
–
+
–
+
C1
SENSE
10
GND
18717 BD
6
GATE
INTVCC
GND
7
VIN
1.248V
9
RUN
C2
1
0.6V
LTC1871-7
8
18717fd
operaTion
Main Control Loop
The LTC1871-7 is a constant frequency, current mode
controller for DC/DC boost, SEPIC and flyback converter
applications. With the LTC1871-7 the current control loop
can be closed by sensing the voltage drop either across
the power MOSFET switch or across a discrete sense
resistor, as shown in Figure 2.
The nominal operating frequency of the LTC1871-7 is
programmed using a resistor from the FREQ pin to ground
and can be controlled over a 50kHz to 1000kHz range. In
addition, the internal oscillator can be synchronized to
an external clock applied to the MODE/SYNC pin and can
be locked to a frequency between 100% and 130% of its
nominal value. When the MODE/SYNC pin is left open, it
is pulled low by an internal 50k resistor and Burst Mode
operation is enabled. If this pin is taken above 2V or an
external clock is applied, Burst Mode operation is disabled
and the IC operates in continuous mode. With no load (or
an extremely light load), the controller will skip pulses
in order to maintain regulation and prevent excessive
output ripple.
The RUN pin controls whether the IC is enabled or is in a low
current shutdown state. A micropower 1.248V reference
and comparator C2 allow the user to program the supply
voltage at which the IC turns on and off (comparator C2
has 100mV of hysteresis for noise immunity). With the
RUN pin below 1.248V, the chip is off and the input supply
current is typically only 10µA.
An overvoltage comparator OV senses when the FB pin
exceeds the reference voltage by 6.5% and provides a
reset pulse to the main RS latch. Because this RS latch is
reset-dominant, the power MOSFET is actively held off for
the duration of an output overvoltage condition.
The LTC1871-7 can be used either by sensing the volt-
age drop across the power MOSFET or by connecting the
SENSE pin to a conventional shunt resistor in the source
of the power MOSFET, as shown in Figure 2. Sensing the
voltage across the power MOSFET maximizes converter
efficiency and minimizes the component count, but limits
the output voltage to the maximum rating for this pin (36V).
By connecting the SENSE pin to a resistor in the source
of the power MOSFET, the user is able to program output
voltages significantly greater than 36V.
Programming the Operating Mode
For applications where maximizing the efficiency at very
light loads (e.g., <100µA) is a high priority, the current in
the output divider could be decreased to a few microamps
and Burst Mode operation should be applied (i.e., the
MODE/SYNC pin should be connected to ground).
For circuit operation, please refer to the Block Diagram of
the IC and Figure 1. In normal operation, the power MOSFET
is turned on when the oscillator sets the PWM latch and
is turned off when the current comparator C1 resets the
latch. The divided-down output voltage is compared to an
internal 1.230V reference by the error amplifier EA, which
outputs an error signal at the ITH pin. The voltage on the
ITH pin sets the current comparator C1 input threshold.
When the load current increases, a fall in the FB voltage
relative to the reference voltage causes the ITH pin to rise,
which causes the current comparator C1 to trip at a higher
peak inductor current value. The average inductor current
will therefore rise until it equals the load current, thereby
maintaining output regulation.
Figure 2. Using the SENSE Pin On the LTC1871-7
COUT
VSW
VSW
2a. SENSE Pin Connection for
Maximum Efficiency (VSW < 36V)
VOUT
VIN
GND
LD
+
COUT
RS
18717 F02
2b. SENSE Pin Connection for Precise
Control of Peak Current or for VSW > 36V
VOUT
VIN
GND
LD
+
GATE
GND
VIN
SENSE
GATE
GND
VIN
SENSE
LTC1871-7
9
18717fd
operaTion
In applications where fixed frequency operation is more
critical than low current efficiency, or where the lowest
output ripple is desired, pulse-skip mode operation should
be used and the MODE/SYNC pin should be connected
to the INTVCC pin. This allows discontinuous conduction
mode (DCM) operation down to near the limit defined by
the chip’s minimum on-time (about 175ns). Below this
output current level, the converter will begin to skip cycles
in order to maintain output regulation. Figures 3 and 4 show
the light load switching waveforms for Burst Mode and
pulse-skip mode operation for the converter in Figure 1.
Burst Mode Operation
Burst Mode operation is selected by leaving the MODE/
SYNC pin unconnected or by connecting it to ground. In
normal operation, the range on the ITH pin corresponding to
no load to full load is 0.30V to 1.2V. In Burst Mode opera-
tion, if the error amplifier EA drives the ITH voltage below
0.525V, the buffered ITH input to the current comparator
C1 will be clamped at 0.525V (which corresponds to 25%
of maximum load current). The inductor current peak is
then held at approximately 30mV divided by the power
MOSFET RDS(ON). If the ITH pin drops below 0.30V, the
Burst Mode comparator B1 will turn off the power MOSFET
and scale back the quiescent current of the IC to 250µA
(sleep mode). In this condition, the load current will be
supplied by the output capacitor until the ITH voltage rises
above the 50mV hysteresis of the burst comparator. At
light loads, short bursts of switching (where the average
inductor current is 20% of its maximum value) followed
by long periods of sleep will be observed, thereby greatly
improving converter efficiency. Oscilloscope waveforms
illustrating Burst Mode operation are shown in Figure 3.
Pulse-Skip Mode Operation
With the MODE/SYNC pin tied to a DC voltage above 2V,
Burst Mode operation is disabled. The internal, 0.525V
buffered ITH burst clamp is removed, allowing the ITH
pin to directly control the current comparator from no
load to full load. With no load, the ITH pin is driven below
0.30V, the power MOSFET is turned off and sleep mode
is invoked. Oscilloscope waveforms illustrating this mode
of operation are shown in Figure 4.
When an external clock signal drives the MODE/SYNC
pin at a rate faster than the chip’s internal oscillator, the
oscillator will synchronize to it. In this synchronized mode,
Burst Mode operation is disabled. The constant frequency
associated with synchronized operation provides a more
controlled noise spectrum from the converter, at the ex-
pense of overall system efficiency of light loads.
When the oscillator’s internal logic circuitry detects a
synchronizing signal on the MODE/SYNC pin, the in-
ternal oscillator ramp is terminated early and the slope
compensation is increased by approximately 30%. As
a result, in applications requiring synchronization, it is
recommended that the nominal operating frequency of
the IC be programmed to be about 75% of the external
clock frequency. Attempting to synchronize to too high an
Figure 3. LTC1871-7 Burst Mode Operation
(MODE/SYNC = 0V) at Low Output Current
Figure 4. LTC1871-7 Low Output Current Operation with
Burst Mode Operation Disabled (MODE/SYNC = INTVCC)
VOUT
50mV/DIV
IL
5A/DIV
10µs/DIV 18717 F03
MODE/SYNC = 0V
(Burst Mode OPERATION)
VOUT
50mV/DIV
IL
5A/DIV
2µs/DIV 18717 F04
MODE/SYNC = INTVCC
(PULSE SKIP MODE)
LTC1871-7
10
18717fd
external frequency (above 1.3fO) can result in inadequate
slope compensation and possible subharmonic oscillation
(or jitter).
The external clock signal must exceed 2V for at least 25ns,
and should have a maximum duty cycle of 80%, as shown
in Figure 5. The MOSFET turn on will synchronize to the
rising edge of the external clock signal.
Programming the Operating Frequency
The choice of operating frequency and inductor value is
a tradeoff between efficiency and component size. Low
frequency operation improves efficiency by reducing
MOSFET and diode switching losses. However, lower
frequency operation requires more inductance for a given
amount of load current.
The LTC1871-7 uses a constant frequency architecture that
can be programmed over a 50kHz to 1000kHz range with
a single external resistor from the FREQ pin to ground, as
shown in Figure 1. The nominal voltage on the FREQ pin is
0.6V, and the current that flows into the FREQ pin is used
to charge and discharge an internal oscillator capacitor. A
graph for selecting the value of RT for a given operating
frequency is shown in Figure 6.
INTVCC Regulator Bypassing and Operation
An internal, P-channel low dropout voltage regulator
produces the 7V supply which powers the gate driver and
operaTion
logic circuitry within the LTC1871-7, as shown in Figure 7.
The INTVCC regulator can supply up to 50mA and must be
bypassed to ground immediately adjacent to the IC pins
with a minimum of 4.7µF tantalum or ceramic capacitor.
Good bypassing is necessary to supply the high transient
currents required by the MOSFET gate driver.
The LTC1871-7 contains an undervoltage lockout circuit
which protects the external MOSFET from switching at low
gate-to-source voltages. This undervoltage circuit senses
the INTVCC voltage and has a 5.6V rising threshold and a
4.6V falling threshold.
For input voltages that don’t exceed 8V (the absolute
maximum rating for INTVCC is 9V), the internal low dropout
regulator in the LTC1871-7 is redundant and the INTVCC
pin can be shorted directly to the VIN pin. With the INTVCC
pin shorted to VIN, however, the divider that programs the
regulated INTVCC voltage will draw 14µA of current from
the input supply, even in shutdown mode. For applications
that require the lowest shutdown mode input supply cur-
rent, do not connect the INTVCC pin to VIN. Regardless
of whether the INTVCC pin is shorted to VIN or not, it is
always necessary to have the driver circuitry bypassed
with a 4.7µF ceramic capacitor to ground immediately
adjacent to the INTVCC and GND pins.
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
As a result, high input voltage applications in which a
large power MOSFET is being driven at high frequencies
Figure 5. MODE/SYNC Clock Input and Switching
Waveforms for Synchronized Operation
Figure 6. Timing Resistor (RT) Value
18717 F05
2V TO 7V
MODE/
SYNC
GATE
IL
tMIN = 25ns
0.8T
D = 40%
T T = 1/fO
FREQUENCY (kHz)
100
RT (kΩ)
300
1000
18717 F06
10
100
200 1000
900
800700600
500
400
0
LTC1871-7
11
18717fd
operaTion
can cause the LTC1871-7 to exceed its maximum junc-
tion temperature rating. The junction temperature can be
estimated using the following equations:
IQ(TOT) ≈ IQ + f • QG
PIC = VIN • (IQ + f • QG)
TJ = TA + PIC • RTH(JA)
The total quiescent current IQ(TOT) consists of the static
supply current (IQ) and the current required to charge and
discharge the gate of the power MOSFET. The 10-pin MSOP
package has a thermal resistance of RTH(JA) = 120°C/W.
As an example, consider a power supply with VIN =10V.
The switching frequency is 200kHz, and the maximum
ambient temperature is 70°C. The power MOSFET chosen
is the FDS3670(Fairchild), which has a maximum RDS(ON)
of 35mΩ (at room temperature) and a maximum total
gate charge of 80nC (the temperature coefficient of the
gate charge is low).
IQ(TOT) = 600µA + 80nC • 200kHz = 16.6mA
PIC = 10V • 16.6mA = 166mW
TJ = 70°C + 120°C/W • 166mW = 89.9°C
TJRISE = 19.9°C
This demonstrates how significant the gate charge current
can be when compared to the static quiescent current in
the IC.
To prevent the maximum junction temperature from being
exceeded, the input supply current must be checked when
operating in a continuous mode at high VIN. A tradeoff
between the operating frequency and the size of the power
MOSFET may need to be made in order to maintain a
reliable IC junction temperature. Prior to lowering the
operating frequency, however, be sure to check with power
MOSFET manufacturers for their latest-and-greatest low
QG, low RDS(ON) devices. Power MOSFET manufacturing
technologies are continually improving, with newer and
better performance devices being introduced almost yearly.
Output Voltage Programming
The output voltage is set by a resistor divider according
to the following formula:
VO=1.230V •1+R2
R1
The external resistor divider is connected to the output
as shown in Figure 1, allowing remote voltage sensing.
Figure 7. Bypassing the LDO Regulator and Gate Driver Supply
–
+
1.230V
R2 R1
P-CH
7V
DRIVER GATE
CVCC
4.7µF
X5R
CIN
INPUT
SUPPLY
6V TO 30V
GND
PLACE AS CLOSE AS
POSSIBLE TO DEVICE PINS
M1
18717 F07
INTVCC
VIN
GND
LOGIC
6V-RATED
POWER
MOSFET
LTC1871-7
12
18717fd
operaTion
The resistors R1 and R2 are typically chosen so that the
error caused by the current flowing into the FB pin dur-
ing normal operation is less than 1% (this translates to a
maximum value of R1 of about 250k).
Programming Turn-On and Turn-Off Thresholds with
the RUN Pin
The LTC1871-7 contains an independent, micropower
voltage reference and comparator detection circuit that
remains active even when the device is shut down, as
shown in Figure 8. This allows users to accurately program
an input voltage at which the converter will turn on and
off. The falling threshold voltage on the RUN pin is equal
to the internal reference voltage of 1.248V. The compara-
tor has 100mV of hysteresis to increase noise immunity.
The turn-on and turn-off input voltage thresholds are
programmed using a resistor divider according to the
following formulas:
V
IN(OFF) =1.248V •1+R2
R1
V
IN(ON) =1.348V •1+R2
R1
The resistor R1 is typically chosen to be less than 1M.
For applications where the RUN pin is only to be used
as a logic input, the user should be aware of the 7V
Absolute Maximum Rating for this pin! The RUN pin can
be connected to the input voltage through an external 1M
resistor, as shown in Figure 8c, for “always on” operation.
Figure 8b. On/Off Control Using External Logic Figure 8c. External Pull-Up Resistor On
RUN Pin for “Always On” Operation
Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin
–
+
RUN
COMPARATOR
VIN
RUN
R2
R1
INPUT
SUPPLY OPTIONAL
FILTER
CAPACITOR
+
–GND
18717 F8a
BIAS AND
START-UP
CONTROL
1.248V
µPOWER
REFERENCE
6V
–
+
RUN
COMPARATOR
1.248V
18717 F08b
RUN
6V
EXTERNAL
LOGIC CONTROL
–
+
RUN
COMPARATOR
VIN
RUN
R2
1M
INPUT
SUPPLY
+
–GND 1.248V
18717 F08c
6V
LTC1871-7
13
18717fd
applicaTions inForMaTion
Application Circuits
A basic LTC1871-7 application circuit is shown in Figure 9.
External component selection is driven by the characteris-
tics of the load and the input supply. The first topology to
be analyzed will be the boost converter, followed by SEPIC
(single-ended primary inductance converter).
Boost Converter: Duty Cycle Considerations
For a boost converter operating in a continuous conduc-
tion mode (CCM), the duty cycle of the main switch is:
D=VO+V
D– V
IN
VO+V
D
where VD is the forward voltage of the boost diode. For
converters where the input voltage is close to the output
voltage, the duty cycle is low and for converters that develop
a high output voltage from a low voltage input supply,
the duty cycle is high. The maximum output voltage for a
boost converter operating in CCM is:
VO(MAX) =V
IN(MIN)
1– DMAX
( )
– V
D
The maximum duty cycle capability of the LTC1871-7 is
typically 92%. This allows the user to obtain high output
voltages from low input supply voltages.
Boost Converter: The Peak and Average Input Currents
The control circuit in the LTC1871-7 is measuring the input
current typically using a sense resistor in the MOSFET
source, so the output current needs to be reflected back
to the input in order to dimension the power MOSFET
properly. Based on the fact that, ideally, the output power
is equal to the input power, the maximum average input
current is:
IIN(MAX) =IO(MAX)
1– DMAX
The peak input current is :
IIN(PEAK) =1+χ
2
•IO(MAX)
1– DMAX
The maximum duty cycle, DMAX, should be calculated at
minimum VIN.
Figure 9. A High Efficiency 42V, 1.5A Automotive Boost Converter
RUN
ITH
FB
FREQ
MODE/SYNC
SENSE
VIN
INTVCC
GATE
GND
1
2
3
4
5
10
9
8
7
6
LTC1871-7
f = 250kHz
RT
100k
1%
R1
12.4k
1%
R2
412k
1%
R3
1M
CVCC
4.7µF
X5R
RSENSE
0.005Ω
1W
CIN2
10µF
50V
X5R
×2
M1
D1
L1
6.8µH
RC
24k
CC1
2.2nF
CC2
100pF
COUT1
68µF
100V
×2
VIN
8V TO 28V
VOUT
42V
1.5A
GND
18717 F09
+
CIN1*
560µF
50V
+
COUT2
10µF
50V
X5R
×2
CIN1: SANYO 50MV560AXL (*RECOMMENDED FOR LAB EVALUATION
FOR SUPPLY LEAD LENGTHS GREATER THAN A FEW INCHES)
CIN2: TDK C5750X5R1H106M
COUT1: SANYO 100CV68FS
COUT2: TDK C5750X5R1H106M
D1: DIODES INC B360B
L1: COOPER DR127-6R8
M1: SILICONIX/VISHAY Si7370DP
LTC1871-7
14
18717fd
applicaTions inForMaTion
Boost Converter: Ripple Current ∆IL and the ‘χ’ Factor
The constant ‘χ’ in the equation above represents the
percentage peak-to-peak ripple current in the inductor,
relative to its maximum value. For example, if 30% ripple
current is chosen, then χ = 0.30, and the peak current is
15% greater than the average.
For a current mode boost regulator operating in CCM,
slope compensation must be added for duty cycles above
50% in order to avoid subharmonic oscillation. For the
LTC1871-7, this ramp compensation is internal. Having an
internally fixed ramp compensation waveform, however,
does place some constraints on the value of the inductor
and the operating frequency. If too large an inductor is
used, the resulting current ramp (∆IL) will be small relative
to the internal ramp compensation (at duty cycles above
50%), and the converter operation will approach voltage
mode (ramp compensation reduces the gain of the current
loop). If too small an inductor is used, but the converter
is still operating in CCM (near critical conduction mode),
the internal ramp compensation may be inadequate to
prevent subharmonic oscillation. To ensure good current
mode gain and avoid subharmonic oscillation, it is recom-
mended that the ripple current in the inductor fall in the
range of 20% to 40% of the maximum average current.
For example, if the maximum average input current is
1A, choose a ∆IL between 0.2A and 0.4A, and a value ‘χ’
between 0.2 and 0.4.
Boost Converter: Inductor Selection
Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
the inductor value can be determined using the following
equation:
L=
V
IN(MIN)
∆IL•f•DMAX
where :
∆IL= χ •IO(MAX)
1– DMAX
Remember that boost converters are not short-circuit
protected. Under a shorted output condition, the inductor
current is limited only by the input supply capability. For
applications requiring a step-up converter that is short-
circuit protected, please refer to the applications section
covering SEPIC converters.
The minimum required saturation current of the inductor
can be expressed as a function of the duty cycle and the
load current, as follows:
IL(SAT) ≥1+χ
2
•IO(MAX)
1– DMAX
The saturation current rating for the inductor should be
checked at the minimum input voltage (which results in
the highest inductor current) and maximum output current.
Boost Converter: Operating in Discontinuous Mode
Discontinuous mode operation occurs when the load cur-
rent is low enough to allow the inductor current to run out
during the off-time of the switch, as shown in Figure 10.
Once the inductor current is near zero, the switch and
diode capacitances resonate with the inductance to form
damped ringing at 1MHz to 10MHz. If the off-time is long
enough, the drain voltage will settle to the input voltage.
Depending on the input voltage and the residual energy
in the inductor, this ringing can cause the drain of the
power MOSFET to go below ground where it is clamped
by the body diode. This ringing is not harmful to the IC
and it has not been shown to contribute significantly to
EMI. Any attempt to damp it with a snubber will degrade
the efficiency.
Figure 10. Discontinuous Mode Waveforms
for the Converter Shown in Figure 9
OUTPUT
VOLTAGE
200mV/DIV
INDUCTOR
CURRENT
1A/DIV
1µs/DIV 18717 F10
MOSFET
DRAIN
VOLTAGE
20V/DIV
LTC1871-7
15
18717fd
applicaTions inForMaTion
Sense Resistor Selection
During the switch on-time, the control circuit limits the
maximum voltage drop across the sense resistor to about
150mV (at low duty cycle). The peak inductor current
is therefore limited to 150mV/RSENSE. The relationship
between the maximum load current, duty cycle and the
sense resistor RSENSE is:
RSENSE ≤VSENSE(MAX) •1– DMAX
1+χ
2
•IO(MAX)
The VSENSE(MAX) term is typically 150mV at low duty cycle,
and is reduced to about 100mV at a duty cycle of 92% due
to slope compensation, as shown in Figure 11.
It is worth noting that the 1 – DMAX relationship between
IO(MAX) and RSENSE can cause boost converters with a wide
input range to experience a dramatic range of maximum
input and output current. This should be taken into con-
sideration in applications where it is important to limit the
maximum current drawn from the input supply.
Figure 11. Maximum SENSE Threshold Voltage vs Duty Cycle
Boost Converter: Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-to-source breakdown voltage (BVDSS), the threshold
voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gate-
to-source voltage, the gate-to-source and gate-to-drain
charges (QGS and QGD, respectively), the maximum drain
current (ID(MAX)) and the MOSFET’s thermal resistances
(RTH(JC) and RTH(JA)).
The gate drive voltage is set by the 7V INTVCC low drop
regulator. Consequently, 6V rated MOSFETs are required
in most high voltage LTC1871-7 applications.
Pay close attention to the BVDSS specifications for the
MOSFETs relative to the maximum actual switch voltage
in the application. The switch node can ring during the
turn-off of the MOSFET due to layout parasitics. Check
the switching waveforms of the MOSFET directly across
the drain and source terminals using the actual PC board
layout (not just on a lab breadboard!) for excessive ringing.
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the power
MOSFET, the power dissipated by the device must be known.
This power dissipation is a function of the duty cycle, the
load current and the junction temperature itself (due to
the positive temperature coefficient of its RDS(ON)). As a
result, some iterative calculation is normally required to
determine a reasonably accurate value. Care should be
taken to ensure that the converter is capable of delivering
the required load current over all operating conditions (line
voltage and temperature), and for the worst-case speci-
fications for VSENSE(MAX) and the RDS(ON) of the MOSFET
listed in the manufacturer’s data sheet.
The power dissipated by the MOSFET in a boost converter
is:
PFET =IO(MAX)
1– D
2
•RDS(ON) •D•ρT
+k•VO2•IO(MAX)
1– D
( )
•CRSS •f
The first term in the equation above represents the I2R
losses in the device, and the second term, the switching
losses. The constant, k = 1.7, is an empirical factor inversely
related to the gate drive current and has the dimension
of 1/current. The ρT term accounts for the temperature
coefficient of the RDS(ON) of the MOSFET, which is typically
0.4%/°C. Figure 12 illustrates the variation of normalized
RDS(ON) over temperature for a typical power MOSFET.
DUTY CYCLE
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
100
150
0.8
18717 F11
50
00.2 0.4 0.5 1.0
200
LTC1871-7
16
18717fd
applicaTions inForMaTion
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
TJ = TA + PFET • RTH(JA)
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the case to the ambient temperature (RTH(CA)). This value
of TJ can then be compared to the original, assumed value
used in the iterative calculation process.
Boost Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desired. The output
diode in a boost converter conducts current during the
switch off-time. The peak reverse voltage that the diode
must withstand is equal to the regulator output voltage.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to the
peak inductor current.
ID(PEAK) =IL(PEAK) =1+χ
2
•IO(MAX)
1– DMAX
The power dissipated by the diode is:
PD = IO(MAX) • VD
and the diode junction temperature is:
TJ = TA + PD • RTH(JA)
Figure 12. Normalized RDS(ON) vs Temperature
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
Remember to keep the diode lead lengths short and to
observe proper switch-node layout (see Board Layout
Checklist) to avoid excessive ringing and increased dis-
sipation.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct component
for a given output ripple voltage. The effects of these three
parameters (ESR, ESL and bulk C) on the output voltage
ripple waveform are illustrated in Figure 13 for a typical
boost converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ∆V.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging ∆V. This percentage
ripple will change, depending on the requirements of the
application, and the equations provided below can easily
be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
ESRCOUT ≤0.01•VO
IIN(PEAK)
where:
IIN(PEAK)=1+χ
2
•
I
O(MAX)
1– DMAX
For the bulk C component, which also contributes 1% to
the total ripple:
COUT ≥IO(MAX)
0.01•VO•f
JUNCTION TEMPERATURE (°C)
–50
ρT NORMALIZED ON RESISTANCE
1.0
1.5
150
18717 F12
0.5
0050 100
2.0
LTC1871-7
17
18717fd
applicaTions inForMaTion
For some designs it may be possible to choose a single
capacitor type that satisfies both the ESR and bulk C require-
ments for the design. In certain demanding applications,
however, the ripple voltage can be improved significantly
by connecting two or more types of capacitors in paral-
lel. For example, using a low ESR ceramic capacitor can
minimize the ESR step, while an electrolytic capacitor can
be used to supply the required bulk C.
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on a dedicated PC board (see Board
Layout section for more information on component place-
ment). Lab breadboards generally suffer from excessive
series inductance (due to inter-component wiring), and
these parasitics can make the switching waveforms look
significantly worse than they would be on a properly
designed PC board.
The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 13. The RMS
output capacitor ripple current is:
IRMS(COUT) ≈IO(MAX) •VO– VIN(MIN)
VIN(MIN)
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
In surface mount applications, multiple capacitors may
have to be placed in parallel in order to meet the ESR or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount packages. In the case of
tantalum, it is critical that the capacitors have been surge
tested for use in switching power supplies. Also, ceramic
capacitors are now available with extremely low ESR, ESL
and high ripple current ratings.
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input and the input current waveform
is continuous (see Figure 13b). The input voltage source
impedance determines the size of the input capacitor,
which is typically in the range of 10µF to 100µF. A low ESR
capacitor is recommended, although it is not as critical as
for the output capacitor.
The RMS input capacitor ripple current for a boost con-
verter is:
IRMS(CIN) =0.3 •V
IN(MIN)
L•f•DMAX
Figure 13. Switching Waveforms for a Boost Converter
VIN
L D
SW
13a. Circuit Diagram
13b. Inductor and Input Currents
COUT
VOUT
RL
IIN
IL
13c. Switch Current
ISW
tON
13d. Diode and Output Currents
13e. Output Voltage Ripple Waveform
IO
18717 F13
ID
VOUT
(AC)
tOFF
ΔVESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
ΔVCOUT
LTC1871-7
18
18717fd
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to
the input of the converter and solid tantalum capacitors
can fail catastrophically under these conditions. Be sure
to specify surge-tested capacitors!
Burst Mode Operation and Considerations
The choice of sense resistor and inductor value also deter-
mines the load current at which the LTC1871-7 enters Burst
Mode operation. When bursting, the controller clamps the
peak inductor current to approximately:
IBURST(PEAK) =
30mV
RSENSE
which represents about 20% of the maximum 150mV
SENSE pin voltage. The corresponding average current
depends upon the amount of ripple current. Lower inductor
values (higher ∆IL) will reduce the load current at which
Burst Mode operations begins, since it is the peak current
that is being clamped.
The output voltage ripple can increase during Burst
Mode operation if ∆IL is substantially less than IBURST.
This can occur if the input voltage is very low or if a very
large inductor is chosen. At high duty cycles, a skipped
cycle causes the inductor current to quickly decay to
zero. However, because ∆IL is small, it takes multiple
cycles for the current to ramp back up to IBURST(PEAK).
Table 1. Recommended Component Manufacturers
VENDOR COMPONENTS TELEPHONE WEB ADDRESS
AVX Capacitors (207) 282-5111 avxcorp.com
BH Electronics Inductors, Transformers (952) 894-9590 bhelectronics.com
Coilcraft Inductors (847) 639-6400 coilcraft.com
Coiltronics Inductors (407) 241-7876 coiltronics.com
Diodes, Inc Diodes (805) 446-4800 diodes.com
Fairchild MOSFETs (408) 822-2126 fairchildsemi.com
General Semiconductor Diodes (516) 847-3000 generalsemiconductor.com
International Rectifier MOSFETs, Diodes (310) 322-3331 irf.com
IRC Sense Resistors (361) 992-7900 irctt.com
Kemet Tantalum Capacitors (408) 986-0424 kemet.com
Magnetics Inc Toroid Cores (800) 245-3984 mag-inc.com
Microsemi Diodes (617) 926-0404 microsemi.com
Murata-Erie Inductors, Capacitors (770) 436-1300 murata.co.jp
Nichicon Capacitors (847) 843-7500 nichicon.com
On Semiconductor Diodes (602) 244-6600 onsemi.com
Panasonic Capacitors (714) 373-7334 panasonic.com
Sanyo Capacitors (619) 661-6835 sanyo.co.jp
Sumida Inductors (847) 956-0667 sumida.com
Taiyo Yuden Capacitors (408) 573-4150 t-yuden.com
TDK Capacitors, Inductors (562) 596-1212 component.tdk.com
Thermalloy Heat Sinks (972) 243-4321 aavidthermalloy.com
Tokin Capacitors (408) 432-8020 nec-tokinamerica.com
Toko Inductors (847) 699-3430 tokoam.com
United Chemicon Capacitors (847) 696-2000 chemi-com.com
Vishay/Dale Resistors (605) 665-9301 vishay.com
Vishay/Siliconix MOSFETs (800) 554-5565 vishay.com
Vishay/Sprague Capacitors (207) 324-4140 vishay.com
Zetex Small-Signal Discretes (631) 543-7100 zetex.com
applicaTions inForMaTion
LTC1871-7
19
18717fd
applicaTions inForMaTion
During this inductor charging interval, the output capacitor
must supply the load current and a significant droop in
the output voltage can occur. Generally, it is a good idea
to choose a value of inductor ∆IL between 25% and 40%
of IIN(MAX). The alternative is to either increase the value
of the output capacitor or disable Burst Mode operation
using the MODE/SYNC pin.
Burst Mode operation can be defeated by connecting the
MODE/SYNC pin to a high logic-level voltage (either with
a control input or by connecting this pin to INTVCC). In
this mode, the burst clamp is removed, and the chip can
operate at constant frequency from continuous conduction
mode (CCM) at full load, down into deep discontinuous
conduction mode (DCM) at light load. Prior to skipping
pulses at very light load (i.e., <5% of full load), the control-
ler will operate with a minimum switch on-time in DCM.
Pulse skipping prevents a loss of control of the output at
very light loads and reduces output voltage ripple.
Efficiency Considerations
The efficiency of a switching regulator is equal to the out-
put power divided by the input power (¥100%). Percent
efficiency can be expressed as:
% Efficiency = 100% – (L1 + L2 + L3 + …),
where L1, L2, etc. are the individual loss components as a
percentage of the input power. It is often useful to analyze
individual losses to determine what is limiting the efficiency
and which change would produce the most improvement.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for the majority
of the losses in LTC1871-7 application circuits:
1. The supply current into VIN. The VIN current is the sum
of the DC supply current IQ (given in the Electrical Char-
acteristics) and the MOSFET driver and control currents.
The DC supply current into the VIN pin is typically about
650µA and represents a small power loss (much less
than 1%) that increases with VIN. The driver current
results from switching the gate capacitance of the power
MOSFET; this current is typically much larger than the
DC current. Each time the MOSFET is switched on and
then off, a packet of gate charge QG is transferred from
INTVCC to ground. The resulting dQ/dt is a current that
must be supplied to the INTVCC capacitor through the
VIN pin by an external supply. If the IC is operating in
CCM:
IQ(TOT) ≈ IQ = f • QG
PIC = VIN • (IQ + f • QG)
2. Power MOSFET switching and conduction losses:
P
FET =IO(MAX)
1– DMAX
2
•RDS(ON) •DMAX •ρT
+k•VO2•IO(MAX)
1– D
MAX
•CRSS •f
3. The I2R losses in the sense resistor can be calculated
almost by inspection.
PR(SENSE) =IO(MAX)
1– DMAX
2
•RSENSE •DMAX
4. The losses in the inductor are simply the DC input cur-
rent squared times the winding resistance. Expressing
this loss as a function of the output current yields:
PR(WINDING) =IO(MAX)
1– DMAX
2
•RW
5. Losses in the boost diode. The power dissipation in the
boost diode is:
PDIODE = IO(MAX) • VD
The boost diode can be a major source of power loss
in a boost converter. For 13.2V input, 42V output at
1.5A example given in Figure 9, a Schottky diode with
a 0.4V forward voltage would dissipate 600mW, which
represents about 1% of the input power. Diode losses
can become significant at low output voltages where
the forward voltage is a significant percentage of the
output voltage.
6. Other losses, including CIN and CO ESR dissipation and
inductor core losses, generally account for less than
2% of the total losses.
LTC1871-7
20
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Checking Transient Response
The regulator loop response can be verified by looking at
the load transient response at minimum and maximum
VIN. Switching regulators generally take several cycles to
respond to an instantaneous step in resistive load current.
When the load step occurs, VO immediately shifts by an
amount equal to (∆ILOAD)(ESR), and then CO begins to
charge or discharge (depending on the direction of the load
step) as shown in Figure 14. The regulator feedback loop
acts on the resulting error amp output signal to return VO
to its steady-state value. During this recovery time, VO can
be monitored for overshoot or ringing that would indicate
a stability problem.
A second, more severe transient can occur when con-
necting loads with large (>1µF) supply bypass capacitors.
The discharged bypass capacitors are effectively put in
parallel with CO, causing a nearly instantaneous drop in
VO. No regulator can deliver enough current to prevent
this problem if the load switch resistance is low and it is
driven quickly. The only solution is to limit the rise time
of the switch drive in order to limit the inrush current di/
dt to the load.
Boost Converter Design Example
The design example given here will be for the circuit shown
in Figure 9. The input voltage is 8V to 28V, and the output
is 42V at a maximum load current of 1.5A.
1. The maximum duty cycle is:
D=VO+V
D– V
IN
VO+V
D
=42 +0.4 – 8
42 +0.4 =81.1%
2. Pulse-skip operation is chosen so the MODE/SYNC pin
is shorted to INTVCC.
3. The operating frequency is chosen to be 250kHz to
reduce the size of the inductor. From Figure 5, the
resistor from the FREQ pin to ground is 100k.
4. An inductor ripple current of 40% of the maximum load
current is chosen, so the peak input current (which is
also the minimum saturation current) is:
IIN(PEAK) =1+χ
2
•
I
O(MAX)
1– DMAX
=1.2 •1.5
1– 0.81=9.47A
The inductor ripple current is:
∆IL= χ •IO(MAX)
1– DMAX
=0.4 •1.5
1– 0.81 =3.2A
And so the inductor value is:
L=
V
IN(MIN)
∆IL•f•DMAX
=8
3.2 •250k •0.81=8.1µH
Figure 14a. Load Transient Response for the Circuit in Figure 9
Figure 14b. Load Transient Response for the Circuit in Figure 9
VOUT
500mV/DIV
IOUT
0.5A/DIV
0.5A
250µs/DIV 18717 F14a
1.5A
VIN = 8V
VOUT
500mV/DIV
IOUT
0.5A/DIV
0.5A
250µs/DIV 18717 F14b
1.5A
VIN = 28V
LTC1871-7
21
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The component chosen is a 6.8µH inductor made by
Cooper (part number DR127-6R8) which has a satura-
tion current of greater than 13.3A.
5. Because the duty cycle is 81%, the maximum SENSE
pin threshold voltage is reduced from its low duty cycle
typical value of 150mV to approximately 115mV. In ad-
dition, we need to apply a worst-case derating factor
to this SENSE threshold to account for manufacturing
tolerances within the IC. Finally, the nominal current
limit value should exceed the maximum load current
by some safety margin (in this case 50%). Therefore,
the value of the sense resistor is:
RSENSE =0.8 •VSENSE(MAX) •
1– D
MAX
1+0.4
2
•1.5 •IO(MAX)
=0.8 •0.115 •1– 0.81
1.2 •1.5 •1.5
=6.5mΩ
A 1W, 5mΩ resistor is used in this design.
6. The MOSFET chosen is a Vishay/Siliconix Si7370DP,
which has a BVDSS of greater than 60V and an RDS(ON)
of less than 13mΩ at a VGS of 6V.
7. The diode for this design must handle a maximum DC
output current of 1.5A and be rated for a minimum
reverse voltage of VOUT, or 42V. A 3A, 60V diode from
Diodes Inc. (B360B) is chosen.
8. The output capacitor usually consists of a high valued
bulk C connected in parallel with a lower valued, low
ESR ceramic. Based on a maximum output ripple voltage
of 1%, or 50mV, the bulk C needs to be greater than:
COUT ≥IOUT(MAX)
0.01•VOUT •f=1.5
0.01•42 •250k =14µF
The RMS ripple current rating for this capacitor needs
to exceed:
IRMS(COUT) ≥IO(MAX) •VO– V
IN(MIN)
V
IN(MIN)
=
1.5 •42 – 8
8=3.09A
T
o satisfy the low ESR, high frequency decoupling
requirements, two 10µF, 50V, X5R ceramic capacitors
are used (TDK part number C5750X5R1H106M). In
parallel with these, two 68µF, 100V electrolytic ca-
pacitors are used (Sanyo part number 100CV68FS).
Check the output ripple with a single oscilloscope
probe connected directly across the output capacitor
terminals, where the HF switching currents flow.
9.
The choice of an input capacitor for a boost converter
depends on the impedance of the source supply and
the amount of input ripple the converter will safely
tolerate. For this particular design and lab setup a
560µF, 50V Sanyo electrolytic (50MV560AXL), in
parallel with two 10µF, 100V TDK ceramic capacitors
(C5750X5R1H106M) is required (the input and return
lead lengths are kept to a few inches, but the peak input
current is close to 10A!). As with the output node,
check the input ripple with a single oscilloscope probe
connected across the input capacitor terminals.
Figure 15. Switching Waveforms for the Converter
in Figure 9 at Minimum VIN (8V)
VOUT
1V/DIV
IL
2A/DIV
MOSFET
DRAIN
VOLTAGE
20V/DIV
1µs/DIV 18717 F15
VIN = 8V
IOUT = 0.5A
VOUT = 42V
D = 81%
LTC1871-7
22
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PC Board Layout Checklist
1. In order to minimize switching noise and improve
output load regulation, the GND pin of the LTC1871-7
should be connected directly to 1) the negative terminal
of the INTVCC decoupling capacitor, 2) the negative
terminal of the output decoupling capacitors, 3) the
bottom terminal of the sense resistor, 4) the negative
terminal of the input capacitor and 5) at least one via
to the ground plane immediately adjacent to Pin 6. The
ground trace on the top layer of the PC board should
be as wide and short as possible to minimize series
resistance and inductance.
2. Beware of ground loops in multiple layer PC boards.
Try to maintain one central ground node on the board
and use the input capacitor to avoid excess input ripple
for high output current power supplies. If the ground
plane is to be used for high DC currents, choose a path
away from the small-signal components.
3. Place the CVCC capacitor immediately adjacent to the
INTVCC and GND pins on the IC package. This capacitor
carries high di/dt MOSFET gate drive currents. A low
ESR and ESL 4.7µF ceramic capacitor works well here.
4. The high di/dt loop from the bottom terminal of the
output capacitor, through the power MOSFET, through
the boost diode and back through the output capacitors
should be kept as tight as possible to reduce inductive
ringing. Excess inductance can cause increased stress
on the power MOSFET and increase HF noise on the
output. If low ESR ceramic capacitors are used on the
output to reduce output noise, place these capacitors
close to the boost diode in order to keep the series
inductance to a minimum.
5. Check the stress on the power MOSFET by measuring
its drain-to-source voltage directly across the device
terminals (reference the ground of a single scope probe
directly to the source pad on the PC board). Beware
of inductive ringing which can exceed the maximum
specified voltage rating of the MOSFET. If this ringing
cannot be avoided and exceeds the maximum rating
of the device, either choose a higher voltage device
or specify an avalanche-rated power MOSFET. Not all
MOSFETs are created equal (some are more equal than
others).
6. Place the small-signal components away from high
frequency switching nodes. In the layout shown in
Figure 18, all of the small-signal components have
been placed on one side of the IC and all of the power
components have been placed on the other. This also
allows the use of a pseudo-Kelvin connection for the
signal ground, where high di/dt gate driver currents
flow out of the IC ground pin in one direction (to the
bottom plate of the INTVCC decoupling capacitor) and
small-signal currents flow in the other direction.
Figure 16. Switching Waveforms for the
Converter in Figure 9 at Maximum VIN (28V)
Figure 17. Efficiency vs Load Current and Input Voltage
for the Converter in Figure 9
VOUT
1V/DIV
IL
1A/DIV
MOSFET
DRAIN
VOLTAGE
20V/DIV
1µs/DIV 18717 F16
VIN = 28V
IOUT = 0.5A
VOUT = 42V
D = 27%
ILOAD (mA)
80
EFFICIENCY (%)
85
90
95
100
0.001 0.1 1 10
18717 F17
75
0.01
VIN = 8V
VIN = 12V
VIN = 28V
LTC1871-7
23
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applicaTions inForMaTion
7. Minimize the capacitance between the SENSE pin
trace and any high frequency switching nodes. The
LTC1871-7 contains an internal leading edge blanking
time of approximately 180ns, which should be adequate
for most applications.
8. For optimum load regulation and true remote sensing,
the top of the output resistor divider should connect
independently to the top of the output capacitor (Kelvin
connection), staying away from any high dV/dt traces.
Place the divider resistors near the LTC1871-7 in order
to keep the high impedance FB node short.
Figure 18. LTC1871-7 Boost Converter Suggested Layout
Figure 19. LTC1871-7 Boost Converter Layout Diagram
LTC1871-7
M1
VIN
1871 F18
VOUT
SWITCH NODE IS ALSO
THE HEAT SPREADER
FOR L1, M1, D1
L1
RT
RS
RCCC
R3
J1
CIN
COUT
CVCC
R1
R2
PSEUDO-KELVIN
SIGNAL GROUND
CONNECTION
TRUE REMOTE
OUTPUT SENSING
VIAS TO GROUND
PLANE
R4
PIN 1
COUT
JUMPER
D1
RUN
ITH
FB
FREQ
MODE/
SYNC
SENSE
VIN
INTVCC
GATE
GND
LTC1871-7
+
R4
J1
10
9
8
7
6
1
2
3
4
5
CVCC
PSEUDO-KELVIN
GROUND CONNECTION
CIN
M1
D1
L1
VIN
GND
18717 F19
VOUT
SWITCH
NODE
COUT
RC
RS
R1
RT
BOLD LINES INDICATE HIGH CURRENT PATHS
R2
CC
R3
+
LTC1871-7
24
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applicaTions inForMaTion
9. For applications with multiple switching power convert-
ers connected to the same input supply, make sure
that the input filter capacitor for the LTC1871-7 is not
shared with other converters. AC input current from
another converter could cause substantial input volt-
age ripple, and this could interfere with the operation
of the LTC1871-7. A few inches of PC trace or wire (L
≈ 100nH) between the CIN of the LTC1871-7 and the
actual source VIN should be sufficient to prevent current
sharing problems.
SEPIC Converter Applications
The LTC1871-7 is also well suited to SEPIC (single-ended
primary inductance converter) converter applications. The
SEPIC converter shown in Figure 20 uses two inductors.
The advantage of the SEPIC converter is the input voltage
may be higher or lower than the output voltage, and the
output is short-circuit protected.
The first inductor, L1, together with the main switch,
resembles a boost converter. The second inductor, L2,
together with the output diode D1, resembles a flyback or
buck-boost converter. The two inductors L1 and L2 can be
independent but can also be wound on the same core since
identical voltages are applied to L1 and L2 throughout the
switching cycle. By making L1 = L2 and winding them on
the same core the input ripple is reduced along with cost
and size. All of the SEPIC applications information that
follows assumes L1 = L2 = L.
SEPIC Converter: Duty Cycle Considerations
For a SEPIC converter operating in a continuous conduc-
tion mode (CCM), the duty cycle of the main switch is:
D=VO+V
D
V
IN +VO+V
D
where VD is the forward voltage of the diode. For convert-
ers where the input voltage is close to the output voltage
the duty cycle is near 50%.
Figure 20. SEPIC Topology and Current Flow Figure 21. SEPIC Converter Switching Waveforms
+
+
+
•
•
•
•
SW L2 COUT RL
VOUT
VIN
C1 D1
L1
20a. SEPIC Topology
+
+
+
•
RL
VOUT
18717 F20
VIN
D1
20c. Current Flow During Switch Off-Time
+
+
+
•
RL
VOUT
VIN
VIN
VIN
20b. Current Flow During Switch On-Time
21a. Input Inductor Current
IIN
IL1 SW
ON
SW
OFF
21b. Output Inductor Current
IO
IL2
21c. DC Coupling Capacitor Current
IO
IIN
IC1
21e. Output Ripple Voltage
VOUT
(AC)
ΔVESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
ΔVCOUT
21d. Diode Current
IO
18717 F21
ID1
LTC1871-7
25
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The maximum output voltage for a SEPIC converter is:
VO(MAX) =V
IN +V
D
( )
DMAX
1– DMAX
– V
D
1
1– DMAX
The maximum duty cycle of the LTC1871-7 is typically 92%.
SEPIC Converter: The Peak and Average
Input Currents
The control circuit in the LTC1871-7 is measuring the input
current (using a sense resistor in the MOSFET source),
so the output current needs to be reflected back to the
input in order to dimension the power MOSFET properly.
Based on the fact that, ideally, the output power is equal
to the input power, the maximum input current for a SEPIC
converter is:
IIN(MAX) =IO(MAX) •DMAX
1– DMAX
The peak input current is :
IIN(PEAK) =1+χ
2
•IO(MAX) •DMAX
1– DMAX
The maximum duty cycle, DMAX, should be calculated at
minimum VIN.
The constant ‘χ’ represents the fraction of ripple current in
the inductor relative to its maximum value. For example, if
30% ripple current is chosen, then χ = 0.30 and the peak
current is 15% greater than the average.
It is worth noting here that SEPIC converters that operate
at high duty cycles (i.e., that develop a high output voltage
from a low input voltage) can have very high input currents,
relative to the output current. Be sure to check that the
maximum load current will not overload the input supply.
SEPIC Converter: Inductor Selection
For most SEPIC applications the equal inductor values
will fall in the range of 10µH to 100µH. Higher values will
reduce the input ripple voltage and reduce the core loss.
Lower inductor values are chosen to reduce physical size
and improve transient response.
Like the boost converter, the input current of the SEPIC
converter is calculated at full load current and minimum
input voltage. The peak inductor current can be significantly
higher than the output current, especially with smaller in-
ductors and lighter loads. The following formulas assume
CCM operation and calculate the maximum peak inductor
currents at minimum VIN:
IL1(PEAK) =1+χ
2
•IO(MAX) •VO+V
D
V
IN(MIN)
IL2(PEAK) =1+χ
2
•IO(MAX) •V
IN(MIN) +V
D
V
IN(MIN)
The ripple current in the inductor is typically 20% to 40%
(i.e., a range of ‘χ’ from 0.20 to 0.40) of the maximum
average input current occurring at VIN(MIN) and IO(MAX) and
∆IL1 = ∆IL2. Expressing this ripple current as a function of
the output current results in the following equations for
calculating the inductor value:
L=V
IN(MIN)
∆IL•f•DMAX
where
∆IL= χ •IO(MAX) •DMAX
1– DMAX
By making L1 = L2 and winding them on the same core,
the value of inductance in the equation above is replace
by 2L due to mutual inductance. Doing this maintains the
same ripple current and energy storage in the inductors. For
example, a Coiltronix CTX10-4 is a 10µH inductor with two
windings. With the windings in parallel, 10µH inductance
is obtained with a current rating of 4A (the number of
turns hasn’t changed, but the wire diameter has doubled).
Splitting the two windings creates two 10µH inductors
with a current rating of 2A each. Therefore, substituting
2L yields the following equation for coupled inductors:
L1=L2 =V
IN(MIN)
2•∆IL•f•DMAX
Specify the maximum inductor current to safely handle
IL(PK) specified in the equation above. The saturation current
LTC1871-7
26
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rating for the inductor should be checked at the minimum
input voltage (which results in the highest inductor cur-
rent) and maximum output current.
SEPIC Converter: Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-to-source breakdown voltage (BVDSS), the threshold
voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gate-
to-source voltage, the gate-to-source and gate-to-drain
charges (QGS and QGD, respectively), the maximum drain
current (ID(MAX)) and the MOSFET’s thermal resistances
(RTH(JC) and RTH(JA)).
The gate drive voltage is set by the 7V INTVCC low dropout
regulator. Consequently, 6V rated threshold MOSFETs are
required in most LTC1871-7 applications.
The maximum voltage that the MOSFET switch must
sustain during the off-time in a SEPIC converter is equal
to the sum of the input and output voltages (VO + VIN).
As a result, careful attention must be paid to the BVDSS
specifications for the MOSFETs relative to the maximum
actual switch voltage in the application. Many logic-level
devices are limited to 30V or less. Check the switching
waveforms directly across the drain and source terminals
of the power MOSFET to ensure the VDS remains below
the maximum rating for the device.
Sense Resistor Selection
During the MOSFET’s on-time, the control circuit limits
the maximum voltage drop across the power MOSFET to
about 150mV (at low duty cycle). The peak inductor cur-
rent is therefore limited to 150mV/RSENSE. The relationship
between the maximum load current, duty cycle and the
sense resistor is:
RSENSE ≤VSENSE(MAX)
IO(MAX)
•1
1+χ
2
•1
VO+V
D
V
IN(MIN)
+1
The VSENSE(MAX) term is typically 150mV at low duty
cycle and is reduced to about 100mV at a duty cycle of
92% due to slope compensation, as shown in Figure 11.
The constant ‘χ’ in the denominator represents the ripple
current in the inductors relative to their maximum current.
For example, if 30% ripple current is chosen, then χ = 0.30.
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the
power MOSFET, the power dissipated by the device must
be known. This power dissipation is a function of the
duty cycle, the load current and the junction temperature
itself. As a result, some iterative calculation is normally
required to determine a reasonably accurate value. Since
the controller is using the MOSFET as both a switching
and a sensing element, care should be taken to ensure
that the converter is capable of delivering the required
load current over all operating conditions (load, line and
temperature) and for the worst-case specifications for
VSENSE(MAX) and the RDS(ON) of the MOSFET listed in the
manufacturer’s data sheet.
The power dissipated by the MOSFET in a SEPIC converter
is:
P
FET =IO(MAX) •D
1– D
2
•RDS(ON) •D•ρT
+k•V
IN +VO
( )
2•IO(MAX) •D
1– D
•CRSS •f
The first term in the equation above represents the I2R
losses in the device and the second term, the switching
losses. The constant k = 1.7 is an empirical factor inversely
related to the gate drive current and has the dimension
of 1/current.
The ρT term accounts for the temperature coefficient of
the RDS(ON) of the MOSFET, which is typically 0.4%/°C.
Figure
12 illustrates the variation of normalized RDS(ON)
over temperature for a typical power MOSFET.
LTC1871-7
27
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From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
TJ = TA + PFET • RTH(JA)
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
This value of TJ can then be used to check the original
assumption for the junction temperature in the iterative
calculation process.
SEPIC Converter: Output Diode Selection
To maximize efficiency, a fast-switching diode with low
forward drop and low reverse leakage is desired. The output
diode in a SEPIC converter conducts current during the
switch off-time. The peak reverse voltage that the diode
must withstand is equal to VIN(MAX) + VO. The average
forward current in normal operation is equal to the output
current, and the peak current is equal to:
ID(PEAK) =1+χ
2
•IO(MAX) •VO+VD
VIN(MIN)
+1
The power dissipated by the diode is:
PD = IO(MAX) • VD
and the diode junction temperature is:
TJ = TA + PD • RTH(JA)
The RTH(JA) to be used in this equation normally includes
the RTH(JC) for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
SEPIC Converter: Output Capacitor Selection
Because of the improved performance of today’s electro-
lytic, tantalum and ceramic capacitors, engineers need
to consider the contributions of ESR (equivalent series
resistance), ESL (equivalent series inductance) and the
bulk capacitance when choosing the correct component
for a given output ripple voltage. The effects of these three
parameters (ESR, ESL, and bulk C) on the output voltage
ripple waveform are illustrated in Figure 21 for a typical
coupled-inductor SEPIC converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging ∆V.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging ∆V. This percentage
ripple will change, depending on the requirements of the
application, and the equations provided below can easily
be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
ESRCOUT ≤0.01•VO
ID(PEAK)
where:
ID(PEAK) =1+χ
2
•IO(MAX) •VO+VD
VIN(MIN)
+1
For the bulk C component, which also contributes 1% to
the total ripple:
COUT ≥IO(MAX)
0.01•VO•f
For many designs it is possible to choose a single capacitor
type that satisfies both the ESR and bulk C requirements
for the design. In certain demanding applications, however,
the ripple voltage can be improved significantly by con-
necting two or more types of capacitors in parallel. For
example, using a low ESR ceramic capacitor can minimize
the ESR step, while an electrolytic or tantalum capacitor
can be used to supply the required bulk C.
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
LTC1871-7
28
18717fd
should be verified on a dedicated PC board (see Board
Layout section for more information on component place-
ment). Lab breadboards generally suffer from excessive
series inductance (due to inter-component wiring), and
these parasitics can make the switching waveforms look
significantly worse than they would be on a properly
designed PC board.
The output capacitor in a SEPIC regulator experiences
high RMS ripple currents, as shown in Figure 21. The
RMS output capacitor ripple current is:
IRMS(COUT) =IO(MAX) •VO
V
IN(MIN)
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
In surface mount applications, multiple capacitors may
have to be placed in parallel in order to meet the ESR or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount packages. In the case of
tantalum, it is critical that the capacitors have been surge
tested for use in switching power supplies. Also, ceramic
capacitors are now available with extremely low ESR, ESL
and high ripple current ratings.
SEPIC Converter: Input Capacitor Selection
The input capacitor of a SEPIC converter is less critical
than the output capacitor due to the fact that an inductor
is in series with the input and the input current waveform
is triangular in shape. The input voltage source impedance
determines the size of the input capacitor which is typi-
cally in the range of 10µF to 100µF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
applicaTions inForMaTion
The RMS input capacitor ripple current for a SEPIC con-
verter is:
IRMS(CIN) =1
12 •∆IL
Please note that the input capacitor can see a very high
surge current when a battery is suddenly connected to
the input of the converter and solid tantalum capacitors
can fail catastrophically under these conditions. Be sure
to specify surge-tested capacitors!
SEPIC Converter: Selecting the DC Coupling Capacitor
The coupling capacitor C1 in Figure 20 sees nearly a rect-
angular current waveform as shown in Figure 21. During
the switch off-time the current through C1 is IO(VO/VIN)
while approximately –IO flows during the on-time. This
current waveform creates a triangular ripple voltage on C1:
∆VC1(P−P) =
I
O(MAX)
C1•f•VO
V
IN +VO+V
D
The maximum voltage on C1 is then:
VC1(MAX) =V
IN +
∆
VC1(P−P)
2
which is typically close to VIN(MAX). The ripple current
through C1 is:
IRMS(C1) =IO(MAX) •VO+V
D
V
IN(MIN)
The value chosen for the DC coupling capacitor normally
starts with the minimum value that will satisfy 1) the RMS
current requirement and 2) the peak voltage requirement
(typically close to VIN). Low ESR ceramic and tantalum
capacitors work well here.
LTC1871-7
29
18717fd
Typical applicaTions
Output Efficiency at 3.3V Output
A 48V Input Flyback Converter Configurable to 3.3V or 5V Outputs
Output Efficiency at 5V Output
9
7
10
8
6
1
2
4
5
3
100k
100k
VIN
36V TO 72V
10V
26.7k
82.5k
12.4k
R2*
21k
*R2 = 38.3k FOR VOUT = 5V
R1
604k
1nF
0.1µF
2.2µF
100V
100µF
6.3V
×3
VOUT
3.3V
3A MAX
T1B
UPS840
CTX-002-15242
T1A
•
•
Q1
FDC2512
ALL CAPACITORS
ARE CERAMIC
X5R TYPE
R3
0.1Ω
4.7µF
18717 TA02a
RUN
ITH
FREQ
MODE/SYNC
VFB
VIN
GATE
SENSE
INTVCC
GND
LTC1871-7
MMBTA42
ILOAD (A)
0
60
EFFICIENCY (%)
65
70
75
80
90
1234
18717 TA02b
5 6
85
36VIN 48VIN
72VIN
ILOAD (A)
0
60
EFFICIENCY (%)
65
70
75
80
90
1234
18717 TA02c
5
85 36VIN
48VIN
72VIN
LTC1871-7
30
18717fd
Typical applicaTions
1.2A Automotive LED Headlamp Boost Converter
Dual Output Cell Phone Base Station Flyback Converter
RUN
ITH
FB
FREQ
MODE/SYNC
10
9
8
7
6
1
2
3
4
5
SENSE
VIN
INTVCC
GATE
GND
LTC1871-7
D4
33V
D5
33V
D6 5V
18717 TA01
R7
4.7M
R6
1M
1%
VIN
GND
RUN
INPUT
0V TO 5V
DIMMING
INPUT
C5
47µF
20V
×2
R8
187k
1% C8
100nF
R10
300k
R15
0.20Ω
0.5W
R13
17.8k
C9
4.7µF
X5R
C5: SANYO OS-CON 20SP47M
C7: ITW PAKTRON 106K100CS4
L1: MAGNETICS INC 58206-A2 WITH 29T 18AWG
C10
4.7µF
R14
1k
R12
4.02k
R11
0.006Ω
R9
1k
Q3
SILICONIX
SUP75N08-9L
C7
10µF
100V
TO
LEDS
FROM
LEDS
USE 68V
OR 75V
SINGLE
ZENER
D3
IRF12CW10
L1
+
RUN
ITH
FB
FREQ
MODE/SYNC
SENSE
VIN
INTVCC
GATE
GND
1
2
3
4
5
10
9
8
7
6
LTC1871-7
R7
33k
R4
75Ω
R5
150k
R13
0.082Ω
R10
64.9k
18717 TA03
C3, C11: TDK C3225X5R0J107M
C4: SANYO POSCAP 10 TPB33M
C7: TDK C4532X7R1H335M
C13, C13A: SANYO POSCAP 4TPB470M
L1: COILCRAFT DO1608 103
T1: COILTRONICS VP4-0047
C13
470µF
R8
20.5k
R3
43.2k
R2
12.5k
5.5V
500mA
3.3V
2A
R14
1k
ISO1
MOC207
R12
80k
R11
12.5k
R1
33k
Q1
Si4482DY
C15
4.7µF
C13A
470µF
C11
100µF
C8
100pF
200V
C12
15nF
C10
330nF
R9
33k
C16
10nF 1kV
C3
100µF
C4
33µF
1 2 3
TAB
4 5
C17
1µF
C14
1nF
D4
BAT54
9
5
8
6
7
T1
VP4-0047
D1
1A 40V
D3
UPS840
R6
1Ω
C9
1nF
4
10
3
11
2
12
1
C6
1µF
35V
VIN
18V TO 33V
SYNC SIGNAL
320kHz
0V TO 2.5V
C5
22µF
50V
C7
3.3µF
50V
D2
10V
L1
10µH
COL
COMP
V+
RTOP
REF
RMID
GNDF
GNDS
1
2
3
4
8
7
6
5
LT1431
SHDN IN GND
GND
LT1963
OUT ADJ
+
+
+
LTC1871-7
31
18717fd
Typical applicaTions
Automotive SEPIC Converter
RUN
ITH
FB
FREQ
MODE/SYNC
SENSE
INTVCC
GATE
1
2
3
4
5
10
8
7
LTC1871-7
VIN
9
Q6
FMMT451
T1
VP5-0155
6
GND
R47
133k
1%
R59
0.005Ω
1W
1%
Q9
Si4486EY
SO-8
R61
12.4k
1%
R60
124k
1%
CR22
1N4148
CR21
MBR10100
C47
6800pF
C49
4.7µF
C50
4µF
X7R
C46
100pF
VBATT
8V TO 25V
R45
33.2k
R43
13.3k
1%
R37
75k
1%
R46
47k
CR4
BZX84C15V
1 12
4
•
•
9
2 11
5
•
•
8
3 10
6
•
•
7
+
C51
150µF
35V
18717 TA04
C52
4.7µF
X7R
×2
C53
22µF
16V
X5R
×2
C57
10µF
X5R
(OPTIONAL
HF FILTER)
C55
4.7µF
16V
X7R
×2
VOUT
13.5V
3A
L7
150Ω 3A
BEAD 1B
(OPTIONAL HF FILTER)
+
LTC1871-7
32
18717fd
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
package DescripTion
MSOP (MS) 0307 REV E
0.53 ± 0.152
(.021 ± .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
1234 5
4.90 ± 0.152
(.193 ± .006)
0.497 ± 0.076
(.0196 ± .003)
REF
8910 76
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ± 0.127
(.035 ± .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ± 0.038
(.0120 ± .0015)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
LTC1871-7
33
18717fd
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
D 11/11 Corrected part numbers from LT to LTC in the Order Information section. 2
(Revision history begins at Rev D)
LTC1871-7
34
18717fd
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
LINEAR TECHNOLOGY CORPORATION 2002
LT 1111 REV D • PRINTED IN USA
relaTeD parTs
Typical applicaTion
A Small, Nonisolated 12V Flyback Telecom Housekeeping Supply
PART NUMBER DESCRIPTION COMMENTS
LT
®
1619 Current Mode PWM Controller 300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology
LTC1624 Current Mode DC/DC Controller SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design;
VIN Up to 36V
LTC1700 No RSENSE Synchronous Step-Up Controller Up to 95% Efficiency, Operation as Low as 0.9V Input
LTC1871 Wide Input Range, No RSENSE Controller Operation as Low as 2.5V Input, Boost Flyback,SEPIC
LTC1872 SOT-23 Boost Controller Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode
LT1930 1.2MHz, SOT-23 Boost Converter Up to 34V Output, 2.6V ≤ VIN ≤ 16V, Miniature Design
LT1931 Inverting 1.2MHz, SOT-23 Converter Positive-to-Negative DC/DC Conversion, Miniature Design
LTC3401/LTC3402 1A/2A 3MHz Synchronous Boost Converters Up to 97% Efficiency, Very Small Solution, 0.5V ≤ VIN ≤ 5V
LTC3803 SOT-23 Flyback Controller Adjustable Slope Compensation, Internal Soft-Start, Current Mode
200kHz Operation
LTC3806 Synchronous Flyback Controller High Efficiency, Improves Cross Regulation in Multiple Output Designs,
Current Mode, 3mm × 4mm 12-Pin DFN Package
RUN
ITH
FB
FREQ
MODE/SYNC
SENSE
VIN
INTVCC
GATE
GND
LTC1871-7
RT
120k f = 200kHz
T1: COILTRONICS VP1-0076
M1: FAIRCHILD FDC2512 (150V, 0.5Ω)
Q1: ZETEX FMMT625 (120V)
C2
4.7µF
X5R
CIN
2.2µF
100V
X7R
M1
RS
0.12Ω
T1
1, 2, 3
(SERIES)
VIN
36V TO 72V
4, 5, 6
(PARALLEL)
RC
3.4k
CC1
2.2nF
CC2
47pF
C1
1nF
OPTIONAL
R2
26.7k
1%
D3
COUT
47µF
X5R
VOUT
12V
0.4A
R1
604k
1%
R3
12.4k
1%
R5
100k
R6
10Ω
Q1
D2
D1
9.1V
UV+ = 31.8V
UV– = 29.5V
D1: ON SEMICONDUCTOR MMBZ5239BLT1 (9.1V)
D2: ON SEMICONDUCTOR MMSD4148T11
D3: INTERNATIONAL RECTIFIER 10BQ060
R4
110k
1%
C3
0.1µF
X5R
18717 TA05
•
•
