LTC1871-7 High Input Voltage, Current Mode Boost, Flyback and SEPIC Controller Description Features n n n n n n n n n n n n n n Optimized for High Input Voltage Applications Wide Chip Supply Voltage Range: 6V to 36V Internal 7V Low Dropout Voltage Regulator Optimized for 6V-Rated MOSFETs Current Mode Control Provides Excellent Transient Response High Maximum Duty Cycle (92% Typ) 2% RUN Pin Threshold with 100mV Hysteresis 1% Internal Voltage Reference Micropower Shutdown: IQ = 10A Programmable Operating Frequency (50kHz to 1MHz) with One External Resistor Synchronizable to an External Clock Up to 1.3 x fOSC User-Controlled Pulse Skip or Burst Mode(R) Operation Output Overvoltage Protection Can be Used in a No RSENSETM Mode for VDS < 36V Small 10-Lead MSOP Package The LTC(R)1871-7 is a current mode, boost, flyback and SEPIC controller optimized for driving 6V-rated MOSFETs in high voltage applications. The LTC1871-7 works equally well in low or high power applications and requires few components to provide a complete power supply solution. The switching frequency can be set with an external resistor over a 50kHz to 1MHz range, and can be synchronized to an external clock using the MODE/SYNC pin. Burst Mode operation at light loads, a low minimum operating supply voltage of 6V and a low shutdown quiescent current of 10A make the LTC1871-7 well suited for battery-operated systems. For applications requiring constant frequency operation, Burst Mode operation can be defeated using the MODE/SYNC pin. The LTC1871-7 is available in the 10-lead MSOP package. PARAMETER n n n LTC1871 7.0V 5.2V UV + 5.6V 2.1V INTVCC UV- 4.6V 1.9V INTVCC Applications n LTC1871-7 INTVCC Telecom Power Supplies 42V Automotive Systems 24V Industrial Controls IP Phone Power Supplies L, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks of Linear Technology Corporation. No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application D3 10BQ060 VIN 36V TO 72V D2 4148 LTC1871-7 FB FREQ MODE/SYNC 110k 120k 47F 16V X5R 10 VIN ITH 12.4k T1 VP1-0076 SENSE RUN 3.4k Q1 FMMT625 * D1 9.1V 2.2nF 3:1 100k * 2.2F 100V X7R 604k 26.7k VOUT 12V 0.4A INTVCC M1 FDC2512 GATE GND 4.7F X5R 0.1F X5R 0.12 18717 F01 Figure 1. Small, Nonisolated 12V Flyback Telecom Housekeeping Supply 18717fd 1 LTC1871-7 Absolute Maximum Ratings (Note 1) Pin Configuration VIN Voltage ................................................ - 0.3V to 36V INTVCC Voltage............................................ -0.3V to 9V INTVCC Output Current...........................................50mA GATE Voltage............................ -0.3V to VINTVCC + 0.3V ITH, FB Voltages........................................ -0.3V to 2.7V RUN Voltage................................................ -0.3V to 7V MODE/SYNC Voltage.................................... -0.3V to 9V FREQ Voltage............................................. -0.3V to 1.5V SENSE Pin Voltage..................................... -0.3V to 36V Operating Temperature Range (Note 2) LTC1871E-7...........................................-40C to 85C LTC1871I-7.......................................... -40C to 125C Junction Temperature (Note 3).............................. 125C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec).................... 300C TOP VIEW RUN ITH FB FREQ MODE/ SYNC 10 9 8 7 6 1 2 3 4 5 SENSE VIN INTVCC GATE GND MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125C, JA = 120C/W Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1871EMS-7#PBF LTC1871EMS-7#TRPBF LTG4 10-Lead Plastic MSOP -40C to 85C LTC1871IMS-7#PBF LTC1871IMS-7#TRPBF LTBTR 10-Lead Plastic MSOP -40C to 125C LEAD BASED FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE LTC1871EMS-7 LTC1871EMS-7#TR LTG4 10-Lead Plastic MSOP -40C to 85C LTC1871IMS-7 LTC1871IMS-7#TR LTBTR 10-Lead Plastic MSOP -40C to 125C Consult LTC Marketing for parts specified with wider operating temperature ranges. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ electrical characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 8V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Main Control Loop VIN(MIN) Minimum Input Voltage I-Grade (Note 2) IQ Input Voltage Supply Current Continuous Mode VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V VMODE/SYNC = 0V, VITH = 0.2V (Note 5) VMODE/SYNC = 0V, VITH = 0.2V (Note 5), I-Grade (Note 2) Shutdown Mode 6 V 6 V (Note 4) VMODE/SYNC = 5V, VFB = 1.4V, VITH = 0.75V, I-Grade (Note 2) Burst Mode Operation, No Load VRUN = 0V VRUN = 0V, I-Grade (Note 2) 550 1000 A 600 1100 A 280 500 A 280 600 A 12 25 A 12 25 A 18717fd 2 LTC1871-7 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 8V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified. SYMBOL PARAMETER VRUN+ Rising RUN Input Threshold Voltage VRUN - Falling RUN Input Threshold Voltage VRUN(HYST) RUN Pin Input Threshold Hysteresis IRUN RUN Input Current VFB Feedback Voltage CONDITIONS VITH = 0.2V (Note 5) VITH = 0.2V (Note 5), I-Grade (Note 2) IFB FB Pin Input Current VITH = 0.2V (Note 5) VFB Line Regulation 6V VIN 30V VIN Load Regulation VITH TYP MAX 1.348 I-Grade (Note 2) VFB MIN UNITS V 1.223 1.198 1.248 1.273 1.298 50 100 150 mV 35 100 175 mV 5 60 nA 1.230 1.242 1.248 V V 1.255 V 1.218 1.212 1.205 V V 18 60 nA 0.002 0.02 %/V 0.002 0.02 %/V 6V VIN 30V, I-Grade (Note 2) VMODE/SYNC = 0V, VITH = 0.5V to 0.9V (Note 5) -1 -0.1 % VMODE/SYNC = 0V, VITH = 0.5V to 0.9V (Note 5) I-Grade (Note 2) -1 -0.1 % 2.5 6 VFB(OV) FB Pin, Overvoltage Lockout VFB(OV) - VFB(NOM) in Percent gm Error Amplifier Transconductance ITH Pin Load = 5A (Note 5) 600 VITH(BURST) Burst Mode Operation ITH Pin Voltage Falling ITH Voltage (Note 5) VSENSE(MAX) Maximum Current Sense Input Threshold Duty Cycle < 20% ISENSE(ON) SENSE Pin Current (GATE High) VSENSE = 0V 35 ISENSE(OFF) SENSE Pin Current (GATE Low) VSENSE = 30V Oscillator Frequency RFREQ = 80k Duty Cycle < 20%, I-Grade (Note 2) 10 mho 0.3 120 150 % V 180 mV 200 mV 70 A 0.1 5 A 250 300 350 kHz 300 350 kHz 100 Oscillator fOSC RFREQ = 80k, I-Grade (Note 2) 250 50 1000 kHz I-Grade (Note 2) 50 1000 kHz I-Grade (Note 2) Oscillator Frequency Range DMAX Maximum Duty Cycle 87 92 97 % 87 92 98.5 % 1.25 1.30 1.25 1.30 fSYNC/fOSC Recommended Maximum Synchronized Frequency Ratio fOSC = 300kHz (Note 6) tSYNC(MIN) MODE/SYNC Minimum Input Pulse Width VSYNC = 0V to 5V 25 ns tSYNC(MAX) MODE/SYNC Maximum Input Pulse Width VSYNC = 0V to 5V 0.8/fOSC ns VIL(MODE) Low Level MODE/SYNC Input Voltage VIH(MODE) fOSC = 300kHz (Note 6), I-Grade (Note 2) I-Grade (Note 2) I-Grade (Note 2) High Level MODE/SYNC Input Voltage RMODE/SYNC MODE/SYNC Input Pull-Down Resistance VFREQ Nominal FREQ Pin Voltage 0.3 V 0.3 V 1.2 V 1.2 V 50 k 0.62 V Low Dropout Regulator VINTVCC INTVCC Regulator Output Voltage VIN = 8V VIN = 8V, I-Grade (Note 2) 6.5 7 7.5 V 6.5 7 7.5 V 18717fd 3 LTC1871-7 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 8V, VRUN = 1.5V, RFREQ = 80k, VMODE/SYNC = 0V, unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS UVLO INTVCC Undervoltage Lockout Threshold Rising INTVCC Falling INTVCC UVLO Hysteresis VINTVCC INTVCC Regulator Line Regulation 8V VIN 15V 8 25 mV VIN1 VINTVCC INTVCC Regulator Line Regulation 15V VIN 30V 70 200 mV VLDO(LOAD) INTVCC Load Regulation 0 IINTVCC 20mA, VIN = 8V VDROPOUT INTVCC Regulator Dropout Voltage tr tf 5.6 4.6 1.0 V V V VIN2 -2 -0.2 % VIN = 6V, INTVCC Load = 20mA 280 mV GATE Driver Output Rise Time CL = 3300pF (Note 7) 17 100 ns GATE Driver Output Fall Time CL = 3300pF (Note 7) 8 100 ns GATE Driver Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC1871E-7 is guaranteed to meet performance specifications from 0C to 70C junction temperature. Specifications over the - 40C to 85C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LTC1871I-7 is guaranteed over the full -40C to 125C operating junction temperature range. Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: TJ = TA + (PD * 120C/W) Note 4: The dynamic input supply current is higher due to power MOSFET gate charging (QG * fOSC). See Applications Information. Note 5: The LTC1871-7 is tested in a feedback loop that servos VFB to the reference voltage with the ITH pin forced to a voltage between 0V and 1.4V (the no load to full load operating voltage range for the ITH pin is 0.3V to 1.23V). Note 6: In a synchronized application, the internal slope compensation gain is increased by 25%. Synchronizing to a significantly higher ratio will reduce the effective amount of slope compensation, which could result in subharmonic oscillation for duty cycles greater than 50%. Note 7: Rise and fall times are measured at 10% and 90% levels. typical performance characteristics FB Voltage vs Temp FB Voltage Line Regulation 1.25 FB Pin Current vs Temperature 60 1.231 50 1.23 FB PIN CURRENT (nA) FB VOLTAGE (V) FB VOLTAGE (V) 1.24 1.230 1.22 40 30 20 10 1.21 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 18717 G01 1.229 0 5 10 15 20 VIN (V) 25 30 35 18717 G02 0 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 18717 G03 18717fd 4 LTC1871-7 Typical Performance Characteristics Shutdown Mode IQ vs VIN Shutdown Mode IQ vs Temperature 30 20 600 VIN = 8V Burst Mode IQ vs VIN 20 10 BURST MODE IQ (A) SHUTDOWN MODE IQ (A) SHUTDOWN MODE IQ (A) 500 15 10 5 400 300 200 100 0 0 10 20 VIN (V) 30 0 -50 -25 40 0 18717 G04 18 500 TIME (ns) IQ (mA) 40 10 8 6 FALL TIME 10 2 0 25 50 75 100 125 150 TEMPERATURE (C) 0 200 400 600 800 FREQUENCY (kHz) RUN Thresholds vs VIN 10 20 VIN (V) 30 40 18717 G10 2000 4000 6000 8000 CL (pF) 10000 12000 18717 G09 RT vs Frequency 1.35 RT (k) RUN THRESHOLDS (V) 1.3 0 1000 1.40 0 0 1200 RUN Thresholds vs Temperature 1.5 RUN THRESHOLDS (V) 1000 18717 G08 18717 G07 1.2 RISE TIME 30 20 4 100 1.4 40 50 12 0 30 60 14 0 -50 -25 20 VIN (V) Gate Drive Rise and Fall Time vs CL CL = 3300pF IQ(TOT) = 600A + Qg * f 16 400 200 10 18717 G06 Dynamic IQ vs Frequency 300 0 18717 G05 Burst Mode IQ vs Temperature Burst Mode IQ (A) 0 25 50 75 100 125 150 TEMPERATURE (C) 1.30 100 1.25 1.20 -50 -25 0 25 50 75 100 125 150 TEMPERATURE (C) 18717 G11 10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 18717 G12 18717fd 5 LTC1871-7 Typical Performance Characteristics Maximum Sense Threshold vs Temperature Frequency vs Temperature 325 SENSE Pin Current vs Temperature 35 160 GATE FREQUENCY (kHz) 315 310 305 300 295 290 285 155 SENSE PIN CURRENT (A) MAX SENSE THRESHOLD (mV) 320 150 145 GATE HIGH VSENSE = 0V 30 280 275 -50 -25 0 140 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 0 0 25 50 75 100 125 150 TEMPERATURE (C) 18717 G14 18717 G13 INTVCC Load Regulation 18717 G15 INTVCC Dropout Voltage vs Current, Temperature INTVCC Line Regulation 500 7.2 VIN = 8V 450 6.9 DROPOUT VOLTAGE (mV) INTVCC VOLTAGE (V) 7.0 INTVCC VOLTAGE (V) 25 -50 -25 25 50 75 100 125 150 TEMPERATURE (C) 7.1 7.0 150C 400 125C 350 75C 300 25C 250 200 0C 150 -50C 100 50 6.8 0 10 20 30 40 50 60 70 80 6.9 0 5 10 15 18717 G16 20 25 VIN (V) 30 35 40 18717 G17 0 0 5 10 15 INTVCC LOAD (mA) 20 18717 G18 pin functions RUN (Pin 1): The RUN pin provides the user with an accurate means for sensing the input voltage and programming the start-up threshold for the converter. The falling RUN pin threshold is nominally 1.248V and the comparator has 100mV of hysteresis for noise immunity. When the RUN pin is below this input threshold, the IC is shut down and the VIN supply current is kept to a low value (typ 10A). The Absolute Maximum Rating for the voltage on this pin is 7V. ITH (Pin 2): Error Amplifier Compensation Pin. The current comparator input threshold increases with this control voltage. Nominal voltage range for this pin is 0V to 1.40V. FB (Pin 3): Receives the feedback voltage from the external resistor divider across the output. Nominal voltage for this pin in regulation is 1.230V. FREQ (Pin 4): A resistor from the FREQ pin to ground programs the operating frequency of the chip. The nominal voltage at the FREQ pin is 0.6V. 18717fd 6 LTC1871-7 Pin Functions MODE/SYNC (Pin 5): This input controls the operating mode of the converter and allows for synchronizing the operating frequency to an external clock. If the MODE/ SYNC pin is connected to ground, Burst Mode operation is enabled. If the MODE/SYNC pin is connected to INTVCC, or if an external logic-level synchronization signal is applied to this input, Burst Mode operation is disabled and the IC operates in a continuous mode. GND (Pin 6): Ground Pin. GATE (Pin 7): Gate Driver Output. INTVCC (Pin 8): The Internal 7V Regulator Output. The gate driver and control circuits are powered from this voltage. Decouple this pin locally to the IC ground with a minimum of 4.7F low ESR tantalum or ceramic capacitor. This 7V regulator has an undervoltage lockout circuit with 5.6V and 4.6V rising and falling thresholds, respectively. VIN (Pin 9): Main Supply Pin. Must be closely decoupled to ground. SENSE (Pin 10): The Current Sense Input for the Control Loop. Connect this pin to a resistor in the source of the power MOSFET. Alternatively, the SENSE pin may be connected to the drain of the power MOSFET, in applications where the maximum VDS is less than 36V. Internal leading edge blanking is provided for both sensing methods. Block Diagram BIAS AND START-UP CONTROL SLOPE COMPENSATION RUN + 1 C2 - 1.248V VIN FREQ 4 0.6V V-TO-I PWM LATCH 85mV 1.230V + - S 50k OV R + 0.30V FB 3 1.230V 9 INTVCC IOSC MODE/SYNC 5 OSC - + EA + BURST COMPARATOR GATE 7 LOGIC Q GND CURRENT COMPARATOR + SENSE 10 C1 - - gm ITH V-TO-I 2 INTVCC 8 7V - 5.6V UP 4.6V DOWN + ILOOP LDO 1.230V SLOPE 1.230V UV TO START-UP CONTROL RLOOP GND BIAS VREF 6 18717 BD VIN 18717fd 7 LTC1871-7 operation Main Control Loop The LTC1871-7 is a constant frequency, current mode controller for DC/DC boost, SEPIC and flyback converter applications. With the LTC1871-7 the current control loop can be closed by sensing the voltage drop either across the power MOSFET switch or across a discrete sense resistor, as shown in Figure 2. L VIN D VOUT VIN + SENSE VSW COUT GATE GND GND 2a. SENSE Pin Connection for Maximum Efficiency (VSW < 36V) L VIN VIN D VOUT VSW GATE SENSE GND + COUT RS GND 18717 F02 2b. SENSE Pin Connection for Precise Control of Peak Current or for VSW > 36V Figure 2. Using the SENSE Pin On the LTC1871-7 For circuit operation, please refer to the Block Diagram of the IC and Figure 1. In normal operation, the power MOSFET is turned on when the oscillator sets the PWM latch and is turned off when the current comparator C1 resets the latch. The divided-down output voltage is compared to an internal 1.230V reference by the error amplifier EA, which outputs an error signal at the ITH pin. The voltage on the ITH pin sets the current comparator C1 input threshold. When the load current increases, a fall in the FB voltage relative to the reference voltage causes the ITH pin to rise, which causes the current comparator C1 to trip at a higher peak inductor current value. The average inductor current will therefore rise until it equals the load current, thereby maintaining output regulation. The nominal operating frequency of the LTC1871-7 is programmed using a resistor from the FREQ pin to ground and can be controlled over a 50kHz to 1000kHz range. In addition, the internal oscillator can be synchronized to an external clock applied to the MODE/SYNC pin and can be locked to a frequency between 100% and 130% of its nominal value. When the MODE/SYNC pin is left open, it is pulled low by an internal 50k resistor and Burst Mode operation is enabled. If this pin is taken above 2V or an external clock is applied, Burst Mode operation is disabled and the IC operates in continuous mode. With no load (or an extremely light load), the controller will skip pulses in order to maintain regulation and prevent excessive output ripple. The RUN pin controls whether the IC is enabled or is in a low current shutdown state. A micropower 1.248V reference and comparator C2 allow the user to program the supply voltage at which the IC turns on and off (comparator C2 has 100mV of hysteresis for noise immunity). With the RUN pin below 1.248V, the chip is off and the input supply current is typically only 10A. An overvoltage comparator OV senses when the FB pin exceeds the reference voltage by 6.5% and provides a reset pulse to the main RS latch. Because this RS latch is reset-dominant, the power MOSFET is actively held off for the duration of an output overvoltage condition. The LTC1871-7 can be used either by sensing the voltage drop across the power MOSFET or by connecting the SENSE pin to a conventional shunt resistor in the source of the power MOSFET, as shown in Figure 2. Sensing the voltage across the power MOSFET maximizes converter efficiency and minimizes the component count, but limits the output voltage to the maximum rating for this pin (36V). By connecting the SENSE pin to a resistor in the source of the power MOSFET, the user is able to program output voltages significantly greater than 36V. Programming the Operating Mode For applications where maximizing the efficiency at very light loads (e.g., <100A) is a high priority, the current in the output divider could be decreased to a few microamps and Burst Mode operation should be applied (i.e., the MODE/SYNC pin should be connected to ground). 18717fd 8 LTC1871-7 Operation In applications where fixed frequency operation is more critical than low current efficiency, or where the lowest output ripple is desired, pulse-skip mode operation should be used and the MODE/SYNC pin should be connected to the INTVCC pin. This allows discontinuous conduction mode (DCM) operation down to near the limit defined by the chip's minimum on-time (about 175ns). Below this output current level, the converter will begin to skip cycles in order to maintain output regulation. Figures 3 and 4 show the light load switching waveforms for Burst Mode and pulse-skip mode operation for the converter in Figure 1. Burst Mode Operation Burst Mode operation is selected by leaving the MODE/ SYNC pin unconnected or by connecting it to ground. In normal operation, the range on the ITH pin corresponding to no load to full load is 0.30V to 1.2V. In Burst Mode operation, if the error amplifier EA drives the ITH voltage below 0.525V, the buffered ITH input to the current comparator C1 will be clamped at 0.525V (which corresponds to 25% of maximum load current). The inductor current peak is then held at approximately 30mV divided by the power MOSFET RDS(ON). If the ITH pin drops below 0.30V, the Burst Mode comparator B1 will turn off the power MOSFET and scale back the quiescent current of the IC to 250A (sleep mode). In this condition, the load current will be supplied by the output capacitor until the ITH voltage rises above the 50mV hysteresis of the burst comparator. At light loads, short bursts of switching (where the average inductor current is 20% of its maximum value) followed by long periods of sleep will be observed, thereby greatly improving converter efficiency. Oscilloscope waveforms illustrating Burst Mode operation are shown in Figure 3. Pulse-Skip Mode Operation With the MODE/SYNC pin tied to a DC voltage above 2V, Burst Mode operation is disabled. The internal, 0.525V buffered ITH burst clamp is removed, allowing the ITH pin to directly control the current comparator from no load to full load. With no load, the ITH pin is driven below 0.30V, the power MOSFET is turned off and sleep mode is invoked. Oscilloscope waveforms illustrating this mode of operation are shown in Figure 4. When an external clock signal drives the MODE/SYNC pin at a rate faster than the chip's internal oscillator, the oscillator will synchronize to it. In this synchronized mode, Burst Mode operation is disabled. The constant frequency associated with synchronized operation provides a more controlled noise spectrum from the converter, at the expense of overall system efficiency of light loads. When the oscillator's internal logic circuitry detects a synchronizing signal on the MODE/SYNC pin, the internal oscillator ramp is terminated early and the slope compensation is increased by approximately 30%. As a result, in applications requiring synchronization, it is recommended that the nominal operating frequency of the IC be programmed to be about 75% of the external clock frequency. Attempting to synchronize to too high an MODE/SYNC = 0V (Burst Mode OPERATION) MODE/SYNC = INTVCC (PULSE SKIP MODE) VOUT 50mV/DIV VOUT 50mV/DIV IL 5A/DIV IL 5A/DIV 10s/DIV 18717 F03 Figure 3. LTC1871-7 Burst Mode Operation (MODE/SYNC = 0V) at Low Output Current 2s/DIV 18717 F04 Figure 4. LTC1871-7 Low Output Current Operation with Burst Mode Operation Disabled (MODE/SYNC = INTVCC) 18717fd 9 LTC1871-7 operation external frequency (above 1.3fO) can result in inadequate slope compensation and possible subharmonic oscillation (or jitter). The external clock signal must exceed 2V for at least 25ns, and should have a maximum duty cycle of 80%, as shown in Figure 5. The MOSFET turn on will synchronize to the rising edge of the external clock signal. Programming the Operating Frequency The choice of operating frequency and inductor value is a tradeoff between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET and diode switching losses. However, lower frequency operation requires more inductance for a given amount of load current. The LTC1871-7 uses a constant frequency architecture that can be programmed over a 50kHz to 1000kHz range with a single external resistor from the FREQ pin to ground, as shown in Figure 1. The nominal voltage on the FREQ pin is 0.6V, and the current that flows into the FREQ pin is used to charge and discharge an internal oscillator capacitor. A graph for selecting the value of RT for a given operating frequency is shown in Figure 6. INTVCC Regulator Bypassing and Operation An internal, P-channel low dropout voltage regulator produces the 7V supply which powers the gate driver and 2V TO 7V For input voltages that don't exceed 8V (the absolute maximum rating for INTVCC is 9V), the internal low dropout regulator in the LTC1871-7 is redundant and the INTVCC pin can be shorted directly to the VIN pin. With the INTVCC pin shorted to VIN, however, the divider that programs the regulated INTVCC voltage will draw 14A of current from the input supply, even in shutdown mode. For applications that require the lowest shutdown mode input supply current, do not connect the INTVCC pin to VIN. Regardless of whether the INTVCC pin is shorted to VIN or not, it is always necessary to have the driver circuitry bypassed with a 4.7F ceramic capacitor to ground immediately adjacent to the INTVCC and GND pins. In an actual application, most of the IC supply current is used to drive the gate capacitance of the power MOSFET. As a result, high input voltage applications in which a large power MOSFET is being driven at high frequencies 1000 tMIN = 25ns 0.8T GATE The LTC1871-7 contains an undervoltage lockout circuit which protects the external MOSFET from switching at low gate-to-source voltages. This undervoltage circuit senses the INTVCC voltage and has a 5.6V rising threshold and a 4.6V falling threshold. T T = 1/fO RT (k) MODE/ SYNC logic circuitry within the LTC1871-7, as shown in Figure 7. The INTVCC regulator can supply up to 50mA and must be bypassed to ground immediately adjacent to the IC pins with a minimum of 4.7F tantalum or ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate driver. D = 40% 100 10 IL 18717 F05 Figure 5. MODE/SYNC Clock Input and Switching Waveforms for Synchronized Operation 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 18717 F06 Figure 6. Timing Resistor (RT) Value 18717fd 10 LTC1871-7 Operation INPUT SUPPLY 6V TO 30V VIN - 1.230V P-CH + CIN R2 R1 LOGIC 7V INTVCC DRIVER CVCC 4.7F X5R GATE M1 GND 18717 F07 6V-RATED POWER MOSFET GND PLACE AS CLOSE AS POSSIBLE TO DEVICE PINS Figure 7. Bypassing the LDO Regulator and Gate Driver Supply can cause the LTC1871-7 to exceed its maximum junction temperature rating. The junction temperature can be estimated using the following equations: IQ(TOT) IQ + f * QG PIC = VIN * (IQ + f * QG) TJ = TA + PIC * RTH(JA) The total quiescent current IQ(TOT) consists of the static supply current (IQ) and the current required to charge and discharge the gate of the power MOSFET. The 10-pin MSOP package has a thermal resistance of RTH(JA) = 120C/W. As an example, consider a power supply with VIN =10V. The switching frequency is 200kHz, and the maximum ambient temperature is 70C. The power MOSFET chosen is the FDS3670(Fairchild), which has a maximum RDS(ON) of 35m (at room temperature) and a maximum total gate charge of 80nC (the temperature coefficient of the gate charge is low). IQ(TOT) = 600A + 80nC * 200kHz = 16.6mA PIC = 10V * 16.6mA = 166mW TJ = 70C + 120C/W * 166mW = 89.9C TJRISE = 19.9C This demonstrates how significant the gate charge current can be when compared to the static quiescent current in the IC. To prevent the maximum junction temperature from being exceeded, the input supply current must be checked when operating in a continuous mode at high VIN. A tradeoff between the operating frequency and the size of the power MOSFET may need to be made in order to maintain a reliable IC junction temperature. Prior to lowering the operating frequency, however, be sure to check with power MOSFET manufacturers for their latest-and-greatest low QG, low RDS(ON) devices. Power MOSFET manufacturing technologies are continually improving, with newer and better performance devices being introduced almost yearly. Output Voltage Programming The output voltage is set by a resistor divider according to the following formula: R2 VO = 1.230V * 1+ R1 The external resistor divider is connected to the output as shown in Figure 1, allowing remote voltage sensing. 18717fd 11 LTC1871-7 operation The resistors R1 and R2 are typically chosen so that the error caused by the current flowing into the FB pin during normal operation is less than 1% (this translates to a maximum value of R1 of about 250k). The turn-on and turn-off input voltage thresholds are programmed using a resistor divider according to the following formulas: R2 VIN(OFF) = 1.248V * 1+ R1 Programming Turn-On and Turn-Off Thresholds with the RUN Pin The LTC1871-7 contains an independent, micropower voltage reference and comparator detection circuit that remains active even when the device is shut down, as shown in Figure 8. This allows users to accurately program an input voltage at which the converter will turn on and off. The falling threshold voltage on the RUN pin is equal to the internal reference voltage of 1.248V. The comparator has 100mV of hysteresis to increase noise immunity. R2 VIN(ON) = 1.348V * 1+ R1 The resistor R1 is typically chosen to be less than 1M. For applications where the RUN pin is only to be used as a logic input, the user should be aware of the 7V Absolute Maximum Rating for this pin! The RUN pin can be connected to the input voltage through an external 1M resistor, as shown in Figure 8c, for "always on" operation. VIN + R2 RUN + RUN COMPARATOR BIAS AND START-UP CONTROL 6V INPUT SUPPLY - OPTIONAL FILTER CAPACITOR R1 1.248V POWER REFERENCE GND - 18717 F8a Figure 8a. Programming the Turn-On and Turn-Off Thresholds Using the RUN Pin + RUN COMPARATOR RUN EXTERNAL LOGIC CONTROL + VIN R2 1M RUN + 6V INPUT SUPPLY - 6V 1.248V - 18717 F08b RUN COMPARATOR - GND 1.248V 18717 F08c Figure 8b. On/Off Control Using External Logic Figure 8c. External Pull-Up Resistor On RUN Pin for "Always On" Operation 18717fd 12 LTC1871-7 applications information Application Circuits A basic LTC1871-7 application circuit is shown in Figure 9. External component selection is driven by the characteristics of the load and the input supply. The first topology to be analyzed will be the boost converter, followed by SEPIC (single-ended primary inductance converter). Boost Converter: Duty Cycle Considerations For a boost converter operating in a continuous conduction mode (CCM), the duty cycle of the main switch is: V +V -V D = O D IN VO + VD Boost Converter: The Peak and Average Input Currents The control circuit in the LTC1871-7 is measuring the input current typically using a sense resistor in the MOSFET source, so the output current needs to be reflected back to the input in order to dimension the power MOSFET properly. Based on the fact that, ideally, the output power is equal to the input power, the maximum average input current is: IIN(MAX) = where VD is the forward voltage of the boost diode. For converters where the input voltage is close to the output voltage, the duty cycle is low and for converters that develop a high output voltage from a low voltage input supply, the duty cycle is high. The maximum output voltage for a boost converter operating in CCM is: VO(MAX) = The maximum duty cycle capability of the LTC1871-7 is typically 92%. This allows the user to obtain high output voltages from low input supply voltages. VIN(MIN) (1- DMAX ) - VD R3 1M 1 2 RC 24k 3 CC1 2.2nF CC2 100pF 4 5 RT 100k 1% SENSE VIN ITH LTC1871-7 FB FREQ CIN2: COUT1: COUT2: GATE MODE/SYNC R1 12.4k 1% CIN1: INTVCC GND 1- DMAX The peak input current is : IO(MAX) IIN(PEAK) = 1+ * 2 1- DMAX The maximum duty cycle, DMAX, should be calculated at minimum VIN. CIN2 10F 50V X5R x2 f = 250kHz RUN IO(MAX) 10 L1 6.8H + VOUT 42V 1.5A D1 9 COUT2 10F 50V X5R x2 8 7 6 VIN 8V TO 28V CIN1* 560F 50V M1 CVCC 4.7F X5R R2 412k 1% SANYO 50MV560AXL (*RECOMMENDED FOR LAB EVALUATION FOR SUPPLY LEAD LENGTHS GREATER THAN A FEW INCHES) TDK C5750X5R1H106M SANYO 100CV68FS TDK C5750X5R1H106M RSENSE 0.005 1W + COUT1 68F 100V x2 GND 18717 F09 D1: DIODES INC B360B L1: COOPER DR127-6R8 M1: SILICONIX/VISHAY Si7370DP Figure 9. A High Efficiency 42V, 1.5A Automotive Boost Converter 18717fd 13 LTC1871-7 applications information Boost Converter: Ripple Current IL and the `' Factor The constant `' in the equation above represents the percentage peak-to-peak ripple current in the inductor, relative to its maximum value. For example, if 30% ripple current is chosen, then = 0.30, and the peak current is 15% greater than the average. For a current mode boost regulator operating in CCM, slope compensation must be added for duty cycles above 50% in order to avoid subharmonic oscillation. For the LTC1871-7, this ramp compensation is internal. Having an internally fixed ramp compensation waveform, however, does place some constraints on the value of the inductor and the operating frequency. If too large an inductor is used, the resulting current ramp (IL) will be small relative to the internal ramp compensation (at duty cycles above 50%), and the converter operation will approach voltage mode (ramp compensation reduces the gain of the current loop). If too small an inductor is used, but the converter is still operating in CCM (near critical conduction mode), the internal ramp compensation may be inadequate to prevent subharmonic oscillation. To ensure good current mode gain and avoid subharmonic oscillation, it is recommended that the ripple current in the inductor fall in the range of 20% to 40% of the maximum average current. For example, if the maximum average input current is 1A, choose a IL between 0.2A and 0.4A, and a value `' between 0.2 and 0.4. Boost Converter: Inductor Selection Given an operating input voltage range, and having chosen the operating frequency and ripple current in the inductor, the inductor value can be determined using the following equation: VIN(MIN) L= * DMAX IL * f applications requiring a step-up converter that is shortcircuit protected, please refer to the applications section covering SEPIC converters. The minimum required saturation current of the inductor can be expressed as a function of the duty cycle and the load current, as follows: IO(MAX) IL(SAT) 1+ * 2 1- DMAX The saturation current rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. Boost Converter: Operating in Discontinuous Mode Discontinuous mode operation occurs when the load current is low enough to allow the inductor current to run out during the off-time of the switch, as shown in Figure 10. Once the inductor current is near zero, the switch and diode capacitances resonate with the inductance to form damped ringing at 1MHz to 10MHz. If the off-time is long enough, the drain voltage will settle to the input voltage. Depending on the input voltage and the residual energy in the inductor, this ringing can cause the drain of the power MOSFET to go below ground where it is clamped by the body diode. This ringing is not harmful to the IC and it has not been shown to contribute significantly to EMI. Any attempt to damp it with a snubber will degrade the efficiency. OUTPUT VOLTAGE 200mV/DIV INDUCTOR CURRENT 1A/DIV where : IL = * IO(MAX) 1- DMAX Remember that boost converters are not short-circuit protected. Under a shorted output condition, the inductor current is limited only by the input supply capability. For MOSFET DRAIN VOLTAGE 20V/DIV 1s/DIV 18717 F10 Figure 10. Discontinuous Mode Waveforms for the Converter Shown in Figure 9 18717fd 14 LTC1871-7 applications information Sense Resistor Selection During the switch on-time, the control circuit limits the maximum voltage drop across the sense resistor to about 150mV (at low duty cycle). The peak inductor current is therefore limited to 150mV/RSENSE. The relationship between the maximum load current, duty cycle and the sense resistor RSENSE is: R SENSE VSENSE(MAX) * 1- DMAX 1+ * IO(MAX) 2 The VSENSE(MAX) term is typically 150mV at low duty cycle, and is reduced to about 100mV at a duty cycle of 92% due to slope compensation, as shown in Figure 11. MAXIMUM CURRENT SENSE VOLTAGE (mV) It is worth noting that the 1 - DMAX relationship between IO(MAX) and RSENSE can cause boost converters with a wide input range to experience a dramatic range of maximum input and output current. This should be taken into consideration in applications where it is important to limit the maximum current drawn from the input supply. 200 150 100 Pay close attention to the BVDSS specifications for the MOSFETs relative to the maximum actual switch voltage in the application. The switch node can ring during the turn-off of the MOSFET due to layout parasitics. Check the switching waveforms of the MOSFET directly across the drain and source terminals using the actual PC board layout (not just on a lab breadboard!) for excessive ringing. Calculating Power MOSFET Switching and Conduction Losses and Junction Temperatures In order to calculate the junction temperature of the power MOSFET, the power dissipated by the device must be known. This power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of its RDS(ON)). As a result, some iterative calculation is normally required to determine a reasonably accurate value. Care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (line voltage and temperature), and for the worst-case specifications for VSENSE(MAX) and the RDS(ON) of the MOSFET listed in the manufacturer's data sheet. The power dissipated by the MOSFET in a boost converter is: 2 IO(MAX) PFET = * RDS(ON) * D * T 1- D 50 0 The gate drive voltage is set by the 7V INTVCC low drop regulator. Consequently, 6V rated MOSFETs are required in most high voltage LTC1871-7 applications. 0 0.2 0.5 0.4 DUTY CYCLE 0.8 1.0 18717 F11 Figure 11. Maximum SENSE Threshold Voltage vs Duty Cycle Boost Converter: Power MOSFET Selection Important parameters for the power MOSFET include the drain-to-source breakdown voltage (BVDSS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gateto-source voltage, the gate-to-source and gate-to-drain charges (QGS and QGD, respectively), the maximum drain current (ID(MAX)) and the MOSFET's thermal resistances (RTH(JC) and RTH(JA)). +k * VO 2 * IO(MAX) (1- D) * CRSS * f The first term in the equation above represents the I2R losses in the device, and the second term, the switching losses. The constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. The T term accounts for the temperature coefficient of the RDS(ON) of the MOSFET, which is typically 0.4%/C. Figure 12 illustrates the variation of normalized RDS(ON) over temperature for a typical power MOSFET. 18717fd 15 LTC1871-7 applications information The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. T NORMALIZED ON RESISTANCE 2.0 1.5 Remember to keep the diode lead lengths short and to observe proper switch-node layout (see Board Layout Checklist) to avoid excessive ringing and increased dissipation. 1.0 0.5 Boost Converter: Output Capacitor Selection 0 -50 50 100 0 JUNCTION TEMPERATURE (C) 150 18717 F12 Figure 12. Normalized RDS(ON) vs Temperature From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + PFET * RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the case to the ambient temperature (RTH(CA)). This value of TJ can then be compared to the original, assumed value used in the iterative calculation process. Boost Converter: Output Diode Selection To maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is desired. The output diode in a boost converter conducts current during the switch off-time. The peak reverse voltage that the diode must withstand is equal to the regulator output voltage. The average forward current in normal operation is equal to the output current, and the peak current is equal to the peak inductor current. IO(MAX) ID(PEAK) = IL(PEAK) = 1+ * 2 1- DMAX The power dissipated by the diode is: PD = IO(MAX) * VD and the diode junction temperature is: TJ = TA + PD * RTH(JA) Contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct component for a given output ripple voltage. The effects of these three parameters (ESR, ESL and bulk C) on the output voltage ripple waveform are illustrated in Figure 13 for a typical boost converter. The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step and the charging/discharging V. For the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the ESR step and the charging/discharging V. This percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: ESRCOUT 0.01* VO IIN(PEAK) where: IO(MAX) IIN(PEAK)= 1+ * 2 1- DMAX For the bulk C component, which also contributes 1% to the total ripple: IO(MAX) COUT 0.01* VO * f 18717fd 16 LTC1871-7 applications information For some designs it may be possible to choose a single capacitor type that satisfies both the ESR and bulk C requirements for the design. In certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. For example, using a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic capacitor can be used to supply the required bulk C. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform should be verified on a dedicated PC board (see Board Layout section for more information on component placement). Lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed PC board. The output capacitor in a boost regulator experiences high RMS ripple currents, as shown in Figure 13. The RMS output capacitor ripple current is: IRMS(COUT) IO(MAX) * VO - VIN(MIN) VIN(MIN) Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. In surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. In the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. Also, ceramic capacitors are now available with extremely low ESR, ESL and high ripple current ratings. L VIN D SW VOUT COUT RL 13a. Circuit Diagram IIN IL 13b. Inductor and Input Currents ISW tON 13c. Switch Current ID tOFF IO 13d. Diode and Output Currents VCOUT VOUT (AC) VESR RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 13e. Output Voltage Ripple Waveform 18717 F13 Figure 13. Switching Waveforms for a Boost Converter Boost Converter: Input Capacitor Selection The input capacitor of a boost converter is less critical than the output capacitor, due to the fact that the inductor is in series with the input and the input current waveform is continuous (see Figure 13b). The input voltage source impedance determines the size of the input capacitor, which is typically in the range of 10F to 100F. A low ESR capacitor is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a boost converter is: VIN(MIN) IRMS(CIN) = 0.3 * * DMAX L*f 18717fd 17 LTC1871-7 applications information Table 1. Recommended Component Manufacturers VENDOR AVX BH Electronics COMPONENTS TELEPHONE WEB ADDRESS Capacitors (207) 282-5111 avxcorp.com Inductors, Transformers (952) 894-9590 bhelectronics.com Coilcraft Inductors (847) 639-6400 coilcraft.com Coiltronics Inductors (407) 241-7876 coiltronics.com Diodes, Inc Fairchild General Semiconductor Diodes (805) 446-4800 diodes.com MOSFETs (408) 822-2126 fairchildsemi.com Diodes (516) 847-3000 generalsemiconductor.com International Rectifier MOSFETs, Diodes (310) 322-3331 irf.com IRC Sense Resistors (361) 992-7900 irctt.com Tantalum Capacitors (408) 986-0424 kemet.com Toroid Cores (800) 245-3984 mag-inc.com Microsemi Diodes (617) 926-0404 microsemi.com Murata-Erie Inductors, Capacitors (770) 436-1300 murata.co.jp Capacitors (847) 843-7500 nichicon.com Kemet Magnetics Inc Nichicon On Semiconductor Diodes (602) 244-6600 onsemi.com Panasonic Capacitors (714) 373-7334 panasonic.com Sanyo Capacitors (619) 661-6835 sanyo.co.jp Sumida Inductors (847) 956-0667 sumida.com Taiyo Yuden Capacitors (408) 573-4150 t-yuden.com Capacitors, Inductors (562) 596-1212 component.tdk.com Thermalloy Heat Sinks (972) 243-4321 aavidthermalloy.com Tokin Capacitors (408) 432-8020 nec-tokinamerica.com TDK Toko Inductors (847) 699-3430 tokoam.com United Chemicon Capacitors (847) 696-2000 chemi-com.com Vishay/Dale Resistors (605) 665-9301 vishay.com Vishay/Siliconix MOSFETs (800) 554-5565 vishay.com Vishay/Sprague Capacitors (207) 324-4140 vishay.com Small-Signal Discretes (631) 543-7100 zetex.com Zetex Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to specify surge-tested capacitors! Burst Mode Operation and Considerations The choice of sense resistor and inductor value also determines the load current at which the LTC1871-7 enters Burst Mode operation. When bursting, the controller clamps the peak inductor current to approximately: 30mV IBURST(PEAK) = RSENSE 18 which represents about 20% of the maximum 150mV SENSE pin voltage. The corresponding average current depends upon the amount of ripple current. Lower inductor values (higher IL) will reduce the load current at which Burst Mode operations begins, since it is the peak current that is being clamped. The output voltage ripple can increase during Burst Mode operation if IL is substantially less than IBURST. This can occur if the input voltage is very low or if a very large inductor is chosen. At high duty cycles, a skipped cycle causes the inductor current to quickly decay to zero. However, because IL is small, it takes multiple cycles for the current to ramp back up to IBURST(PEAK). 18717fd LTC1871-7 applications information During this inductor charging interval, the output capacitor must supply the load current and a significant droop in the output voltage can occur. Generally, it is a good idea to choose a value of inductor IL between 25% and 40% of IIN(MAX). The alternative is to either increase the value of the output capacitor or disable Burst Mode operation using the MODE/SYNC pin. Burst Mode operation can be defeated by connecting the MODE/SYNC pin to a high logic-level voltage (either with a control input or by connecting this pin to INTVCC). In this mode, the burst clamp is removed, and the chip can operate at constant frequency from continuous conduction mode (CCM) at full load, down into deep discontinuous conduction mode (DCM) at light load. Prior to skipping pulses at very light load (i.e., <5% of full load), the controller will operate with a minimum switch on-time in DCM. Pulse skipping prevents a loss of control of the output at very light loads and reduces output voltage ripple. Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power (100%). Percent efficiency can be expressed as: % Efficiency = 100% - (L1 + L2 + L3 + ...), where L1, L2, etc. are the individual loss components as a percentage of the input power. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Although all dissipative elements in the circuit produce losses, four main sources usually account for the majority of the losses in LTC1871-7 application circuits: 1. The supply current into VIN. The VIN current is the sum of the DC supply current IQ (given in the Electrical Characteristics) and the MOSFET driver and control currents. The DC supply current into the VIN pin is typically about 650A and represents a small power loss (much less than 1%) that increases with VIN. The driver current results from switching the gate capacitance of the power MOSFET; this current is typically much larger than the DC current. Each time the MOSFET is switched on and then off, a packet of gate charge QG is transferred from INTVCC to ground. The resulting dQ/dt is a current that must be supplied to the INTVCC capacitor through the VIN pin by an external supply. If the IC is operating in CCM: IQ(TOT) IQ = f * QG PIC = VIN * (IQ + f * QG) 2. Power MOSFET switching and conduction losses: 2 PFET IO(MAX) = * RDS(ON) * DMAX * T 1- DMAX + k * VO2 * IO(MAX) 1- DMAX * CRSS * f 3. The I2R losses in the sense resistor can be calculated almost by inspection. 2 IO(MAX) PR(SENSE) = * R SENSE * DMAX 1- DMAX 4. The losses in the inductor are simply the DC input current squared times the winding resistance. Expressing this loss as a function of the output current yields: 2 IO(MAX) PR(WINDING) = * RW 1- DMAX 5. Losses in the boost diode. The power dissipation in the boost diode is: PDIODE = IO(MAX) * VD The boost diode can be a major source of power loss in a boost converter. For 13.2V input, 42V output at 1.5A example given in Figure 9, a Schottky diode with a 0.4V forward voltage would dissipate 600mW, which represents about 1% of the input power. Diode losses can become significant at low output voltages where the forward voltage is a significant percentage of the output voltage. 6. Other losses, including CIN and CO ESR dissipation and inductor core losses, generally account for less than 2% of the total losses. 18717fd 19 LTC1871-7 applications information Checking Transient Response The regulator loop response can be verified by looking at the load transient response at minimum and maximum VIN. Switching regulators generally take several cycles to respond to an instantaneous step in resistive load current. When the load step occurs, VO immediately shifts by an amount equal to (ILOAD)(ESR), and then CO begins to charge or discharge (depending on the direction of the load step) as shown in Figure 14. The regulator feedback loop acts on the resulting error amp output signal to return VO to its steady-state value. During this recovery time, VO can be monitored for overshoot or ringing that would indicate a stability problem. A second, more severe transient can occur when connecting loads with large (>1F) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with CO, causing a nearly instantaneous drop in VO. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive in order to limit the inrush current di/ dt to the load. Boost Converter Design Example The design example given here will be for the circuit shown in Figure 9. The input voltage is 8V to 28V, and the output is 42V at a maximum load current of 1.5A. 1. The maximum duty cycle is: VIN = 8V V + V - V 42 + 0.4 - 8 D = O D IN = = 81.1% 42 + 0.4 VO + VD VOUT 500mV/DIV 1.5A 2. Pulse-skip operation is chosen so the MODE/SYNC pin is shorted to INTVCC. IOUT 0.5A/DIV 3. The operating frequency is chosen to be 250kHz to reduce the size of the inductor. From Figure 5, the resistor from the FREQ pin to ground is 100k. 0.5A 250s/DIV 18717 F14a Figure 14a. Load Transient Response for the Circuit in Figure 9 VIN = 28V 4. An inductor ripple current of 40% of the maximum load current is chosen, so the peak input current (which is also the minimum saturation current) is: IO(MAX) IIN(PEAK) = 1+ * 2 1- DMAX VOUT 500mV/DIV = 1.2 * 1.5A IOUT 0.5A/DIV 0.5A 250s/DIV 18717 F14b Figure 14b. Load Transient Response for the Circuit in Figure 9 1.5 = 9.47A 1- 0.81 The inductor ripple current is: IO(MAX) 1.5 IL = * = 0.4 * = 3.2A 1- 0.81 1- D MAX And so the inductor value is: VIN(MIN) L= * DMAX IL * f = 8 * 0.81= 8.1H 3.2 * 250k 18717fd 20 LTC1871-7 applications information The component chosen is a 6.8H inductor made by Cooper (part number DR127-6R8) which has a saturation current of greater than 13.3A. 5. Because the duty cycle is 81%, the maximum SENSE pin threshold voltage is reduced from its low duty cycle typical value of 150mV to approximately 115mV. In addition, we need to apply a worst-case derating factor to this SENSE threshold to account for manufacturing tolerances within the IC. Finally, the nominal current limit value should exceed the maximum load current by some safety margin (in this case 50%). Therefore, the value of the sense resistor is: 1- DMAX RSENSE = 0.8 * VSENSE(MAX) * 0.4 1+ * 1.5 *IO(MAX) 2 1- 0.81 = 6.5m 1.2 * 1.5 * 1.5 A 1W, 5m resistor is used in this design. = 0.8 * 0.115 * 6. The MOSFET chosen is a Vishay/Siliconix Si7370DP, which has a BVDSS of greater than 60V and an RDS(ON) of less than 13m at a VGS of 6V. 7. The diode for this design must handle a maximum DC output current of 1.5A and be rated for a minimum reverse voltage of VOUT, or 42V. A 3A, 60V diode from Diodes Inc. (B360B) is chosen. 8. The output capacitor usually consists of a high valued bulk C connected in parallel with a lower valued, low ESR ceramic. Based on a maximum output ripple voltage of 1%, or 50mV, the bulk C needs to be greater than: IOUT(MAX) 1.5 COUT = = 14F 0.01* VOUT * f 0.01* 42 * 250k The RMS ripple current rating for this capacitor needs to exceed: VO - VIN(MIN) IRMS(COUT) IO(MAX) * = VIN(MIN) 1.5 * To satisfy the low ESR, high frequency decoupling requirements, two 10F, 50V, X5R ceramic capacitors are used (TDK part number C5750X5R1H106M). In parallel with these, two 68F, 100V electrolytic capacitors are used (Sanyo part number 100CV68FS). Check the output ripple with a single oscilloscope probe connected directly across the output capacitor terminals, where the HF switching currents flow. 9. The choice of an input capacitor for a boost converter depends on the impedance of the source supply and the amount of input ripple the converter will safely tolerate. For this particular design and lab setup a 560F, 50V Sanyo electrolytic (50MV560AXL), in parallel with two 10F, 100V TDK ceramic capacitors (C5750X5R1H106M) is required (the input and return lead lengths are kept to a few inches, but the peak input current is close to 10A!). As with the output node, check the input ripple with a single oscilloscope probe connected across the input capacitor terminals. VOUT 1V/DIV IL 2A/DIV MOSFET DRAIN VOLTAGE 20V/DIV VIN = 8V IOUT = 0.5A VOUT = 42V D = 81% 1s/DIV 18717 F15 Figure 15. Switching Waveforms for the Converter in Figure 9 at Minimum VIN (8V) 42 - 8 = 3.09A 8 18717fd 21 LTC1871-7 applications information VOUT 1V/DIV 100 95 EFFICIENCY (%) IL 1A/DIV MOSFET DRAIN VOLTAGE 20V/DIV VIN = 8V VIN = 12V VIN = 28V 90 85 80 VIN = 28V IOUT = 0.5A VOUT = 42V D = 27% 1s/DIV 18717 F16 Figure 16. Switching Waveforms for the Converter in Figure 9 at Maximum VIN (28V) PC Board Layout Checklist 1. In order to minimize switching noise and improve output load regulation, the GND pin of the LTC1871-7 should be connected directly to 1) the negative terminal of the INTVCC decoupling capacitor, 2) the negative terminal of the output decoupling capacitors, 3) the bottom terminal of the sense resistor, 4) the negative terminal of the input capacitor and 5) at least one via to the ground plane immediately adjacent to Pin 6. The ground trace on the top layer of the PC board should be as wide and short as possible to minimize series resistance and inductance. 2. Beware of ground loops in multiple layer PC boards. Try to maintain one central ground node on the board and use the input capacitor to avoid excess input ripple for high output current power supplies. If the ground plane is to be used for high DC currents, choose a path away from the small-signal components. 3. Place the CVCC capacitor immediately adjacent to the INTVCC and GND pins on the IC package. This capacitor carries high di/dt MOSFET gate drive currents. A low ESR and ESL 4.7F ceramic capacitor works well here. 4. The high di/dt loop from the bottom terminal of the output capacitor, through the power MOSFET, through the boost diode and back through the output capacitors should be kept as tight as possible to reduce inductive 75 0.001 0.01 0.1 ILOAD (mA) 1 10 18717 F17 Figure 17. Efficiency vs Load Current and Input Voltage for the Converter in Figure 9 ringing. Excess inductance can cause increased stress on the power MOSFET and increase HF noise on the output. If low ESR ceramic capacitors are used on the output to reduce output noise, place these capacitors close to the boost diode in order to keep the series inductance to a minimum. 5. Check the stress on the power MOSFET by measuring its drain-to-source voltage directly across the device terminals (reference the ground of a single scope probe directly to the source pad on the PC board). Beware of inductive ringing which can exceed the maximum specified voltage rating of the MOSFET. If this ringing cannot be avoided and exceeds the maximum rating of the device, either choose a higher voltage device or specify an avalanche-rated power MOSFET. Not all MOSFETs are created equal (some are more equal than others). 6. Place the small-signal components away from high frequency switching nodes. In the layout shown in Figure 18, all of the small-signal components have been placed on one side of the IC and all of the power components have been placed on the other. This also allows the use of a pseudo-Kelvin connection for the signal ground, where high di/dt gate driver currents flow out of the IC ground pin in one direction (to the bottom plate of the INTVCC decoupling capacitor) and small-signal currents flow in the other direction. 18717fd 22 LTC1871-7 applications information 7. Minimize the capacitance between the SENSE pin trace and any high frequency switching nodes. The LTC18717 contains an internal leading edge blanking time of approximately 180ns, which should be adequate for most applications. 8. For optimum load regulation and true remote sensing, the top of the output resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LTC1871-7 in order to keep the high impedance FB node short. VIN L1 R3 RC CC JUMPER R4 PIN 1 R2 R1 CIN LTC1871-7 J1 RT CVCC SWITCH NODE IS ALSO THE HEAT SPREADER FOR L1, M1, D1 M1 RS PSEUDO-KELVIN SIGNAL GROUND CONNECTION COUT COUT D1 VIAS TO GROUND PLANE VOUT TRUE REMOTE OUTPUT SENSING 1871 F18 Figure 18. LTC1871-7 Boost Converter Suggested Layout VIN R3 CC R1 R2 R4 1 RC 2 3 4 RT 5 RUN L1 SENSE VIN ITH LTC1871-7 FB INTVCC FREQ GATE MODE/ SYNC GND 10 J1 SWITCH NODE 9 D1 8 7 6 CVCC M1 + CIN RS GND + PSEUDO-KELVIN GROUND CONNECTION COUT BOLD LINES INDICATE HIGH CURRENT PATHS 18717 F19 VOUT Figure 19. LTC1871-7 Boost Converter Layout Diagram 18717fd 23 LTC1871-7 applications information 9. For applications with multiple switching power converters connected to the same input supply, make sure that the input filter capacitor for the LTC1871-7 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the LTC1871-7. A few inches of PC trace or wire (L 100nH) between the CIN of the LTC1871-7 and the actual source VIN should be sufficient to prevent current sharing problems. the same core the input ripple is reduced along with cost and size. All of the SEPIC applications information that follows assumes L1 = L2 = L. SEPIC Converter Applications where VD is the forward voltage of the diode. For converters where the input voltage is close to the output voltage the duty cycle is near 50%. The LTC1871-7 is also well suited to SEPIC (single-ended primary inductance converter) converter applications. The SEPIC converter shown in Figure 20 uses two inductors. The advantage of the SEPIC converter is the input voltage may be higher or lower than the output voltage, and the output is short-circuit protected. The first inductor, L1, together with the main switch, resembles a boost converter. The second inductor, L2, together with the output diode D1, resembles a flyback or buck-boost converter. The two inductors L1 and L2 can be independent but can also be wound on the same core since identical voltages are applied to L1 and L2 throughout the switching cycle. By making L1 = L2 and winding them on VIN C1 L1 D1 + + * SW L2 COUT SEPIC Converter: Duty Cycle Considerations For a SEPIC converter operating in a continuous conduction mode (CCM), the duty cycle of the main switch is: VO + VD D= VIN + VO + VD IL1 IIN SW ON SW OFF 21a. Input Inductor Current IO IL2 21b. Output Inductor Current IIN IC1 IO VOUT + RL 21c. DC Coupling Capacitor Current * 20a. SEPIC Topology ID1 VIN * VOUT + + + VIN IO 21d. Diode Current RL * 20b. Current Flow During Switch On-Time VIN * + + D1 + VIN * VOUT (AC) VOUT VCOUT RL 18717 F20 20c. Current Flow During Switch Off-Time Figure 20. SEPIC Topology and Current Flow VESR 18717 F21 RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 21e. Output Ripple Voltage Figure 21. SEPIC Converter Switching Waveforms 18717fd 24 LTC1871-7 applications information The maximum output voltage for a SEPIC converter is: D 1 VO(MAX) = ( VIN + VD ) MAX - VD 1- DMAX 1- DMAX The maximum duty cycle of the LTC1871-7 is typically 92%. SEPIC Converter: The Peak and Average Input Currents The control circuit in the LTC1871-7 is measuring the input current (using a sense resistor in the MOSFET source), so the output current needs to be reflected back to the input in order to dimension the power MOSFET properly. Based on the fact that, ideally, the output power is equal to the input power, the maximum input current for a SEPIC converter is: IIN(MAX) = IO(MAX) * DMAX 1- DMAX The peak input current is : D IIN(PEAK) = 1+ * IO(MAX) * MAX 1- DMAX 2 The maximum duty cycle, DMAX, should be calculated at minimum VIN. The constant `' represents the fraction of ripple current in the inductor relative to its maximum value. For example, if 30% ripple current is chosen, then = 0.30 and the peak current is 15% greater than the average. It is worth noting here that SEPIC converters that operate at high duty cycles (i.e., that develop a high output voltage from a low input voltage) can have very high input currents, relative to the output current. Be sure to check that the maximum load current will not overload the input supply. SEPIC Converter: Inductor Selection For most SEPIC applications the equal inductor values will fall in the range of 10H to 100H. Higher values will reduce the input ripple voltage and reduce the core loss. Lower inductor values are chosen to reduce physical size and improve transient response. Like the boost converter, the input current of the SEPIC converter is calculated at full load current and minimum input voltage. The peak inductor current can be significantly higher than the output current, especially with smaller inductors and lighter loads. The following formulas assume CCM operation and calculate the maximum peak inductor currents at minimum VIN: V +V IL1(PEAK) = 1+ *IO(MAX) * O D 2 VIN(MIN) VIN(MIN) + VD IL2(PEAK) = 1+ *IO(MAX) * 2 VIN(MIN) The ripple current in the inductor is typically 20% to 40% (i.e., a range of `' from 0.20 to 0.40) of the maximum average input current occurring at VIN(MIN) and IO(MAX) and IL1 = IL2. Expressing this ripple current as a function of the output current results in the following equations for calculating the inductor value: L= VIN(MIN) IL * f * DMAX where IL = *IO(MAX) * DMAX 1- DMAX By making L1 = L2 and winding them on the same core, the value of inductance in the equation above is replace by 2L due to mutual inductance. Doing this maintains the same ripple current and energy storage in the inductors. For example, a Coiltronix CTX10-4 is a 10H inductor with two windings. With the windings in parallel, 10H inductance is obtained with a current rating of 4A (the number of turns hasn't changed, but the wire diameter has doubled). Splitting the two windings creates two 10H inductors with a current rating of 2A each. Therefore, substituting 2L yields the following equation for coupled inductors: L1= L2 = VIN(MIN) 2 * IL * f * DMAX Specify the maximum inductor current to safely handle IL(PK) specified in the equation above. The saturation current 18717fd 25 LTC1871-7 applications information rating for the inductor should be checked at the minimum input voltage (which results in the highest inductor current) and maximum output current. SEPIC Converter: Power MOSFET Selection Important parameters for the power MOSFET include the drain-to-source breakdown voltage (BVDSS), the threshold voltage (VGS(TH)), the on-resistance (RDS(ON)) versus gateto-source voltage, the gate-to-source and gate-to-drain charges (QGS and QGD, respectively), the maximum drain current (ID(MAX)) and the MOSFET's thermal resistances (RTH(JC) and RTH(JA)). The gate drive voltage is set by the 7V INTVCC low dropout regulator. Consequently, 6V rated threshold MOSFETs are required in most LTC1871-7 applications. The maximum voltage that the MOSFET switch must sustain during the off-time in a SEPIC converter is equal to the sum of the input and output voltages (VO + VIN). As a result, careful attention must be paid to the BVDSS specifications for the MOSFETs relative to the maximum actual switch voltage in the application. Many logic-level devices are limited to 30V or less. Check the switching waveforms directly across the drain and source terminals of the power MOSFET to ensure the VDS remains below the maximum rating for the device. Sense Resistor Selection During the MOSFET's on-time, the control circuit limits the maximum voltage drop across the power MOSFET to about 150mV (at low duty cycle). The peak inductor current is therefore limited to 150mV/RSENSE. The relationship between the maximum load current, duty cycle and the sense resistor is: RSENSE VSENSE(MAX) IO(MAX) * 1 * 1 1+ VO + VD 2 +1 VIN(MIN) 92% due to slope compensation, as shown in Figure 11. The constant `' in the denominator represents the ripple current in the inductors relative to their maximum current. For example, if 30% ripple current is chosen, then = 0.30. Calculating Power MOSFET Switching and Conduction Losses and Junction Temperatures In order to calculate the junction temperature of the power MOSFET, the power dissipated by the device must be known. This power dissipation is a function of the duty cycle, the load current and the junction temperature itself. As a result, some iterative calculation is normally required to determine a reasonably accurate value. Since the controller is using the MOSFET as both a switching and a sensing element, care should be taken to ensure that the converter is capable of delivering the required load current over all operating conditions (load, line and temperature) and for the worst-case specifications for VSENSE(MAX) and the RDS(ON) of the MOSFET listed in the manufacturer's data sheet. The power dissipated by the MOSFET in a SEPIC converter is: 2 D PFET = IO(MAX) * * RDS(ON) * D * T 1- D + k * ( VIN + VO ) *IO(MAX) * 2 D *C *f 1- D RSS The first term in the equation above represents the I2R losses in the device and the second term, the switching losses. The constant k = 1.7 is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. The T term accounts for the temperature coefficient of the RDS(ON) of the MOSFET, which is typically 0.4%/C. Figure 12 illustrates the variation of normalized RDS(ON) over temperature for a typical power MOSFET. The VSENSE(MAX) term is typically 150mV at low duty cycle and is reduced to about 100mV at a duty cycle of 18717fd 26 LTC1871-7 applications information From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula: TJ = TA + PFET * RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. This value of TJ can then be used to check the original assumption for the junction temperature in the iterative calculation process. SEPIC Converter: Output Diode Selection To maximize efficiency, a fast-switching diode with low forward drop and low reverse leakage is desired. The output diode in a SEPIC converter conducts current during the switch off-time. The peak reverse voltage that the diode must withstand is equal to VIN(MAX) + VO. The average forward current in normal operation is equal to the output current, and the peak current is equal to: ID(PEAK) = 1+ * IO(MAX) * 2 + 1 VIN(MIN) VO + VD The power dissipated by the diode is: PD = IO(MAX) * VD and the diode junction temperature is: TJ = TA + PD * RTH(JA) The RTH(JA) to be used in this equation normally includes the RTH(JC) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. SEPIC Converter: Output Capacitor Selection Because of the improved performance of today's electrolytic, tantalum and ceramic capacitors, engineers need to consider the contributions of ESR (equivalent series resistance), ESL (equivalent series inductance) and the bulk capacitance when choosing the correct component for a given output ripple voltage. The effects of these three parameters (ESR, ESL, and bulk C) on the output voltage ripple waveform are illustrated in Figure 21 for a typical coupled-inductor SEPIC converter. The choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the ESR step and the charging/discharging V. For the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the ESR step and the charging/discharging V. This percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. For a 1% contribution to the total ripple voltage, the ESR of the output capacitor can be determined using the following equation: 0.01* VO ESRCOUT ID(PEAK) where: V +V D ID(PEAK) = 1+ * IO(MAX) * O + 1 2 VIN(MIN) For the bulk C component, which also contributes 1% to the total ripple: IO(MAX) COUT 0.01* VO * f For many designs it is possible to choose a single capacitor type that satisfies both the ESR and bulk C requirements for the design. In certain demanding applications, however, the ripple voltage can be improved significantly by connecting two or more types of capacitors in parallel. For example, using a low ESR ceramic capacitor can minimize the ESR step, while an electrolytic or tantalum capacitor can be used to supply the required bulk C. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform 18717fd 27 LTC1871-7 applications information should be verified on a dedicated PC board (see Board Layout section for more information on component placement). Lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look significantly worse than they would be on a properly designed PC board. The output capacitor in a SEPIC regulator experiences high RMS ripple currents, as shown in Figure 21. The RMS output capacitor ripple current is: IRMS(COUT) = IO(MAX) * VO VIN(MIN) Note that the ripple current ratings from capacitor manufacturers are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. Several capacitors may also be placed in parallel to meet size or height requirements in the design. In surface mount applications, multiple capacitors may have to be placed in parallel in order to meet the ESR or RMS current handling requirements of the application. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount packages. In the case of tantalum, it is critical that the capacitors have been surge tested for use in switching power supplies. Also, ceramic capacitors are now available with extremely low ESR, ESL and high ripple current ratings. SEPIC Converter: Input Capacitor Selection The input capacitor of a SEPIC converter is less critical than the output capacitor due to the fact that an inductor is in series with the input and the input current waveform is triangular in shape. The input voltage source impedance determines the size of the input capacitor which is typically in the range of 10F to 100F. A low ESR capacitor is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a SEPIC converter is: 1 IRMS(CIN) = * IL 12 Please note that the input capacitor can see a very high surge current when a battery is suddenly connected to the input of the converter and solid tantalum capacitors can fail catastrophically under these conditions. Be sure to specify surge-tested capacitors! SEPIC Converter: Selecting the DC Coupling Capacitor The coupling capacitor C1 in Figure 20 sees nearly a rectangular current waveform as shown in Figure 21. During the switch off-time the current through C1 is IO(VO/VIN) while approximately -IO flows during the on-time. This current waveform creates a triangular ripple voltage on C1: IO(MAX) VO VC1(P-P) = * C1* f VIN + VO + VD The maximum voltage on C1 is then: VC1(P-P) VC1(MAX) = VIN + 2 which is typically close to VIN(MAX). The ripple current through C1 is: V +V IRMS(C1) = IO(MAX) * O D VIN(MIN) The value chosen for the DC coupling capacitor normally starts with the minimum value that will satisfy 1) the RMS current requirement and 2) the peak voltage requirement (typically close to VIN). Low ESR ceramic and tantalum capacitors work well here. 18717fd 28 LTC1871-7 Typical Applications A 48V Input Flyback Converter Configurable to 3.3V or 5V Outputs VIN 36V TO 72V 0.1F 100k 1 2 1nF 100k MMBTA42 R1 604k 26.7k 82.5k 4 5 12.4k 3 RUN VIN ITH GATE LTC1871-7 SENSE FREQ MODE/SYNC INTVCC VFB GND 10V CTX-002-15242 T1A * * 2.2F 100V UPS840 100F 6.3V x3 T1B VOUT 3.3V 3A MAX 9 7 Q1 FDC2512 10 8 4.7F R3 0.1 6 ALL CAPACITORS ARE CERAMIC X5R TYPE R2* 21k *R2 = 38.3k FOR VOUT = 5V 18717 TA02a Output Efficiency at 3.3V Output Output Efficiency at 5V Output 90 90 48VIN 80 72VIN 75 70 65 60 36VIN 85 36VIN EFFICIENCY (%) EFFICIENCY (%) 85 48VIN 80 72VIN 75 70 65 0 1 2 3 4 5 6 ILOAD (A) 18717 TA02b 60 0 1 2 3 ILOAD (A) 4 5 18717 TA02c 18717fd 29 LTC1871-7 typical applications 1.2A Automotive LED Headlamp Boost Converter D3 IRF12CW10 L1 VIN + C5 47F 20V x2 GND R6 1M 1% 1 RUN INPUT R8 187k 1% 2 C8 100nF 3 4 5 R10 300k SENSE RUN VIN ITH LTC1871-7 FB INTVCC FREQ GATE MODE/SYNC GND R13 17.8k 0V TO 5V DIMMING INPUT 10 9 8 Q3 SILICONIX SUP75N08-9L 7 C9 4.7F X5R 6 R12 4.02k C10 4.7F R15 0.20 0.5W TO LEDS C7 10F 100V R7 4.7M R9 1k D4 USE 68V 33V OR 75V D5 SINGLE 33V ZENER R11 0.006 D6 5V R14 1k FROM LEDS 18717 TA01 C5: SANYO OS-CON 20SP47M C7: ITW PAKTRON 106K100CS4 L1: MAGNETICS INC 58206-A2 WITH 29T 18AWG Dual Output Cell Phone Base Station Flyback Converter TAB GND LT1963 L1 10H VIN 18V TO 33V C6 1F 35V + T1 VP4-0047 C5 22F 50V C7 3.3F 50V R4 75 D2 10V R5 150k 1 2 3 4 SYNC SIGNAL 320kHz 0V TO 2.5V 5 R11 12.5k C14 1nF VIN ITH LTC1871-7 FB INTVCC FREQ GATE MODE/SYNC GND R12 80k R1 33k SENSE RUN 4 9 D4 BAT54 D1 1A 40V 1 7 2 3 4 5.5V 500mA C4 33F 8 5 3.3V 2A C10 330nF D3 UPS840 C12 15nF R9 33k 8 Q1 Si4482DY 6 5 C9 R6 1nF 1 9 7 R2 12.5k R3 43.2k C3 100F 6 10 1 C11 100F 2 3 C15 4.7F C17 1F 2 11 3 10 C8 100pF 200V R7 33k 1 12 SHDN IN GND OUT ADJ R13 0.082 4 R14 1k C16 10nF 1kV ISO1 MOC207 LT1431 COL REF COMP RMID V+ GNDF RTOP GNDS R8 20.5k 8 7 6 C13A 470F R10 64.9k + 5 C3, C11: TDK C3225X5R0J107M C4: SANYO POSCAP 10 TPB33M C7: TDK C4532X7R1H335M C13, C13A: SANYO POSCAP 4TPB470M L1: COILCRAFT DO1608 103 T1: COILTRONICS VP4-0047 + C13 470F 18717 TA03 18717fd 30 LTC1871-7 typical applications Automotive SEPIC Converter T1 VP5-0155 R46 47k VBATT 8V TO 25V 4* Q6 FMMT451 CR4 BZX84C15V R37 75k 1% * 1 C50 C46 4F 100pF X7R 12 5* 8 * 2 11 6* 7 * 3 C52 4.7F X7R x2 10 1 3 R45 33.2k C47 6800pF 4 R47 133k 1% 5 RUN VIN SENSE 10 ITH LTC1871-7 INTVCC FB FREQ MODE/SYNC GND 6 GATE CR22 1N4148 L7 150 3A BEAD 1B (OPTIONAL HF FILTER) CR21 MBR10100 9 2 R43 13.3k 1% 9 Q9 Si4486EY SO-8 8 7 + C49 4.7F R59 0.005 1W 1% R60 124k 1% C53 22F 16V X5R x2 C55 4.7F 16V X7R x2 + C51 150F 35V VOUT 13.5V 3A C57 10F X5R (OPTIONAL HF FILTER) R61 12.4k 1% 18717 TA04 18717fd 31 LTC1871-7 Package Description MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661 Rev E) 0.889 0.127 (.035 .005) 5.23 (.206) MIN 3.20 - 3.45 (.126 - .136) 3.00 0.102 (.118 .004) (NOTE 3) 0.50 0.305 0.038 (.0197) (.0120 .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 10 9 8 7 6 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) DETAIL "A" 0.497 0.076 (.0196 .003) REF 0 - 6 TYP GAUGE PLANE 1 2 3 4 5 0.53 0.152 (.021 .006) DETAIL "A" 0.18 (.007) SEATING PLANE 0.86 (.034) REF 1.10 (.043) MAX 0.17 - 0.27 (.007 - .011) TYP 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.1016 0.0508 (.004 .002) MSOP (MS) 0307 REV E 18717fd 32 LTC1871-7 Revision History (Revision history begins at Rev D) REV DATE DESCRIPTION D 11/11 Corrected part numbers from LT to LTC in the Order Information section. PAGE NUMBER 2 18717fd Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 33 LTC1871-7 Typical Application A Small, Nonisolated 12V Flyback Telecom Housekeeping Supply D3 VIN 36V TO 72V R5 100k D1 9.1V UV+ = 31.8V - = 29.5V UV CC2 47pF T1 1, 2, 3 (SERIES) Q1 4, 5, 6 (PARALLEL) * C1 1nF OPTIONAL CIN 2.2F 100V X7R * R2 26.7k 1% R1 604k 1% R6 10 SENSE RUN COUT 47F X5R VOUT 12V 0.4A D2 VIN ITH LTC1871-7 FB RC 3.4k CC1 2.2nF R4 110k 1% R3 12.4k 1% INTVCC FREQ GATE MODE/SYNC GND RT 120k f = 200kHz T1: COILTRONICS VP1-0076 M1: FAIRCHILD FDC2512 (150V, 0.5) Q1: ZETEX FMMT625 (120V) M1 C2 4.7F X5R C3 0.1F X5R RS 0.12 D1: ON SEMICONDUCTOR MMBZ5239BLT1 (9.1V) D2: ON SEMICONDUCTOR MMSD4148T11 D3: INTERNATIONAL RECTIFIER 10BQ060 18717 TA05 Related Parts PART NUMBER DESCRIPTION COMMENTS LT 1619 Current Mode PWM Controller 300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology LTC1624 Current Mode DC/DC Controller SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design; VIN Up to 36V (R) LTC1700 No RSENSE Synchronous Step-Up Controller Up to 95% Efficiency, Operation as Low as 0.9V Input LTC1871 Wide Input Range, No RSENSE Controller Operation as Low as 2.5V Input, Boost Flyback,SEPIC LTC1872 SOT-23 Boost Controller Delivers Up to 5A, 550kHz Fixed Frequency, Current Mode LT1930 1.2MHz, SOT-23 Boost Converter Up to 34V Output, 2.6V VIN 16V, Miniature Design LT1931 Inverting 1.2MHz, SOT-23 Converter Positive-to-Negative DC/DC Conversion, Miniature Design LTC3401/LTC3402 1A/2A 3MHz Synchronous Boost Converters Up to 97% Efficiency, Very Small Solution, 0.5V VIN 5V LTC3803 SOT-23 Flyback Controller Adjustable Slope Compensation, Internal Soft-Start, Current Mode 200kHz Operation LTC3806 Synchronous Flyback Controller High Efficiency, Improves Cross Regulation in Multiple Output Designs, Current Mode, 3mm x 4mm 12-Pin DFN Package 18717fd 34 Linear Technology Corporation LT 1111 REV D * PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2002