SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DHighest-Performance Floating-Point Digital
Signal Processor (DSP): TMS320C6713B
− Eight 32-Bit Instructions/Cycle
− 32/64-Bit Data Word
− 300-, 225-, 200-MHz (GDP and ZDP), and
225-, 200-, 167-MHz (PYP) Clock Rates
− 3.3-, 4.4-, 5-, 6-Instruction Cycle Times
− 2400/1800, 1800/1350, 1600/1200, and
1336/1000 MIPS/MFLOPS
− Rich Peripheral Set, Optimized for Audio
− Highly Optimized C/C++ Compiler
− Extended Temperature Devices Available
DAdvanced Very Long Instruction Word
(VLIW) TMS320C67x DSP Core
− Eight Independent Functional Units:
− 2 ALUs (Fixed-Point)
− 4 ALUs (Floating-/Fixed-Point)
− 2 Multipliers (Floating-/Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
DInstruction Set Features
− Native Instructions for IEEE 754
− Single- and Double-Precision
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation; Bit-Field Extract, Set, Clear;
Bit-Counting; Normalization
DL1/L2 Memory Architecture
− 4K-Byte L1P Program Cache
(Direct-Mapped)
− 4K-Byte L1D Data Cache (2-Way)
− 256K-Byte L2 Memory Total: 64K-Byte
L2 Unified Cache/Mapped RAM, and
192K-Byte Additional L2 Mapped RAM
DDevice Configuration
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot
− Endianness: Little Endian, Big Endian
D32-Bit External Memory Interface (EMIF)
− Glueless Interface to SRAM, EPROM,
Flash, SBSRAM, and SDRAM
− 512M-Byte Total Addressable External
Memory Space
DEnhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
D16-Bit Host-Port Interface (HPI)
DTwo McASPs
− Two Independent Clock Zones Each
(1 TX and 1 RX)
− Eight Serial Data Pins Per Port:
Individually Assignable to any of the
Clock Zones
− Each Clock Zone Includes:
− Programmable Clock Generator
− Programmable Frame Sync Generator
− TDM Streams From 2-32 Time Slots
− Support for Slot Size:
8, 12, 16, 20, 24, 28, 32 Bits
− Data Formatter for Bit Manipulation
− Wide Variety of I2S and Similar Bit
Stream Formats
− Integrated Digital Audio Interface
Transmitter (DIT) Supports:
− S/PDIF, IEC60958-1, AES-3, CP-430
Formats
− Up to 16 transmit pins
− Enhanced Channel Status/User Data
− Extensive Error Checking and Recovery
DTwo Inter-Integrated Circuit Bus (I2C Bus)
Multi-Master and Slave Interfaces
DTwo Multichannel Buffered Serial Ports:
− Serial-Peripheral-Interface (SPI)
− High-Speed TDM Interface
− AC97 Interface
DTwo 32-Bit General-Purpose Timers
DDedicated GPIO Module With 16 pins
(External Interrupt Capable)
DFlexible Phase-Locked-Loop (PLL) Based
Clock Generator Module
DIEEE-1149.1 (JTAG†)
Boundary-Scan-Compatible
D208-Pin PowerPAD PQFP (PYP)
D272-BGA Packages (GDP and ZDP)
D0.13-µm/6-Level Copper Metal Process
− CMOS Technology
D3.3-V I/Os, 1.2‡-V Internal (GDP/ZDP/ PYP)
D3.3-V I/Os, 1.4-V Internal (GDP/ZDP) [300
MHz]
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2006, Texas Instruments Incorporated
TMS320C67x and PowerPAD are trademarks of Texas Instruments.
I2C Bus is a trademark of Philips Electronics N.V. Corporation
All trademarks are the property of their respective owners.
†IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
‡These values are compatible with existing 1.26-V designs.
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"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
2POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table of Contents
EMIF device speed 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMIF big endian mode correctness 97. . . . . . . . . . . . . . . .
bootmode 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
absolute maximum ratings over operating case
temperature range 99. . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions 99. . . . . . . . . . . . . . . .
electrical characteristics over recommended ranges of
supply voltage and operating case temperature 100
parameter measurement information 101. . . . . . . . . . . . . .
signal transition levels 101. . . . . . . . . . . . . . . . . . . . . . . . . . .
timing parameters and board routing analysis 103. . . . . .
input and output clocks 105. . . . . . . . . . . . . . . . . . . . . . . . . .
asynchronous memory timing 108. . . . . . . . . . . . . . . . . . . .
synchronous-burst memory timing 111. . . . . . . . . . . . . . . . .
synchronous DRAM timing 113. . . . . . . . . . . . . . . . . . . . . . .
HOLD/HOLDA timing 119. . . . . . . . . . . . . . . . . . . . . . . . . . .
BUSREQ timing 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
reset timing 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
external interrupt timing 123. . . . . . . . . . . . . . . . . . . . . . . . .
multichannel audio serial port (McASP) timing 124. . . . . .
inter-integrated circuits (I2C) timing 127. . . . . . . . . . . . . . .
host-port interface timing 129. . . . . . . . . . . . . . . . . . . . . . . .
multichannel buffered serial port timing 132. . . . . . . . . . . .
timer timing 142. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
general-purpose input/output (GPIO) port timing 143. . . .
JTAG test-port timing 144. . . . . . . . . . . . . . . . . . . . . . . . . . .
mechanical data 145. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
revision history 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GDP and ZDP 272-Ball BGA package (bottom view) 5. . . . .
PYP PowerPAD QFP package (top view) 10. . . . . . . . . . . .
description 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device characteristics 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
functional block and CPU (DSP core) diagram 13. . . . . . . . . .
CPU (DSP core) description 14. . . . . . . . . . . . . . . . . . . . . . . . .
memory map summary 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
peripheral register descriptions 18. . . . . . . . . . . . . . . . . . . . . . .
signal groups description 27. . . . . . . . . . . . . . . . . . . . . . . . . . . .
device configurations 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
configuration examples 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
debugging considerations 47. . . . . . . . . . . . . . . . . . . . . . . . . . .
terminal functions 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
development support 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
device support 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CPU CSR register description 68. . . . . . . . . . . . . . . . . . . . . . . .
cache configuration (CCFG) register description 70. . . . . . . .
interrupts and interrupt selector 71. . . . . . . . . . . . . . . . . . . . . . .
external interrupt sources 73. . . . . . . . . . . . . . . . . . . . . . . . . . . .
EDMA module and EDMA selector 74. . . . . . . . . . . . . . . . . . . .
PLL and PLL controller 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
multichannel audio serial port (McASP) peripherals 84. . . . .
I2C 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
general-purpose input/output (GPIO) 90. . . . . . . . . . . . . . . . . .
power-down mode logic 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
power-supply sequencing 93. . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 1149.1 JTAG compatibility statement 95. . . . . . . . . . . . .
power-supply decoupling 94. . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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REVISION HISTORY
The TMS320C6713B device-specific documentation has been split from TMS320C6713, TMS320C6713B Float-
ing−Point Digital Signal Processors, literature number SPRS186K, into a separate Data Sheet, literature number
SPRS294. It also highlights technical changes made to SPRS294 to generate SPRS294A. These changes are
marked by “[Revision A].” Additionally, made changes to SPRS294A to generate SPRS294B. These changes
are marked by “[Revision B].” Both Revision A and B changes are noted in the Revision History table below.
Scope: Updated information on McASP, McBSP and JTAG for clarification. Changed Pin Description for A12 and
B11 (Revisions SPRS294 and SPRS294A). Updated Nomenclature figure by adding device−specific information
for the ZDP package. TI Recommends for new designs that the following pins be configured as such:
DPin A12 connected directly to CVDD (core power)
DPin B11 connected directly to Vss (ground)
PAGE(S)
NO. ADDITIONS/CHANGES/DELETIONS
6Terminal Assignments for the 272-Ball GDP and ZDP Packages (in Order of Ball No.) table:
Updated Signal Name for Ball No. A12
Updated Signal Name for Ball No. B11
10 PYP PowerPAD QFP package (top view):
Updated drawing
32 Device Configurations, device configurations at device reset section:
Updated “For proper device operation...” paragraph [Revision B]
33 Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section:
Removed “CE1 width 32−bit” from Functional Description for “00” in HD[4:3](BOOTMODE) Configuration Pin
33 Device Configurations, Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0) section:
Updated “All other HD pins...” footnote [Revision B]
37 Table 22 Peripheral Pin Selection Matrix:
Updated/changed MCBSP0DIS (DEVCFG bit) from “ACLKKO” to “ACLKXO”
46 Configuration Example F (1 McBSP + HPI + 1 McASP) figure:
Updated from McBSP1DIS = 1 to McBSP1DIS = 0
47 Device Configurations, debugging considerations section:
Updated “Internal pullup/pulldown resistors...” paragraph [Revision B]
49 Terminal Functions, Resets and Interrupts section:
Updated IPU/IPD for RESET Signal Name from “IPU” to “−−”
50 Terminal Functions table, Host Port Interface section:
Removed “CE1 width 32−bit” from Description for “00” in Bootmode HD[4:3]
50 Terminal Functions table, Host Port Interface section:
Updated “Other HD pins...” paragraph [Revision B]
55 Terminal Functions, Timer 1 section:
Updated Description for TINP1/AHCLKX0 Signal Name
57 Terminal Functions, Reserved for Test section:
Updated Description for RSV Signal Name, 181 PYP, A12 GDP/ZDP
Updated Description for RSV Signal Name, 180 PYP, B11 GDP/ZDP
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
4POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PAGE(S)
NO. ADDITIONS/CHANGES/DELETIONS
57 Terminal Functions, Reserved for Test section:
Updated/changed Description for RSV Signal Name, A12 GDP (to “recommended”) − [Revision A]
Updated/changed Description for RSV Signal Name, B11 GDP (to “recommended”) − [Revision A]
57 Terminal Functions, Reserved for Test section:
Updated/changed Description for RSV Signal Name D12 to include PYP 178 as follows:
“...the D12/178 pin must be externally pulled down with a 10−kΩ resistor.” [Revision B]
66 Device Support, device and development-support tool nomenclature section:
Updated figure for clarity
67 Device Support, document support section:
Updated paragraphs for clarity
92 Power−Down Mode Logic − Triggering, Wake−up and Effects section:
Updated paragraphs [Revision B]
93 Power−Down Mode Logic − Triggering, Wake−up and Effects section, Characteristics of the Power-Down Modes table:
Added “It is recommended to use the PLLPWDN bit (PLLCSR.1) as an alternative to PD3” to PRWD Field (BITS 15−10) −
011100 − Effect on Chip’s Operation [Revision B]
93 Power−Down Mode Logic − Triggering, Wake−up and Effects section, Characteristics of the Power-Down Modes table:
Deleted three paragraphs following table [Revision B]
95 IEEE 1149.1 JTAG Compatibility Statement section:
Updated/added paragraphs for clarity
96 EMIF Device Speed section, Example Boards and Maximum EMIF Speed table:
Type − 3−Loads Short Traces, EMIF Interface Components section:
Updated from “32−Bit SDRAMs” to “16−Bit SDRAMs” [Revision B]
95 IEEE 1149.1 JTAG Compatibility Statement section:
Updated/added paragraphs for clarity
99 Recommended Operating Conditions:
Added VOS, Maximum voltage during overshoot row and associated footnote
Added VUS, Maximum voltage during undershoot row and associated footnote
102 Parameter Measurement Information, AC transient rise/fall time specifications section:
Added AC Transient Specification Rise Time figure
Added AC Transient Specification Fall Time figure
124 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING:
timing requirements for McASP section:
Updated Parameter No. 3, tc(ACKRX), from “33” to “greater of 2P or 33 ns” and added associated footnote
124 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING:
switching characteristics over recommended operating conditions for McASP section:
Updated Parameter No. 11, tc(ACKRX), from “33” to “greater of 2P or 33 ns” and added associated footnote
125, 126 MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING section:
Updated McASP Input and Output drawings
134 MULTICHANNEL BUFFERED SERIAL PORT TIMING section:
switching characteristics over recommended operating conditions for McBSP section:
Updated McBSP Timings figure
147 Mechanical Data section:
Added statement to the Packaging Information section
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
GDP and ZDP 272-Ball BGA package (bottom view)
0 0
1 0
0 0
0 0 0 2 0
0 0
3 4 0 0
536
7893:;
526;
7892:;
0 3 <
2 0
0
=4;
546
=;
=1 0 =2;
56
=;
4
0 1
=0
;
;
0
=2;
526
=;
56
0 0
0 0 0 0
0
0
;
;
0
0
=3;
536
=;
56
0
=<;
5<6 =3;
=18 0 0
0 0
<
0 0
0 0 0 0
0
0 0
0
0
0
0
0
0
0
0
0
23 <4 23<4
>
?
0
1
@
=
0
?;
?;
?
0 1 0 0 0 0
=;
56
=;
56 0 =;
56
0
0 4 0 2 < 0
> 1 1 1;
56
0 3
0
0
0
0
0
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 0 0 0 0 0 0 =;
8 0 =;
856
56
789:
1;
0 56
789: 0 0
3 2
0 0
=;
856
=;
18
=;
8526
2 3 0
0
0
0 =;
8536 0 =;
856
;
8526 ;
=18 0 0
0 0
;
856
;
856
18;
18 0
0 4 0
0
< 4
0 =;
856
=;
856
=;?;
856
8;
8
0 0 <
1;
1 0
8;
856
0 0 =>;
1
==?;
;
1;
856
;
0 0 0 2 3
;
856 0 0
;
856
= =
A
=;
56
8 8;
8536
18;
0 0 0
0 0 1;
=1 0 0 0
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
6POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 1. Terminal Assignments for the 272-Ball GDP and ZDP Packages (in Order of Ball No.)
BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME
A1 VSS C1 GP[5](EXT_INT5)/AMUTEIN0
A2 VSS C2 GP[4](EXT_INT4)/AMUTEIN1
A3 CLKIN C3 CVDD
A4 CVDD C4 CLKMODE0
A5 RSV C5 PLLHV
A6 TCK C6 VSS
A7 TDI C7 CVDD
A8 TDO C8 VSS
A9 CVDD C9 VSS
A10 CVDD C10 DVDD
A11 VSS C11 EMU4
A12 RSV [connect directly to CVDD] C12 RSV
A13 RESET C13 NMI
A14 VSS C14 HD14/GP[14]
A15 HD13/GP[13] C15 HD12/GP[12]
A16 HD11/GP[11] C16 HD9/GP[9]
A17 DVDD C17 HD6/AHCLKR1
A18 HD7/GP[3] C18 CVDD
A19 VSS C19 HD4/GP[0]
A20 VSS C20 HD3/AMUTE1
B1 VSS D1 DVDD
B2 CVDD D2 GP[6](EXT_INT6)
B3 DVDD D3 EMU2
B4 VSS D4 VSS
B5 RSV D5 CVDD
B6 TRST D6 CVDD
B7 TMS D7 RSV
B8 DVDD D8 VSS
B9 EMU1 D9 EMU0
B10 EMU3 D10 CLKOUT3
B11 RSV [connect directly to VSS] D11 CVDD
B12 EMU5 D12 RSV
B13 DVDD D13 VSS
B14 HD15/GP[15] D14 CVDD
B15 VSS D15 CVDD
B16 HD10/GP[10] D16 DVDD
B17 HD8/GP[8] D17 VSS
B18 HD5/AHCLKX1 D18 HD2/AFSX1
B19 CVDD D19 DVDD
B20 VSS D20 HD1/AXR1[7]
Shading denotes the GDP and ZDP package pin functions that drop out on the PYP package.
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Table 1. Terminal Assignments for the 272-Ball GDP and ZDP Package (in Order of Ball No.) (Continued)
BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME
E1 CLKS1/SCL1 J17 HOLD
E2 VSS J18 HOLDA
E3 GP[7](EXT_INT7) J19 BUSREQ
E4 VSS J20 HINT/GP[1]
E17 VSS K1 CVDD
E18 HAS/ACLKX1 K2 VSS
E19 HDS1/AXR1[6] K3 CLKS0/AHCLKR0
E20 HD0/AXR1[4] K4 CVDD
F1 TOUT1/AXR0[4] K9 VSS
F2 TINP1/AHCLKX0 K10 VSS
F3 DVDD K11 VSS
F4 CVDD K12 VSS
F17 CVDD K17 CVDD
F18 HDS2/AXR1[5] K18 ED0
F19 VSS K19 ED1
F20 HCS/AXR1[2] K20 VSS
G1 TOUT0/AXR0[2] L1 FSX1
G2 TINP0/AXR0[3] L2 DX1/AXR0[5]
G3 CLKX0/ACLKX0 L3 CLKX1/AMUTE0
G4 VSS L4 CVDD
G17 VSS L9 VSS
G18 HCNTL0/AXR1[3] L10 VSS
G19 HCNTL1/AXR1[1] L11 VSS
G20 HR/W/AXR1[0] L12 VSS
H1 FSX0/AFSX0 L17 CVDD
H2 DX0/AXR0[1] L18 ED2
H3 CLKR0/ACLKR0 L19 ED3
H4 VSS L20 CVDD
H17 VSS M1 CLKR1/AXR0[6]
H18 DVDD M2 DR1/SDA1
H19 HRDY/ACLKR1 M3 FSR1/AXR0[7]
H20 HHWIL/AFSR1 M4 VSS
J1 DR0/AXR0[0] M9 VSS
J2 DVDD M10 VSS
J3 FSR0/AFSR0 M11 VSS
J4 VSS M12 VSS
J9 VSS M17 VSS
J10 VSS M18 DVDD
J11 VSS M19 ED4
J12 VSS M20 ED5
Shading denotes the GDP and ZDP package pin functions that drop out on the PYP package.
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8POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 1. Terminal Assignments for the 272-Ball GDP and ZDP Package (in Order of Ball No.) (Continued)
BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME
N1 SCL0 U9 VSS
N2 SDA0 U10 CVDD
N3 ED31 U11 CVDD
N4 VSS U12 DVDD
N17 VSS U13 VSS
N18 ED6 U14 CVDD
N19 ED7 U15 CVDD
N20 ED8 U16 DVDD
P1 ED28 U17 VSS
P2 ED29 U18 EA21
P3 ED30 U19 BE1
P4 VSS U20 VSS
P17 VSS V1 ED20
P18 ED9 V2 ED19
P19 VSS V3 CVDD
P20 ED10 V4 ED16
R1 DVDD V5 BE3
R2 ED27 V6 CE3
R3 ED26 V7 EA3
R4 CVDD V8 EA5
R17 CVDD V9 EA8
R18 DVDD V10 EA10
R19 ED11 V11 ARE/SDCAS/SSADS
R20 ED12 V12 AWE/SDWE/SSWE
T1 ED24 V13 DVDD
T2 ED25 V14 EA12
T3 DVDD V15 DVDD
T4 VSS V16 EA17
T17 VSS V17 CE0
T18 ED13 V18 CVDD
T19 ED15 V19 DVDD
T20 ED14 V20 BE0
U1 ED22 W1 VSS
U2 ED21 W2 CVDD
U3 ED23 W3 DVDD
U4 VSS W4 ED17
U5 DVDD W5 VSS
U6 CVDD W6 CE2
U7 DVDD W7 EA4
U8 VSS W8 EA6
Shading denotes the GDP and ZDP package pin functions that drop out on the PYP package.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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Table 1. Terminal Assignments for the 272-Ball GDP and ZDP Package (in Order of Ball No.) (Continued)
BALL NO. SIGNAL NAME BALL NO. SIGNAL NAME
W9 DVDD Y5 ARDY
W10 AOE/SDRAS/SSOE Y6 EA2
W11 VSS Y7 DVDD
W12 DVDD Y8 EA7
W13 EA11 Y9 EA9
W14 EA13 Y10 ECLKOUT
W15 EA15 Y11 ECLKIN
W16 VSS Y12 CLKOUT2/GP[2]
W17 EA19 Y13 VSS
W18 CE1 Y14 EA14
W19 CVDD Y15 EA16
W20 VSS Y16 EA18
Y1 VSS Y17 DVDD
Y2 VSS Y18 EA20
Y3 ED18 Y19 VSS
Y4 BE2 Y20 VSS
Shading denotes the GDP and ZDP package pin functions that drop out on the PYP package.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PYP PowerPAD QFP package (top view)
TRST
HD5/AHCLKX1
HD8/GP[8]
HD6/AHCLKR1
HD7/GP[3]
HD9/GP[9]
HD10/GP[10]
HD11/GP[11]
HD12/GP[12]
HD13/GP[13]
HD14/GP[14]
HD15/GP[15]
NMI
RSV
RSV
EMU1
EMU0
TDO
TDI
TMS
TCK
RSV
RSV
CLKIN
CLKMODE0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
HD4/GP[0]
HD2/AFSX1
HD3/AMUTE1
HD1/AXR1[7]
HD0/AXR1[4]
HCNTL0/AXR1[3]
HCNTL1/AXR1[1]
HR/
HHWIL/AFSR1
BUSREQ
HINT
ED0
ED1
ED2
ED3
ED5
ED4
ED8
ED7
ED6
ED10
ED9
ED12
ED11
ED14
ED15
ED13
EA21
EA20
EA19
EA17
EA18
EA15
EA12
EA16
EA13
EA14
EA11
CLKOUT2/GP[2]
ECLKIN
ECLKOUT
EA10
EA9
EA7
EA8
EA6
EA5
EA4
EA3
EA2
ARDY
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
GP[4](EXT_INT4)/AMUTEIN1
GP[6](EXT_INT6)
GP[5](EXT_INT5)/AMUTEIN0
DD
GP[7](EXT_INT7)
CLKS1/SCL1
TINP1/AHCLKX0
TOUT1/AXR0[4]
CLKX0/ACLKX0
TINP0/AXR0[3]
TOUT0/AXR0[2]
CLKR0/ACLKR0
DX0/AXR0[1]
FSX0/AFSX0
FSR0/AFSR0
DR0/AXR0[0]
CLKS0/AHCLKR0
FSX1
DX1/AXR0[5]
CLKX1/AMUTE0
CLKR1/AXR0[6]
DR1/SDA1
FSR1/AXR0[7]
SCL0
SDA0
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
RESET
/GP[1]
W/AXR1[0]
HAS/ACLKX1
HCS/AXR1[2]
HDS1/AXR1[6]
HDS2/AXR1[5]
HRDY/ACLKR1
CE3
CE2
CE1
CE0
BE1
BE0
HOLDA
HOLD
ARE/SDCAS/SSADS
AOE/SDRAS/SSOE
AWE/SDWE/SSWE
DVDD
DVDD
RSV
PLLHV
CLKOUT3
DV
DVDD
DD
DV
DD
DV
DD
DV DD
DV
DD
DV
DVDD
DVDD
DVDD
DVDD
DD
CV
CVDD
DVDD
DVDD
CVDD
CVDD
CVDD
CVDD
DD
CV
DD
CV
DD
CV
CVDD
CVDD
DD
CV
CVDD
DD
CV
DD
CV
DD
CV
DD
CV
CVDD
CVDD
DD
CV
DD
CV
CVDD
CVDD
VSS
VSS
VSS
SS
V
VSS
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
VSS
SS
V
VSS
VSS
SS
V
VSS
SS
V
SS
V
VSS
VSS
VSS
SS
V
VSS
RSV
VSS
SS
V
DD
CV
DVDD
DD
DV
DD
CV
DD
CV
DD
DV
SS
V
DD
CV
DVDD
VSS
CVDD
DD
DV
DD
CV
VSS
CVDD
CVDD
PYP 208-PIN PowerPAD PLASTIC QUAD FLATPACK (PQFP)
(TOP VIEW)
VSS
CVDD
VSS
NOTE: All linear dimensions are in millimeters. This pad is electrically and thermally connected to the backside of the die.
For the TMS320C6713B 208-Pin PowerPAD plastic quad flatpack, the external thermal pad dimensions are: 7.2 x 7.2 mm and the thermal
pad is externally flush with the mold compound.
6,79
8,30
Exposed
Thermal
PAD
6,79
8,30
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
description
The TMS320C67xt DSPs (including the TMS320C6713B device†) compose the floating-point DSP generation
in the TMS320C6000t DSP platform. The C6713B device is based on the high-performance, advanced
very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an
excellent choice for multichannel and multifunction applications.
Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS),
1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million
multiply-accumulate operations per second (MMACS).
Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS),
2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million
multiply-accumulate operations per second (MMACS).
The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The
Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte
2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is
shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as
mapped me m o r y, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM.
The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two
Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated
General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a
glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous
peripherals.
The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP
has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports
time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support
all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and
received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips
Inter-IC Sound (I2S) format.
In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430
encoded data channels simultaneously, with a single RAM containing the full implementation of user data and
channel status fields.
The McASP also provides extensive error-checking and recovery features, such as the bad clock detection
circuit for each high-frequency master clock which verifies that the master clock is within a programmed
frequency range.
The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate
with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to
communicate with serial peripheral interface (SPI) mode peripheral devices.
The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more
detailed information, see the bootmode section of this data sheet.
The TMS320C67x DSP generation is supported by the TI eXpressDSPt set of industry benchmark
development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studiot Integrated
Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOSt
kernel.
TMS320C6000, eXpressDSP, Code Composer Studio, and DSP/BIOS are trademarks of Texas Instruments.
†Throughout the remainder of this document, TMS320C6713B shall be referred to as C6713B or 13B.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
12 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
device characteristics
Table 2 provides an overview of the C6713B DSP. The table shows significant features of the device, including
the capacity of on-chip RAM, the peripherals, the execution time, and the package type with pin count. For more
details on the C67x DSP device part numbers and part numbering, see Figure 12.
Table 2. Characteristics of the C6713B Processor
HARDWARE FEATURES
INTERNAL CLOCK
SOURCE
C6713B
(FLOATING-POINT DSP)
HARDWARE FEATURES
SOURCE
GDP/ZDP PYP
Peripherals EMIF SYSCLK3 or ECLKIN 1 (32 bit) 1 (16 bit)
Peripherals
Not all peripheral pins are
EDMA
(16 Channels) CPU clock frequency 1
Not all peripheral pins are
available at the same HPI (16 bit) SYSCLK2 1
available at the same
time. (For more details,
see the Device
McASPs AUXCLK, SYSCLK2†2
see the Device
Configurations section.)
I2Cs SYSCLK2 2
Configurations section.)
Peripheral performance is
McBSPs SYSCLK2 2
Peripheral performance is
dependent on chip-level
32-Bit Timers 1/2 of SYSCLK2 2
dependent on chip-level
configuration. GPIO Module SYSCLK2 1
Size (Bytes) 264K
On-Chip Memory Organization
4K-Byte (4KB) L1 Program (L1P) Cache
4KB L1 Data (L1D) Cache
64KB Unified L2 Cache/Mapped RAM
192KB L2 Mapped RAM
CPU ID+CPU Rev ID Control Status Register (CSR.[31:16]) 0x0203
BSDL File For the C6713B BSDL file, contact your Field Sales Representative.
Frequency MHz 300, 225, 200 225, 200, 167
Cycle Time ns
3.3 ns (GDP-300, ZDP-300)
4.4 ns (GDP-225, ZDP-225)
5 ns (GDPA-200,
ZDPA-200)
5 ns (PYP-200)
4.4 ns (PYP-225)
6 ns (PYPA−167)
5 ns (PYPA-200)
Voltage
Core (V) 1.20‡ V
1.4 V (−300) 1.2 V
Voltage
I/O (V) 3.3 V
Clock Generator Options Prescaler
Multiplier
Postscaler
/1, /2, /3, ..., /32
x4, x5, x6, ..., x25
/1, /2, /3, ..., /32
Packages
27 x 27 mm 272-Ball BGA (GDP)
272-Ball BGA (ZDP) −
Packages 28 x 28 mm −208-Pin PowerPAD
PQFP (PYP)
Process Technology µm 0.13
Product Status
Product Preview (PP)
Advance Information (AI)
Production Data (PD)
PD§
†AUXCLK is the McASP internal high-frequency clock source for serial transfers. SYSCLK2 is the McASP system clock used for the clock
check (high-frequency) circuit.
‡This value is compatible with existing 1.26-V designs.
§PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include testing of all parameters.
C67x is a trademark of Texas Instruments.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
functional block and CPU (DSP core) diagram
Test
C67x CPU
Data Path B
B Register File
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
Power-Down
Logic
.L1†.S1†.M1†.D1 .D2 .M2†.S2†.L2†
L1P Cache
Direct Mapped
4K Bytes Total
Control
Registers
Control
Logic
L1D Cache
2-Way
Set Associative
4K Bytes
In-Circuit
Emulation
Interrupt
Control
Digital Signal Processor
†In addition to fixed-point instructions, these functional units execute floating-point instructions.
Enhanced
DMA
Controller
(16 channel)
L2 Cache/
Memory
4 Banks
64K Bytes
Total
(up to
4-Way)
Clock Generator and PLL
x4 through x25 Multiplier
/1 through /32 Dividers
L2
Memory
192K
Bytes
EMIF
McASP1
McASP0
McBSP1
McBSP0
I2C1
I2C0
Timer 1
Timer 0
GPIO
HPI
Pin Multiplexing
McBSPs interface to:
−SPI Control Port
−High-Speed TDM Codecs
−AC97 Codecs
−Serial EEPROM
EMIF interfaces to:
−SDRAM
−SBSRAM
−SRAM,
−ROM/Flash, and
−I/O devices
McASPs interface to:
−I2S Multichannel ADC, DAC, Codec, DIR
−DIT: Multiple Outputs
32
16
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
14 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
CPU (DSP core) description
The TMS320C6713B floating-point digital signal processor is based on the C67x CPU. The CPU fetches
advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight
functional units during every clock cycle. The VLIW architecture features controls by which all eight units do no t
have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction
determines if the next instruction belongs to the same execute packet as the previous instruction, or whether
it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256
bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key
memory-saving feature, distinguishing the C67x CPU from other VLIW architectures.
The CPU features two sets of functional units. Each set contains four units and a register file. One set contains
functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files
each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along
with two register files, compose sides A and B of the CPU (see the functional block and CPU diagram and
Figure 1). The four functional units on each side of the CPU can freely share the 16 registers belonging to that
side. Additionally, each side features a single data bus connected to all the registers on the other side, by which
the two sets of functional units can access data from the register files on the opposite side. While register access
by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle,
register access using the register file across the CPU supports one read and one write per cycle.
The C67x CPU executes all C62x instructions. In addition to C62x fixed-point instructions, the six out of eight
functional units (.L1, .S1, .M1, .M2, .S2, and .L2) also execute floating-point instructions. The remaining two
functional units (.D1 and .D2) also execute the new LDDW instruction which loads 64 bits per CPU side for a
total of 128 bits per cycle.
Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers
(as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data
transfers between the register files and the memory. The data address driven by the .D units allows data
addresses generated from one register file to be used to load or store data to or from the other register file. The
C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes
with 5- o r 15-bit of fsets. All instructions are conditional, and most can access any one of the 32 registers. Some
registers, however, are singled out to support specific addressing or to hold the condition for conditional
instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies.
The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results
available every clock cycle.
The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory.
The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least
significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous
execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain,
effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the
fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of
the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet
can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one
per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units
for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit
registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store
instructions are byte-, half-word, or word-addressable.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
CPU (DSP core) description (continued)
8
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
ÁÁÁÁ
8
long src
dst
src2
src1
src1
src1
src1
src1
src1
src1
src1
long dst
long dst
dst
dst
dst
dst
dst
dst
dst
src2
src2
src2
src2
src2
src2
src2
long src
long src
long dst
long dst
long src
8
8
8
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
2X
1X
.L2†
.S2†
.M2†
.D2
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
.D1
.M1†
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
.S1†
Á
Á
Á
Á
Á
.L1†
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Control
Register File
Á
DA1
DA2
ST1
LD1 32 LSB
LD2 32 LSB
LD2 32 MSB
32
32
Data Path A
Data Path B
Register
File A
(A0−A15)
Register
File B
(B0−B15)
LD1 32 MSB
32
ST2 32
8
8
8
Á
Á
†In addition to fixed-point instructions, these functional units execute floating-point instructions.
Figure 1. TMS320C67x CPU (DSP Core) Data Paths
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
16 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
memory map summary
Table 3 shows the memory map address ranges of the device.
Table 3. Memory Map Summary
MEMORY BLOCK DESCRIPTION BLOCK SIZE (BYTES) HEX ADDRESS RANGE
Internal RAM (L2) 192K 0000 0000 – 0002 FFFF
Internal RAM/Cache 64K 0003 0000 – 0003 FFFF
Reserved 24M – 256K 0004 0000 – 017F FFFF
External Memory Interface (EMIF) Registers 256K 0180 0000 – 0183 FFFF
L2 Registers 128K 0184 0000 – 0185 FFFF
Reserved 128K 0186 0000 – 0187 FFFF
HPI Registers 256K 0188 0000 – 018B FFFF
McBSP 0 Registers 256K 018C 0000 – 018F FFFF
McBSP 1 Registers 256K 0190 0000 – 0193 FFFF
Timer 0 Registers 256K 0194 0000 – 0197 FFFF
Timer 1 Registers 256K 0198 0000 – 019B FFFF
Interrupt Selector Registers 512 019C 0000 – 019C 01FF
Device Configuration Registers 4019C 0200 – 019C 0203
Reserved 256K − 516 019C 0204 – 019F FFFF
EDMA RAM and EDMA Registers 256K 01A0 0000 – 01A3 FFFF
Reserved 768K 01A4 0000 – 01AF FFFF
GPIO Registers 16K 01B0 0000 – 01B0 3FFF
Reserved 240K 01B0 4000 – 01B3 FFFF
I2C0 Registers 16K 01B4 0000 – 01B4 3FFF
I2C1 Registers 16K 01B4 4000 – 01B4 7FFF
Reserved 16K 01B4 8000 – 01B4 BFFF
McASP0 Registers 16K 01B4 C000 – 01B4 FFFF
McASP1 Registers 16K 01B5 0000 – 01B5 3FFF
Reserved 160K 01B5 4000 – 01B7 BFFF
PLL Registers 8K 01B7 C000 – 01B7 DFFF
Reserved 264K 01B7 E000 – 01BB FFFF
Emulation Registers 256K 01BC 0000 – 01BF FFFF
Reserved 4M 01C0 0000 – 01FF FFFF
QDMA Registers 52 0200 0000 – 0200 0033
Reserved 16M − 52 0200 0034 – 02FF FFFF
Reserved 720M 0300 0000 – 2FFF FFFF
McBSP0 Data Port 64M 3000 0000 – 33FF FFFF
McBSP1 Data Port 64M 3400 0000 – 37FF FFFF
Reserved 64M 3800 0000 – 3BFF FFFF
McASP0 Data Port 1M 3C00 0000 – 3C0F FFFF
McASP1 Data Port 1M 3C10 0000 – 3C1F FFFF
Reserved 1G + 62M 3C20 0000 – 7FFF FFFF
EMIF CE0†256M 8000 0000 – 8FFF FFFF
EMIF CE1†256M 9000 0000 – 9FFF FFFF
EMIF CE2†256M A000 0000 – AFFF FFFF
EMIF CE3†256M B000 0000 – BFFF FFFF
Reserved 1G C000 0000 – FFFF FFFF
†The number of EMIF address pins (EA[21:2]) limits the maximum addressable memory (SDRAM) to 128MB per CE space.
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
L2 memory structure expanded
Figure 2 shows the detail of the L2 memory structure.
0x0000 0000
011010001 111
0x0003 0000
000
L2 Mode L2 Memory Block Base Address
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎ
0x0003 C000
0x0003 8000
0x0003 4000
0x0003 FFFF
16K
1-Way
Cache
32K
2-Way Cache
48K 3-Way Cache
64K 4-Way Cache
256K SRAM (All)
240K SRAM
224K SRAM
208K SRAM
192K SRAM
192K-Byte RAM
16K-Byte RAM
16K-Byte RAM
16K-Byte RAM
16K-Byte RAM
Figure 2. L2 Memory Configuration
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
18 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
peripheral register descriptions
Table 4 through Table 17 identify the peripheral registers for the device by their register names, acronyms, and
hex address or hex address range. For more detailed information on the register contents, bit names and their
descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview
Reference Guide (literature number SPRU190).
Table 4. EMIF Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0180 0000 GBLCTL EMIF global control
0180 0004 CECTL1 EMIF CE1 space control
0180 0008 CECTL0 EMIF CE0 space control
0180 000C − Reserved
0180 0010 CECTL2 EMIF CE2 space control
0180 0014 CECTL3 EMIF CE3 space control
0180 0018 SDCTL EMIF SDRAM control
0180 001C SDTIM EMIF SDRAM refresh control
0180 0020 SDEXT EMIF SDRAM extension
0180 0024 − 0183 FFFF − Reserved
Table 5. L2 Cache Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0184 0000 CCFG Cache configuration register
0184 4000 L2WBAR L2 writeback base address register
0184 4004 L2WWC L2 writeback word count register
0184 4010 L2WIBAR L2 writeback-invalidate base address register
0184 4014 L2WIWC L2 writeback-invalidate word count register
0184 4020 L1PIBAR L1P invalidate base address register
0184 4024 L1PIWC L1P invalidate word count register
0184 4030 L1DWIBAR L1D writeback-invalidate base address register
0184 4034 L1DWIWC L1D writeback-invalidate word count register
0184 5000 L2WB L2 writeback all register
0184 5004 L2WBINV L2 writeback-invalidate all register
0184 8200 MAR0 Controls CE0 range 8000 0000 − 80FF FFFF
0184 8204 MAR1 Controls CE0 range 8100 0000 − 81FF FFFF
0184 8208 MAR2 Controls CE0 range 8200 0000 − 82FF FFFF
0184 820C MAR3 Controls CE0 range 8300 0000 − 83FF FFFF
0184 8240 MAR4 Controls CE1 range 9000 0000 − 90FF FFFF
0184 8244 MAR5 Controls CE1 range 9100 0000 − 91FF FFFF
0184 8248 MAR6 Controls CE1 range 9200 0000 − 92FF FFFF
0184 824C MAR7 Controls CE1 range 9300 0000 − 93FF FFFF
0184 8280 MAR8 Controls CE2 range A000 0000 − A0FF FFFF
0184 8284 MAR9 Controls CE2 range A100 0000 − A1FF FFFF
0184 8288 MAR10 Controls CE2 range A200 0000 − A2FF FFFF
0184 828C MAR11 Controls CE2 range A300 0000 − A3FF FFFF
0184 82C0 MAR12 Controls CE3 range B000 0000 − B0FF FFFF
0184 82C4 MAR13 Controls CE3 range B100 0000 − B1FF FFFF
0184 82C8 MAR14 Controls CE3 range B200 0000 − B2FF FFFF
0184 82CC MAR15 Controls CE3 range B300 0000 − B3FF FFFF
0184 82D0 − 0185 FFFF − Reserved
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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peripheral register descriptions (continued)
Table 6. Interrupt Selector Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
019C 0000 MUXH Interrupt multiplexer high Selects which interrupts drive CPU interrupts
10−15 (INT10−INT15)
019C 0004 MUXL Interrupt multiplexer low Selects which interrupts drive CPU interrupts 4−9
(INT04−INT09)
019C 0008 EXTPOL External interrupt polarity Sets the polarity of the external interrupts
(EXT_INT4−EXT_INT7)
019C 000C − 019F FFFF − Reserved
Table 7. Device Registers
HEX ADDRESS RANGE ACRONYM REGISTER DESCRIPTION
019C 0200 DEVCFG Device Configuration
Allows the user to control peripheral selection.
This register also offers the user control of the
EMIF input clock source. For more detailed
information on the device configuration register, see
the Device Configurations section of this data
sheet.
019C 0204 − 019F FFFF − Reserved
N/A CSR CPU Control Status Register
Identifies which CPU and defines the silicon
revision of the CPU. This register also offers the
user control of device operation.
For more detailed information on the CPU Control
Status Register, see the CPU CSR Register
Description section of this data sheet.
Table 8. EDMA Parameter RAM†
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0000 − 01A0 0017 −Parameters for Event 0 (6 words) or Reload/Link Parameters for other Event
01A0 0018 − 01A0 002F −Parameters for Event 1 (6 words) or Reload/Link Parameters for other Event
01A0 0030 − 01A0 0047 −Parameters for Event 2 (6 words) or Reload/Link Parameters for other Event
01A0 0048 − 01A0 005F −Parameters for Event 3 (6 words) or Reload/Link Parameters for other Event
01A0 0060 − 01A0 0077 −Parameters for Event 4 (6 words) or Reload/Link Parameters for other Event
01A0 0078 − 01A0 008F −Parameters for Event 5 (6 words) or Reload/Link Parameters for other Event
01A0 0090 − 01A0 00A7 −Parameters for Event 6 (6 words) or Reload/Link Parameters for other Event
01A0 00A8 − 01A0 00BF −Parameters for Event 7 (6 words) or Reload/Link Parameters for other Event
01A0 00C0 − 01A0 00D7 −Parameters for Event 8 (6 words) or Reload/Link Parameters for other Event
01A0 00D8 − 01A0 00EF −Parameters for Event 9 (6 words) or Reload/Link Parameters for other Event
01A0 00F0 − 01A0 00107 −Parameters for Event 10 (6 words) or Reload/Link Parameters for other Event
01A0 0108 − 01A0 011F −Parameters for Event 11 (6 words) or Reload/Link Parameters for other Event
01A0 0120 − 01A0 0137 −Parameters for Event 12 (6 words) or Reload/Link Parameters for other Event
01A0 0138 − 01A0 014F −Parameters for Event 13 (6 words) or Reload/Link Parameters for other Event
01A0 0150 − 01A0 0167 −Parameters for Event 14 (6 words) or Reload/Link Parameters for other Event
01A0 0168 − 01A0 017F −Parameters for Event 15 (6 words) or Reload/Link Parameters for other Event
01A0 0180 − 01A0 0197 −Reload/link parameters for Event 0−15
01A0 0198 − 01A0 01AF −Reload/link parameters for Event 0−15
... ...
01A0 07E0 − 01A0 07F7 −Reload/link parameters for Event 0−15
01A0 07F8 − 01A0 07FF −Scratch pad area (2 words)
†The device has 85 EDMA parameters total: 16 Event/Reload parameters and 69 Reload-only parameters.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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peripheral register descriptions (continued)
For more details on the EDMA parameter RAM 6-word parameter entry structure, see Figure 3.
31 0 EDMA Parameter
Word 0 EDMA Channel Options Parameter (OPT) OPT
Word 1 EDMA Channel Source Address (SRC) SRC
Word 2 Array/Frame Count (FRMCNT) Element Count (ELECNT) CNT
Word 3 EDMA Channel Destination Address (DST) DST
Word 4 Array/Frame Index (FRMIDX) Element Index (ELEIDX) IDX
Word 5 Element Count Reload (ELERLD) Link Address (LINK) RLD
Figure 3. EDMA Channel Parameter Entries (6 Words) for Each EDMA Event
Table 9. EDMA Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01A0 0800 − 01A0 FEFC − Reserved
01A0 FF00 ESEL0 EDMA event selector 0
01A0 FF04 ESEL1 EDMA event selector 1
01A0 FF08 − 01A0 FF0B − Reserved
01A0 FF0C ESEL3 EDMA event selector 3
01A0 FF1F − 01A0 FFDC − Reserved
01A0 FFE0 PQSR Priority queue status register
01A0 FFE4 CIPR Channel interrupt pending register
01A0 FFE8 CIER Channel interrupt enable register
01A0 FFEC CCER Channel chain enable register
01A0 FFF0 ER Event register
01A0 FFF4 EER Event enable register
01A0 FFF8 ECR Event clear register
01A0 FFFC ESR Event set register
01A1 0000 − 01A3 FFFF – Reserved
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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peripheral register descriptions (continued)
Table 10. Quick DMA (QDMA) and Pseudo Registers†
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0200 0000 QOPT QDMA options parameter register
0200 0004 QSRC QDMA source address register
0200 0008 QCNT QDMA frame count register
0200 000C QDST QDMA destination address register
0200 0010 QIDX QDMA index register
0200 0014 − 0200 001C − Reserved
0200 0020 QSOPT QDMA pseudo options register
0200 0024 QSSRC QDMA pseudo source address register
0200 0028 QSCNT QDMA pseudo frame count register
0200 002C QSDST QDMA pseudo destination address register
0200 0030 QSIDX QDMA pseudo index register
†All the QDMA and Pseudo registers are write-accessible only
Table 11. PLL Controller Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B7 C000 PLLPID Peripheral identification register (PID) [0x00010801 for PLL Controller]
01B7 C004 − 01B7 C0FF − Reserved
01B7 C100 PLLCSR PLL control/status register
01B7 C104 − 01B7 C10F − Reserved
01B7 C110 PLLM PLL multiplier control register
01B7 C114 PLLDIV0 PLL controller divider 0 register
01B7 C118 PLLDIV1 PLL controller divider 1 register
01B7 C11C PLLDIV2 PLL controller divider 2 register
01B7 C120 PLLDIV3 PLL controller divider 3 register
01B7 C124 OSCDIV1 Oscillator divider 1 register
01B7 C128 − 01B7 DFFF − Reserved
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
22 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
peripheral register descriptions (continued)
Table 12. McASP0 and McASP1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
McASP0 McASP1
ACRONYM
REGISTER NAME
3C00 0000 − 3C00 FFFF 3C10 0000 − 3C10 FFFF RBUF/XBUFx McASPx receive buffer or McASPx transmit buffer via the
Peripheral Data Bus.
(Used when RSEL or XSEL bits = 0 [these bits are located
in the RFMT or XFMT registers, respectively].)
01B4 C000 01B5 0000 MCASPPIDx Peripheral Identification register
[0x00100101 for McASP0 and for McASP1]
01B4 C004 01B5 0004 PWRDEMUx Power down and emulation management register
01B4 C008 01B5 0008 − Reserved
01B4 C00C 01B5 000C − Reserved
01B4 C010 01B5 0010 PFUNCx Pin function register
01B4 C014 01B5 0014 PDIRx Pin direction register
01B4 C018 01B5 0018 PDOUTx Pin data out register
01B4 C01C 01B5 001C PDIN/PDSETx Pin data in / data set register
Read returns: PDIN
Writes affect: PDSET
01B4 C020 01B5 0020 PDCLRx Pin data clear register
01B4 C024 − 01B4 C040 01B5 0024 − 01B5 0040 − Reserved
01B4 C044 01B5 0044 GBLCTLx Global control register
01B4 C048 01B5 0048 AMUTEx Mute control register
01B4 C04C 01B5 004C DLBCTLx Digital Loop-back control register
01B4 C050 01B5 0050 DITCTLx DIT mode control register
01B4 C054 − 01B4 C05C 01B5 0054 − 01B5 005C − Reserved
01B4 C060 01B5 0060 RGBLCTLx Alias of GBLCTL containing only Receiver Reset bits,
allows transmit to be reset independently from receive.
01B4 C064 01B5 0064 RMASKx Receiver format unit bit mask register
01B4 C068 01B5 0068 RFMTx Receive bit stream format register
01B4 C06C 01B5 006C AFSRCTLx Receive frame sync control register
01B4 C070 01B5 0070 ACLKRCTLx Receive clock control register
01B4 C074 01B5 0074 AHCLKRCTLx High-frequency receive clock control register
01B4 C078 01B5 0078 RTDMx Receive TDM slot 0−31 register
01B4 C07C 01B5 007C RINTCTLx Receiver interrupt control register
01B4 C080 01B5 0080 RSTATx Status register − Receiver
01B4 C084 01B5 0084 RSLOTx Current receive TDM slot register
01B4 C088 01B5 0088 RCLKCHKx Receiver clock check control register
01B4 C08C − 01B4 C09C 01B5 008C − 01B5 009C − Reserved
01B4 C0A0 01B5 00A0 XGBLCTLx Alias of GBLCTL containing only Transmitter Reset bits,
allows transmit to be reset independently from receive.
01B4 C0A4 01B5 00A4 XMASKx Transmit format unit bit mask register
01B4 C0A8 01B5 00A8 XFMTx Transmit bit stream format register
01B4 C0AC 01B5 00AC AFSXCTLx Transmit frame sync control register
01B4 C0B0 01B5 00B0 ACLKXCTLx Transmit clock control register
01B4 C0B4 01B5 00B4 AHCLKXCTLx High-frequency Transmit clock control register
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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Table 12. McASP0 and McASP1 Registers (Continued)
HEX ADDRESS RANGE REGISTER NAMEACRONYM
McASP0 REGISTER NAMEACRONYM
McASP1
01B4 C0B8 01B5 00B8 XTDMx Transmit TDM slot 0−31 register
01B4 C0BC 01B5 00BC XINTCTLx Transmit interrupt control register
01B4 C0C0 01B5 00C0 XSTATx Status register − Transmitter
01B4 C0C4 01B5 00C4 XSLOTx Current transmit TDM slot
01B4 C0C8 01B5 00C8 XCLKCHKx Transmit clock check control register
01B4 C0D0 − 01B4 C0FC 01B5 00CC − 01B5 00FC − Reserved
01B4 C100 01B5 0100 DITCSRA0x Left (even TDM slot) channel status register file
01B4 C104 01B5 0104 DITCSRA1x Left (even TDM slot) channel status register file
01B4 C108 01B5 0108 DITCSRA2x Left (even TDM slot) channel status register file
01B4 C10C 01B5 010C DITCSRA3x Left (even TDM slot) channel status register file
01B4 C110 01B5 0110 DITCSRA4x Left (even TDM slot) channel status register file
01B4 C114 01B5 0114 DITCSRA5x Left (even TDM slot) channel status register file
01B4 C118 01B5 0118 DITCSRB0x Right (odd TDM slot) channel status register file
01B4 C11C 01B5 011C DITCSRB1x Right (odd TDM slot) channel status register file
01B4 C120 01B5 0120 DITCSRB2x Right (odd TDM slot) channel status register file
01B4 C124 01B5 0124 DITCSRB3x Right (odd TDM slot) channel status register file
01B4 C128 01B5 0128 DITCSRB4x Right (odd TDM slot) channel status register file
01B4 C12C 01B5 012C DITCSRB5x Right (odd TDM slot) channel status register file
01B4 C130 01B5 0130 DITUDRA0x Left (even TDM slot) user data register file
01B4 C134 01B5 0134 DITUDRA1x Left (even TDM slot) user data register file
01B4 C138 01B5 0138 DITUDRA2x Left (even TDM slot) user data register file
01B4 C13C 01B5 013C DITUDRA3x Left (even TDM slot) user data register file
01B4 C140 01B5 0140 DITUDRA4x Left (even TDM slot) user data register file
01B4 C144 01B5 0144 DITUDRA5x Left (even TDM slot) user data register file
01B4 C148 01B5 0148 DITUDRB0x Right (odd TDM slot) user data register file
01B4 C14C 01B5 014C DITUDRB1x Right (odd TDM slot) user data register file
01B4 C150 01B5 0150 DITUDRB2x Right (odd TDM slot) user data register file
01B4 C154 01B5 0154 DITUDRB3x Right (odd TDM slot) user data register file
01B4 C158 01B5 0158 DITUDRB4x Right (odd TDM slot) user data register file
01B4 C15C 01B5 015C DITUDRB5x Right (odd TDM slot) user data register file
01B4 C160 − 01B4 C17C 01B5 0160 − 01B5 017C − Reserved
01B4 C180 01B5 0180 SRCTL0x Serializer 0 control register
01B4 C184 01B5 0184 SRCTL1x Serializer 1 control register
01B4 C188 01B5 0188 SRCTL2x Serializer 2 control register
01B4 C18C 01B5 018C SRCTL3x Serializer 3 control register
01B4 C190 01B5 0190 SRCTL4x Serializer 4 control register
01B4 C194 01B5 0194 SRCTL5x Serializer 5 control register
01B4 C198 01B5 0198 SRCTL6x Serializer 6 control register
01B4 C19C 01B5 019C SRCTL7x Serializer 7 control register
01B4 C1A0 − 01B4 C1FC 01B5 01A0 − 01B5 01FC − Reserved
peripheral register descriptions (continued)
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
24 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Table 12. McASP0 and McASP1 Registers (Continued)
HEX ADDRESS RANGE REGISTER NAMEACRONYM
McASP0 REGISTER NAMEACRONYM
McASP1
01B4 C200 01B5 0200 XBUF0x Transmit Buffer for Serializer 0 through configuration bus†
01B4 C204 01B5 0204 XBUF1x Transmit Buffer for Serializer 1 through configuration bus†
01B4 C208 01B5 0208 XBUF2x Transmit Buffer for Serializer 2 through configuration bus†
01B4 C20C 01B5 020C XBUF3x Transmit Buffer for Serializer 3 through configuration bus†
01B4 C210 01B5 0210 XBUF4x Transmit Buffer for Serializer 4 through configuration bus†
01B4 C214 01B5 0214 XBUF5x Transmit Buffer for Serializer 5 through configuration bus†
01B4 C218 01B5 0218 XBUF6x Transmit Buffer for Serializer 6 through configuration bus†
01B4 C21C 01B5 021C XBUF7x Transmit Buffer for Serializer 7 through configuration bus†
01B4 C220 − 01B4 C27C 01B5 C220 − 01B5 027C − Reserved
01B4 C280 01B5 0280 RBUF0x Receive Buffer for Serializer 0 through configuration bus‡
01B4 C284 01B5 0284 RBUF1x Receive Buffer for Serializer 1 through configuration bus‡
01B4 C288 01B5 0288 RBUF2x Receive Buffer for Serializer 2 through configuration bus‡
01B4 C28C 01B5 028C RBUF3x Receive Buffer for Serializer 3 through configuration bus‡
01B4 C290 01B5 0290 RBUF4x Receive Buffer for Serializer 4 through configuration bus‡
01B4 C294 01B5 0294 RBUF5x Receive Buffer for Serializer 5 through configuration bus‡
01B4 C298 01B5 0298 RBUF6x Receive Buffer for Serializer 6 through configuration bus‡
01B4 C29C 01B5 029C RBUF7x Receive Buffer for Serializer 7 through configuration bus‡
01B4 C2A0 − 01B4 FFFF 01B5 02A0 − 01B5 3FFF − Reserved
†The transmit buffers for serializers 0 − 7 are accessible to the CPU via the peripheral bus if the XSEL bit = 1 (XFMT register).
‡The receive buffers for serializers 0 − 7 are accessible to the CPU via the peripheral bus if the RSEL bit = 1 (RFMT register).
Table 13. I2C0 and I2C1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER DESCRIPTION
I2C0 I2C1
ACRONYM
REGISTER DESCRIPTION
01B4 0000 01B4 4000 I2COARx I2Cx own address register
01B4 0004 01B4 4004 I2CIERx I2Cx interrupt enable register
01B4 0008 01B4 4008 I2CSTRx I2Cx interrupt status register
01B4 000C 01B4 400C I2CCLKLx I2Cx clock low-time divider register
01B4 0010 01B4 4010 I2CCLKHx I2Cx clock high-time divider register
01B4 0014 01B4 4014 I2CCNTx I2Cx data count register
01B4 0018 01B4 4018 I2CDRRx I2Cx data receive register
01B4 001C 01B4 401C I2CSARx I2Cx slave address register
01B4 0020 01B4 4020 I2CDXRx I2Cx data transmit register
01B4 0024 01B4 4024 I2CMDRx I2Cx mode register
01B4 0028 01B4 4028 I2CISRCx I2Cx interrupt source register
01B4 002C 01B4 402C − Reserved
01B4 0030 01B4 4030 I2CPSCx I2Cx prescaler register
01B4 0034 01B4 4034 I2CPID10
I2CPID11 I2Cx Peripheral Identification register 1
[0x0000 0103]
01B4 0038 01B4 4038 I2CPID20
I2CPID21 I2Cx Peripheral Identification register 2
[0x0000 0005]
01B4 003C − 01B4 3FFF 01B4 403C − 01B4 7FFF − Reserved
peripheral register descriptions (continued)
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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peripheral register descriptions (continued)
Table 14. HPI Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS
−HPID HPI data register Host read/write access only
−HPIA HPI address register Host read/write access only
0188 0000 HPIC HPI control register Both Host/CPU read/write access
0188 0004 − 018B FFFF − Reserved
Table 15. Timer 0 and Timer 1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
COMMENTS
TIMER 0 TIMER 1
ACRONYM
REGISTER NAME
COMMENTS
0194 0000 0198 0000 CTLx Timer x control register Determines the operating
mode of the timer, monitors the
timer status, and controls the
function of the TOUT pin.
0194 0004 0198 0004 PRDx Timer x period register Contains the number of timer
input clock cycles to count.
This number controls the
TSTAT signal frequency.
0194 0008 0198 0008 CNTx Timer x counter register Contains the current value of
the incrementing counter.
0194 000C − 0197 FFFF 0198 000C − 019B FFFF − Reserved −
Table 16. McBSP0 and McBSP1 Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER DESCRIPTION
McBSP0 McBSP1
ACRONYM
REGISTER DESCRIPTION
018C 0000 0190 0000 DRRx McBSPx data receive register via Configuration Bus
The CPU and EDMA controller can only read this register;
they cannot write to it.
3000 0000 − 33FF FFFF 3400 0000 − 37FF FFFF DRRx McBSPx data receive register via Peripheral Data Bus
018C 0004 0190 0004 DXRx McBSPx data transmit register via Configuration Bus
3000 0000 − 33FF FFFF 3400 0000 − 37FF FFFF DXRx McBSPx data transmit register via Peripheral Data Bus
018C 0008 0190 0008 SPCRx McBSPx serial port control register
018C 000C 0190 000C RCRx McBSPx receive control register
018C 0010 0190 0010 XCRx McBSPx transmit control register
018C 0014 0190 0014 SRGRx McBSPx sample rate generator register
018C 0018 0190 0018 MCRx McBSPx multichannel control register
018C 001C 0190 001C RCERx McBSPx receive channel enable register
018C 0020 0190 0020 XCERx McBSPx transmit channel enable register
018C 0024 0190 0024 PCRx McBSPx pin control register
018C 0028 − 018F FFFF 0190 0028 − 0193 FFFF − Reserved
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
26 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
peripheral register descriptions (continued)
Table 17. GPIO Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
01B0 0000 GPEN GPIO enable register
01B0 0004 GPDIR GPIO direction register
01B0 0008 GPVAL GPIO value register
01B0 000C − Reserved
01B0 0010 GPDH GPIO delta high register
01B0 0014 GPHM GPIO high mask register
01B0 0018 GPDL GPIO delta low register
01B0 001C GPLM GPIO low mask register
01B0 0020 GPGC GPIO global control register
01B0 0024 GPPOL GPIO interrupt polarity register
01B0 0028 − 01B0 3FFF − Reserved
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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signal groups description
TRST
GP[7](EXT_INT7)‡§
IEEE Standard
1149.1
(JTAG)
Emulation
Reset and
Interrupts
Control/Status
TDI
TDO
TMS
TCK
EMU0
EMU1
NMI
GP[6](EXT_INT6)‡§
GP[5](EXT_INT5)/AMUTEIN0‡§
GP[4](EXT_INT4)/AMUTEIN1‡§
RESET
Clock/PLL
Oscillator
CLKIN
CLKMODE0
PLLHV
CLKOUT2/GP[2]
EMU2†
EMU3†
EMU4†
EMU5†
HHWIL/AFSR1
HCNTL0/AXR1[3]
HCNTL1/AXR1[1]
Data
Register Select
Half-Word
Select
Control
HPI
(Host-Port Interface)
HAS/ACLKX1
HR/W/AXR1[0]
HCS/AXR1[2]
HDS1/AXR1[6]
HDS2/AXR1[5]
HRDY/ACLKR1
HINT/GP[1]
HD15/GP[15]
HD14/GP[14]
HD13/GP[13]
HD12/GP[12]
HD11/GP[11]
HD10/GP[10]
HD9/GP[9]
HD8/GP[8]
HD7/GP[3]
HD6/AHCLKR1
HD5/AHCLKX1
HD4/GP[0]
HD3/AMUTE1
HD2/AFSX1
HD1/AXR1[7]
HD0/AXR1[4]
CLKOUT3
†These external pins are applicable to the GDP and ZDP packages only.
‡The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. For more details, see the External
Interrupt Sources section of this data sheet. For more details on interrupt sharing, see the TMS320C6000 DSP Interrupt Selector
Reference Guide (literature number SPRU646).
§All of these pins are external interrupt sources. For more details, see the External Interrupt Sources section of this data sheet.
HD4/GP[0]‡
NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.
Figure 4. CPU (DSP Core) and Peripheral Signals
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
28 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
signal groups description (continued)
General-Purpose Input/Output (GPIO) Port
GP[7](EXT_INT7)
GP[6](EXT_INT6)
GP[5](EXT_INT5)/AMUTEIN0
GP[4](EXT_INT4)/AMUTEIN1
HD7/GP[3]
CLKOUT2/GP[2]
HINT/GP[1]
HD4/GP[0]
GPIO†
HD15/GP[15]
HD14/GP[14]
HD13/GP[13]
HD12/GP[12]
HD11/GP[11]
HD10/GP[10]
HD9/GP[9]
HD8/GP[8]
TOUT1/AXR0[4] TOUT0/AXR0[2]
Timer 1 Timer 0
Timers
TINP1/AHCLKX0 TINP0/AXR0[3]
CLKS1/SCL1 SCL0
I2C1 I2C0
I2Cs
DR1/SDA1 SDA0
NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.
†The GP[15:0] pins, through interrupt sharing, are external interrupt capable via GPINT0. GP[15:0] are also external EDMA event
source capable. For more details, see the External Interrupt Sources and External EDMA Event Sources sections of this data sheet.
Figure 5. Peripheral Signals
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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signal groups description (continued)
CE3
ECLKOUT
ED[31:16]†
CE2
CE1
CE0
EA[21:2]
BE3†
BE2†
BE1
BE0
CLKX1/AMUTE0
FSX1
DX1/AXR0[5]
CLKR1/AXR0[6]
FSR1/AXR0[7]
DR1/SDA1
CLKS1/SCL1
AOE/SDRAS/SSOE
AWE/SDWE/SSWE
ARDY
CLKX0/ACLKX0
FSX0/AFSX0
DX0/AXR0[1]
CLKR0/ACLKR0
FSR0/AFSR0
DR0/AXR0[0]
CLKS0/AHCLKR0
Data
Memory Map
Space Select
Address
Byte Enables
16
20
Memory
Control
EMIF
(External Memory Interface)
Receive Receive
McBSP1 McBSP0
Transmit Transmit
Clock Clock
McBSPs
(Multichannel Buffered Serial Ports)
ECLKIN
HOLD
HOLDA
BUSREQ
Bus
Arbitration
ARE/SDCAS/SSADS
†These external pins are applicable to the GDP and ZDP packages only.
ED[15:0] 16
NOTE A: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.
Figure 5. Peripheral Signals (Continued)
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signal groups description (continued)
McASP0
(Multichannel Audio Serial Port 0)
CLKX0/ACLKX0
CLKS0/AHCLKR0
Transmit
Clock
Generator
GP[5](EXT_INT5)/AMUTEIN0
Auto Mute
Logic CLKX1/AMUTE0
FSX0/AFSX0
Transmit
Frame Sync
FSR0/AFSR0 Receive
Frame Sync
CLKR0/ACLKR0 TINP1/AHCLKX0
Receive Clock
Generator
TOUT1/AXR0[4]
TOUT0/AXR0[2]
DX0/AXR0[1]
DR0/AXR0[0]
DX1/AXR0[5]
TINP0/AXR0[3]
CLKR1/AXR0[6]
FSR1/AXR0[7]
8-Serial Ports
Flexible
Partitioning
Tx, Rx, OFF
Transmit
Clock Check
Circuit
Receive Clock
Check Circuit
Error Detect
(see Note A)
(Transmit/Receive Data Pins)
(Receive Bit Clock) (Transmit Bit Clock)
(Receive Master Clock) (Transmit Master Clock)
(Receive Frame Sync or
Left/Right Clock) (Transmit Frame Sync or
Left/Right Clock)
NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input.
B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.
C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 5. Peripheral Signals (Continued)
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signal groups description (continued)
HD0/AXR1[4]
HCS/AXR1[2]
HCNTL1/AXR1[1]
HR/W/AXR1[0]
McASP1
(Multichannel Audio Serial Port 1)
HDS2/AXR1[5]
HAS/ACLKX1
HD5/AHCLKX1
Transmit
Clock
Generator
HCNTL0/AXR1[3]
GP[4](EXT_INT4)/AMUTEIN1
Auto Mute
Logic HD3/AMUTE1
HD2/AFSX1
Transmit
Frame Sync
HHWIL/AFSR1 Receive
Frame Sync
HDS1/AXR1[6]
HD1/AXR1[7]
HRDY/ACLKR1
HD6/AHCLKR1 Receive Clock
Generator
8-Serial Ports
Flexible
Partitioning
Tx, Rx, OFF
Transmit
Clock Check
Circuit
Receive Clock
Check Circuit
Error Detect
(see Note A)
(Transmit/Receive Data Pins)
(Receive Bit Clock) (Transmit Bit Clock)
(Receive Master Clock) (Transmit Master Clock)
(Receive Frame Sync or
Left/Right Clock) (Transmit Frame Sync or
Left/Right Clock)
NOTES: A. The McASPs’ Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external mute input
.
B. On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.
C. Bolded and italicized text within parentheses denotes the function of the pins in an audio system.
Figure 5. Peripheral Signals (Continued)
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DEVICE CONFIGURATIONS
On the C6713B device, bootmode and certain device configurations/peripheral selections are determined at
device reset, while other device configurations/peripheral selections are software-configurable via the device
configurations register (DEVCFG) [address location 0x019C0200] after device reset.
device configurations at device reset
Table 18 describes the device configuration pins, which are set up via internal or external pullup/pulldown
resistors through the HPI data pins (HD[4:3], HD8, HD12), and CLKMODE0 pin. These configuration pins must
be in the desired state until reset is released.
For proper device operation, do not oppose the HD [13, 11:9, 7, 1, 0] pins with external pull−ups/pulldowns at
reset.
For more details on these device configuration pins, see the Terminal Functions table and the Debugging
Considerations section of this data sheet.
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Table 18. Device Configurations Pins at Device Reset (HD[4:3], HD8, HD12, and CLKMODE0)†
CONFIGURATION
PIN PYP GDP/ZDP FUNCTIONAL DESCRIPTION
HD12‡168 C15
EMIF Big Endian mode correctness (EMIFBE)
For a C6713BGDP or C6713BZDP:
0 – The EMIF data will always be presented on the ED[7:0] side of the
bus, regardless of the endianess mode (Little/Big Endian).
1 − In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will
be present on the ED[7:0] side of the bus.
In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be
present on the ED[31:24] side of the bus [default].
For a C6713BPYP, when Big Endian mode is selected (LENDIAN = 0), for
proper device operation the EMIFBE pin must be externally pulled low.
This new functionality does not affect systems using the current default value
of HD12=1. For more detailed information on the big endian mode
correctness, see the EMIF Big Endian Mode Correctness portion of this data
sheet.
HD8‡160 B17 Device Endian mode (LEND)
0 – System operates in Big Endian mode
1 − System operates in Little Endian mode (default)
HD[4:3]
(BOOTMODE)‡156, 154 C19, C20
Bootmode Configuration Pins (BOOTMODE)
00 – HPI boot/Emulation boot
01 – CE1 width 8-bit, Asynchronous external ROM boot with default
timings (default mode)
10 − CE1 width 16-bit, Asynchronous external ROM boot with default
timings
11 − CE1 width 32-bit, Asynchronous external ROM boot with default
timings
For more detailed information on these bootmode configurations, see the
bootmode section of this data sheet.
CLKMODE0 205 C4
Clock generator input clock source select
0 – Reserved. Do not use.
1 − CLKIN square wave [default]
This pin must be pulled to the correct level even after reset.
†All other HD pins (HD [15, 13, 11:9, 7:5, 2:0]) have pullups/pulldowns (IPUs or IPDs). For proper device operation, do not oppose the HD [13,
11:9, 7, 1, 0] pins with external pull−ups/pulldowns at reset; however, the HD[15, 6, 5, 2] pins can be opposed and driven during reset.
‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
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DEVICE CONFIGURATIONS (CONTINUED)
peripheral pin selection at device reset
Some peripherals share the same pins (internally muxed) and are mutually exclusive (i.e., HPI, general-purpose
input/output pins GP[15:8, 3, 1, 0] and McASP1).
DHPI, McASP1, and GPIO peripherals
The HPI_EN (HD14 pin) is latched at reset. This pin selects whether the HPI peripheral pins or McASP1
peripheral pins and GP[15:8, 3, 1, 0] pins are functionally enabled (see Table 19).
Table 19. HPI_EN (HD14 Pin) Peripheral Selection (HPI or McASP1, and Select GPIO Pins)†
PERIPHERAL PIN
SELECTION PERIPHERAL
PINS SELECTED
DESCRIPTION
HPI_EN
(HD14 Pin) [173, C14] HPI McASP1 and
GP[15:8,3,1,0]
DESCRIPTION
0√
HPI_EN = 0
HPI pins are disabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins
are enabled. All multiplexed HPI/McASP1 and HPI/GPIO pins function as
McASP1 and GPIO pins, respectively. To use the GPIO pins, the
appropriate bits in the GPEN and GPDIR registers need to be
configured.
1√
HPI_EN = 1
HPI pins are enabled; McASP1 peripheral pins and GP[15:8, 3, 1,0] pins
are disabled [default]. All multiplexed HPI/McASP1 and HPI/GPIO pins
function as HPI pins.
†The HPI_EN (HD[14]) pin cannot be controlled via software.
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DEVICE CONFIGURATIONS (CONTINUED)
peripheral selection/device configurations via the DEVCFG control register
The device configuration register (DEVCFG) allows the user to control the pin availability of the McBSP0,
McBSP1, McASP0, I2C1, and T imer peripherals. The DEVCFG register also of fers the user control of the EMIF
input clock source and the timer output pins. For more detailed information on the DEVCFG register control bits,
see Table 20 and Table 21.
Table 20. Device Configuration Register (DEVCFG) [Address location: 0x019C0200 − 0x019C02FF]
31 16
Reserved†
RW-0
15 54 3 210
Reserved†EKSRC TOUT1SEL TOUT0SEL MCBSP0DIS MCBSP1DIS
RW-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Read/Write; -n = value after reset
†Do not write non-zero values to these bit locations.
Table 21. Device Configuration (DEVCFG) Register Selection Bit Descriptions
BIT # NAME DESCRIPTION
31:5 Reserved Reserved. Do not write non-zero values to these bit locations.
4 EKSRC
EMIF input clock source bit.
Determines which clock signal is used as the EMIF input clock.
0 = SYSCLK3 (from the clock generator) is the EMIF input clock source (default)
1 = ECLKIN external pin is the EMIF input clock source
3 TOUT1SEL
Timer 1 output (TOUT1) pin function select bit.
Selects the pin function of the TOUT1/AXR0[4] external pin independent of the rest of the peripheral
selection bits in the DEVCFG register.
0 = The pin functions as a Timer 1 output (TOUT1) pin (default)
1 = The pin functions as the McASP0 transmit/receive data pin 4 (AXR0[4]).
The Timer 1 module is still active.
2 TOUT0SEL
Timer 0 output (TOUT0) pin function select bit.
Selects the pin function of the TOUT0/AXR0[2] external pin independent of the rest of the peripheral
selection bits in the DEVCFG register.
0 = The pin functions as a Timer 0 output (TOUT0) pin (default)
1 = The pin functions as the McASP0 transmit/receive data pin 2 (AXR0[2]).
The Timer 0 module is still active.
1 MCBSP0DIS
Multichannel Buffered Serial Port 0 (McBSP0) disable bit.
Selects whether McBSP0 or the McASP0 multiplexed peripheral pins are enabled or disabled.
0 = McBSP0 peripheral pins are enabled, McASP0 peripheral pins (AHCLKR0, ACLKR0,
ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are disabled (default).
[If the McASP0 data pins are available, the McASP0 peripheral is functional for DIT
mode only.]
1 = McBSP0 peripheral pins are disabled, McASP0 peripheral pins (AHCLKR0, ACLKR0,
ACLKX0, AXR0[0], AXR0[1], AFSR0, and AFSX0) are enabled.
0 MCBSP1DIS
Multichannel Buffered Serial Port 1 (McBSP1) disable bit.
Selects whether McBSP1 or I2C1 and McASP0 multiplexed peripheral pins are enabled or disabled.
0 = McBSP1 peripheral pins are enabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0
peripheral pins (AXR0[7:5] and AMUTE0) are disabled (default)
1 = McBSP1 peripheral pins are disabled, I2C1 peripheral pins (SCL1 and SDA1) and McASP0
peripheral pins (AXR0[7:5] and AMUTE0) are enabled.
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DEVICE CONFIGURATIONS (CONTINUED)
multiplexed pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Most of
these pins are configured by software via the device configuration register (DEVCFG), and the others
(specifically, the HPI pins) are configured by external pullup/pulldown resistors only at reset. The muxed pins
that are configured by software can be programmed to switch functionalities at any time. The muxed pins that
are configured by external pullup/pulldown resistors are mutually exclusive; only one peripheral has primary
control of the function of these pins after reset. Table 22 summarizes the peripheral pins affected by the HPI_EN
(HD14 pin) and DEVCFG register. Table 23 identifies the multiplexed pins on the device; shows the default
(primary) function and the default settings after reset; and describes the pins, registers, etc. necessary to
configure the specific multiplexed functions.
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DEVICE CONFIGURATIONS (CONTINUED)
Table 22. Peripheral Pin Selection Matrix†
SELECTION BITS PERIPHERAL PINS AVAILABILITY
B
I
T
N
A
M
E
B
I
T
V
A
L
U
E
M
c
A
S
P
0‡
M
c
A
S
P
1
I
2
C
0
I
2
C
1
M
c
B
S
P
0
M
c
B
S
P
1
T
I
M
E
R
0
T
I
M
E
R
1
H
P
I
G
P
I
O
P
I
N
S
E
M
I
F
HPI_EN
(boot config
pin)
0
AHCLKX1
AHCLKR1
ACLKX1
ACLKR1
AFSX1
AFSR1
AMUTE1
AXR1[0] to
AXR1[7]
None
GP[0:1],
GP[3],
GP[8:15]
Plus:
GP[2]
ctrl’d by
GP2EN
bit
1 None All
NO
GP[0:1],
GP[3],
GP[8:15]
0 None All
MCBSP0DIS
(DEVCFG bit) 1
ACLKX0
ACLKR0
AFSX0
AFSR0
AHCLKR0
AXR0[0]
AXR0[1]
None
MCBSP1DIS
(DEVCFG bit)
0
NO
AMUTE0
AXR0[5]
AXR0[6]
AXR0[7]
None All
(DEVCFG bit)
1
AMUTE0
AXR0[5]
AXR0[6]
AXR0[7]
All None
TOUT0SEL
0NO
AXR0[2] TOUT0
TOUT0SEL
(DEVCFG bit) 1 AXR0[2] NO
TOUT0
TOUT1SEL
0NO
AXR0[4] TOUT1
TOUT1SEL
(DEVCFG bit) 1 AXR0[4] NO
TOUT1
0ED[7:0];
HD8 = 1/0
HD12 (boot
config pin) §1
ED[7:0] side
[HD8 = 1 (Little)]
ED[31:24] side
[HD8 = 0 (Big)]
†Gray blocks indicate that the peripheral is not affected by the selection bit.
‡The McASP0 pins AXR0[3] and AHCLKX0 are shared with the timer input pins TINP0 and TINP1, respectively. See Table 23 for more detailed
information.
§For more detailed information on endianness correction, see the EMIF Big Endian Mode Correctness portion of this data sheet.
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DEVICE CONFIGURATIONS (CONTINUED)
Table 23. C6713B Device Multiplexed/Shared Pins
MULTIPLEXED PINS
DEFAULT
NAME PYP GDP/
ZDP
DEFAULT
FUNCTION DEFAULT SETTING DESCRIPTION
CLKOUT2/GP[2] 82 Y12 CLKOUT2
GP2EN = 0
(GPEN register bit)
GP[2] function disabled,
CLKOUT2 enabled
When the CLKOUT2 pin is enabled,
the CLK2EN bit in the EMIF global
control register (GBLCTL) controls the
CLKOUT2 pin.
CLK2EN = 0: CLKOUT2 held high
CLK2EN = 1: CLKOUT2 enabled
to clock [default]
To use these software-configurable
GPIO pins, the GPxEN bits in the GP
Enable Register and the GPxDIR bits
GP[5](EXT_INT5)/AMUTEIN0
GP[4](EXT_INT4)/AMUTEIN1 6
1C1
C2 GP[5](EXT_INT5)
GP[4](EXT_INT4)
No Function
GPxDIR = 0 (input)
GP5EN = 0 (disabled)
GP4EN = 0 (disabled)
[(GPEN register bits)
GP[x] function disabled]
Enable Register and the GPxDIR bits
in the GP Direction Register must be
properly configured.
GPxEN = 1: GP[x] pin enabled
GPxDIR = 0: GP[x] pin is an input
GPxDIR = 1: GP[x] pin is an
output
To use AMUTEIN0/1 pin function, the
GP[5]/GP[4] pins must be configured
as an input, the INEN bit set to 1, and
the polarity through the INPOL bit
selected in the associated McASP
AMUTE register.
CLKS0/AHCLKR0 28 K3
By default, McBSP0 peripheral pins are
DR0/AXR0[0] 27 J1
By default, McBSP0 peripheral pins are
enabled upon reset (McASP0 pins are
DX0/AXR0[1] 20 H2 MCBSP0DIS = 0
(DEVCFG register bit)
enabled upon reset (McASP0 pins are
disabled).
FSR0/AFSR0 24 J3 McBSP0 pin function
MCBSP0DIS = 0
(DEVCFG register bit)
McASP0 pins disabled,
disabled).
To enable the McASP0 peripheral pins,
FSX0/AFSX0 21 H1
McBSP0 pin function
McASP0 pins disabled,
McBSP0 pins enabled
To enable the McASP0 peripheral pins,
the MCBSP0DIS bit in the DEVCFG
CLKR0/ACLKR0 19 H3
McBSP0 pins enabled
the MCBSP0DIS bit in the DEVCFG
register must be set to 1 (disabling the
McBSP0 peripheral pins).
CLKX0/ACLKX0 16 G3 McBSP0 peripheral pins).
CLKS1/SCL1 8 E1 By default, McBSP1 peripheral pins are
enabled upon reset (I2C1 and McASP0
DR1/SDA1 37 M2
MCBSP1DIS = 0
By default, McBSP1 peripheral pins are
enabled upon reset (I2C1 and McASP0
pins are disabled).
DX1/AXR0[5] 32 L2
McBSP1 pin function
MCBSP1DIS = 0
(DEVCFG register bit)
I2C1 and McASP0 pins
pins are disabled).
FSR1/AXR0[7] 38 M3 McBSP1 pin function
I2C1 and McASP0 pins
disabled, McBSP1 pins
To enable the I2C1 and McASP0
peripheral pins, the MCBSP1DIS bit in
CLKR1/AXR0[6] 36 M1
disabled, McBSP1 pins
enabled
peripheral pins, the MCBSP1DIS bit in
the DEVCFG register must be set to 1
CLKX1/AMUTE0 33 L3
enabled
the DEVCFG register must be set to 1
(disabling the McBSP1 peripheral pins)
.
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Table 23. C6713B Device Multiplexed/Shared Pins (Continued)
DESCRIPTIONDEFAULT SETTING
DEFAULT
FUNCTION
MULTIPLEXED PINS DESCRIPTIONDEFAULT SETTING
DEFAULT
FUNCTION
GDP/
ZDP
PYPNAME
HINT/GP[1] 135 J20
HD15/GP[15] 174 B14
HD14/GP[14] 173 C14
HD13/GP[13] 172 A15
By default, the HPI peripheral pins are
HD12/GP[12] 168 C15 By default, the HPI peripheral pins are
enabled at reset. McASP1 peripheral
HD11/GP[11] 167 A16
enabled at reset. McASP1 peripheral
pins and eleven GPIO pins are
HD10/GP[10] 166 B16
pins and eleven GPIO pins are
disabled.
HD9/GP[9] 165 C16
To enable the McASP1 peripheral pins
HD8/GP[8] 160 B17
To enable the McASP1 peripheral pins
and the eleven GPIO pins, an externa
l
HD7/GP[3] 164 A18
and the eleven GPIO pins, an external
pulldown resistor must be provided on
the HD14 pin setting HPI_EN = 0 at
HD4/GP[0] 156 C19 the HD14 pin setting HPI_EN = 0 a
t
reset.
HD1/AXR1[7] 152 D20 HPI_EN (HD14 pin) = 1
(HPI enabled)
reset.
HD0/AXR1[4] 147 E20
HPI pin function
HPI_EN (HD14 pin) = 1
(HPI enabled)
To use these software-configurable
HCNTL1/AXR1[1] 144 G19 HPI pin function
McASP1 pins and eleven
To use these software-configurable
GPIO pins, the GPxEN bits in the GP
HCNTL0/AXR1[3] 146 G18
McASP1 pins and eleven
GPIO pins are disabled.
GPIO pins, the GPxEN bits in the GP
Enable Register and the GPxDIR bits in
the GP Direction Register must be
HR/W/AXR1[0] 143 G20
GPIO pins are disabled.
Enable Register and the GPxDIR bits in
the GP Direction Register must be
properly configured.
HDS1/AXR1[6] 151 E19
properly configured.
GPxEN = 1: GP[x] pin enabled
HDS2/AXR1[5] 150 F18
GPxEN = 1: GP[x] pin enabled
GPxDIR = 0: GP[x] pin is an input
GPxDIR = 1: GP[x] pin is an
HCS/AXR1[2] 145 F20
GPxDIR = 0: GP[x] pin is an input
GPxDIR = 1: GP[x] pin is an
output
HD6/AHCLKR1 161 C17
output
HD5/AHCLKX1 159 B18 McASP1 pin direction is controlled b
y
the PDIR[x] bits in the McASP1PDIR
HD3/AMUTE1 154 C20
McASP1 pin direction is controlled by
the PDIR[x] bits in the McASP1PDIR
register.
HD2/AFSX1 155 D18
register.
HHWIL/AFSR1 139 H20
HRDY/ACLKR1 140 H19
HAS/ACLKX1 153 E18
TINP0/AXR0[3] 17 G2 Timer 0 input
function McASP0PDIR = 0 (input)
[specifically AXR0[3] bit]
By default, the Timer 0 input pin is
enabled (and a shared input until the
McASP0 peripheral forces an output).
McASP0PDIR = 0 input, = 1 output
TOUT0/AXR0[2] 18 G1 Timer 0 output
function
TOUT0SEL = 0
(DEVCFG register bit)
[TOUT0 pin enabled and
McASP0 AXR0[2] pin
disabled]
By default, the Timer 0 output pin is
enabled.
To enable the McASP0 AXR0[2] pin, the
TOUT0SEL bit in the DEVCFG register
must be set to 1 (disabling the Timer 0
peripheral output pin function).
The AXR2 bit in the McASP0PDIR
register controls the direction
(input/output) of the AXR0[2] pin
McASP0PDIR = 0 input, = 1 output
DEVICE CONFIGURATIONS (CONTINUED)
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Table 23. C6713B Device Multiplexed/Shared Pins (Continued)
DESCRIPTIONDEFAULT SETTING
DEFAULT
FUNCTION
MULTIPLEXED PINS DESCRIPTIONDEFAULT SETTING
DEFAULT
FUNCTION
GDP/
ZDP
PYPNAME
TINP1/AHCLKX0 12 F2 Timer 1 input
function McASP0PDIR = 0 (input)
[specifically AHCLKX bit]
By default, the Timer 1 input and
McASP0 clock function are enabled as
inputs.
For the McASP0 clock to function as an
output:
McASP0PDIR = 1 (specifically the
AHCLKX bit]
TOUT1/AXR0[4] 13 F1 Timer 1 output
function
TOUT1SEL = 0
(DEVCFG register bit)
[TOUT1 pin enabled and
McASP0 AXR0[4] pin
disabled]
By default, the Timer 1 output pin is
enabled.
To enable the McASP0 AXR0[4] pin, the
TOUT1SEL bit in the DEVCFG register
must be set to 1 (disabling the Timer 1
peripheral output pin function).
The AXR4 bit in the McASP0PDIR
register controls the direction
(input/output) of the AXR0[4] pin
McASP0PDIR = 0 input, = 1 output
configuration examples
Figure 6 through Figure 11 illustrate examples of peripheral selections that are configurable on this device.
DEVICE CONFIGURATIONS (CONTINUED)
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DEVICE CONFIGURATIONS (CONTINUED)
configuration examples (continued)
EMIF
ED [31:16],
ED[15:0]
CE[3:0], BE[3:0],
HOLDA, HOLD,
BUSREQ, ECLKIN,
ECLKOUT,
ARE/SDCAS/SSADS,
AWE/SDWE/SSWE,
AOE/SDRAS/SSOE,
ARDY
HPI
I2C1
McBSP1
McBSP0
TIMER1
TIMER0
Clock,
System,
EMU, and
Reset
I2C0
GPIO
and
EXT_INT
McASP1
CLKIN, CLKOUT3, CLKMODE0
,
PLLHV, TMS, TDO, TDI, TCK,
TRST, EMU[5:3,1,0], RESET,
NMI
GP[0],
GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)
GP[15:8, 3:1]
McASP0
SCL0, SDA0
32
20
8
DEVCFG Register Value: 0x0000 000F
MCBSP0DIS = 1
MCBSP1DIS = 1
TOUT0SEL = 1
TOUT1SEL = 1
EKSRC = 0
HPI_EN(HD14) = 0
GP2EN BIT = 1 (enabling GPEN.[2])
EA[21:2]
Shading denotes a peripheral module not available for this configuration.
SCL1, SDA1
8AXR0[7:0]
{TINP0/AXR0[3]}
AXR1[7:0]
AFSX1, AFSR1, ACLKX1,
ACLKR1, AHCLKR1,
AHCLKX1, AMUTE1
AMUTE0,
TINP1/AHCLKX0,
AHCLKR0,
ACLKR0,
ACLKX0, AFSR0,
AFSX0
Figure 6. Configuration Example A (2 I2C + 2 McASP + GPIO)
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DEVICE CONFIGURATIONS (CONTINUED)
configuration examples (continued)
EMIF
ED [31:16],
ED[15:0]
CE[3:0], BE[3:0],
HOLDA, HOLD,
BUSREQ, ECLKIN,
ECLKOUT,
ARE/SDCAS/SSADS,
AWE/SDWE/SSWE,
AOE/SDRAS/SSOE,
ARDY
HPI
I2C1
McBSP1
McBSP0
TIMER1
TIMER0
Clock,
System,
EMU, and
Reset
I2C0
GPIO
and
EXT_INT
McASP1
CLKIN, CLKOUT3, CLKMODE0
,
PLLHV, TMS, TDO, TDI, TCK,
TRST, EMU[5:3,1,0], RESET,
NMI
GP[0],
GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)
GP[15:8, 3:1]
McASP0
SCL0, SDA0
AFSX1, AFSR1, ACLKX1,
ACLKR1, AHCLKR1,
AHCLKX1, AMUTE1
32
20
8
DEVCFG Register Value: 0x0000 000E
MCBSP0DIS = 1
MCBSP1DIS = 0
TOUT0SEL = 1
TOUT1SEL = 1
EKSRC = 0
HPI_EN(HD14) = 0
GP2EN BIT = 1 (enabling GPEN.[2])
EA[21:2]
Shading denotes a peripheral module not available for this configuration.
DR1, CLKS1,
CLKR1, CLKX1,
FSR1, DX1,
FSX1
5
AXR1[7:0]
AXR0[4:0]
{TINP0/AXR0[3]}
TINP1/AHCLKX0,
AHCLKR0,
ACLKR0,
ACLKX0, AFSR0,
AFSX0
Figure 7. Configuration Example B (1 I2C + 1 McBSP + 2 McASP + GPIO)
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DEVICE CONFIGURATIONS (CONTINUED)
configuration examples (continued)
EMIF
ED [31:16],
ED[15:0]
CE[3:0], BE[3:0],
HOLDA, HOLD,
BUSREQ, ECLKIN,
ECLKOUT,
ARE/SDCAS/SSADS,
AWE/SDWE/SSWE,
AOE/SDRAS/SSOE,
ARDY
HPI
I2C1
McBSP1
SCL1, SDA1
McBSP0
TIMER1
TIMER0
Clock,
System,
EMU, and
Reset
I2C0
GPIO
and
EXT_INT
McASP1
CLKIN, CLKOUT3, CLKMODE0
,
PLLHV, TMS, TDO, TDI, TCK,
TRST, EMU[5:3,1,0], RESET,
NMI
GP[0],
GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)
GP[15:8, 3:1]
McASP0
(DIT Mode)
SCL0, SDA0
AFSX1, AFSR1, ACLKX1,
ACLKR1, AHCLKR1,
AHCLKX1, AMUTE1
32
20
8
DEVCFG Register Value: 0x0000 000D
MCBSP0DIS = 0
MCBSP1DIS = 1
TOUT0SEL = 1
TOUT1SEL = 1
EKSRC = 0
HPI_EN(HD14) = 0
GP2EN BIT = 1 (enabling GPEN.[2])
EA[21:2]
Shading denotes a peripheral module not available for this configuration.
DR0, CLKS0,
CLKR0, CLKX0,
FSR0, DX0,
FSX0
6
AXR1[7:0]
AXR0[7:2]
{TINP0/AXR0[3]}
AMUTE0,
TINP1/AHCLKX0
Figure 8. Configuration Example C [2 I2C + 1 McBSP + 1 McASP + 1 McASP (DIT) + GPIO]
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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DEVICE CONFIGURATIONS (CONTINUED)
configuration examples (continued)
EMIF
ED [31:16],
ED[15:0]
CE[3:0], BE[3:0],
HOLDA, HOLD,
BUSREQ, ECLKIN,
ECLKOUT,
ARE/SDCAS/SSADS,
AWE/SDWE/SSWE,
AOE/SDRAS/SSOE,
ARDY
HPI
I2C1
McBSP1
DR1, CLKS1,
CLKR1, CLKX1,
FSR1, DX1,
FSX1
McBSP0
TIMER1
TIMER0
Clock,
System,
EMU, and
Reset
I2C0
GPIO
and
EXT_INT
McASP1
CLKIN, CLKOUT3, CLKMODE0
,
PLLHV, TMS, TDO, TDI, TCK,
TRST, EMU[5:3,1,0], RESET,
NMI
GP[0],
GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)
GP[15:8, 3:1]
McASP0
(DIT Mode)
SCL0, SDA0
AFSX1, AFSR1, ACLKX1,
ACLKR1, AHCLKR1,
AHCLKX1, AMUTE1
32
20
8
DEVCFG Register Value: 0x0000 000C
MCBSP0DIS = 0
MCBSP1DIS = 0
TOUT0SEL = 1
TOUT1SEL = 1
EKSRC = 0
HPI_EN(HD14) = 0
GP2EN BIT = 1 (enabling GPEN.[2])
EA[21:2]
Shading denotes a peripheral module not available for this configuration.
DR0, CLKS0,
CLKR0, CLKX0,
FSR0, DX0,
FSX0
3
AXR1[7:0]
AXR0[4:2]
{TINP0/AXR0[3]}
TINP1/AHCLKX0
TOUT0/AXR0[2]
TOUT1/AXR0[4]
Figure 9. Configuration Example D [1 I2C + 2 McBSP + 1 McASP + 1 McASP (DIT) + GPIO + Timers]
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DEVICE CONFIGURATIONS (CONTINUED)
configuration examples (continued)
EMIF
ED [31:16],
ED[15:0]
CE[3:0], BE[3:0],
HOLDA, HOLD,
BUSREQ, ECLKIN,
ECLKOUT,
ARE/SDCAS/SSADS,
AWE/SDWE/SSWE,
AOE/SDRAS/SSOE,
ARDY
HPI
I2C1
McBSP1
SCL1, SDA1
McBSP0
TIMER1
TIMER0
Clock,
System,
EMU, and
Reset
GPIO
and
EXT_INT
McASP1
CLKIN, CLKOUT3, CLKMODE0
,
PLLHV, TMS, TDO, TDI, TCK,
TRST, EMU[5:3,1,0], RESET,
NMI
GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)
McASP0
AXR0[7:0],
{TINP0/AXR0[3]}
32
20
8
DEVCFG Register Value: 0x0000 000F
MCBSP0DIS = 1
MCBSP1DIS = 1
TOUT0SEL = 1
TOUT1SEL = 1
EKSRC = 0
HPI_EN(HD14) = 1
GP2EN BIT = 0 (enabling GPEN.[2])
EA[21:2]
Shading denotes a peripheral module not available for this configuration.
CLKOUT2
HD[15:0] 16
HINT, HHWIL,
HRDY, HR/W,
HCNTRL1,
HCNTRL0, HCS,
HDS2, HDS1,
HAS
I2C0
AMUTE0,
TINP1/AHCLKX0,
AHCLKR0,
ACLKR0,
ACLKX0, AFSR0,
AFSX0
SCL0, SDA0
Figure 10. Configuration Example E (1 I2C + HPI + 1 McASP)
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DEVICE CONFIGURATIONS (CONTINUED)
configuration examples (continued)
EMIF
ED [31:16],
ED[15:0]
CE[3:0], BE[3:0],
HOLDA, HOLD,
BUSREQ, ECLKIN,
ECLKOUT,
ARE/SDCAS/SSADS,
AWE/SDWE/SSWE,
AOE/SDRAS/SSOE,
ARDY
HPI
I2C1
McBSP1
McBSP0
TIMER1
TIMER0
Clock,
System,
EMU, and
Reset
GPIO
and
EXT_INT
McASP1
CLKIN, CLKOUT3, CLKMODE0
,
PLLHV, TMS, TDO, TDI, TCK,
TRST, EMU[5:3,1,0], RESET,
NMI
GP[4](EXT_INT4)/AMUTEIN1,
GP[5](EXT_INT5)/AMUTEIN0,
GP[6](EXT_INT6),
GP[7](EXT_INT7)
McASP0
32
20
5
DEVCFG Register Value: 0x0000 000E
MCBSP0DIS = 1
MCBSP1DIS = 0
TOUT0SEL = 1
TOUT1SEL = 1
EKSRC = 0
HPI_EN(HD14) = 1
GP2EN BIT = 0 (enabling GPEN.[2])
EA[21:2]
Shading denotes a peripheral module not available for this configuration.
DR1, CLKS1,
CLKR1, CLKX1,
FSR1, DX1,
FSX1
CLKOUT2
HD[15:0] 16
HINT, HHWIL,
HRDY, HR/W,
HCNTRL1,
HCNTRL0, HCS,
HDS2, HDS1,
HAS
AXR0[4:0]
{TINP0/AXR0[3]}
I2C0
TINP1/AHCLKX0,
AHCLKR0,
ACLKR0,
ACLKX0, AFSR0,
AFSX0
SCL0, SDA0
Figure 11. Configuration Example F (1 McBSP + HPI + 1 McASP)
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DEVICE CONFIGURATIONS (CONTINUED)
debugging considerations
It is recommended that external connections be provided to peripheral selection/device configuration pins,
including HD[14, 8, 12, 4, 3], and CLKMODE0. Although internal pullup resistors exist on these pins, providing
external connectivity adds convenience to the user in debugging and flexibility in switching operating modes.
Internal pullup/pulldown resistors also exist on the non-configuration pins on the HPI data bus and HD[15, 13,
11:9, 7:5, 2:0]. For proper device operation, do not oppose the HD [13, 11:9, 7, 1, 0] pins with external
pull−ups/pulldowns at reset. If an external controller provides signals to these HD[13, 11:9, 7, 1, 0]
non-configuration pins, these signals must be driven to the default state of the pins at reset, or not be driven
at all. For a list of routed out, 3-stated, or not-driven pins recommended for external pullup/pulldown resistors,
and internal pullup/pulldown resistors for all device pins, etc., see the Terminal Functions table. However, the
HD[15, 6, 5, 2] non-configuration pins can be opposed and driven during reset.
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48 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TERMINAL FUNCTIONS
The terminal functions table identifies the external signal names, the associated pin (ball) numbers along with
the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin has any internal
pullup/pulldown resistors and a functional pin description. For more detailed information on device
configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see the Device
Configurations section of this data sheet.
Terminal Functions
SIGNAL PIN NO.
IPD/
NAME PYP GDP/
ZDP TYPE†
IPD/
IPU‡ DESCRIPTION
CLOCK/PLL CONFIGURATION
CLKIN 204 A3 I IPD Clock Input
CLKOUT2/GP[2] 82 Y12 O/Z IPD Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal
from the clock generator) or this pin can be programmed as GP[2] pin (I/O/Z)
CLKOUT3 184 D10 O IPD Clock output programmable by OSCDIV1 register in the PLL controller.
CLKMODE0 205 C4 I IPU
Clock generator input clock source select
0 − Reserved, do not use.
1 – CLKIN square wave [default]
For proper device operation, this pin must be either left unconnected or
externally pulled up with a 1-kΩ resistor.
PLLHV 202 C5 A Analog power (3.3 V) for PLL (PLL Filter)
JTAG EMULATION
TMS 192 B7 I IPU JTAG test-port mode select
TDO 187 A8 O/Z IPU JTAG test-port data out
TDI 191 A7 I IPU JTAG test-port data in
TCK 193 A6 I IPU JTAG test-port clock
TRST§ 197 B6 I IPD JT AG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1
JTAG Compatibility Statement section of this data sheet.
EMU5 — B12 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected.
EMU4 — C11 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected.
EMU3 — B10 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected.
EMU2 — D3 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected.
EMU1
185
B9
I/O/Z
IPU
Emulation [1:0] pins
•Select the device functional mode of operation
EMU[1:0] Operation
00 Boundary Scan/Functional Mode (see Note)
01 Reserved
10 Reserved
11 Emulation/Functional Mode [default] (see the IEEE 1149.1
JTAG Compatibility Statement section of this data sheet)
EMU1
EMU0
185
186
B9
D9 I/O/Z IPU
JTAG Compatibility Statement section of this data sheet)
The DSP can be placed in Functional mode when the EMU[1:0] pins are
configured for either Boundary Scan or Emulation.
Note: When the EMU[1:0] pins are configured for Boundary Scan mode, the
internal pulldown (IPD) on the TRST signal must not be opposed in order to
operate in Functional mode.
For the Boundary Scan mode drive EMU[1:0] and RESET pins low.
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
§To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended to include an
external 10 kΩ pullup/pulldown resistor to sustain the IPU/IPD, respectively.
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Terminal Functions (Continued)
SIGNAL PIN NO.
IPD/
NAME PYP GDP/
ZDP TYPE†
IPD/
IPU‡ DESCRIPTION
RESETS AND INTERRUPTS
RESET 176 A13 I — Device reset. When using Boundary Scan mode, drive the EMU[1:0] and
RESET pins low. For this device, this pin does not have an IPU.
NMI 175 C13 I IPD
Nonmaskable interrupt
•Edge-driven (rising edge)
Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the NMI pin is
not used, it is recommended that the NMI pin be grounded versus relying on the
IPD.
GP[7](EXT_INT7) 7 E3 General-purpose input/output pins (I/O/Z) which also function as external
interrupts
GP[6](EXT_INT6) 2 D2
interrupts
•Edge-driven
Polarity independently selected via the External Interrupt Polarity Register
GP[5](EXT_INT5)/
AMUTEIN0 6 C1 I/O/Z IPU •Polarity independently selected via the External Interrupt Polarity Registe
r
bits (EXTPOL.[3:0]), in addition to the GPIO registers.
GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and
GP[4](EXT_INT4)/
AMUTEIN1 1 C2 GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and
AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the
associated McASP AMUTE register.
HOST-PORT INTERFACE (HPI)
HINT/GP[1] 135 J20 O/Z IPU Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as
a GP[1] pin (I/O/Z).
HCNTL1/AXR1[1] 144 G19 I IPU Host control − selects between control, address, or data registers (I) [default] or
McASP1 data pin 1 (I/O/Z).
HCNTL0/AXR1[3] 146 G18 I IPU Host control − selects between control, address, or data registers (I) [default] or
McASP1 data pin 3 (I/O/Z).
HHWIL/AFSR1 139 H20 I IPU Host half-word select − first or second half-word (not necessarily high or low
order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK)
(I/O/Z).
HR/W/AXR1[0] 143 G20 I IPU Host read or write select (I) [default] or McASP1 data pin 0 (I/O/Z).
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
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50 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL PIN NO.
IPD/
NAME PYP GDP/
ZDP TYPE†
IPD/
IPU‡ DESCRIPTION
HOST-PORT INTERFACE (HPI) (CONTINUED)
HD15/GP[15] 174 B14 IPU
Host-port data pins (I/O/Z) [default] or general-purpose input/output pins
(I/O/Z)
•Used for transfer of data, address, and control
•Also controls initialization of DSP modes at reset via pullup/pulldown
resistors
HD14/GP[14]§173 C14 IPU
resistors
− Device Endian Mode (HD8)
0 – Big Endian
1 − Little Endian
HD13/GP[13]§172 A15 IPU
For a C6713BGDP or C6713BZDP:
− Big Endian Mode Correctness EMIFBE (HD12)
0 – The EMIF data will always be presented on the ED[7:0] side of the
bus, regardless of the endianess mode (Little/Big Endian).
1 − In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be
HD12/GP[12]§168 C15 IPU
1 − In Little Endian mode (HD8 =1), the 8-bit or 16-bit EMIF data will be
present on the ED[7:0] side of the bus.
In Big Endian mode (HD8 =0), the 8-bit or 16-bit EMIF data will be
present on the ED[31:24] side of the bus [default].
For a C6713BPYP, when Big Endian mode is selected (LENDIAN = 0), for
HD11/GP[11] 167 A16 I/O/Z IPU
For a C6713BPYP, when Big Endian mode is selected (LENDIAN = 0), for
proper device operation the EMIFBE pin must be externally pulled low.
This new functionality does not a ffect systems using the current default value o
f
HD12=1. For more detailed information on the big endian mode correctness,
see the EMIF Big Endian Mode Correctness portion of this data
HD10/GP[10] 166 B16 IPU
see the EMIF Big Endian Mode Correctness portion of this data
sheet.
− Bootmode (HD[4:3])
00 – HPI boot/Emulation boot
01 – CE1 width 8-bit, Asynchronous external ROM boot with default
HD9/GP[9] 165 C16 IPU
01 – CE1 width 8-bit, Asynchronous external ROM boot with default
timings (default mode)
10 − CE1 width 16-bit, Asynchronous external ROM boot with default
timings
11 − CE1 width 32-bit, Asynchronous external ROM boot with default
timings
HD8/GP[8]§160 B17 IPU
timings
− HPI_EN (HD14)
0 – HPI disabled, McASP1 enabled
1 − HPI enabled, McASP1 disabled (default)
HD7/GP[3] 164 A18 IPU
Other HD pins HD [13, 11:9, 7:5, 2:0] have pullups/pulldowns (IPUs/IPDs). Fo
r
proper device operation, do not oppose the HD [13, 11:9, 7, 1, 0] pins with exter
-
nal pull−ups/pulldowns at reset; however, the HD[15, 6, 5, 2] pins can be op
-
posed and driven at reset. For more details, see the Device Configurations
section of this data sheet.
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡ IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
§To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended to include an
external 10 kΩ pullup/pulldown resistor to sustain the IPU/IPD, respectively.
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Terminal Functions (Continued)
SIGNAL PIN NO.
IPD/
NAME PYP GDP/
ZDP TYPE†
IPD/
IPU‡ DESCRIPTION
HOST-PORT INTERFACE (HPI) (CONTINUED)
HD6/AHCLKR1 161 C17
I/O/Z
IPU Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master
clock (I/O/Z).
HD5/AHCLKX1 159 B18 I/O/Z IPU Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency master
clock (I/O/Z).
HD4/GP[0]§156 C19 I/O/Z IPD Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP[0]
pin (I/O/Z).
HD3/AMUTE1§154 C20 IPU Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z).
HD2/AFSX1 155 D18 I/O/Z IPU Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/right
clock (LRCLK) (I/O/Z).
HD1/AXR1[7] 152 D20 IPU Host-port data pin 1 (I/O/Z) [ default] or McASP1 data pin 7 (I/O/Z).
HD0/AXR1[4] 147 E20 I/O/Z IPU Host-port data pin 0 (I/O/Z) [ default] or McASP1 data pin 4 (I/O/Z).
HAS/ACLKX1 153 E18 I IPU Host address strobe (I) [default] or McASP1 transmit bit clock (I/O/Z).
HCS/AXR1[2] 145 F20 I IPU Host chip select (I) [default] or McASP1 data pin 2 (I/O/Z).
HDS1/AXR1[6] 151 E19 I IPU Host data strobe 1 (I) [default] or McASP1 data pin 6 (I/O/Z).
HDS2/AXR1[5] 150 F18 I IPU Host data strobe 2 (I) [default] or McASP1 data pin 5 (I/O/Z) .
HRDY/ACLKR1 140 H19 O/Z IPD Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z).
EMIF − COMMON SIGNALS TO ALL TYPES OF MEMORY¶
CE3 57 V6 O/Z IPU
Memory space enables
CE2 61 W6 O/Z IPU Memory space enables
•Enabled by bits 28 through 31 of the word address
CE1 103 W18 O/Z IPU •
Enabled by bits 28 through 31 of the word address
•
Only one asserted during any external data access
CE0 102 V17 O/Z IPU
•Only one asserted during any external data access
BE3 — V5 O/Z IPU
Byte-enable control
BE2 — Y4 O/Z IPU
Byte-enable control
•
Decoded from the two lowest bits of the internal address
BE1 108 U19 O/Z IPU
•Decoded from the two lowest bits of the internal address
•Byte-write enables for most types of memory
Can be directly connected to SDRAM read and write mask signal (SDQM)
BE0 110 V20 O/Z IPU
Byte-write enables for most types of memory
•Can be directly connected to SDRAM read and write mask signal (SDQM
)
EMIF − BUS ARBITRATION¶
HOLDA 137 J18 O/Z IPU Hold-request-acknowledge to the host
HOLD 138 J17 I IPU Hold request from the host
BUSREQ 136 J19 O/Z IPU Bus request output
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
§To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended to include an
external 10 kΩ pullup/pulldown resistor to sustain the IPU/IPD, respectively.
¶To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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52 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL PIN NO.
IPD/
NAME PYP GDP/
ZDP TYPE†
IPD/
IPU‡DESCRIPTION
EMIF − ASYNCHRONOUS/SYNCHRONOUS MEMORY CONTROL¶
ECLKIN 78 Y11 I IPD External EMIF input clock source
ECLKOUT 77 Y10 O/Z IPD
EMIF output clock depends on the EKSRC bit (DEVCFG.[4]) and on EKEN bit
(GBLCTL.[5]).
EKSRC = 0 – ECLKOUT is based on the internal SYSCLK3 signal
from the clock generator (default).
EKSRC = 1 – ECLKOUT is based on the the external EMIF input clock
source pin (ECLKIN)
EKEN = 0 – ECLKOUT held low
EKEN = 1 – ECLKOUT enabled to clock (default)
ARE/SDCAS/
SSADS 79 V11 O/Z IPU Asynchronous memory read enable/SDRAM column-address strobe/SBSRAM
address strobe
AOE/SDRAS/
SSOE 75 W10 O/Z IPU Asynchronous memory output enable/SDRAM row-address strobe/SBSRAM
output enable
AWE/SDWE/
SSWE 83 V12 O/Z IPU Asynchronous memory write enable/SDRAM write enable/SBSRAM write
enable
ARDY 56 Y5 I IPU Asynchronous memory ready input
EMIF − ADDRESS¶
EA21 109 U18
EA20 101 Y18
EA19 100 W17
EA18 95 Y16
EA17 99 V16
EA16 92 Y15
EA15 94 W15
EA14 90 Y14
EMIF external address
EA13 91 W14
EMIF external address
Note: EMIF address numbering for the C6713BPYP device
starts with EA2 to maintain signal name compatibility with other C671x devices
EA12 93 V14
O/Z
IPU
Note: EMIF address numbering for the C6713BPYP device
starts with EA2 to maintain signal name compatibility with other C671x device
s
(e.g., C6711, C6713BGDP and C6713BZDP) [see the 32-bit EMIF addressing
EA11 86 W13
O/Z
IPU
(e.g., C6711, C6713BGDP and C6713BZDP) [see the 32-bit EMIF addressing
scheme in the TMS320C6000 DSP External Memory Interface (EMIF)
EA10 76 V10
scheme in the TMS320C6000 DSP External Memory Interface (EMIF)
Reference Guide (literature number SPRU266)].
EA9 74 Y9
EA8 71 V9
EA7 70 Y8
EA6 69 W8
EA5 68 V8
EA4 64 W7
EA3 63 V7
EA2 62 Y6
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
¶To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
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Terminal Functions (Continued)
SIGNAL PIN NO.
IPD/
NAME PYP GDP/
ZDP TYPE†
IPD/
IPU‡ DESCRIPTION
EMIF − DATA¶
ED31 — N3
ED30 — P3
ED29 — P2
ED28 — P1
ED27 — R2
ED26 — R3
ED25 — T2
ED24 — T1
ED23 — U3
ED22 — U1
ED21 — U2
ED20 — V1
ED19 — V2
ED18 — Y3
ED17 — W4
ED16 — V4
I/O/Z
IPU
External data pins (ED[31:16] pins applicable to GDP and ZDP packages only)
ED15 112 T19 I/O/Z IPU External data pins (ED[31:16] pins applicable to GDP and ZDP packages only
)
ED14 113 T20
ED13 111 T18
ED12 118 R20
ED11 117 R19
ED10 120 P20
ED9 119 P18
ED8 123 N20
ED7 122 N19
ED6 121 N18
ED5 128 M20
ED4 127 M19
ED3 129 L19
ED2 130 L18
ED1 131 K19
ED0 132 K18
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
¶To maintain signal integrity for the EMIF signals, serial termination resistors should be inserted into all EMIF output signal lines.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
54 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL PIN NO. TYPE†IPD/
IPU‡ DESCRIPTION
MULTICHANNEL AUDIO SERIAL PORT 1 (McASP1)
GP[4](EXT_INT4)/
AMUTEIN1 1 C2 I/O/Z IPU General-purpose input/output pin 4 and external interrupt 4 (I/O/Z) [default] or
McASP1 mute input (I/O/Z).
HD3/AMUTE1 154 C20 I/O/Z IPU Host-port data pin 3 (I/O/Z) [ default] or McASP1 mute output (O/Z).
HRDY/ACLKR1 140 H19 I/O/Z IPD Host ready (from DSP to host) (O) [default] or McASP1 receive bit clock (I/O/Z).
HD6/AHCLKR1 161 C17 I/O/Z IPU Host-port data pin 6 (I/O/Z) [ default] or McASP1 receive high-frequency master
clock (I/O/Z).
HAS/ACLKX1 153 E18 I/O/Z IPU Host address strobe (I) [default] or McASP 1 transmit bit clock (I/O/Z).
HD5/AHCLKX1 159 B18 I/O/Z IPU Host-port data pin 5 (I/O/Z) [ default] or McASP1 transmit high-frequency
master clock (I/O/Z).
HHWIL/AFSR1 139 H20 I/O/Z IPU Host half-word select − first or second half-word (not necessarily high or low
order) (I) [default] or McASP1 receive frame sync or left/right clock (LRCLK)
(I/O/Z).
HD2/AFSX1 155 D18 I/O/Z IPU Host-port data pin 2 (I/O/Z) [ default] or McASP1 transmit frame sync or left/
right clock (LRCLK) (I/O/Z).
HD1/AXR1[7] 152 D20 I/O/Z IPU Host-port data pin 1 (I/O/Z) [ default] or McASP1 TX/RX data pin 7 (I/O/Z).
HDS1/AXR1[6] 151 E19 I/O/Z IPU Host data strobe 1 (I) [default] or McASP1 TX/RX data pin 6 (I/O/Z).
HDS2/AXR1[5] 150 F18 I/O/Z IPU Host data strobe 2 (I) [default] or McASP1 TX/RX data pin 5 (I/O/Z).
HD0/AXR1[4] 147 E20 I/O/Z IPU Host-port data pin 0 (I/O/Z) [ default] or McASP1 TX/RX data pin 4 (I/O/Z).
HCNTL0/AXR1[3] 146 G18 I/O/Z IPU Host control − selects between control, address, or data registers (I) [default] or
McASP1 TX/RX data pin 3 (I/O/Z).
HCS/AXR1[2] 145 F20 I/O/Z IPU Host chip select (I) [default] or McASP1 TX/RX data pin 2 (I/O/Z).
HCNTL1/AXR1[1] 144 G19 I/O/Z IPU Host control − selects between control, address, or data registers (I) [default] or
McASP1 TX/RX data pin 1 (I/O/Z).
HR/W/AXR1[0] 143 G20 I/O/Z IPU Host read or write select (I) [default] or McASP1 TX/RX data pin 0 (I/O/Z).
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0)
GP[5](EXT_INT5)/
AMUTEIN0 6 C1 I/O/Z IPU General-purpose input/output pin 5 and external interrupt 5 (I/O/Z) [default] or
McASP0 mute input (I/O/Z).
CLKX1/AMUTE0 33 L3 I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z).
CLKR0/ACLKR0 19 H3 I/O/Z IPD McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z).
TINP1/AHCLKX0 12 F2 I/O/Z IPD T imer 1 input (I) or McASP0 transmit high−frequency master clock (I/O/Z). This
pin defaults as Timer 1 input (I) and McASP transmit high−frequency master
clock input (I).
CLKX0/ACLKX0 16 G3 I/O/Z IPD McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z).
CLKS0/AHCLKR0 28 K3 I/O/Z IPD McBSP0 ex t ernal clock source (as opposed to internal) ( I) [default] or McASP0
receive high-frequency master clock (I/O/Z).
FSR0/AFSR0 24 J3 I/O/Z IPD McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or
left/right clock (LRCLK) (I/O/Z).
FSX0/AFSX0 21 H1 I/O/Z IPD McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync
or left/right clock (LRCLK) (I/O/Z).
FSR1/AXR0[7] 38 M3 I/O/Z IPD McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7
(I/O/Z).
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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Terminal Functions (Continued)
SIGNAL PIN NO.
IPD/
NAME PYP GDP/
ZDP TYPE†
IPD/
IPU‡ DESCRIPTION
MULTICHANNEL AUDIO SERIAL PORT 0 (McASP0) (CONTINUED)
CLKR1/AXR0[6] 36 M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z).
DX1/AXR0[5] 32 L2 I/O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z).
TOUT1/AXR0[4] 13 F1 I/O/Z IPD Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z).
TINP0/AXR0[3] 17 G2 I/O/Z IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z).
TOUT0/AXR0[2] 18 G1 I/O/Z IPD Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z).
DX0/AXR0[1] 20 H2 I/O/Z IPU McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z).
DR0/AXR0[0] 27 J1 I/O/Z IPU McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z).
TIMER 1
TOUT1/AXR0[4] 13 F1 O IPD Timer 1 output (O) [default] or McASP0 TX/RX data pin 4 (I/O/Z).
TINP1/AHCLKX0 12 F2 I IPD Timer 1 input (I) or McASP0 transmit high−frequency master clock (I/O/Z). This
pin defaults as Timer 1 input (I) and McASP transmit high−frequency master
clock input (I).
TIMER0
TOUT0/AXR0[2] 18 G1 O IPD Timer 0 output (O) [default] or McASP0 TX/RX data pin 2 (I/O/Z).
TINP0/AXR0[3] 17 G2 I IPD Timer 0 input (I) [default] or McASP0 TX/RX data pin 3 (I/O/Z).
MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP1)
CLKS1/SCL1 8 E1 I —
McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1
clock (I/O/Z).
This pin does not have an internal pullup or pulldown. When this pin is used as a
McBSP pin, this pin should either be driven externally at all times or be pulled up
with a 10-kΩ resistor to a valid logic level. Because it is common for some ICs to
3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even
when an external device is driving the pin.
CLKR1/AXR0[6] 36 M1 I/O/Z IPD McBSP1 receive clock (I/O/Z) [default] or McASP0 TX/RX data pin 6 (I/O/Z).
CLKX1/AMUTE0 33 L3 I/O/Z IPD McBSP1 transmit clock (I/O/Z) [default] or McASP0 mute output (O/Z).
DR1/SDA1 37 M2 I —
McBSP1 receive data (I) [default] or I2C1 data (I/O/Z).
This pin does not have an internal pullup or pulldown. When this pin is used as a
McBSP pin, this pin should either be driven externally at all times or be pulled up
with a 10-kΩ resistor to a valid logic level. Because it is common for some ICs to
3-state their outputs at times, a 10-kΩ pullup resistor may be desirable even
when an external device is driving the pin.
DX1/AXR0[5] 32 L2 O/Z IPU McBSP1 transmit data (O/Z) [default] or McASP0 TX/RX data pin 5 (I/O/Z).
FSR1/AXR0[7] 38 M3 I/O/Z IPD McBSP1 receive frame sync (I/O/Z) [default] or McASP0 TX/RX data pin 7
(I/O/Z).
FSX1 31 L1 I/O/Z IPD McBSP1 transmit frame sync
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
56 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL PIN NO.
IPD/
NAME PYP GDP/
ZDP TYPE†
IPD/
IPU‡ DESCRIPTION
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP0)
CLKS0/AHCLKR0 28 K3 I IPD McBSP0 external clock source (as opposed to internal) (I) [default] or McASP0
receive high-frequency master clock (I/O/Z).
CLKR0/ACLKR0 19 H3 I/O/Z IPD McBSP0 receive clock (I/O/Z) [default] or McASP0 receive bit clock (I/O/Z).
CLKX0/ACLKX0 16 G3 I/O/Z IPD McBSP0 transmit clock (I/O/Z) [default] or McASP0 transmit bit clock (I/O/Z).
DR0/AXR0[0] 27 J1 I IPU McBSP0 receive data (I) [default] or McASP0 TX/RX data pin 0 (I/O/Z).
DX0/AXR0[1] 20 H2 O/Z IPU McBSP0 transmit data (O/Z) [default] or McASP0 TX/RX data pin 1 (I/O/Z).
FSR0/AFSR0 24 J3 I/O/Z IPD McBSP0 receive frame sync (I/O/Z) [default] or McASP0 receive frame sync or
left/right clock (LRCLK) (I/O/Z).
FSX0/AFSX0 21 H1 I/O/Z IPD McBSP0 transmit frame sync (I/O/Z) [default] or McASP0 transmit frame sync or
left/right clock (LRCLK) (I/O/Z).
INTER-INTEGRATED CIRCUIT 1 (I2C1)
CLKS1/SCL1 8 E1 I/O/Z —
McBSP1 external clock source (as opposed to internal) (I) [default] or I2C1 clock
(I/O/Z).
This pin must be externally pulled up. When this pin is used as an I2C pin, the
value of the pullup resistor is dependent on the number of devices connected to
the I2C bus. For more details, see the Philips I 2C Specification Revision 2.1
(January 2000).
DR1/SDA1 37 M2 I/O/Z —
McBSP1 receive data (I) [default] or I2C1 data (I/O/Z).
This pin must be externally pulled up. When this pin is used as an I2C pin, the
value of the pullup resistor is dependent on the number of devices connected to
the I2C bus. For more details, see the Philips I 2C Specification Revision 2.1
(January 2000).
INTER-INTEGRATED CIRCUIT 0 (I2C0)
SCL0 41 N1 I/O/Z —
I2C0 clock.
This pin must be externally pulled up. The value of the pullup resistor on this pin
is dependent on the number of devices connected to the I2C bus. For more
details, see the Philips I2C Specification Revision 2.1 (January 2000).
SDA0 42 N2 I/O/Z —
I2C0 data.
This pin must be externally pulled up. The value of the pullup resistor on this pin
is dependent on the number of devices connected to the I2C bus. For more
details, see the Philips I2C Specification Revision 2.1 (January 2000).
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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Terminal Functions (Continued)
SIGNAL PIN NO.
IPD/
NAME PYP GDP/
ZDP TYPE†
IPD/
IPU‡ DESCRIPTION
GENERAL-PURPOSE INPUT/OUTPUT (GPIO)
HD15/GP[15] 174 B14 IPU Host-port data pins (I/O/Z) [default] or general-purpose input/output pins
(I/O/Z) and some function as boot configuration pins at reset.
HD14/GP[14] 173 C14 IPU
(I/O/Z) and some function as boot configuration pins at reset.
•Used for transfer of data, address, and control
•
Also controls initialization of DSP modes at reset via pullup/pulldown
HD13/GP[13] 172 A15 IPU
•Also controls initialization of DSP modes at reset via pullup/pulldown
resistors
As general-purpose input/output (GP[x]) functions, these pins are software-con-
HD12/GP[12] 168 C15
I/O/Z
IPU As general-purpose input/output (GP[x]) functions, these pins are software-con
-
figurable through registers. The “GPxEN” bits in the GP Enable register and the
GPxDIR bits in the GP Direction register must be properly configured:
HD11/GP[11] 167 A16 I/O/Z IPU GPxDIR bits in the GP Direction register must be properly configured:
GPxEN = 1; GP[x] pin is enabled.
HD10/GP[10] 166 B16 IPU
GPxEN = 1; GP[x] pin is enabled.
GPxDIR = 0; GP[x] pin is an input.
GPxDIR = 1; GP[x] pin is an output.
HD9/GP[9] 165 C16 IPU
GPxDIR = 1; GP[x] pin is an output.
For the functionality description of the Host-port data pins or the boot configura
-
HD8/GP[8] 160 B17 IPU
For the functionality description of the Host-port data pins or the boot configura-
tion pins, see the Host-Port Interface (HPI) portion of this table.
GP[7](EXT_INT7) 7 E3 General-purpose input/output pins (I/O/Z) which also function as external
interrupts
GP[6](EXT_INT6) 2 D2
interrupts
•Edge-driven
Polarity independently selected via the External Interrupt Polarity Register
GP[5](EXT_INT5)/
AMUTEIN0 6 C1 I/O/Z IPU •Polarity independently selected via the External Interrupt Polarity Registe
r
bits (EXTPOL.[3:0])
GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and
GP[4](EXT_INT4)/
AMUTEIN1 1 C2 GP[4] and GP[5] pins also function as AMUTEIN1 McASP1 mute input and
AMUTEIN0 McASP0 mute input, respectively, if enabled by the INEN bit in the
associated McASP AMUTE register.
HD7/GP[3] 164 A18 I/O/Z IPU Host-port data pin 7 (I/O/Z) [default] or general-purpose input/output pin 3
(I/O/Z)
CLKOUT2/GP[2] 82 Y12 I/O/Z IPD Clock output at half of device speed (O/Z) [default] or this pin can be
programmed as GP[2] pin.
HINT/GP[1] 135 J20 O IPU Host interrupt (from DSP to host) (O) [default] or this pin can be programmed as
a GP[1] pin (I/O/Z).
HD4/GP[0] 156 C19 I/O/Z IPD Host-port data pin 4 (I/O/Z) [ default] or this pin can be programmed as a GP[0]
pin (I/O/Z).
RESERVED FOR TEST
RSV 198 A5 O/Z IPU Reserved. (Leave unconnected, do not connect to power or ground)
RSV 200 B5 A§Reserved. (Leave unconnected, do not connect to power or ground)
RSV 179 C12 O — Reserved. (Leave unconnected, do not connect to power or ground)
RSV — D7 O/Z IPD Reserved. (Leave unconnected, do not connect to power or ground)
RSV 178 D12 I — Reserved. This pin does not have an IPU. For proper device
operation, the D12/178 pin must be externally pulled down with a 10-kΩ resistor.
RSV 181 A12 — Reserved. [For new designs, it is recommended that this pin be connected di-
rectly to CVDD (core power). For old designs, this can be left unconnected.
RSV 180 B11 — Reserved. [For new designs, it is recommended that this pin be connected di-
rectly to Vss (ground). For old designs, this pin can be left unconnected.
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors
no greater than 4.4 kΩ and 2.0 kΩ, respectively.]
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
58 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL PIN NO.
NAME PYP GDP/
ZDP TYPE†DESCRIPTION
SUPPLY VOLTAGE PINS
— A17
— B3
— B8
— B13
— C10
— D1
— D16
— D19
— F3
— H18
— J2
— M18
— R1
— R18
— T3
— U5
— U7
— U12
— U16
DVDD
— V13
S
3.3-V supply voltage
DVDD — V15 S
3.3-V supply voltage
(see the power-supply decoupling portion of this data sheet)
— V19
(see the power-supply decoupling portion of this data sheet)
— W3
— W9
— W12
— Y7
— Y17
5 —
9 —
25 —
44 —
47 —
55 —
58 —
65 —
72 —
84 —
87 —
98 —
107 —
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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Terminal Functions (Continued)
SIGNAL PIN NO.
NAME PYP GDP/
ZDP TYPE†DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
114 —
126 —
141 —
3.3-V supply voltage
DV
DD
162 — S3.3-V supply voltage
(see the power-supply decoupling portion of this data sheet)
DVDD
183 —
S
(see the power-supply decoupling portion of this data sheet)
188 —
206 —
— A4
— A9
— A10
— B2
— B19
— C3
— C7
— C18
— D5
— D6
— D11
— D14
— D15
— F4
— F17 1.2-V supply voltage [PYP package]
CVDD
— K1
S
1.2-V supply voltage [PYP package]
1.20-V supply voltage [GDP and ZDP packages] (See Note)
1.4-V supply voltage [GDP and ZDP packages C6711D-300 only]
CVDD — K4 S
1.4-V supply voltage [GDP and ZDP packages C6711D-300 only]
(see the power-supply decoupling portion of this data sheet)
— K17
(see the power-supply decoupling portion of this data sheet)
— L4
— L17
— L20
— R4
— R17
— U6
— U10
— U11
— U14
— U15
— V3
— V18
— W2
Note: This value is compatible with existing 1.26-V designs.
— W19
Note: This value is compatible with existing 1.26-V designs.
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
60 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
Terminal Functions (Continued)
SIGNAL PIN NO.
NAME PYP GDP/
ZDP TYPE†DESCRIPTION
SUPPLY VOLTAGE PINS (CONTINUED)
3 —
11 —
14 —
22 —
29 —
35 —
40 —
43 —
46 —
50 —
51 —
53 —
60 —
67 —
80 —
CVDD
89 —
S
1.2-V supply voltage [PYP package]
1.20-V supply voltage [GDP and ZDP packages] (See Note)
CVDD 96 — S
1.20-V supply voltage [GDP and ZDP packages] (See Note)
1.4-V supply voltage [GDP and ZDP packages C6711D-300 only]
104 —
1.4-V supply voltage [GDP and ZDP packages C6711D-300 only]
(see the power-supply decoupling portion of this data sheet)
105 —
(see the power-supply decoupling portion of this data sheet)
116 —
124 —
133 —
149 —
157 —
169 —
171 —
177 —
190 —
195 —
196 —
201 —
Note: This value is compatible with existing 1.26-V designs.
208 —
Note: This value is compatible with existing 1.26-V designs.
GROUND PINS
— A1
— A2
— A11
VSS
— A14
GND
Ground pins
VSS — A19 GND Ground pins
— A20
— B1
— B4
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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Terminal Functions (Continued)
SIGNAL PIN NO.
NAME PYP GDP/
ZDP TYPE†DESCRIPTION
GROUND PINS (CONTINUED)
— B15
— B20
— C6
— C8
— C9
— D4
— D8
— D13
— D17
— E2
— E4
— E17
— F19
— G4
— G17
— H4
— H17
— J4
Ground pins#
VSS
— J9
GND
Ground pins#
The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground
VSS — J10 GND
The center thermal balls (J9−J12, K9−K12, L9−L12, M9−M12) [shaded] are all tied to ground
and act as both electrical grounds and thermal relief (thermal dissipation).
— J11
and act as both electrical grounds and thermal relief (thermal dissipation).
— J12
— K2
— K9
— K10
— K11
— K12
— K20
— L9
— L10
— L11
— L12
— M4
— M9
— M10
— M11
— M12
— M17
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
#Shaded pin numbers denote the center thermal balls.
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Terminal Functions (Continued)
SIGNAL PIN NO.
NAME PYP GDP/
ZDP TYPE†DESCRIPTION
GROUND PINS (CONTINUED)
— N4
— N17
— P4
— P17
— P19
— T4
— T17
— U4
— U8
— U9
— U13
— U17
— U20
— W1
— W5
— W11
— W16
— W20
— Y1
VSS
— Y2
GND
Ground pins
VSS — Y13 GND Ground pins
— Y19
— Y20
4 —
10 —
15 —
23 —
26 —
30 —
34 —
39 —
45 —
48 —
49 —
52 —
54 —
59 —
66 —
73 —
81 —
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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Terminal Functions (Continued)
SIGNAL PIN NO.
NAME PYP GDP/
ZDP TYPE†DESCRIPTION
GROUND PINS (CONTINUED)
85 —
88 —
97 —
106 —
115 —
125 —
134 —
142 —
VSS
148 —
GND
Ground pins
VSS 158 — GND Ground pins
163 —
170 —
182 —
189 —
194 —
199 —
203 —
207 —
†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
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development support
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of C6000 DSP-based applications:
Software Development Tools:
Code Composer Studio Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Scalable, Real-Time Foundation Software (DSP/BIOS), which provides the basic run-time target software
needed to support any DSP application.
Hardware Development Tools:
Extended Development System (XDS) Emulator (supports C6000 DSP multiprocessor system debug)
EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320C6000 DSP platform, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL). For
information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
TI offers an extensive line of development tools for the TMS320C6000 DSP platform, including tools to
evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
C6000 and XDS are trademarks of Texas Instruments.
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device support
device and development-support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all DSP
devices and support tools. Each DSP commercial family member has one of three prefixes: TMX, TMP, or TMS.
(e.g., TMS320C6713BGDP300). Texas Instruments recommends two of three possible prefix designators for
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from
engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device’s electrical
specifications.
TMP Final silicon die that conforms to the device’s electrical specifications but has not completed
quality and reliability verification.
TMS Fully qualified production device.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal qualification
testing.
TMDS Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped with the following disclaimer:
“Developmental product is intended for internal evaluation purposes.”
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability
of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, GDP), the temperature range (for example, blank is the default commercial temperature range),
and the device speed range in megahertz (for example, -225 is 225 MHz).
The ZDP package, like the GDP package, is a 272-ball plastic BGA only with Pb-free balls. For device part
numbers and further ordering information for TMS320C6713B in the PYP, GDP and ZDP package types, see
the TI website (http://www.ti.com) or contact your TI sales representative.
TMS320 is a trademark of Texas Instruments.
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device and development-support tool nomenclature (continued)
PREFIX
DEVICE SPEED RANGE
TMS 320 C 6713B GDP 300
TMX= Experimental device
TMP= Prototype device
TMS= Qualified device
SMJ = MIL-PRF-38535, QML
SM = High Rel (non-38535)
DEVICE FAMILY
320 = TMS320 DSP family
TECHNOLOGY
PACKAGE TYPE†‡§
C = CMOS
DEVICE
†BGA = Ball Grid Array
QFP = Quad Flatpack
‡The ZDP mechanical package designator represents the version of the GDP with Pb−Free soldered balls. The ZDP package
devices are supported in the same speed grades as the GDP package devices (available upon request).
§For actual device part numbers (P/Ns) and ordering information, see the Mechanical Data section of this
document or the TI website (www.ti.com).
TEMPERATURE RANGE (DEFAULT: 0°C TO 90°C)
( )
Blank = 0°C to 90°C, commercial temperature
A = −40°C to 105°C, extended temperature
GDP = 272-pin plastic BGA
PYP = 208-pin PowerPADt plastic QFP
ZDP = 272-pin plastic BGA, with Pb-free soldered balls
167 MHz
200 MHz 225 MHz
300 MHz
C6713B
Figure 12. TMS320C6000 DSP Device Nomenclature (Including the TMS320C6713B Device)
MicroStar BGA and PowerPAD are trademarks of Texas Instruments.
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documentation support
Extensive documentation supports all TMS320 DSP family generations of devices from product
announcement through applications development. The types of documentation available include: data sheets,
such as this document, with design specifications; complete user’s reference guides for all devices and tools;
technical briefs; development-support tools; on-line help; and hardware and software applications. The
following is a brief, descriptive list of support documentation specific to the C6000 DSP devices:
The TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes the
C6000 CPU (DSP core) architecture, instruction set, pipeline, and associated interrupts.
The TMS320C6000 DSP Peripherals Overview Reference Guide [hereafter referred to as the C6000 PRG
Overview] (literature number SPRU190) provides an overview and briefly describes the functionality of the
peripherals available on the C6000 DSP platform of devices. This document also includes a table listing the
peripherals available on the C6000 devices along with literature numbers and hyperlinks to the associated
peripheral documents. These C6713B peripherals are similar to the peripherals on the TMS320C6711 and
TMS320C64x devices; therefore, see the TMS320C6711 (C6711 or C67x) peripheral information, and in some
cases, where indicated, see the TMS320C6711 (C6711 or C671x) peripheral information and in some cases,
where indicated, see the C64x information in the C6000 PRG Overview (literature number SPRU190).
The TMS320DA6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number
SPRU041) describes the functionality of the McASP peripherals available on the C6713B device.
TMS320C6000 DSP Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide
(literature number SPRU233) describes the functionality of the PLL peripheral available on the C6713B device.
TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU175)
describes the functionality of the I2C peripherals available on the C6713B device.
The PowerPAD Thermally Enhanced Package Technical Brief (literature number SLMA002) focuses on the
specifics of integrating a PowerPAD package into the printed circuit board design to make optimum use of the
thermal efficiencies designed into the PowerPAD package.
The TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the C62x/C67x
devices, associated development tools, and third-party support.
The Migrating from TMS320C6211(B)/C6711(B) to TMS320C6713 application report (literature number
SPRA851) indicates the differences and describes the issues of interest related to the migration from the Texas
Instruments TMS320C6211(B)/C6711(B), GFN package, to the TMS320C6713, GDP and ZDP packages.
The TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature number SPRZ191)
describes the known exceptions to the functional specifications for particular silicon revisions of the
TMS320C6713B device.
The TMS320C6711D, C6712D, C6713B Power Consumption Summary application report (literature number
SPRA889A2 or later) discusses the power consumption for user applications with the TMS320C6713B,
TMS320C6712D, and TMS320C6711D DSP devices.
The Using IBIS Models for Timing Analysis application report (literature number SPRA839) describes how to
properly use IBIS models to attain accurate timing analysis for a given system.
The tools support documentation is electronically available within the Code Composer Studio Integrated
Development Environment (IDE). For a complete listing of C6000 DSP latest documentation, visit the Texas
Instruments web site on the Worldwide Web at http://www.ti.com uniform resource locator (URL).
See the Worldwide Web URL for the application report How To Begin Development Today With the
TMS320C6713 Floating-Point DSP (literature number SPRA809), which describes in more detail the
similarities/differences between the C6713 and C6711 C6000 DSP devices.
C62x is a trademark of Texas Instruments.
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CPU CSR register description
The CPU control status register (CSR) contains the CPU ID and CPU Revision ID (bits 16−31) as well as the
status of the device power-down modes [PWRD field (bits 15−10)], program and data cache control modes, the
endian bit (EN, bit 8) and the global interrupt enable (GIE, bit 0) and previous GIE (PGIE, bit 1). Figure 13 and
Table 24 identify the bit fields in the CPU CSR register.
For more detailed information on the bit fields in the CPU CSR register, see the TMS320C6000 DSP Peripherals
Overview Reference Guide (literature number SPRU190) and the TMS320C6000 CPU and Instruction Set
Reference Guide (literature number SPRU189).
31 24 23 16
CPU ID REVISION ID
R-0x02 R-0x03
15 10 9 8 7 6 5 4 2 1 0
PWRD SAT EN PCC DCC PGIE GIE
R/W-0 R/C-0 R-1 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R = Readable by the MVC instruction, R/W = Readable/Writeable by the MVC instruction; W = Read/write; -n = value after reset, -x = undefined value after
reset, C = Clearable by the MVC instruction
Figure 13. CPU Control Status Register (CPU CSR)
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CPU CSR register description (continued)
Table 24. CPU CSR Register Bit Field Description
BIT # NAME DESCRIPTION
31:24 CPU ID CPU ID + REV ID. Read only.
Identifies which CPU is used and defines the silicon revision of the CPU.
23:16 REVISION ID
Identifies which CPU is used and defines the silicon revision of the CPU.
CPU ID + REVISION ID (31:16) are combined for a value of 0x0203
15:10 PWRD
Control power-down modes. The values are always read as zero.
000000 = no power-down (default)
001001 = PD1, wake-up by an enabled interrupt
010001 = PD1, wake-up by an enabled or not enabled interrupt
011010 = PD2, wake-up by a device reset
011100 = PD3, wake-up by a device reset
Others = Reserved
9 SAT
Saturate bit.
Set when any unit performs a saturate. This bit can be cleared only by the MVC instruction and can
be set only by a functional unit. The set by the a functional unit has priority over a clear (by the MVC
instruction) if they occur on the same cycle. The saturate bit is set one full cycle (one delay slot) after
a saturate occurs. This bit will not be modified by a conditional instruction whose condition is false.
8 EN
Endian bit. This bit is read-only.
Depicts the device endian mode.
0 = Big Endian mode.
1 = Little Endian mode [default].
7:5 PCC
Program Cache control mode.
L1D, Level 1 Program Cache
000/010 = Cache Enabled / Cache accessed and updated on reads.
All other PCC values reserved.
4:2 DCC
Data Cache control mode.
L1D, Level 1 Data Cache
000/010 = Cache Enabled / 2-Way Cache
All other DCC values reserved
1 PGIE
Previous GIE (global interrupt enable); saves the Global Interrupt Enable (GIE) when an interrupt is
taken. Allows for proper nesting of interrupts.
0 = Previous GIE value is 0. (default)
1 = Previous GIE value is 1.
0 GIE
Global interrupt enable bit.
Enables (1) or disables (0) all interrupts except the reset interrupt and NMI (nonmaskable interrupt).
0 = Disables all interrupts (except the reset interrupt and NMI) [default]
1 = Enables all interrupts (except the reset interrupt and NMI)
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cache configuration (CCFG) register description
The C6713B device includes an enhancement to the cache configuration (CCFG) register. A “P” bit
(CCFG.31) allows the programmer to select the priority of accesses to L2 memory originating from the transfer
crossbar (TC) over accesses originating from the L1D memory system. An important class of TC accesses is
EDMA transfers, which move data to or from the L2 memory. While the EDMA normally has no issue accessing
L2 memory due to the high hit rates on the L1D memory system, there are pathological cases where certain
CPU behavior could block the EDMA from accessing the L2 memory for long enough to cause a missed deadline
when transferring data to a peripheral such as the McASP or McBSP. This can be avoided by setting the P bit
to “1” because the EDMA will assume a higher priority than the L1D memory system when accessing L2
memory.
For more detailed information on the P-bit function and for silicon advisories concerning EDMA L2 memory
accesses blocked, see the TMS320C6713, TMS320C6713B Digital Signal Processors Silicon Errata (literature
number SPRZ191).
31 30 10 9 8 732 0
P†Reserved IP ID Reserved L2MODE
R/W-0 R-x W-0 W-0 R-0 0000 R/W-000
Legend: R = Readable; R/W = Readable/Writeable; -n = value after reset; -x = undefined value after reset
†This device includes a P bit.
Figure 14. Cache Configuration Register (CCFG)
Table 25. CCFG Register Bit Field Description
BIT # NAME DESCRIPTION
31 P L1D requestor priority to L2 bit.
P = 0: L1D requests to L2 higher priority than TC requests
P = 1: TC requests to L2 higher priority than L1D requests
30:10 Reserved Reserved. Read-only, writes have no effect.
9 IP Invalidate L1P bit.
0 = Normal L1P operation
1 = All L1P lines are invalidated
8 ID Invalidate L1D bit.
0 = Normal L1D operation
1 = All L1D lines are invalidated
7:3 Reserved Reserved. Read-only, writes have no effect.
2:0 L2MODE
L2 operation mode bits (L2MODE).
000b = L2 Cache disabled (All SRAM mode) [256K SRAM]
001b = 1-way Cache (16K L2 Cache) / [240K SRAM]
010b = 2-way Cache (32K L2 Cache) / [224K SRAM]
011b = 3-way Cache (48K L2 Cache) / [208K SRAM]
111b = 4-way Cache (64K L2 Cache) / [192K SRAM]
All others Reserved
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interrupts and interrupt selector
The C67x DSP core supports 16 prioritized interrupts, which are listed in Table 26. The highest priority interrupt
is INT_00 (dedicated to RESET) while the lowest priority is INT_15. The first four interrupts are non-maskable
and fixed. The remaining interrupts (4−15) are maskable and default to the interrupt source listed in Table 26.
However, their interrupt source may be reprogrammed to any one of the sources listed in Table 27 (Interrupt
Selector). Table 27 lists the selector value corresponding to each of the alternate interrupt sources. The selector
choice for interrupts 4−15 is made by programming the corresponding fields (listed in Table 26) in the MUXH
(address 0x019C0000) and MUXL (address 0x019C0004) registers.
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Table 26. DSP Interrupts Table 27. Interrupt Selector
DSP
INTERRUPT
NUMBER
INTERRUPT
SELECTOR
CONTROL
REGISTER
DEFAULT
SELECTOR
VALUE
(BINARY)
DEFAULT
INTERRUPT
EVENT
INTERRUPT
SELECTOR
VALUE
(BINARY)
INTERRUPT
EVENT MODULE
INT_00 − − RESET 00000 DSPINT HPI
INT_01 − − NMI 00001 TINT0 Timer 0
INT_02 − − Reserved 00010 TINT1 Timer 1
INT_03 − − Reserved 00011 SDINT EMIF
INT_04 MUXL[4:0] 00100 GPINT4†00100 GPINT4†GPIO
INT_05 MUXL[9:5] 00101 GPINT5†00101 GPINT5†GPIO
INT_06 MUXL[14:10] 00110 GPINT6†00110 GPINT6†GPIO
INT_07 MUXL[20:16] 00111 GPINT7†00111 GPINT7†GPIO
INT_08 MUXL[25:21] 01000 EDMAINT 01000 EDMAINT EDMA
INT_09 MUXL[30:26] 01001 EMUDTDMA 01001 EMUDTDMA Emulation
INT_10 MUXH[4:0] 00011 SDINT 01010 EMURTDXRX Emulation
INT_11 MUXH[9:5] 01010 EMURTDXRX 01011 EMURTDXTX Emulation
INT_12 MUXH[14:10] 01011 EMURTDXTX 01100 XINT0 McBSP0
INT_13 MUXH[20:16] 00000 DSPINT 01101 RINT0 McBSP0
INT_14 MUXH[25:21] 00001 TINT0 01110 XINT1 McBSP1
INT_15 MUXH[30:26] 00010 TINT1 01111 RINT1 McBSP1
10000 GPINT0 GPIO
10001 Reserved −
10010 Reserved −
10011 Reserved −
10100 Reserved −
10101 Reserved −
10110 I2CINT0 I2C0
10111 I2CINT1 I2C1
11000 Reserved −
11001 Reserved −
11010 Reserved −
11011 Reserved −
11100 AXINT0 McASP0
11101 ARINT0 McASP0
11110 AXINT1 McASP1
11111 ARINT1 McASP1
†Interrupt Events GPINT4, GPINT5, GPINT6, and GPINT7 are outputs from the GPIO module (GP). They originate from the device pins
GP[4](EXT_INT4)/AMUTEIN1, GP[5](EXT_INT5)/AMUTEIN0, GP[6](EXT_INT6), and GP[7](EXT_INT7). These pins can be used as
edge-sensitive EXT_INTx with polarity controlled by the External Interrupt Polarity Register (EXTPOL.[3:0]). The corresponding pins must
first b e enabled in the GPIO module by setting the corresponding enable bits in the GP Enable Register (GPEN.[7:4]), and configuring them
as inputs in the GP Direction Register (GPDIR.[7:4]). These interrupts can be controlled through the GPIO module in addition to the simple
EXTPOL.[3:0] bits. For more information on interrupt control via the GPIO module, see the TMS320C6000 DSP General-Purpose
Input/Output (GPIO) Reference Guide (literature number SPRU584).
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external interrupt sources
The device supports many external interrupt sources as indicated in Table 28. Control of the interrupt source
is done by the associated module and is made available by enabling the corresponding binary interrupt selector
value (see Table 27 Interrupt Selector shaded rows). Due to pin muxing and module usage, not all external
interrupt sources are available at the same time.
Table 28. External Interrupt Sources and Peripheral Module Control
PIN
NAME INTERRUPT
EVENT MODULE
GP[15] GPINT0 GPIO
GP[14] GPINT0 GPIO
GP[13] GPINT0 GPIO
GP[12] GPINT0 GPIO
GP[11] GPINT0 GPIO
GP[10] GPINT0 GPIO
GP[9] GPINT0 GPIO
GP[8] GPINT0 GPIO
GP[7] GPINT0 or GPINT7 GPIO
GP[6] GPINT0 or GPINT6 GPIO
GP[5] GPINT0 or GPINT5 GPIO
GP[4] GPINT0 or GPINT4 GPIO
GP[3] GPINT0 GPIO
GP[2] GPINT0 GPIO
GP[1] GPINT0 GPIO
GP[0] GPINT0 GPIO
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EDMA module and EDMA selector
The C67x EDMA supports up to 16 EDMA channels. Four of the sixteen channels (channels 8−11) are reserved
for EDMA chaining, leaving 12 EDMA channels available to service peripheral devices.
The EDMA selector registers that control the EDMA channels servicing peripheral devices are located at
addresses 0x01A0FF00 (ESEL0), 0x01A0FF04 (ESEL1), and 0x01A0FF0C (ESEL3). These EDMA selector
registers control the mapping of the EDMA events to the EDMA channels. Each EDMA event has an assigned
EDMA selector code (see Table 30). By loading each EVTSELx register field with an EDMA selector code, users
can map any desired EDMA event to any specified EDMA channel. Table 29 lists the default EDMA selector
value for each EDMA channel.
See Table 31 and Table 32 for the EDMA Event Selector registers and their associated bit descriptions.
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EDMA module and EDMA selector (continued)
Table 29. EDMA Channels Table 30. EDMA Selector
EDMA
CHANNEL
EDMA
SELECTOR
CONTROL
REGISTER
DEFAULT
SELECTOR
VALUE
(BINARY)
DEFAULT
EDMA
EVENT
EDMA
SELECTOR
CODE (BINARY)
EDMA
EVENT MODULE
0 ESEL0[5:0] 000000 DSPINT 000000 DSPINT HPI
1 ESEL0[13:8] 000001 TINT0 000001 TINT0 TIMER0
2 ESEL0[21:16] 000010 TINT1 000010 TINT1 TIMER1
3 ESEL0[29:24] 000011 SDINT 000011 SDINT EMIF
4 ESEL1[5:0] 000100 GPINT4 000100 GPINT4 GPIO
5 ESEL1[13:8] 000101 GPINT5 000101 GPINT5 GPIO
6 ESEL1[21:16] 000110 GPINT6 000110 GPINT6 GPIO
7 ESEL1[29:24] 000111 GPINT7 000111 GPINT7 GPIO
8− − TCC8 (Chaining) 001000 GPINT0 GPIO
9− − TCC9 (Chaining) 001001 GPINT1 GPIO
10 − − TCC10 (Chaining) 001010 GPINT2 GPIO
11 − − TCC11 (Chaining) 001011 GPINT3 GPIO
12 ESEL3[5:0] 001100 XEVT0 001100 XEVT0 McBSP0
13 ESEL3[13:8] 001101 REVT0 001101 REVT0 McBSP0
14 ESEL3[21:16] 001110 XEVT1 001110 XEVT1 McBSP1
15 ESEL3[29:24] 001111 REVT1 001111 REVT1 McBSP1
010000−011111 Reserved
100000 AXEVTE0 McASP0
100001 AXEVTO0 McASP0
100010 AXEVT0 McASP0
100011 AREVTE0 McASP0
100100 AREVTO0 McASP0
100101 AREVT0 McASP0
100110 AXEVTE1 McASP1
100111 AXEVTO1 McASP1
101000 AXEVT1 McASP1
101001 AREVTE1 McASP1
101010 AREVTO1 McASP1
101011 AREVT1 McASP1
101100 I2CREVT0 I2C0
101101 I2CXEVT0 I2C0
101110 I2CREVT1 I2C1
101111 I2CXEVT1 I2C1
110000 GPINT8 GPIO
110001 GPINT9 GPIO
110010 GPINT10 GPIO
110011 GPINT11 GPIO
110100 GPINT12 GPIO
110101 GPINT13 GPIO
110110 GPINT14 GPIO
110111 GPINT15 GPIO
111000−111111 Reserved
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EDMA module and EDMA selector (continued)
Table 31. EDMA Event Selector Registers (ESEL0, ESEL1, and ESEL3)
ESEL0 Register (0x01A0 FF00)
31 30 29 28 27 24 23 22 21 20 19 16
Reserved EVTSEL3 Reserved EVTSEL2
R−0 R/W−00 0011b R−0 R/W−00 0010b
15 14 13 12 11 87 65 43 0
Reserved EVTSEL1 Reserved EVTSEL0
R−0 R/W−00 0001b R−0 R/W−00 0000b
Legend: R = Read only, R/W = Read/Write; -n = value after reset
ESEL1 Register (0x01A0 FF04)
31 30 29 28 27 24 23 22 21 20 19 16
Reserved EVTSEL7 Reserved EVTSEL6
R−0 R/W−00 0111b R−0 R/W−00 0110b
15 14 13 12 11 87 6543 0
Reserved EVTSEL5 Reserved EVTSEL4
R−0 R/W−00 0101b R−0 R/W−00 0100b
Legend: R = Read only, R/W = Read/Write; -n = value after reset
ESEL3 Register (0x01A0 FF0C)
31 30 29 28 27 24 23 22 21 20 19 16
Reserved EVTSEL15 Reserved EVTSEL14
R−0 R/W−00 1111b R−0 R/W−00 1110b
15 14 13 12 11 87 65 43 0
Reserved EVTSEL13 Reserved EVTSEL12
R−0 R/W−00 1101b R−0 R/W−00 1100b
Legend: R = Read only, R/W = Read/Write; -n = value after reset
Table 32. EDMA Event Selection Registers (ESEL0, ESEL1, and ESEL3) Description
BIT # NAME DESCRIPTION
31:30
23:22
15:14
7:6
Reserved Reserved. Read-only, writes have no effect.
29:24
21:16
13:8
5:0
EVTSELx
EDMA event selection bits for channel x. Allows mapping of the EDMA events to the EDMA channels.
The EVTSEL0 through EVTSEL15 bits correspond to the channels 0 to 15, respectively. These
EVTSELx fields are user−selectable. By configuring the EVTSELx fields to the EDMA selector value
of the desired EDMA sync event number (see Table 30), users can map any EDMA event to the
EDMA channel.
For example, if EVTSEL15 is programmed to 00 0001b (the EDMA selector code for TINT0), then
channel 15 is triggered by Timer0 TINT0 events.
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PLL and PLL controller
The TMS320C6713B includes a PLL and a flexible PLL Controller peripheral consisting of a prescaler (D0) and
four dividers (OSCDIV1, D1, D2, and D3). The PLL controller is able to generate different clocks for different
parts of the system (i.e., DSP core, Peripheral Data Bus, External Memory Interface, McASP, and other
peripherals). Figure 15 illustrates the PLL, the PLL controller, and the clock generator logic.
CLKIN
CLKOUT3
For Use
in System /1, /2,
..., /32
..., /32
/1, /2, PLL
x4 to x25
PLLEN (PLL_CSR.[0])
..., /32
/1, /2,
/1, /2,
..., /32
/1, /2,
..., /32
(DSP Core)
SYSCLK1
(Peripherals)
SYSCLK2
ECLKIN
EKSRC Bit
(DEVCFG.[4])
EMIF
†Dividers D1 and D2 must never be disabled. Never write a “0” to the D1EN or D2EN bits in the PLLDIV1 and PLLDIV2 registers.
SYSCLK3
CLKMODE0
(EMIF Clock Input)
C6713B DSP
PLLOUT
PLLREF
DIVIDER D0
OSCDIV1
DIVIDER D1†
DIVIDER D2†
DIVIDER D3
ECLKOUT
AUXCLK
(Internal Clock Source
to McASP0 and McASP1)
1
0
1 0
1
0
PLLHV
C2C1
EMI filter
+3.3 V
10 µF 0.1 µF
D0EN (PLLDIV0.[15])
ENA
ENA
OD1EN (OSCDIV1.[15])
ENAENA
ENA
D1EN (PLLDIV1.[15])
ENAD2EN (PLLDIV2.[15])
ENA
D3EN (PLLDIV3.[15])
Reserved
NOTES: A. Place all PLL external components (C1, C2, and the EMI Filter) as close to the C67x DSP device as possible. For the best
performance, TI recommends that all the PLL external components be on a single side of the board without jumpers, switches, or
components other than the ones shown.
B. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external components (C1, C2, and the EMI
Filter).
C. The 3.3-V supply for the EMI filter must be from the same 3.3-V power plane supplying the I/O voltage, DVDD.
D. EMI filter manufacturer TDK part number ACF451832-333, -223, -153, -103. Panasonic part number EXCCET103U.
Figure 15. PLL and Clock Generator Logic
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PLL and PLL controller (continued)
The PLL Reset Time is the amount of wait time needed when resetting the PLL (writing PLLRST=1), in order
for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL Reset Time
value, see Table 33. The PLL Lock Time is the amount of time from when PLLRST = 0 with PLLEN = 0 (PLL
out of reset, but still bypassed) to when the PLLEN bit can be safely changed to “1” (switching from bypass to
the PLL path), see Table 33 and Figure 15.
Under some operating conditions, the maximum PLL Lock Time may vary from the specified typical value. For
the PLL Lock Time values, see Table 33.
Table 33. PLL Lock and Reset Times
MIN TYP MAX UNIT
PLL Lock Time 75 187.5 µs
PLL Reset Time 125 ns
Table 34 shows the device’s CLKOUT signals, how they are derived and by what register control bits, and what
is the default settings. For more details on the PLL, see the PLL and Clock Generator Logic diagram (Figure 15).
Table 34. CLKOUT Signals, Default Settings, and Control
CLOCK OUTPUT
SIGNAL NAME DEFAULT SETTING
(ENABLED or DISABLED) CONTROL
BIT(s) (Register) DESCRIPTION
CLKOUT2 ON (ENABLED) D2EN = 1 (PLLDIV2.[15])
CK2EN = 1 (EMIF GBLCTL.[3]) SYSCLK2 selected [default]
CLKOUT3 ON (ENABLED) OD1EN = 1 (OSCDIV1.[15]) Derived from CLKIN
ECLKOUT ON (ENABLED);
derived from SYSCLK3 EKSRC = 0 (DEVCFG.[4])
EKEN = 1 (EMIF GBLCTL.[5])
SYSCLK3 selected [default].
To select ECLKIN source:
EKSRC = 1 (DEVCFG.[4]) and
EKEN = 1 (EMIF GBLCTL.[5])
The input clock (CLKIN) is directly available to the McASP modules as AUXCLK for use as an internal
high-frequency clock source. The input clock (CLKIN) may also be divided down by a programmable divider
OSCDIV1 (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system.
Figure 15 shows that the input clock source may be divided down by divider PLLDIV0 (/1, /2, ..., /32) and then
multiplied up by a factor of x4, x5, x6, and so on, up to x25.
Either the input clock (PLLEN = 0) or the PLL output (PLLEN = 1) then serves as the high-frequency reference
clock for the rest of the DSP system. The DSP core clock, the peripheral bus clock, and the EMIF clock may
be divided down from this high-frequency clock (each with a unique divider) . For example, with a 30 MHz input
if the PLL output is configured for 450 MHz, the DSP core may be operated at 225 MHz (/2) while the EMIF may
be configured to operate at a rate of 75 MHz (/6). Note that there is a specific minimum and maximum reference
clock (PLLREF) and output clock (PLLOUT) for the block labeled PLL in Figure 15, as well as for the DSP core,
peripheral bus, and EMIF. The clock generator must not be configured to exceed any of these constraints
(certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported).
See Table 35 for the PLL clocks input and output frequency ranges.
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PLL and PLL controller (continued)
Table 35. PLL Clock Frequency Ranges†‡
CLOCK SIGNAL
PYP −200, -225
GDP/ZDP −225, -300
PYPA −167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
PLLREF (PLLEN = 1) 12 100 MHz
PLLOUT 140 600 MHz
SYSCLK1 − Device Speed (DSP Core) MHz
SYSCLK3 (EKSRC = 0) − 100 MHz
AUXCLK − 50§MHz
†SYSCLK2 rate must be exactly half of SYSCLK1.
‡Also see the electrical specification (timing requirements and switching characteristics parameters) in the input and output clocks section of this
data sheet.
§When the McASP module is not used, the AUXCLK maximum frequency can be any frequency up to the CLKIN maximum frequency.
The EMIF itself may be clocked by an external reference clock via the ECLKIN pin or can be generated on-chip
as SYSCLK3. SYSCLK3 is derived from divider D3 off of PLLOUT (see Figure 15, PLL and Clock Generator
Logic). The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register.
The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured
via software at run time. If either the input to the PLL changes due to D0, CLKMODE0, or CLKIN, or if the PLL
multiplier is changed, then software must enter bypass first and stay in bypass until the PLL has had enough
time to lock (see electrical specifications). For the programming procedure, see the TMS320C6000 DSP
Software-Programmable Phase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233).
SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2) must be programmed
to be half of the SYSCLK1 rate. For example, if D1 is configured to divide-by-2 mode (/2), then D2 must be
programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 15).
During the programming transition of Divider D1 and Divider D2 (resulting in SYSCLK1 and SYSCLK2 output
clocks, see Figure 15), the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to
ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower. For example, if the divider ratios of D1
and D2 are to be changed from /1, /2 (respectively) to /5, /10 (respectively) then, the PLLDIV2 register must be
programmed before the PLLDIV1 register. The transition ratios become /1, /2; /1, /10; and then /5, /10. If the
divider ratios of D1 and D2 are to be changed from /3, /6 to /1, /2 then, the PLLDIV1 register must be programmed
before the PLLDIV2 register. The transition ratios, for this case, become /3, /6; /1, /6; and then /1, /2. The final
SYSCLK2 rate must be exactly half of the SYSCLK1 rate.
Note that Divider D1 and Divider D2 must always be enabled (i. e., D1EN and D2EN bits are set to “1” in the
PLLDIV1 and PLLDIV2 registers).
The PLL Controller registers should be modified only by the CPU or via emulation. The HPI should not be used
to directly access the PLL Controller registers.
For detailed information on the clock generator (PLL Controller registers) and their associated software bit
descriptions, see Table 37 through Table 43.
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PLL and PLL controller (continued)
Table 36. PLL Control/Status Register (PLLCSR) [0x01B7 C100]
31 28 27 24 23 20 19 16
Reserved
R−0
15 12 11 87 6543 21 0
Reserved STABLE Reserved PLLRST Reserved PLLPWRDN PLLEN
R−0 R−x R−0 RW−1 R/W−0 R/W−0b RW−0
Legend: R = Read only, R/W = Read/Write; -n = value after reset
Table 37. PLL Control/Status Register (PLLCSR) Description
BIT # NAME DESCRIPTION
31:7 Reserved Reserved. Read-only, writes have no effect.
6 STABLE Clock Input Stable. This bit indicates if the clock input has stabilized.
0 – Clock input not yet stable. Clock counter is not finished counting (default).
1 – Clock input stable.
5:4 Reserved Reserved. Read-only, writes have no effect.
3 PLLRST Asserts RESET to PLL
0 – PLL Reset Released.
1 – PLL Reset Asserted (default).
2 Reserved Reserved. The user must write a “0” to this bit.
1 PLLPWRDN Select PLL Power Down
0 – PLL Operational (default).
1 – PLL Placed in Power-Down State.
0 PLLEN
PLL Mode Enable
0 – Bypass Mode (default). PLL disabled.
Divider D0 and PLL are bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
directly from input reference clock.
1 – PLL Enabled.
Divider D0 and PLL are not bypassed. SYSCLK1/SYSCLK2/SYSCLK3 are divided down
from PLL output.
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PLL and PLL controller (continued)
Table 38. PLL Multiplier Control Register (PLLM) [0x01B7 C110]
31 28 27 24 23 20 19 16
Reserved
R−0
15 12 11 87654321 0
Reserved PLLM
R−0 R/W−0 0111
Legend: R = Read only, R/W = Read/Write; -n = value after reset
Table 39. PLL Multiplier Control Register (PLLM) Description
BIT # NAME DESCRIPTION
31:5 Reserved Reserved. Read-only, writes have no effect.
4:0 PLLM
PLL multiply mode [default is x7 (0 0111)].
00000 = Reserved 10000 = x16
00001 = Reserved 10001 = x17
00010 = Reserved 10010 = x18
00011 = Reserved 10011 = x19
00100 = x4 10100 = x20
00101 = x5 10101 = x21
00110 = x6 10110 = x22
00111 = x7 10111 = x23
01000 = x8 11000 = x24
01001 = x9 11001 = x25
01010 = x10 11010 = Reserved
01011 = x11 11011 = Reserved
01100 = x12 11100 = Reserved
01101 = x13 11101 = Reserved
01110 = x14 11110 = Reserved
01111 = x15 11111 = Reserved
PLLM select values 00000 through 00011 and 11010 through 11111 are not supported.
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PLL and PLL controller (continued)
Table 40. PLL Wrapper Divider x Registers (PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3)
[0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively]
31 28 27 24 23 20 19 16
Reserved
R−0
15 14 12 11 87 54 3 21 0
DxEN Reserved PLLDIVx
R/W−1 R−0 R/W−x xxxx†
Legend: R = Read only, R/W = Read/Write; -n = value after reset
†Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively.
CAUTION:
D1 and D2 should never be disabled. D3 should only be disabled if ECLKIN is used.
Table 41. PLL Wrapper Divider x Registers (Prescaler Divider D0 and Post-Scaler Dividers D1,
D2, and D3) Description‡
BIT # NAME DESCRIPTION
31:16 Reserved Reserved. Read-only, writes have no effect.
15 DxEN
Divider Dx Enable (where x denotes 0 through 3).
0 – Divider x Disabled. No clock output.
1 − Divider x Enabled (default).
These divider-enable bits are device-specific and must be set to 1 to enable.
14:5 Reserved Reserved. Read-only, writes have no effect.
4:0 PLLDIVx
PLL Divider Ratio [Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1,
/2, and /2, respectively].
00000 = /1 10000 = /17
00001 = /2 10001 = /18
00010 = /3 10010 = /19
00011 = /4 10011 = /20
00100 = /5 10100 = /21
00101 = /6 10101 = /22
00110 = /7 10110 = /23
00111 = /8 10111 = /24
01000 = /9 11000 = /25
01001 = /10 11001 = /26
01010 = /11 11010 = /27
01011 = /12 11011 = /28
01100 = /13 11100 = /29
01101 = /14 11101 = /30
01110 = /15 11110 = /31
01111 = /16 11111 = /32
‡Note that SYSCLK2 must run at half the rate of SYSCLK1. Therefore, the divider ratio of D2 must be two times slower than D1. For example,
if D1 is set to /2, then D2 must be set to /4.
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PLL and PLL controller (continued)
Table 42. Oscillator Divider 1 Register (OSCDIV1) [0x01B7 C124]
31 28 27 24 23 20 19 16
Reserved
R−0
15 14 12 11 87 54 3 21 0
OD1EN Reserved OSCDIV1
R/W−1 R−0 R/W−0 0111
Legend: R = Read only, R/W = Read/Write; -n = value after reset
The OSCDIV1 register controls the oscillator divider 1 for CLKOUT3. The CLKOUT3 signal does not go through
the PLL path.
Table 43. Oscillator Divider 1 Register (OSCDIV1) Description
BIT # NAME DESCRIPTION
31:16 Reserved Reserved. Read-only, writes have no effect.
15 OD1EN Oscillator Divider 1 Enable.
0 – Oscillator Divider 1 Disabled.
1 − Oscillator Divider 1 Enabled (default).
14:5 Reserved Reserved. Read-only, writes have no effect.
4:0 OSCDIV1
Oscillator Divider 1 Ratio [default is /8 (0 0111)].
00000 = /1 10000 = /17
00001 = /2 10001 = /18
00010 = /3 10010 = /19
00011 = /4 10011 = /20
00100 = /5 10100 = /21
00101 = /6 10101 = /22
00110 = /7 10110 = /23
00111 = /8 10111 = /24
01000 = /9 11000 = /25
01001 = /10 11001 = /26
01010 = /11 11010 = /27
01011 = /12 11011 = /28
01100 = /13 11100 = /29
01101 = /14 11101 = /30
01110 = /15 11110 = /31
01111 = /16 11111 = /32
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multichannel audio serial port (McASP) peripherals
The device includes two multi-channel audio serial port (McASP) interface peripherals (McASP1 and McASP0).
The McASP is a serial port optimized for the needs of multi-channel audio applications. With two McASP
peripherals, the device is capable of supporting two completely independent audio zones simultaneously.
Each McASP consists of a transmit and receive section. These sections can operate completely independently
with di fferent data formats, separate master clocks, bit clocks, and frame syncs or alternatively, the transmit and
receive sections may be synchronized. Each McASP module also includes a pool of 16 shift registers that may
be configured to operate as either transmit data, receive data, or general-purpose I/O (GPIO).
The transmit section of the McASP can transmit data in either a time-division-multiplexed (TDM) synchronous
serial format or in a digital audio interface (DIT) format where the bit stream is encoded for S/PDIF, AES-3,
IEC-60958, CP-430 transmission. The receive section of the McASP supports the TDM synchronous serial
format.
Each McASP can support one transmit data format (either a TDM format or DIT format) and one receive format
at a time. All transmit shift registers use the same format and all receive shift registers use the same format.
However, the transmit and receive formats need not be the same.
Both the transmit and receive sections of the McASP also support burst mode which is useful for non-audio data
(for example, passing control information between two DSPs).
The McASP peripherals have additional capability for flexible clock generation, and error detection/handling,
as well as error management.
McASP block diagram
Figure 16 illustrates the major blocks along with external signals of the McASP1 and McASP0 peripherals; and
shows the 8 serial data [AXR] pins for each McASP. Each McASP also includes full general-purpose I/O (GPIO)
control, so any pins not needed for serial transfers can be used for general-purpose I/O.
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multichannel audio serial port (McASP) peripherals (continued)
Receive
Clock
Generator
AHCLKR0
ACLKR0
Clock Check
Transmit
Generator
Clock
Transmit
ACLKX0
AHCLKX0
DIT
RAM
Transmit
Generator
Frame Sync AFSX0
Detect
Error
Receive
Frame Sync
GeneratorFormatter
Transmit
Data
AMUTE0
AMUTEIN0
AFSR0
Serializer 0
Serializer 1
Serializer 3
Serializer 2
Serializer 6
Serializer 7
Serializer 5
Serializer 4
(High-
Frequency)
Receive
Clock Check
(High-
Frequency)
Receive
Formatter
Data Formatter
Data
Receive
Serializer 4
Serializer 3
Serializer 7
Serializer 6
Serializer 5
Serializer 0
Serializer 1
Frame Sync
Generator
Receive
Frame Sync
Generator
Transmit
Transmit
Generator
Receive
Generator
Serializer 2
Error
Transmit
Formatter
Data
Clock Check
Frequency)
(High-
Receive
Detect
Frequency)
Clock Check
(High-
Transmit
RAM
DIT
AMUTE1
AFSR1
ACLKR1
AMUTEIN1
AHCLKR1
Clock
AFSX1
ACLKX1
AHCLKX1
Clock
AXR1[0]
AXR1[1]
AXR1[3]
AXR1[2]
AXR1[6]
AXR1[7]
AXR1[5]
AXR1[4]
McASP0 McASP1
DMA Transmit
DMA Transmit
DMA Receive
DMA Receive
INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO
INDIVIDUALLY PROGRAMMABLE TX/RX/GPIO
Control
GPIO
Control
GPIO
AXR0[0]
AXR0[1]
AXR0[3]
AXR0[2]
AXR0[6]
AXR0[7]
AXR0[5]
AXR0[4]
Figure 16. McASP0 and McASP1 Configuration
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multichannel audio serial port (McASP) peripherals (continued)
multichannel time division multiplexed (TDM) synchronous transfer mode
The McASP supports a multichannel, time-division-multiplexed (TDM) synchronous transfer mode for both
transmit and receive. Within this transfer mode, a wide variety of serial data formats are supported, including
formats compatible with devices using the Inter-Integrated Sound (IIS) protocol.
TDM synchronous transfer mode is typically used when communicating between integrated circuits such as
between a DSP and one or more ADC, DAC, CODEC, or S/PDIF receiver devices. In multichannel applications,
it is typical to find several devices operating synchronized with each other. For example, to provide six analog
outputs, three stereo DAC devices would be driven with the same bit clock and frame sync, but each stereo DAC
would use a different McASP serial data pin carrying stereo data (2 TDM time slots, left and right).
The TDM synchronous serial transfer mode utilizes several control signals and one or more serial data signals:
DA bit clock signal (ACLKX for transmit, ACKLR for receive)
DA frame sync signal (AFSX for transmit, AFSR for receive)
DAn (Optional) high frequency master clock (AHCLKX for transmit, AHCLKR for receive) from which the bit
clock is derived
DOne or more serial data pins (AXR for transmit and for receive).
Except for the optional high-frequency master clock, all of the signals in the TDM synchronous serial transfer
mode protocol are synchronous to the bit clocks (ACLKX and ACLKR).
In the TDM synchronous transfer mode, the McASP continually transmits and receives data periodically (since
audio ADCs and DACs operate at a fixed-data rate). The data is organized into frames, and the beginning of
a frame is marked by a frame sync pulse on the AFSX, AFSR pin.
In a typical audio system, one frame is transferred per sample period. To support multiple channels, the choices
are to either include more time slots per frame (and therefore operate with a higher bit clock) or to keep the bit
clock period constant and use additional data pins to transfer the same number of channels. For example, a
particular six-channel DAC might require three McASP serial data pins; transferring two channels of data on
each serial data pin during each sample period (frame). Another similar DAC may be designed to use only a
single McASP serial data pin, but clocked three times faster and transferring six channels of data per sample
period. The McASP is flexible enough to support either type of DAC but a transmitter cannot be configured to
do both at the same time.
For multiprocessor applications, the McASP supports any number of time slots per frame (between 2 and 32),
and includes the ability to “disable” transfers during specific time slots.
In addition, to support of S/PDIF, AES-3, IEC-60958, CP-430 receivers chips whose natural block (McASP
frame) size is 384 samples; the McASP receiver supports a 384 time slot mode. The advantage to using the
384 time slot mode is that interrupts may be generated synchronous to the S/PDIF, AES-3, IEC-60958, CP-430
receivers, for example the “last slot” interrupt.
burst transfer mode
The McASP also supports a burst transfer mode, which is useful for non-audio data (for example, passing
control information between two DSPs). Burst transfer mode uses a synchronous serial format similar to TDM,
except the frame sync is generated for each data word transferred. In addition, frame sync generation is not
periodic or time-driven as in TDM mode but rather data-driven.
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multichannel audio serial port (McASP) peripherals (continued)
supported bit stream formats for TDM and burst transfer modes
The serial data pins support a wide variety of formats. In the TDM and burst synchronous modes, the data may
be transmitted / received with the following options:
DTime slots per frame: 1 (Burst/Data Driven), or 2,3...32 (TDM/Time-Driven).
DTime slot size: 8, 12, 16, 20, 24, 28, 32 bits per time slot
DData size: 8, 12, 16, 20, 24, 28, 32 bits (must be less than or equal to time slot)
DData alignment within time slot: Left- or Right-Justified
DBit order: MSB or LSB first.
DUnused bits in time slot: Padded with 0, 1 or extended with value of another bit.
DTime slot delay from frame sync: 0,1, or 2 bit delay
The data format can be programmed independently for transmit and receive, and for McASP0 vs. McASP1. In
addition, the McASP can automatically re-align the data as processed natively by the DSP (any format on a
nibble boundary) adjusting the data in hardware to any of the supported serial bit stream formats (TDM, Burst,
and DIT modes). This reduces the amount of bit manipulation that the DSP must perform and simplifies software
architecture.
digital audio interface transmitter (DIT) transfer mode (transmitter only)
The McASP transmit section may also be configured in digital audio interface transmitter (DIT) mode where it
outputs data formatted for transmission over an S/PDIF, AES-3, IEC-60958, or CP-430 standard link. These
standards encode the serial data such that the equivalent of ’clock’ and ’frame sync’ are embedded within the
data stream. DIT transfer mode is used as an interconnect between audio components and can transfer
multichannel digital audio data over a single optical or coaxial cable.
From an internal DSP standpoint, the McASP operation in DIT transfer mode is similar to the two time slot TDM
mode, but the data transmitted is output as a bi-phase mark encoded bit stream with preamble, channel status,
user data, validity, and parity automatically stuffed into the bit stream by the McASP module. The McASP
includes separate validity bits for even/odd subframes and two 384-bit register file modules to hold channel
status and user data bits.
DIT mode requires at minimum:
DOne serial data pin (if the AUXCLK is used as the reference [see the PLL and Clock Generator Logic
Figure 15]) or
DOne serial data pin plus either the AHCLKX or ACLKX pin (if an external clock is needed).
If additional serial data pins are used, each McASP may be used to transmit multiple encoded bit streams (one
per pin). However, the bit streams will all be synchronized to the same clock and the user data, channel status,
and validity information carried by each bit stream will be the same for all bit streams transmitted by the same
McASP module.
The McASP can also automatically re-align the data as processed by the DSP (any format on a nibble boundary)
in DIT mode; reducing the amount of bit manipulation that the DSP must perform and simplifies software
architecture.
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multichannel audio serial port (McASP) peripherals (continued)
McASP flexible clock generators
The McASP transmit and receive clock generators are identical. Each clock generator can accept a
high-frequency master clock input (on the AHCLKX and AHCLKR pins).
The transmit and receive bit clocks (on the ACLKX and ACLKR pins) can also be sourced externally or can be
sourced internally by dividing down the high-frequency master clock input (programmable factor /1, /2, /3, ...
/4096). The polarity of each bit clock is individually programmable.
The frame sync pins are AFSX (transmit) and AFSR (receive). A typical usage for these pins is to carry the
left-right clock (LRCLK) signal when transmitting and receiving stereo data. The frame sync signals are
individually programmable for either internal or external generation, either bit or slot length, and either rising or
falling edge polarity.
Some examples of the things that a system designer can use the McASP clocking flexibility for are:
DInput a high-frequency master clock (for example, 512fs of the receiver), receive with an internally
generated bit clock ratio of /8, while transmitting with an internally generated bit clock ratio of /4 or /2. [An
example application would be to receive data from a DVD at 48 kHz but output up-sampled or decoded
audio at 96 kHz or 192 kHz.]
DTransmit/receive data based one sample rate (for example, 44.1 kHz) using McASP0 while transmitting and
receiving at a different sample rate (for example, 48 kHz) on McASP1.
DUse the DSP’s on-board AUXCLK to supply the system clock when the input source is an A/D converter.
McASP error handling and management
To support the design of a robust audio system, the McASP module includes error-checking capability for the
serial protocol, data underrun, and data overrun. In addition, each McASP includes a timer that continually
measures the high-frequency master clock every 32-SYSCLK2 clock cycles. The timer value can be read to
get a measurement of the high-frequency master clock frequency and has a min-max range setting that can
raise an error flag if the high-frequency master clock goes out of a specified range. The user would read the
high-frequency transmit master clock measurement (AHCLKX0 or AHCLKX1) by reading the XCNT field of the
XCLKCHK register and the user would read the high-frequency receive master clock measurement (AHCLKR0
or AHCLKR1) by reading the RCNT field of the RCLKCHK register.
Upon the detection of any one or more of the above errors (software selectable), or the assertion of the
AMUTE_IN pin, the AMUTE output pin may be asserted to a high or low level (selectable) to immediately mute
the audio output. In addition, an interrupt may be generated if enabled based on any one or more of the error
sources.
McASP interrupts and EDMA events
The McASP transmitter and receiver sections each generate an event on every time slot. This event can be
serviced by an interrupt or by the EDMA controller.
When using interrupts to service the McASP, each shift register buffer has a unique address in the McASP
Registers space (see Table 3).
When using the EDMA to service the McASP, the McASP DATA Port space in Table 3 is accessed. In this case,
the address least-significant bits are ignored. Writes to any address in this range access the transmitting buffers
in order from lowest (serializer 0) to highest (serializer 15), skipping over disabled and receiving serializers.
Likewise, reads from any address in this space access the receiving buffers in the same order but skip over
disabled and transmitting buffers.
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I2C
Having two I2C modules on the TMS320C6713B simplifies system architecture, since one module may be used
by the DSP to control local peripherals ICs (DACs, ADCs, etc.) while the other may be used to communicate
with other controllers in a system or to implement a user interface.
The TMS320C6713B also includes two I2C serial ports for control purposes. Each I2C port supports:
DCompatible with Philips I2C Specification Revision 2.1 (January 2000)
DFast Mode up to 400 Kbps (no fail-safe I/O buffers)
DNoise Filter to Remove Noise 50 ns or less
DSeven- and Ten-Bit Device Addressing Modes
DMaster (Transmit/Receive) and Slave (Transmit/Receive) Functionality
DEvents: DMA, Interrupt, or Polling
DSlew-Rate Limited Open-Drain Output Buffers
Figure 17 is a block diagram of the I2Cx module.
Clock
Prescale
I2CPSCx
SYSCLK2
From PLL
Clock Generator
I2CCLKHx
Generator
Bit Clock
I2CCLKLx
Noise
Filter
I2C Clock
SCL
I2CXSRx
I2CDXRx
Transmit
Transmit
Shift
Transmit
Buffer
I2CDRRx
Shift
I2CRSRx
Receive
Buffer
Receive
Receive
Filter
SDA
I2C Data Noise
I2COARx
I2CSARx Slave
Address
Control
Address
Own
I2CMDRx
I2CCNTx
Mode
Data
Count
Source
Interrupt
Interrupt
Status
I2CISRCx
I2CSTRx
Enable
Interrupt
I2CIERx
Interrupt/DMA
I2Cx Module
NOTE A: Shading denotes control/status registers.
Figure 17. I2Cx Module Block Diagram
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general-purpose input/output (GPIO)
To use the GP[15:0] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and
the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.
GPxEN = 1 GP[x] pin is enabled
GPxDIR = 0 GP[x] pin is an input
GPxDIR = 1 GP[x] pin is an output
where “x” represents one of the 15 through 0 GPIO pins
Figure 18 shows the GPIO enable bits in the GPEN register for the C6713B device. To use any of the GPx pins
as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1” (enabled). Default
values are device-specific, so refer to Figure 18 for the C6713B default configuration.
31 24 23 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6543210
GP15
EN GP14
EN GP13
EN GP12
EN GP11
EN GP10
EN GP9
EN GP8
EN GP7
EN GP6
EN GP5
EN GP4
EN GP3
EN GP2
EN GP1
EN GP0
EN
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 18. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]
Figure 19 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is
an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register. By
default, all the GPIO pins are configured as input pins.
31 24 23 16
Reserved
R-0
15 14 13 12 11 10 9 8 7 6543210
GP15
DIR GP14
DIR GP13
DIR GP12
DIR GP11
DIR GP10
DIR GP9
DIR GP8
DIR GP7
DIR GP6
DIR GP5
DIR GP4
DIR GP3
DIR GP2
DIR GP1
DIR GP0
DIR
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Legend: R/W = Readable/Writeable; -n = value after reset, -x = undefined value after reset
Figure 19. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]
For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).
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power-down mode logic
Figure 20 shows the power-down mode logic on the C6713B.
PWRD
Internal Clock Tree
CPU
IFR
IER
CSR
PD1
PD2
Power-
Down
Logic
Clock
PLL
CLKIN RESET
PD3
Internal
Peripherals
Clock
and Dividers
Distribution
†External input clocks, with the exception of CLKIN and CLKOUT3, are not gated by the power-down mode logic.
TMS320C6713B
CLKOUT2
Figure 20. Power-Down Mode Logic†
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triggering, wake-up, and effects
The device includes a programmable PLL which allows software control of PLL bypass via the PLLEN bit in the
PLLCSR register. With this enhanced functionality come some additional considerations when entering
power−down modes.
The power−down modes (PD2 and PD3) function by disabling the PLL to stop clocks to the C6713 device.
However, if the PLL is bypassed (PLLEN = 0), the device will still receive clocks from the external clock input
(CLKIN). Therefore, bypassing the PLL makes the power−down modes PD2 and PD3 ineffective.
The PLL needs to be enabled by writing a “1” to PLLEN bit (PLLCSR.0) before being able to enter either PD3
(CSR.11) or PD2 (CSR.10) in order for these modes to have an effect.
For the TMS320C6713B device it is recommended to use the PLLPWDN bit (PLLCSR.1) to enter a deep
power−down state equivalent to PD3 since the PLLPWDN bit takes full advantage of the PLL power−down
feature.
The power−down modes (PD1, PD2, and PD3) and their wake−up methods are programmed by setting the
PWRD field (bits 15−10) of the control status register (CSR). The PWRD field of the CSR is shown in Figure 21
and described in Table 44. When writing to the CSR, all bits of the PWRD field should be set at the same time.
Logic 0 should be used when “writing” to the reserved bit (bit 15) of the PWRD field. The CSR is discussed in
detail in the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
31 16
15 14 13 12 11 10 9 8
Reserved Enable or
Non-Enabled
Interrupt Wake
Enabled
Interrupt Wake PD3 PD2 PD1
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 0
Legend: R/W−x = Read/write reset value
NOTE: The shadowed bits are not part of the power-down logic discussion and therefore are not covered here. For information on these other
bit fields in the CSR register, see the TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189).
Figure 21. PWRD Field of the CSR Register
A delay of up to nine clock cycles may occur after the instruction that sets the PWRD bits in the CSR before the
PD mode t akes e ffect. A s b est p ractice, N OPs s hould b e p added a fter t he P WRD b its a re s et i n t he C SR t o a ccount
for this delay.
If P D1 m ode i s t erminated b y a n on-enabled i nterrupt, t he p rogram e x ecution r eturns t o t he i nstruction w here P D 1
took ef fect. I f P D1 m ode i s t erminated by an enabled i nterrupt, t he interrupt service r outine w ill b e e xecuted f irst,
then t he p rogram e xecution r eturns t o t he i nstruction w here P D1 t ook e f fect. I n t he c ase w ith an e nabled i nterrupt,
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the GIE bit in the CSR and the NMIE bit in the interrupt enable register (IER) must also be set in order for the
interrupt service routine to execute; otherwise, execution returns to the instruction where PD1 took effect upon
PD1 mode termination by an enabled interrupt.
PD2 and PD3 modes can only be aborted by device reset. Table 44 summarizes all the power-down modes.
Table 44. Characteristics of the Power-Down Modes
PRWD FIELD
(BITS 15−10) POWER-DOWN
MODE WAKE-UP METHOD EFFECT ON CHIP’S OPERATION
000000 No power-down — —
001001 PD1 Wake by an enabled interrupt CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
010001 PD1 Wake by an enabled or
non-enabled interrupt
Power-down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU’s logic from
switching. During PD1, EDMA transactions can proceed
between peripherals and internal memory.
011010 PD2†Wake by a device reset
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O “freeze” in the last state when the PLL clock is
turned off.
011100 PD3†Wake by a device reset
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O freeze in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re−lock, just as it does following power−up.
Wake−up from PD3 takes longer than wake−up from PD2
because the PLL needs to be re−locked, just as it does following
power−up.
It is recommended to use the PLLPWDN bit (PLLCSR.1) as an
alternative to PD3.
All others Reserved — —
†When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time
(>1 second) if the other supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up prior to (and powered down after), the I/O
buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the output buffers are
powered up, thus, preventing bus contention with other chips on the board.
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power-supply design considerations
A dual-power supply with simultaneous sequencing can be used to eliminate the delay between core and I/O
power up. A Schottky diode can also be used to tie the core rail to the I/O rail (see Figure 22).
DVDD
CVDD
VSS
C6000
DSP
Schottky
Diode
I/O Supply
Core Supply
GND
Figure 22. Schottky Diode Diagram
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the C6000 platform of DSPs, the PC board should include separate power planes for
core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
power-supply decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as possible
close to the DSP. Assuming 0603 caps, the user should be able to fit a total of 60 caps — 30 for the core supply
and 30 for the I/O supply. These caps need to be close (no more than 1.25 cm maximum distance) to the DSP
to be effective. Physically smaller caps are better, such as 0402, but the size needs to be evaluated from a
yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling capacitors,
therefore physically smaller capacitors should be used while maintaining the largest available capacitance
value. As with the selection of any component, verification of capacitor availability over the product’ s production
lifetime needs to be considered.
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IEEE 1149.1 JTAG compatibility statement
The TMS320C6713B DSP requires that both TRST and RESET resets be asserted upon power up to be
properly initialized. While RESET initializes the DSP core, TRST initializes the DSP’s emulation logic. Both
resets are required for proper operation.
Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as expected
after TRST is asserted.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for the
DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port interface
and DSP’s emulation logic in the reset state. TRST only needs to be released when it is necessary to use a JTAG
controller to debug the DSP or exercise the DSP’s boundary scan functionality.
The TMS320C6713B DSP includes an internal pulldown (IPD) on the TRST pin to ensure that TRST will always
be asserted upon power up and the DSP’s internal emulation logic will always be properly initialized when this
pin is not routed out. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party J TAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the DSP after powerup and externally drive
TRST high before attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRST must be “seen” to latch the state of EMU1
and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For
more detailed information, see the terminal functions section of this data sheet.
Note: The DESIGN−WARNING section of the TMS320C6713B BSDL file contains information and constraints
regarding proper device operation while in Boundary Scan Mode.
For more detailed information on the C6713B JTAG emulation, see the TMS320C6000 DSP Designing for JTAG
Emulation Reference Guide (literature number SPRU641).
EMIF device speed
The maximum EMIF speed on the C6713B device is 100 MHz. TI recommends utilizing I/O buffer information
specification (IBIS) to analyze all AC timings to determine if the maximum EMIF speed is achievable for a given
board layout. To properly use IBIS models to attain accurate timing analysis for a given system, see the Using
IBIS Models for Timing Analysis application report (literature number SPRA839).
For ease of design evaluation, Table 45 contains IBIS simulation results showing the maximum EMIF-SDRAM
interface speeds for the given example boards (TYPE) and SDRAM speed grades. Timing analysis should be
performed to verify that all AC timings are met for the specified board layout. Other configurations are also
possible, but again, timing analysis must be done to verify proper AC timings.
To maintain signal integrity, serial termination resistors should be inserted into all EMIF output signal lines (see
the Terminal Functions table for the EMIF output signals).
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Table 45. C6713B Example Boards and Maximum EMIF Speed
BOARD CONFIGURATION
MAXIMUM ACHIEVABLE
TYPE EMIF INTERFACE
COMPONENTS BOARD TRACE SDRAM SPEED GRADE
MAXIMUM ACHIEVABLE
EMIF-SDRAM
INTERFACE SPEED
143 MHz 32-bit SDRAM (−7) 100 MHz
1-Load
One bank of one
1 to 3-inch traces with proper
termination resistors;
166 MHz 32-bit SDRAM (−6) For short traces, SDRAM data
output hold time on these
1-Load
Short Traces
One bank of one
32-Bit SDRAM
1 to 3-inch traces with proper
termination resistors;
Trace impedance ~ 50 Ω183 MHz 32-bit SDRAM (−55)
output hold time on these
SDRAM speed grades cannot
meet EMIF input hold time
Trace impedance ~ 50 Ω
200 MHz 32-bit SDRAM (−5) meet EMIF input hold time
requirement (see NOTE 1).
125 MHz 16-bit SDRAM (−8E) 100 MHz
2-Loads
One bank of two
1.2 to 3 inches from EMIF to
each load, with proper
133 MHz 16-bit SDRAM (−75) 100 MHz
2-Loads
Short Traces
One bank of two
16-Bit SDRAMs
1.2 to 3 inches from EMIF to
each load, with proper
termination resistors;
143 MHz 16-bit SDRAM (−7E) 100 MHz
Short Traces
16-Bit SDRAMs
termination resistors;
Trace impedance ~ 78
Ω167 MHz 16-bit SDRAM (−6A) 100 MHz
Trace impedance ~ 78 Ω
167 MHz 16-bit SDRAM (−6) 100 MHz
125 MHz 16-bit SDRAM (−8E) For short traces, EMIF cannot
meet SDRAM input hold
requirement (see NOTE 1).
3-Loads
One bank of two
1.2 to 3 inches from EMIF to
each load, with proper
133 MHz 16-bit SDRAM (−75) 100 MHz
3-Loads
Short Traces
One bank of two
16-Bit SDRAMs
One bank of buffer
1.2 to 3 inches from EMIF to
each load, with proper
termination resistors;
143 MHz 16-bit SDRAM (−7E) 100 MHz
Short Traces
16-Bit SDRAMs
One bank of buffer
termination resistors;
Trace impedance ~ 78
Ω167 MHz 16-bit SDRAM (−6A) 100 MHz
Trace impedance ~ 78 Ω
167 MHz 16-bit SDRAM (−6) For short traces, EMIF cannot
meet SDRAM input hold
requirement (see NOTE 1).
One bank of one
143 MHz 32-bit SDRAM (−7) 83 MHz
One bank of one
32-Bit SDRAM
166 MHz 32-bit SDRAM (−6) 83 MHz
3-Loads
Long Traces
32-Bit SDRAM
One bank of one
4 to 7 inches from EMIF;
Trace impedance ~ 63 Ω
183 MHz 32-bit SDRAM (−55) 83 MHz
3-Loads
Long Traces
One bank of one
32-Bit SBSRAM
One bank of buffer
4 to 7 inches from EMIF;
Trace impedance ~ 63 Ω
200 MHz 32-bit SDRAM (−5) SDRAM data output hold time
cannot meet EMIF input hold
requirement (see NOTE 1).
NOTE 1: Results are based on IBIS simulations for the given example boards (TYPE). Timing analysis should be performed to determine if timing
requirements can be met for the particular system.
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EMIF big endian mode correctness
The HD8 pin device endian mode (LENDIAN) selects the endian mode of operation (Little or Big Endian). For
the C6713B device Little Endian is the default setting.
The HD12 pin (EMIF Big Endian Mode Correctness) [EMIFBE] enhancement allows the flexibility to change the
EMIF data placement on the EMIF bus.
When using the default setting of HD12 = 1 for the C6713B, the EMIF will present 8-bit or 16-bit data on the
ED[7:0] side of the bus if using Little Endian mode (HD8 = 1) and to the ED[31:24] side of the bus if using Big
Endian mode. Figure 23 shows the mapping of 16-bit and 8-bit C6713B devices.
EMIF DATA LINES (PINS) WHERE DATA PRESENT
ED[31:24] (BE3)ED[23:16] (BE2)ED[15:8] (BE1)ED[7:0] (BE0)
32-Bit Device in Any Endianness Mode
16-Bit Device in Big Endianness Mode 16-Bit Device in Little Endianness Mode
8-Bit Device in Big
Endianness Mode 8-Bit Device in Little Endianness Mode
Figure 23. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 1)
When HD12 = 0, enabling EMIF endianness correction, the EMIF will present 8-bit or 16-bit data on the ED[7:0]
side of the bus, regardless of the endianess mode (see Figure 24).
EMIF DATA LINES (PINS) WHERE DATA PRESENT
ED[31:24] (BE3)ED[23:16] (BE2)ED[15:8] (BE1)ED[7:0] (BE0)
32-Bit Device in Any Endianness Mode
16-Bit Device in Any Endianness Mode
8-Bit Device in Any Endianness Mode
Figure 24. 16/8-Bit EMIF Big Endian Mode Correctness Mapping (HD12 = 0)
This new endianness correction functionality does not affect systems using the default value of HD12 = 1.
This new feature does not affect systems operating in Little Endian mode.
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bootmode
The device resets using the active-low signal RESET and the internal reset signal. While RESET is low, the
internal reset is also asserted and the device is held in reset and is initialized to the prescribed reset state. Refer
to reset timing for reset timing characteristics and states of device pins during reset. The release of the internal
reset signal (see the Reset Phase 3 discussion in the Reset Timing section of this data sheet) starts the
processor running with the prescribed device configuration and boot mode.
The C6713B has three types of boot modes:
DHost boot
If host boot is selected, upon release of internal reset, the CPU is internally “stalled” while the remainder of
the device is released. During this period, an external host can initialize the CPU’s memory space as
necessary through the host interface, including internal configuration registers, such as those that control
the EMIF or other peripherals. Once the host is finished with all necessary initialization, it must set the
DSPINT bit in the HPIC register to complete the boot process. This transition causes the boot configuration
logic to bring the CPU out of the “stalled” state. The CPU then begins execution from address 0. The DSPINT
condition i s not latched by the CPU, because it occurs while the CPU is still internally “stalled”. Also, DSPINT
brings the CPU out of the “stalled” state only if the host boot process is selected. All memory may be written
to and read by the host. This allows for the host to verify what it sends to the DSP if required. After the CPU is
out of the “stalled” state , the CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.
DEmulation boot
Emulation boot mode is a variation of host boot. In this mode, it is not necessary for a host to load code or to
set DSPINT to release the CPU from the “stalled” state. Instead, the emulator will set DSPINT if it has not
been previously set so that the CPU can begin executing code from address 0. Prior to beginning execution,
the emulator sets a breakpoint at address 0. This prevents the execution of invalid code by halting the CPU
prior to executing the first instruction. Emulation boot is a good tool in the debug phase of development.
DEMIF boot (using default ROM timings)
Upon the release of internal reset, the 1K-Byte ROM code located in the beginning of CE1 is copied to
address 0 b y the EDMA using the default ROM timings, while the CPU is internally “stalled”. The data should
be stored in the endian format that the system is using. The boot process also lets you choose the width of
the ROM. In this case, the EMIF automatically assembles consecutive 8-bit bytes or 16-bit half-words to
form the 32-bit instruction words to be copied. The transfer is automatically done by the EDMA as a
single-frame block transfer from the ROM to address 0. After completion of the block transfer, the CPU is
released from the “stalled” state and start running from address 0.
reset
A hardware reset (RESET) is required to place the DSP into a known good state out of power−up. The RESET
signal can be asserted (pulled low) prior to ramping the core and I/O voltages or after the core and I/O voltages
have reached their proper operating conditions. As a best practice, reset should be held low during power−up.
Prior to deasserting RESET (low−to−high transition), the core and I/O voltages should be at their proper
operating conditions and CLKIN should also be running at the correct frequency.
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absolute maximum ratings over operating case temperature range (unless otherwise noted)†
Supply voltage range, CVDD (see Note 2) −0.3 V to 1.8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage range, DVDD (see Note 2) −0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range −0.3 V to DVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range −0.3 V to DVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature ranges, TC: (default) 0_C to 90_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(A version) [GDPA/ZDPA-200, PYPA-167,-200] −40_C to105_C
Storage temperature range, Tstg −65_C to 150_C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 2: All voltage values are with respect to VSS.
recommended operating conditions†
MIN NOM MAX UNIT
PYP packages only 1.14 1.20 1.32 V
CV
DD
Supply voltage, Core referenced to V
SS
GDP/ZDP packages for C6713B only 1.14‡1.20‡1.32 V
CVDD
Supply voltage, Core referenced to VSS
GDP/ZDP packages for C6713B−300 only 1.33 1.4 1.47 V
DVDD Supply voltage, I/O referenced to VSS 3.13 3.3 3.47 V
VIH
High-level input voltage (See Figure 28)
All signals except CLKS1/SCL1,
DR1/SDA1, SCL0, SDA0, and RESET 2 V
VIH High-level input voltage (See Figure 28) CLKS1/SCL1, DR1/SDA1, SCL0, SDA0,
and RESET 2 V
VIL
Low-level input voltage (See Figure 29)
All signals except CLKS1/SCL1,
DR1/SDA1, SCL0, SDA0, and RESET 0.8 V
VIL Low-level input voltage (See Figure 29) CLKS1/SCL1, DR1/SDA1, SCL0, SDA0,
and RESET 0.3*DVDD V
IOH High-level output current§
All signals except ECLKOUT, CLKOUT2,
CLKS1/SCL1, DR1/SDA1, SCL0, and
SDA0 −8 mA
OH
ECLKOUT and CLKOUT2 −16 mA
I
Low-level output current§
All signals except ECLKOUT, CLKOUT2,
CLKS1/SCL1, DR1/SDA1, SCL0, and
SDA0 8 mA
IOL Low-level output current§ECLKOUT and CLKOUT2 16 mA
CLKS1/SCL1, DR1/SDA1, SCL0, and
SDA0 3 mA
VOS Maximum voltage during overshoot (See Figure 28) 4¶V
VUS Maximum voltage during undershoot (See Figure 29) −0.7¶V
Default 0 90
TCOperating case temperature A version (GDPA/ZDPA -200,
PYPA-167,−200) –40 105 _C
†The core supply should be powered up prior to (and powered down after), the I/O supply. Systems should be designed to ensure that neither
supply is powered up for an extended period of time if the other supply is below the proper operating voltage.
‡These values are compatible with existing 1.26-V designs.
§Refers to DC (or steady state) currents only, actual switching currents are higher. For more details, see the device-specific IBIS models.
¶The absolute maximum ratings should not be exceeded for more than 30% of the cycle period.
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electrical characteristics over recommended ranges of supply voltage and operating case
temperature† (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output
voltage All signals except SCL1, SDA1,
SCL0, and SDA0 IOH =MAX 2.4 V
VOL
Low-level output
voltage
All signals except SCL1, SDA1,
SCL0, and SDA0 IOL = MAX 0.4 V
VOL
voltage SCL1, SDA1, SCL0, and SDA0 IOL = MAX 0.4 V
II
Input current
All signals except SCL1, SDA1,
SCL0, and SDA0
VI = VSS to DVDD
±170 uA
II
Input current
SCL1, SDA1, SCL0, and SDA0
VI = VSS to DVDD
±10 uA
IOZ
Off-state output
current
All signals except SCL1, SDA1,
SCL0, and SDA0
VO = DVDD or 0 V
±170 uA
IOZ
current SCL1, SDA1, SCL0, and SDA0
VO = DVDD or 0 V
±10 uA
GDP/ZDP, CVDD = 1.4 V,
CPU clock = 300 MHz 945 mA
GDP/ZDP/PYP, CVDD =
1.26 V, CPU clock = 225
MHz 625 mA
IDD2V Core supply current‡GDPA/ZDPA, CVDD =1.26V
CPU clock = 200 MHz 560 mA
GDPA/ZDPA/PYP/ PYPA
CVDD =1.2 V CPU clock =
200 MHz 565 mA
PYPA, CVDD =1.2 V CPU
clock = 167 MHz 480 mA
IDD3V I/O supply current‡DVDD = 3.3 V, EMIF speed
= 100 MHz 75 mA
CiInput capacitance 7 pF
CoOutput capacitance 7 pF
†For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
‡Measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF. This model represents a device
performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity
models are defined as follows:
High-DSP-Activity Model:
CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;
L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
Low-DSP-Activity Model:
CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles;
L2/EMIF EDMA: None]
McBSP: 2 channels at E1 rate
Timers: 2 timers at maximum rate
The actual current draw is highly application-dependent. For more details on core and I/O activity, r ef e r t o t he TMS320C6711D, C6712D, C6713B
Power Consumption Summary application report (literature number SPRA889A2 or later).
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PARAMETER MEASUREMENT INFORMATION
Transmission Line
4.0 pF 1.85 pF
Z0 = 50 W
(see note)
Tester Pin Electronics Data Sheet Timing Reference Point
Output
Under
Test
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects
must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line ef fect.
The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from
the data sheet timings.
42 W3.5 nH
Device Pin
(see note)
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 25. Test Load Circuit for AC Timing Measurements
signal transition levels
All input and output timing parameters are referenced to 1.5 V for both “0” and “1” logic levels.
Vref = 1.5 V
Figure 26. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX
and VOH MIN for output clocks.
Vref = VIL MAX (or VOL MAX)
Vref = VIH MIN (or VOH MIN)
Figure 27. Rise and Fall Transition Time Voltage Reference Levels
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PARAMETER MEASUREMENT INFORMATION (CONTINUED)
AC transient rise/fall time specifications
Figure 28 and Figure 29 show the AC transient specifications for Rise and Fall Time. For device-specific
information on these values, refer to the Recommended Operating Conditions section of this Data Sheet.
VOS (max)
VIH (min)
Minimum
Risetime
Waveform
Valid Region
t = 0.3 tc (max)†
Ground
Figure 28. AC Transient Specification Rise Time
†tc = the peripheral cycle time.
t = 0.3 tc(max)†
VIL (max)
Ground
VUS (max)
Figure 29. AC Transient Specification Fall Time
†tc = the peripheral cycle time.
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PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a good
board design practice, such delays must always be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to attain accurate
timing analysis for a given system, see the Using IBIS Models for Timing Analysis application report (literature
number SPRA839). If needed, external logic hardware such as buffers may be used to compensate any timing
differences.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 46 and Figure 30).
Figure 30 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
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PARAMETER MEASUREMENT INFORMATION (CONTINUED)
Table 46. Board-Level Timings Example (see Figure 30)
NO. DESCRIPTION
1Clock route delay
2Minimum DSP hold time
3Minimum DSP setup time
4External device hold time requirement
5External device setup time requirement
6Control signal route delay
7External device hold time
8External device access time
9DSP hold time requirement
10 DSP setup time requirement
11 Data route delay
1
2
3
4
5
6
7
8
10
11
ECLKOUT
(Output from DSP)
ECLKOUT
(Input to External Device)
Control Signals†
(Output from DSP)
Control Signals
(Input to External Device)
Data Signals‡
(Output from External Device)
Data Signals‡
(Input to DSP)
9
† Control signals include data for Writes.
‡ Data signals are generated during Reads from an external device.
Figure 30. Board-Level Input/Output Timings
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INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN for PYP-200 and GDP/ZDP-225†‡§ (see Figure 31)
PYP−200 GDP/ZDP−225
NO
.
PLL MODE
(PLLEN = 1) BYPASS MODE
(PLLEN = 0) PLL MODE
(PLLEN = 1) BYPASS MODE
(PLLEN = 0) UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 tc(CLKIN) Cycle time, CLKIN 5 83.3 6.7 4.4 83.3 6.7 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns
4 tt(CLKIN) Transition time, CLKIN 5 5 5 5 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.
§See the PLL and PLL controller section of this data sheet.
timing requirements for CLKIN for PYP-225 and GDP/ZDP-300 †‡§ (see Figure 31)
PYP−225 GDP/ZDP−300
NO
.
PLL MODE
(PLLEN = 1) BYPASS MODE
(PLLEN = 0) PLL MODE
(PLLEN = 1) BYPASS MODE
(PLLEN = 0) UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 tc(CLKIN) Cycle time, CLKIN 4.4 83.3 6.7 4 83.3 6.7 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns
4 tt(CLKIN) Transition time, CLKIN 5 5 5 5 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.
§See the PLL and PLL controller section of this data sheet.
timing requirements for CLKIN for PYPA-167, GDPA/ZDPA-200 and PYPA-200†‡§ (see Figure 31)
PYPA−167 GDPA/ZDPA−200 AND PYPA−200
NO
.
PLL MODE
(PLLEN = 1) BYPASS MODE
(PLLEN = 0) PLL MODE
(PLLEN = 1) BYPASS MODE
(PLLEN = 0) UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
1 tc(CLKIN) Cycle time, CLKIN 6 83.3 6.7 5 83.3 6.7 ns
2 tw(CLKINH) Pulse duration, CLKIN high 0.4C 0.4C 0.4C 0.4C ns
3 tw(CLKINL) Pulse duration, CLKIN low 0.4C 0.4C 0.4C 0.4C ns
4 tt(CLKIN) Transition time, CLKIN 5 5 5 5 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
‡C = CLKIN cycle time in nanoseconds (ns). For example, when CLKIN frequency is 40 MHz, use C = 25 ns.
§See the PLL and PLL controller section of this data sheet.
CLKIN
1
2
3
4
4
Figure 31. CLKIN Timings
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INPUT AND OUTPUT CLOCKS (CONTINUED)
switching characteristics over recommended operating conditions for CLKOUT2†‡
(see Figure 32)
NO. PARAMETER
PYP −200, −225
GDP/ZDP −225, -300
PYPA −167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tc(CKO2) Cycle time, CLKOUT2 C2 − 0.8 C2 + 0.8 ns
2 tw(CKO2H) Pulse duration, CLKOUT2 high (C2/2) − 0.8 (C2/2) + 0.8 ns
3 tw(CKO2L) Pulse duration, CLKOUT2 low (C2/2) − 0.8 (C2/2) + 0.8 ns
4 tt(CKO2) Transition time, CLKOUT2 2 ns
†The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
‡C2 = CLKOUT2 period in ns. CLKOUT2 period is determined by the PLL controller output SYSCLK2 period, which must be set to CPU period
divide-by-2.
CLKOUT2
1
2
3
4
4
Figure 32. CLKOUT2 Timings
switching characteristics over recommended operating conditions for CLKOUT3†§
(see Figure 33)
NO. PARAMETER
PYP −200, −225
GDP/ZDP −225, -300
PYPA −167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tc(CKO3) Cycle time, CLKOUT3 C3 − 0.9 C3 + 0.9 ns
2 tw(CKO3H) Pulse duration, CLKOUT3 high (C3/2) − 0.9 (C3/2) + 0.9 ns
3 tw(CKO3L) Pulse duration, CLKOUT3 low (C3/2) − 0.9 (C3/2) + 0.9 ns
4 tt(CKO3) Transition time, CLKOUT3 3 ns
5 td(CLKINH-CKO3V) Delay time, CLKIN high to CLKOUT3 valid 1.5 7.5 ns
†The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
§C3 = CLKOUT3 period in ns. CLKOUT3 period is a divide-down of the CPU clock, configurable via the OSCDIV1 register . For more de tails, see
PLL and PLL controller.
CLKIN
CLKOUT3
NOTE A: For this example, the CLKOUT3 frequency is CLKIN divide-by-2.
3
1
2
4
4
55
Figure 33. CLKOUT3 Timings
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INPUT AND OUTPUT CLOCKS (CONTINUED)
timing requirements for ECLKIN† (see Figure 34)
NO
.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tc(EKI) Cycle time, ECLKIN 10 ns
2 tw(EKIH) Pulse duration, ECLKIN high 4.5 ns
3 tw(EKIL) Pulse duration, ECLKIN low 4.5 ns
4 tt(EKI) Transition time, ECLKIN 3 ns
†The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
ECLKIN
1
2
3
4
4
Figure 34. ECLKIN Timings
switching characteristics over recommended operating conditions for ECLKOUT‡§#
(see Figure 35)
NO
.
PARAMETER
PYP−200, -225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tc(EKO) Cycle time, ECLKOUT E − 0.9 E + 0.9 ns
2 tw(EKOH) Pulse duration, ECLKOUT high EH − 0.9 EH + 0.9 ns
3 tw(EKOL) Pulse duration, ECLKOUT low EL − 0.9 EL + 0.9 ns
4 tt(EKO) Transition time, ECLKOUT 2 ns
5 td(EKIH-EKOH) Delay time, ECLKIN high to ECLKOUT high 1 6.5 ns
6 td(EKIL-EKOL) Delay time, ECLKIN low to ECLKOUT low 1 6.5 ns
‡The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
§E = ECLKIN period in ns
¶EH is the high period of ECLKIN in ns and EL is the low period of ECLKIN in ns.
561
23
ECLKINECLKIN
ECLKOUT
44
Figure 35. ECLKOUT Timings
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ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles†‡§ (see Figure 36−Figure 37)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA −167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
3 tsu(EDV-AREH) Setup time, EDx valid before ARE high 6.5 ns
4 th(AREH-EDV) Hold time, EDx valid after ARE high 1 ns
6 tsu(ARDY-EKOH) Setup time, ARDY valid before ECLKOUT high 3 ns
7 th(EKOH-ARDY) Hold time, ARDY valid after ECLKOUT high 2.3 ns
†To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is recognized in
the cycle for which the setup and hold time is met. To use ARDY as an asynchronous input, the pulse width of the ARDY signal should be wide
enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
‡RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§E = ECLKOUT period in ns
switching characteristics over recommended operating conditions for asynchronous memory
cycles‡§¶ (see Figure 36−Figure 37)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tosu(SELV-AREL) Output setup time, select signals valid to ARE low RS*E − 1.7 ns
2 toh(AREH-SELIV) Output hold time, ARE high to select signals invalid RH*E − 1.7 ns
5 td(EKOH-AREV) Delay time, ECLKOUT high to ARE valid 1.5 7 ns
8 tosu(SELV-AWEL) Output setup time, select signals valid to AWE low WS*E − 1.7 ns
9 toh(AWEH-SELIV) Output hold time, AWE high to select signals and EDx invalid WH*E − 1.7 ns
10 td(EKOH-AWEV) Delay time, ECLKOUT high to AWE valid 1.5 7 ns
11 tosu(EDV-AWEL) Output setup time, ED valid to AWE low (WS−1)*E −
1.7 ns
‡RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters are
programmed via the EMIF CE space control registers.
§E = ECLKOUT period in ns
¶Select signals include: CEx, BE[3:0], EA[21:2], and AOE.
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Not Ready Hold = 2
BE
Address
Read Data 21
21
21
21
5
4
3
ARDY
77
66
5
ECLKOUT
CEx
EA[21:2]
ED[31:0]
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
BE[3:0]
AWE/SDWE/SSWE†
†AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 36. Asynchronous Memory Read Timing
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ASYNCHRONOUS MEMORY TIMING (CONTINUED)
Setup = 2 Strobe = 3 Not Ready Hold = 2
BE
Address
Write Data
1010
9
11
9
8
9
8
9
8
77 66
ECLKOUT
CEx
EA[21:2]
ED[31:0]
BE[3:0]
ARDY
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
†AOE/SDRAS/SSOE, ARE/SDCAS/SSADS, and AWE/SDWE/SSWE operate as AOE (identified under select signals), ARE, and AWE,
respectively, during asynchronous memory accesses.
Figure 37. Asynchronous Memory Write Timing
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SYNCHRONOUS-BURST MEMORY TIMING
timing requirements for synchronous-burst SRAM cycles† (see Figure 38)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 1.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 ns
†The C6713B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts,
but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous-burst SRAM
cycles†‡ (see Figure 38 and Figure 39)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA
-167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.2 7 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 7 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.2 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 7 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.2 ns
8 td(EKOH-ADSV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.2 7 ns
9 td(EKOH-OEV) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.2 7 ns
10 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 7 ns
11 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.2 ns
12 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.2 7 ns
†The C6713B SBSRAM interface takes advantage of the internal burst counter in the SBSRAM. Accesses default to incrementing 4-word bursts,
but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
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SYNCHRONOUS-BURST MEMORY TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
ARE/SDCAS/SSADS†
AOE/SDRAS/SSOE†
AWE/SDWE/SSWE†
BE1 BE2 BE3 BE4
EA
Q1 Q2 Q3 Q4
9
1
45
88
9
67
3
1
2
†ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
Figure 38. SBSRAM Read Timing
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
ARE/SDCAS/SSADS†
AOE/SDRAS/SSOE†
AWE/SDWE/SSWE†
BE1 BE2 BE3 BE4
Q1 Q2 Q3 Q4
12
11
3
1
8
12
10
4
2
1
8
5
EA
†ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE operate as SSADS, SSOE, and SSWE, respectively, during SBSRAM
accesses.
Figure 39. SBSRAM Write Timing
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SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles† (see Figure 40)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
6 tsu(EDV-EKOH) Setup time, read EDx valid before ECLKOUT high 1.5 ns
7 th(EKOH-EDV) Hold time, read EDx valid after ECLKOUT high 2.5 ns
†The C6713B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts,
but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
switching characteristics over recommended operating conditions for synchronous DRAM
cycles†‡ (see Figure 40−Figure 46)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 td(EKOH-CEV) Delay time, ECLKOUT high to CEx valid 1.5 7 ns
2 td(EKOH-BEV) Delay time, ECLKOUT high to BEx valid 7 ns
3 td(EKOH-BEIV) Delay time, ECLKOUT high to BEx invalid 1.5 ns
4 td(EKOH-EAV) Delay time, ECLKOUT high to EAx valid 7 ns
5 td(EKOH-EAIV) Delay time, ECLKOUT high to EAx invalid 1.5 ns
8 td(EKOH-CASV) Delay time, ECLKOUT high to ARE/SDCAS/SSADS valid 1.5 7 ns
9 td(EKOH-EDV) Delay time, ECLKOUT high to EDx valid 7 ns
10 td(EKOH-EDIV) Delay time, ECLKOUT high to EDx invalid 1.5 ns
11 td(EKOH-WEV) Delay time, ECLKOUT high to AWE/SDWE/SSWE valid 1.5 7 ns
12 td(EKOH-RAS) Delay time, ECLKOUT high to, AOE/SDRAS/SSOE valid 1.5 7 ns
†The C6713B SDRAM interface takes advantage of the internal burst counter in the SDRAM. Accesses default to incrementing 4-word bursts,
but random bursts and decrementing bursts are done by interrupting bursts in progress. All burst types can sustain continuous data flow.
‡ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
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SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[11:2]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
EA[21:13]
BE1 BE2 BE3 BE4
Bank
Column
D1 D2 D3 D4
8
7
6
5
5
5
1
3
2
8
4
4
4
1
READ
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 40. SDRAM Read Command (CAS Latency 3)
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SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[11:2]
ED[31:0]
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
EA12
EA[21:13]
BE1 BE2 BE3 BE4
Bank
Column
D1 D2 D3 D4
11
8
9
5
5
5
2
1
11
8
9
4
4
2
1
10
3
4
WRITE
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 41. SDRAM Write Command
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SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:13]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
Bank Activate
Row Address
Row Address
12
5
5
5
1
EA[11:2]
ACTV
12
4
4
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 42. SDRAM ACTV Command
ECLKOUT
CEx
BE[3:0]
EA[21:13, 11:2]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†11
12
5
1
DCAB
11
12
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 43. SDRAM DCAB Command
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SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:13]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
EA[11:2]
Bank
11
12
5
5
1
DEAC
11
12
4
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 44. SDRAM DEAC Command
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
EA12
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
8
12
1
REFR
8
12
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 45. SDRAM REFR Command
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SYNCHRONOUS DRAM TIMING (CONTINUED)
ECLKOUT
CEx
BE[3:0]
EA[21:2]
ED[31:0]
AOE/SDRAS/SSOE†
ARE/SDCAS/SSADS†
AWE/SDWE/SSWE†
MRS value
11
8
12
5
1
MRS
11
8
12
4
1
†ARE/SDCAS/SSADS, AWE/SDWE/SSWE, and AOE/SDRAS/SSOE operate as SDCAS, SDWE, and SDRAS, respectively, during SDRAM
accesses.
Figure 46. SDRAM MRS Command
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HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles† (see Figure 47)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
3 th(HOLDAL-HOLDL) Hold time, HOLD low after HOLDA low E ns
†E = ECLKOUT period in ns
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles†‡
(see Figure 47)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 td(HOLDL-EMHZ) Delay time, HOLD low to EMIF Bus high impedance 2E § ns
2 td(EMHZ-HOLDAL) Delay time, EMIF Bus high impedance to HOLDA low 0 2E ns
4 td(HOLDH-EMLZ) Delay time, HOLD high to EMIF Bus low impedance 2E 7E ns
5 td(EMLZ-HOLDAH) Delay time, EMIF Bus low impedance to HOLDA high 0 2E ns
†E = ECLKOUT period in ns
‡EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
§All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus†
DSP Owns Bus External Requestor
Owns Bus DSP Owns Bus
C6713B C6713B
1
3
25
4
†EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE/SDCAS/SSADS, AOE/SDRAS/SSOE, and AWE/SDWE/SSWE.
Figure 47. HOLD/HOLDA Timing
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BUSREQ TIMING
switching characteristics over recommended operating conditions for the BUSREQ cycles
(see Figure 48)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA
-167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 td(EKOH-BUSRV) Delay time, ECLKOUT high to BUSREQ valid 1.5 7.2 ns
ECLKOUT
1
BUSREQ
1
Figure 48. BUSREQ Timing
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RESET TIMING
timing requirements for reset†‡ (see Figure 49)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tw(RST) Pulse duration, RESET 100 ns
13 tsu(HD) Setup time, HD boot configuration bits valid before RESET high§2P ns
14 th(HD) Hold time, HD boot configuration bits valid after RESET high§2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For the C6713B device, the PLL is bypassed immediately after the device comes out of reset. The PLL Controller can be programmed to change
the PLL mode in software. For more detailed information on the PLL Controller , see the TMS320C6000 DSP Phase-Lock Loop (PLL) Controller
Peripheral Reference Guide (literature number SPRU233).
§The Boot and device configurations bits are latched asynchronously when RESET is transitioning high. The Boot and device configurations bits
consist of: HD[14, 8, 4:3].
switching characteristics over recommended operating conditions during reset¶ (see Figure 49)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA-167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
2 td(RSTH-ZV) Delay time, external RESET high to internal reset high and
all signal groups valid#|| CLKMODE0 = 1 512 x CLKIN
period ns
3 td(RSTL-ECKOL) Delay time, RESET low to ECLKOUT high impedance 0 ns
4 td(RSTH-ECKOV) Delay time, RESET high to ECLKOUT valid 6P ns
5 td(RSTL-CKO2IV) Delay time, RESET low to CLKOUT2 high impedance 0 ns
6 td(RSTH-CKO2V) Delay time, RESET high to CLKOUT2 valid 6P ns
7 td(RSTL-CKO3L) Delay time, RESET low to CLKOUT3 low 0 ns
8 td(RSTH-CKO3V) Delay time, RESET high to CLKOUT3 valid 6P ns
9 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z group high impedance|| 0 ns
10 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group (BUSREQ) invalid|| 0 ns
11 td(RSTL-Z1HZ) Delay time, RESET low to Z group 1 high impedance|| 0 ns
12 td(RSTL-Z2HZ) Delay time, RESET low to Z group 2 high impedance|| 0 ns
¶P = 1/CPU clock frequency in ns.
Note that while internal reset is asserted low, the CPU clock (SYSCLK1) period is equal to the input clock (CLKIN) period multiplied by 8. For
example, if the CLKIN period is 20 ns, then the CPU clock (SYSCLK1) period is 20 ns x 8 = 160 ns. Therefore, P = SYSCLK1 = 160 ns while
internal reset is asserted.
#The internal reset is stretched exactly 512 x CLKIN cycles if CLKIN is used (CLKMODE0 = 1). If the input clock (CLKIN) is not stable when RESET
is deasserted, the actual delay time may vary.
|| EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and
HOLDA
EMIF low group consists of: BUSREQ
Z group 1 consists of: CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7],
FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0.
Z group 2 consists of: All other HPI, McASP0/1, GPIO, and I2C1 signals.
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RESET TIMING (CONTINUED)
Phase 1 Phase 2
12
11
10
9
87
65
43
14
13
2
11
CLKIN
ECLKIN
Internal Reset
Internal SYSCLK1
Internal SYSCLK2
Internal SYSCLK3
CLKOUT3
RESET
Phase 3
EMIF Z Group†
EMIF Low Group†
Z Group 1†
Z Group 2†
Boot and Device
Configuration Pins‡
2
2
2
2
ECLKOUT
CLKOUT2
†EMIF Z group consists of: EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and
HOLDA
EMIF low group consists of: BUSREQ
Z group 1 consists of: CLKR0/ACLKR0, CLKR1/AXR0[6], CLKX0/ACLKX0, CLKX1/AMUTE0, FSR0/AFSR0, FSR1/AXR0[7],
FSX0/AFSX0, FSX1, DX0/AXR0[1], DX1/AXR0[5], TOUT0/AXR0[2], TOUT1/AXR0[4], SDA0 and SCL0.
Z group 2 consists of: All other HPI, McASP0/1, GPIO, and I2C1 signals.
‡Boot and device configurations consist of: HD[14, 8, 4:3].
Figure 49. Reset Timing
Reset Phase 1: The RESET pin is asserted. During this time, all internal clocks are running at the CLKIN
frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8.
Reset Phase 2: The RESET pin is deasserted but the internal reset is stretched. During this time, all internal
clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency
divide-by-8.
Reset Phase 3: Both the RESET pin and internal reset are deasserted. During this time, all internal clocks are
running at their default divide-down frequency of CLKIN. The CPU clock (SYSCLK1) is running at CLKIN
frequency. The peripheral clock (SYSCLK2) is running at CLKIN frequency divide-by-2. The EMIF internal clock
source (SYSCLK3) is running at CLKIN frequency divide-by-2. SYSCLK3 is reflected on the ECLKOUT pin
(when EKSRC bit = 0 [default]). CLKOUT3 is running at CLKIN frequency divide-by-8.
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EXTERNAL INTERRUPT TIMING
timing requirements for external interrupts† (see Figure 50)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1
tw(ILOW)
Width of the NMI interrupt pulse low 2P ns
1 tw(ILOW) Width of the EXT_INT interrupt pulse low 4P ns
2
tw(IHIGH)
Width of the NMI interrupt pulse high 2P ns
2
t
w(IHIGH) Width of the EXT_INT interrupt pulse high 4P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
2
1
EXT_INT, NMI
Figure 50. External/NMI Interrupt Timing
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MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING
timing requirements for McASP (see Figure 51 and Figure 52)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tc(AHCKRX) Cycle time, AHCLKR/X 20 ns
2 tw(AHCKRX) Pulse duration, AHCLKR/X high or low 7.5 ns
3 tc(ACKRX) Cycle time, ACLKR/X ACLKR/X ext greater of 2P
or 33 ns†ns
4 tw(ACKRX) Pulse duration, ACLKR/X high or low ACLKR/X ext 14 ns
5
tsu(AFRXC-ACKRX)
Setup time, AFSR/X input valid before ACLKR/X latches
ACLKR/X int 6 ns
5 tsu(AFRXC-ACKRX
)
Setup time, AFSR/X input valid before ACLKR/X latches
data ACLKR/X ext 3 ns
6
th(ACKRX-AFRX)
Hold time, AFSR/X input valid after ACLKR/X latches
ACLKR/X int 0 ns
6 th(ACKRX-AFRX
)
Hold time, AFSR/X input valid after ACLKR/X latches
data ACLKR/X ext 3 ns
7
tsu(AXR-ACKRX)
Setup time, AXR input valid before ACLKR/X latches
ACLKR/X int 8 ns
7 tsu(AXR-ACKRX
)
Setup time, AXR input valid before ACLKR/X latches
data ACLKR/X ext 3 ns
8
th(ACKRX-AXR)
Hold time, AXR input valid after ACLKR/X latches data
ACLKR/X int 1 ns
8 th(ACKRX-AXR) Hold time, AXR input valid after ACLKR/X latches data ACLKR/X ext 3 ns
†P = SYSCLK2 period.
switching characteristics over recommended operating conditions for McASP‡ (see Figure 51
and Figure 52)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
9 tc(AHCKRX) Cycle time, AHCLKR/X 20 ns
10 tw(AHCKRX) Pulse duration, AHCLKR/X high or low (AH/2) − 2.5 ns
11 tc(ACKRX) Cycle time, ACLKR/X ACLKR/X int greater of 2P
or 33 ns†ns
12 tw(ACKRX) Pulse duration, ACLKR/X high or low ACLKR/X int (A/2) − 2.5 ns
13
td(ACKRX-AFRX)
Delay time, ACLKR/X transmit edge to AFSX/R output
ACLKR/X int −1 5 ns
13 td(ACKRX-AFRX)
Delay time, ACLKR/X transmit edge to AFSX/R output
valid ACLKR/X ext 0 10 ns
14
td(ACKX-AXRV)
Delay time, ACLKX transmit edge to AXR output valid
ACLKR/X int −1 5 ns
14 td(ACKX-AXRV) Delay time, ACLKX transmit edge to AXR output valid ACLKR/X ext 0 10 ns
15
tdis(ACKRX−AXRHZ)
Disable time, AXR high impedance following last data bit
ACLKR/X int −1 10 ns
15 tdis(ACKRX−AXRHZ
)
Disable time, AXR high impedance following last data bit
from ACLKR/X transmit edge ACLKR/X ext −1 10 ns
†P = SYSCLK2 period.
‡AH = AHCLKR/X period in ns.
A = ACLKR/X period in ns.
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MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)
8
7
4
4
3
2
21
A0 A1 B0 B1A30 A31 B30 B31 C0 C1 C2 C3 C31
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data In/Receive)
6
5
ACLKR/X (CLKRP = CLKXP = 0)†
ACLKR/X (CLKRP = CLKXP = 1)‡
†For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling
edge (to shift data in).
‡For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising
edge (to shift data in).
Figure 51. McASP Input Timings
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MULTICHANNEL AUDIO SERIAL PORT (McASP) TIMING (CONTINUED)
15
14
13
13
13
13
13
13
13
12
12
11
10
10
9
A0 A1 B0 B1A30 A31 B30 B31 C0 C1 C2 C3 C31
AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
ACLKR/X (CLKRP = CLKXP = 0)‡
ACLKR/X (CLKRP = CLKXP = 1)†
†For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP receiver is configured for rising
edge (to shift data in).
‡For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP receiver is configured for falling
edge (to shift data in).
Figure 52. McASP Output Timings
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INTER-INTEGRATED CIRCUITS (I2C) TIMING
timing requirements for I2C timings† (see Figure 53)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200
UNIT
NO.
STANDARD
MODE FAST
MODE
UNIT
MIN MAX MIN MAX
1 tc(SCL) Cycle time, SCL 10 2.5 µs
2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START
condition) 4.7 0.6 µs
3 th(SCLL-SDAL) Hold time, SCL low after SDA low (for a START and a repeated
START condition) 4 0.6 µs
4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
5 tw(SCLH) Pulse duration, SCL high 4 0.6 µs
6 tsu(SDAV-SDLH) Setup time, SDA valid before SCL high 250 100‡ns
7 th(SDA-SDLL) Hold time, SDA valid after SCL low (For I2C bus devices) 0§0§0.9¶µs
8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
9 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb#300 ns
10 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb#300 ns
11 tf(SDA) Fall time, SDA 300 20 + 0.1Cb#300 ns
12 tf(SCL) Fall time, SCL 300 20 + 0.1Cb#300 ns
13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 µs
14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
15 Cb#Capacitive load for each bus line 400 400 pF
†The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
‡A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA−SCLH) ≥ 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA−SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode
I2C-Bus Specification) before the SCL line is released.
§A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
¶The maximum th(SDA−SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
#Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
10
84
3712
5
614
2
3
13
Stop Start Repeated
Start Stop
SDA
SCL
1
11 9
Figure 53. I2C Receive Timings
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128 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
INTER-INTEGRATED CIRCUITS (I2C) TIMING (CONTINUED)
switching characteristics for I2C timings† (see Figure 54)
NO.
PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200
UNIT
NO.
PARAMETER
STANDARD
MODE FAST
MODE
UNIT
MIN MAX MIN MAX
16 tc(SCL) Cycle time, SCL 10 2.5 µs
17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 µs
18 td(SDAL-SCLL) Delay time, SDA low to SCL low (for a START and a repeated
START condition) 4 0.6 µs
19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 µs
20 tw(SCLH) Pulse duration, SCL high 4 0.6 µs
21 td(SDAV-SDLH) Delay time, SDA valid to SCL high 250 100 ns
22 tv(SDLL-SDAV) Valid time, SDA valid after SCL low (For I2C bus devices) 0 0 0.9 µs
23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 µs
24 tr(SDA) Rise time, SDA 1000 20 + 0.1Cb†300 ns
25 tr(SCL) Rise time, SCL 1000 20 + 0.1Cb†300 ns
26 tf(SDA) Fall time, SDA 300 20 + 0.1Cb†300 ns
27 tf(SCL) Fall time, SCL 300 20 + 0.1Cb†300 ns
28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 4 0.6 µs
29 CpCapacitance for each I2C pin 10 10 pF
†Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
25
23 19
18 22 27
20
21
17
18
28
Stop Start Repeated
Start Stop
SDA
SCL
16
26 24
Figure 54. I2C Transmit Timings
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HOST-PORT INTERFACE TIMING
timing requirements for host-port interface cycles†‡ (see Figure 55, Figure 56, Figure 57, and
Figure 58)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tsu(SELV-HSTBL) Setup time, select signals§ valid before HSTROBE low 5 ns
2 th(HSTBL-SELV) Hold time, select signals§ valid after HSTROBE low 4 ns
3
tw(HSTBL)
Pulse duration, HSTROBE low (host read access) 4P
ns
3 tw(HSTBL) Pulse duration, HSTROBE low (host write access) 4P ns
4 tw(HSTBH) Pulse duration, HSTROBE high between consecutive accesses 4P ns
10 tsu(SELV-HASL) Setup time, select signals§ valid before HAS low 5 ns
11 th(HASL-SELV) Hold time, select signals§ valid after HAS low 3 ns
12 tsu(HDV-HSTBH) Setup time, host data valid before HSTROBE high 5 ns
13 th(HSTBH-HDV) Hold time, host data valid after HSTROBE high 3 ns
14 th(HRDYL-HSTBL) Hold time, HSTROBE low after HRDY low. HSTROBE should not be inactivated
until HRDY is active (low); otherwise, HPI writes will not complete properly. 2 ns
18 tsu(HASL-HSTBL) Setup time, HAS low before HSTROBE low 2 ns
19 th(HSTBL-HASL) Hold time, HAS low after HSTROBE low 2 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
§Select signals include: HCNTL[1:0], HR/W, and HHWIL.
switching characteristics over recommended operating conditions during host-port interface
cycles†‡ (see Figure 55, Figure 56, Figure 57, and Figure 58)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
5 td(HCS-HRDY) Delay time, HCS to HRDY¶1 12 ns
6 td(HSTBL-HRDYH) Delay time, HSTROBE low to HRDY high#3 12 ns
7 td(HSTBL-HDLZ) Delay time, HSTROBE low to HD low impedance for an HPI read 2 ns
8 td(HDV-HRDYL) Delay time, HD valid to HRDY low 2P − 4 ns
9 toh(HSTBH-HDV) Output hold time, HD valid after HSTROBE high 3 12 ns
15 td(HSTBH-HDHZ) Delay time, HSTROBE high to HD high impedance 3 12 ns
16 td(HSTBL-HDV) Delay time, HSTROBE low to HD valid 3 12.5 ns
17 td(HSTBH-HRDYH) Delay time, HSTROBE high to HRDY high|| 3 12 ns
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
¶HCS enables HRDY, and HRDY is always low when HCS is high. The case where HRDY goes high when HCS falls indicates that HPI is busy
completing a previous HPID write or READ with autoincrement.
#This parameter is used during an HPID read. At the beginning of the first half-word transfer on the falling edge of HSTROBE, the HPI sends the
request to the EDMA internal address generation hardware, and HRDY remains high until the EDMA internal address generation hardware loads
the requested data into HPID.
|| This parameter is used after the second half-word of an HPID write or autoincrement read. HRDY remains low if the access is not an HPID write
or autoincrement read. Reading or writing to HPIC or HPIA does not affect the HRDY signal.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
130 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING (CONTINUED)
1st halfword 2nd halfword
5
17
86
5
17
85
15
916
15
97
4
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
3
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 55. HPI Read Timing (HAS Not Used, Tied High)
HAS†
HCNTL[1:0]
HR/W
HHWIL
HSTROBE‡
HCS
HD[15:0] (output)
HRDY (case 1)
HRDY (case 2)
1st half-word 2nd half-word
5178
51785
15
916
15
97
4
3
11
10
11
10
11
10
11
10
11
1011
10 19 19
18
18
†For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 56. HPI Read Timing (HAS Used)
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
131
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
HOST-PORT INTERFACE TIMING (CONTINUED)
1st halfword 2nd halfword 5
17
5
13
12
13
12
4
14
3
2
1
2
1
2
1
2
1
2
1
2
1
HAS
HCNTL[1:0]
HR/W
HHWIL
HSTROBE†
HCS
HD[15:0] (input)
HRDY
3
†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 57. HPI Write Timing (HAS Not Used, Tied High)
1st half-word 2nd half-word 5
17
5
13
12
13
12
4
14
3
11
10
11
10
11
10
11
10
11
10
11
10
HAS†
HCNTL[1:0]
HR/W
HHWIL
HSTROBE‡
HCS
HD[15:0] (input)
HRDY
19
19
18 18
†For correct operation, strobe the HAS signal only once per HSTROBE active cycle.
‡HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.
Figure 58. HPI Write Timing (HAS Used)
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
132 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING
timing requirements for McBSP†‡ (see Figure 59)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
2 tc(CKRX) Cycle time, CLKR/X CLKR/X ext 2P§ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext 0.5 * t c(CKRX) −1¶ns
5
tsu(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int 9
ns
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low CLKR ext 1ns
6
th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int 6
ns
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low CLKR ext 3ns
7
tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int 8
ns
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low CLKR ext 0ns
8
th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int 3
ns
8 th(CKRL-DRV) Hold time, DR valid after CLKR low CLKR ext 4ns
10
tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int 9
ns
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low CLKX ext 1ns
11
th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int 6
ns
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low CLKX ext 3ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
§The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for
communications between the McBSP and other devices is 75 Mbps for 167-MHz and 225-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock;
where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The
maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle
time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 15 ns as the minimum
CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =
33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port
is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM
= 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
¶This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the resonable range of 40/60 duty cycle.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
133
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 59)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 td(CKSH-CKRXH) Delay time, CLKS high to CLKR/X high for internal CLKR/X generated from
CLKS input 1.8 10 ns
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P§¶ ns
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C − 1#C + 1#ns
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid CLKR int −2 3 ns
9
td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int −2 3
ns
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid CLKX ext 2 9 ns
12
tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
CLKX int −1 4
ns
12 tdis(CKXH-DXHZ)
Disable time, DX high impedance following last data bit
from CLKX high CLKX ext 1.5 10 ns
13
td(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX int −3.2 + D1|| 4 + D2||
ns
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 0.5 + D1|| 10+ D2|| ns
14
td(FXH-DXV)
Delay time, FSX high to DX valid FSX int −1 7.5
ns
14 td(FXH-DXV) ONLY applies when in data delay 0 (XDATDLY = 00b)
mode FSX ext 2 11.5 ns
†CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also inverted.
‡Minimum delay times also represent minimum output hold times.
§P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
¶The minimum CLKR/X period is twice the CPU cycle time (2P) and not faster than 75 Mbps (13.3 ns). This means that the maximum bit rate for
communications between the McBSP and other devices is 75 Mbps for 167-MHz and 225-MHz CPU clocks or 50 Mbps for 100-MHz CPU clock;
where the McBSP is either the master or the slave. Care must be taken to ensure that the AC timings specified in this data sheet are met. The
maximum bit rate for McBSP-to-McBSP communications is 67 Mbps; therefore, the minimum CLKR/X clock cycle is either twice the CPU cycle
time (2P), or 15 ns (67 MHz), whichever value is larger. For example, when running parts at 150 MHz (P = 6.7 ns), use 15 ns as the minimum
CLKR/X clock cycle (by setting the appropriate CLKGDV ratio or external clock source). When running parts at 60 MHz (P = 16.67 ns), use 2P =
33 ns (30 MHz) as the minimum CLKR/X clock cycle. The maximum bit rate for McBSP-to-McBSP communications applies when the serial port
is a master of the clock and frame syncs (with CLKR connected to CLKX, FSR connected to FSX, CLKXM = FSXM = 1, and CLKRM = FSRM
= 0) in data delay 1 or 2 mode (R/XDATDLY = 01b or 10b) and the other device the McBSP communicates to is a slave.
#C = H or L
S = sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see ¶ footnote above).
|| Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.
If DXENA = 0, then D1 = D2 = 0
If DXENA = 1, then D1 = 2P, D2 = 4P
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
134 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit(n-1) (n-2) (n-3)
Bit 0 Bit(n-1) (n-2) (n-3)
14
1312
11
10
9
3
32
8
7
6
5
4
4
3
1
32
CLKS
CLKR
FSR (int)
FSR (ext)
DR
CLKX
FSX (int)
FSX (ext)
FSX (XDATDLY=00b)
DX
13
13
Figure 59. McBSP Timings
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
135
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for FSR when GSYNC = 1 (see Figure 60)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tsu(FRH-CKSH) Setup time, FSR high before CLKS high 4 ns
2 th(CKSH-FRH) Hold time, FSR high after CLKS high 4 ns
2
1
CLKS
FSR external
CLKR/X (no need to resync)
CLKR/X (needs resync)
Figure 60. FSR Timing When GSYNC = 1
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0 †‡ (see Figure 61)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 12 2 − 6P ns
5 th(CKXL-DRV) Hold time, DR valid after CLKX low 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
136 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 61)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶T − 2 T + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#L − 2 L + 3 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −3 4 6P + 2 10P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low L − 2 L + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high 2P + 3 6P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
87
6
21
CLKX
FSX
DX
DR
Figure 61. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
137
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 62)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 62)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXL-FXL) Hold time, FSX low after CLKX low¶L − 2 L + 3 ns
2 td(FXL-CKXH) Delay time, FSX low to CLKX high#T − 2 T + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −3 4 6P + 2 10P + 17 ns
6 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from
CLKX low −2 4 6P + 3 10P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid H − 2 H + 6.5 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
138 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
4
376
21
CLKX
FSX
DX
DR 5
Figure 62. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1 †‡ (see Figure 63)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
139
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 63)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶T − 2 T + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#H − 2 H + 3 ns
3 td(CKXL-DXV) Delay time, CLKX low to DX valid −3 4 6P + 2 10P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high H − 2 H + 3 ns
7 tdis(FXH-DXHZ) Disable time, DX high impedance following last data bit from
FSX high 2P + 3 6P + 17 ns
8 td(FXL-DXV) Delay time, FSX low to DX valid 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
38
7
6
21
CLKX
FSX
DX
DR
Figure 63. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
140 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 64)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
4 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 12 2 − 6P ns
5 th(CKXH-DRV) Hold time, DR valid after CLKX high 45 + 12P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
switching characteristics over recommended operating conditions for McBSP as SPI master or
slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 64)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
NO.
PARAMETER
MASTER§SLAVE
UNIT
MIN MAX MIN MAX
1 th(CKXH-FXL) Hold time, FSX low after CLKX high¶H − 2 H + 3 ns
2 td(FXL-CKXL) Delay time, FSX low to CLKX low#T − 2 T + 3 ns
3 td(CKXH-DXV) Delay time, CLKX high to DX valid −3 4 6P + 2 10P + 17 ns
6 tdis(CKXH-DXHZ) Disable time, DX high impedance following last data bit from
CLKX high −2 4 6P + 3 10P + 17 ns
7 td(FXL-DXV) Delay time, FSX low to DX valid L − 2 L + 6.5 4P + 2 8P + 17 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
§S = Sample rate generator input clock = 2P if CLKSM = 1 (P = 1/CPU clock frequency)
= Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
= (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
¶FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX
and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
#FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock
(CLKX).
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
141
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MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
5
4
3
7
6
21
CLKX
FSX
DX
DR
Figure 64. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
142 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TIMER TIMING
timing requirements for timer inputs† (see Figure 65)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tw(TINPH) Pulse duration, TINP high 2P ns
2 tw(TINPL) Pulse duration, TINP low 2P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
switching characteristics over recommended operating conditions for timer outputs†
(see Figure 65)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
3 tw(TOUTH) Pulse duration, TOUT high 4P − 3 ns
4 tw(TOUTL) Pulse duration, TOUT low 4P − 3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
TINPx
TOUTx
4
3
2
1
Figure 65. Timer Timing
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING
timing requirements for GPIO inputs†‡ (see Figure 66)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tw(GPIH) Pulse duration, GPIx high 4P ns
2 tw(GPIL) Pulse duration, GPIx low 4P ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
‡The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the DSP recognize the GPIx
changes through software polling of the GPIO register, the GPIx duration must be extended to at least 24P to allow the DSP enough time to access
the GPIO register through the CFGBUS.
switching characteristics over recommended operating conditions for GPIO outputs†§
(see Figure 66)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA -167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
3 tw(GPOH) Pulse duration, GPOx high 12P − 3 ns
4 tw(GPOL) Pulse duration, GPOx low 12P − 3 ns
†P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.3 ns.
§The number of CFGBUS cycles between two back-to-back CFGBUS writes to the GPIO register is 12 SYSCLK1 cycles; therefore, the minimum
GPOx pulse width is 12P.
GPIx
GPOx
4
3
2
1
Figure 66. GPIO Port Timing
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
144 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
JTAG TEST-PORT TIMING
timing requirements for JTAG test port (see Figure 67)
NO.
PYP-200,-225
GDP/ZDP -225, -300
PYPA
-167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
1 tc(TCK) Cycle time, TCK 35 ns
3 tsu(TDIV-TCKH) Setup time, TDI/TMS/TRST valid before TCK high 10 ns
4 th(TCKH-TDIV) Hold time, TDI/TMS/TRST valid after TCK high 7 ns
switching characteristics over recommended operating conditions for JTAG test port
(see Figure 67)
NO. PARAMETER
PYP-200,-225
GDP/ZDP -225, -300
PYPA
-167, -200
GDPA/ZDPA −200 UNIT
MIN MAX
2 td(TCKL-TDOV) Delay time, TCK low to TDO valid 0 15 ns
TCK
TDO
TDI/TMS/TRST
1
2
34
2
Figure 67. JTAG Test-Port Timing
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
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MECHANICAL DATA
The following tables show the thermal resistance characteristics for the GDP and ZDP mechanical packages.
thermal resistance characteristics (S-PBGA package) for GDP
NO °C/W Air Flow (m/s)†
Two Signals, Two Planes (4-Layer Board)
1 RΘJC Junction-to-case 9.7 N/A
2 PsiJT Junction-to-package top 1.5 0.0
3 RΘJB Junction-to-board 19 N/A
4 RΘJA Junction-to-free air 22 0.0
5 RΘJA Junction-to-free air 21 0.5
6 RΘJA Junction-to-free air 20 1.0
7 RΘJA Junction-to-free air 19 2.0
8 RΘJA Junction-to-free air 18 4.0
9 PsiJB Junction-to-board 16 0.0
†m/s = meters per second
thermal resistance characteristics (S-PBGA package) for ZDP
NO °C/W Air Flow (m/s)†
Two Signals, Two Planes (4-Layer Board)
1 RΘJC Junction-to-case 9.7 N/A
2 PsiJT Junction-to-package top 1.5 0.0
3 RΘJB Junction-to-board 19 N/A
4 RΘJA Junction-to-free air 22 0.0
5 RΘJA Junction-to-free air 21 0.5
6 RΘJA Junction-to-free air 20 1.0
7 RΘJA Junction-to-free air 19 2.0
8 RΘJA Junction-to-free air 18 4.0
9 PsiJB Junction-to-board 16 0.0
†m/s = meters per second
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
146 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
The following table shows the thermal resistance characteristics for the PYP mechanical package.
thermal resistance characteristics (S-PQFP-G208 package) for PYP
NO °C/W
Junction-to-Pad
Two Signals, Two Planes (4-Layer Board) − 208-pin PYP
1 RΘJP Junction-to-pad, 26 x 26 copper pad on top and bottom of PCB with solder connection and vias going to
GND plane, isolated from power plane. 0.2
Junction-to-Package Top
Two Signals, Two Planes (4-Layer Board) − 208-pin PYP
2 PsiJT Junction-to-package top, 26 x 26 copper pad on top and bottom of PCB with solder connection and vias
going to GND plane, isolated from power plane. 0.18
3 PsiJT Junction-to-package top, 7.5 x 7.5 copper pad on top and bottom of PCB with solder connection and
vias going to GND plane, isolated from power plane. 0.23
Two Signals (2-Layer Board)
4 PsiJT Junction-to-package top, 26 x 26 copper pad on top of PCB with solder connection and vias going to
copper plane on bottom of board. 0.18
5 PsiJT Junction-to-package top, 7.5 x 7.5 copper pad on top of PCB with solder connection and vias going to
copper plane on bottom of board. 0.23
Junction-to-Still Air
Two Signals, Two Planes (4-Layer Board) − 208-pin PYP
6 RΘJA Junction-to-still air, 26 x 26 copper pad on top and bottom of PCB with solder connection and vias going
to GND plane, isolated from power plane. 13
7 RΘJA Junction-to-still air, 7.5 x 7.5 copper pad on top and bottom of PCB with solder connection and vias
going to GND plane, isolated from power plane. 20
Two Signals (2-Layer Board)
8 RΘJA Junction-to-still air, 26 x 26 copper pad on top of PCB with solder connection and vias going to copper
plane on bottom of board. 14
9 RΘJA Junction-to-still air, 7.5 x 7.5 copper pad on top of PCB with solder connection and vias going to copper
plane on bottom of board. 20
SPRS294B − O C TOBER 2005 − REVISED JUNE 2006
147
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
packaging information
For proper device thermal performance, the thermal pad must be soldered to an external ground thermal plane.
This pad is electrically and thermally connected to the backside of the die. For the TMS320C6713B 208−Pin
PowerPAD plastic quad flatpack, the external thermal pad dimensions are: 7.2 x 7.2 mm and the thermal pad
is externally flush with the mold compound.
The following packaging information and addendum reflect the most current released data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TMS320C6713BGDP225 ACTIVE BGA GDP 272 40 TBD SNPB Level-3-220C-168 HR
TMS320C6713BGDP300 ACTIVE BGA GDP 272 40 TBD SNPB Level-3-220C-168 HR
TMS320C6713BPYP200 ACTIVE HLQFP PYP 208 36 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TMS320C6713BZDP225 ACTIVE BGA ZDP 272 40 Pb-Free
(RoHS) SNAGCU Level-3-260C-168 HR
TMS320C6713BZDP300 ACTIVE BGA ZDP 272 40 Pb-Free
(RoHS) SNAGCU Level-3-260C-168 HR
TMS32C6713BGDPA200 ACTIVE BGA GDP 272 40 TBD SNPB Level-3-220C-168 HR
TMS32C6713BPYPA167 ACTIVE HLQFP PYP 208 36 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TMS32C6713BPYPA200 ACTIVE HLQFP PYP 208 36 Green (RoHS &
no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TMS32C6713BZDPA200 ACTIVE BGA ZDP 272 40 Pb-Free
(RoHS) SNAGCU Level-3-260C-168 HR
TMX320C6713BGDP OBSOLETE BGA GDP 272 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-May-2009
Addendum-Page 1
MECHANICAL DATA
MPBG276 – MAY 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ZDP (S–PBGA–N272) PLASTIC BALL GRID ARRAY
2468 201816141210
M
E
A
1
C
B
D
G
F
H
K
J
L
W
R
N
P
U
T
V
Y
357911 171513 19
0,635
0,635
26,80SQ
23,80
24,20SQ
27,20 24,13 TYP
0,57
0,65 0,60
0,90
Seating Plane
0,50
0,70
2,57 MAX
0,15
0,10
A1 Corner
1,27
1,27
4204398/A 04/02
Bottom View
1,12
1,22
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-151
D. This package is lead-free.
MECHANICAL DATA
MPBG274 – MAY 2002
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GDP (S–PBGA–N272) PLASTIC BALL GRID ARRAY
2468 201816141210
M
E
A
1
C
B
D
G
F
H
K
J
L
W
R
N
P
U
T
V
Y
357911 171513 19
0,635
0,635
26,80SQ
23,80
24,20SQ
27,20 24,13 TYP
0,57
0,65 0,60
0,90
Seating Plane
0,50
0,70
2,57 MAX
0,15
0,10
A1 Corner
1,27
1,27
4204396/A 04/02
Bottom View
1,12
1,22
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-151
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