1. FEATURES
• A single chip solution integrates 100/10 Base-T fast
Ethernet MAC, PHY and PMD
• Fully comply to IEEE 802.3u specification
• Operates over 100 meters of STP and category 5
UTP cable
• Fully comply to PCI spec. 2.1 up to 33MHz
• Fully comply to Advanced Configuration and Power
Interface (ACPI) Rev 1.0
• Fully comply to PCI Bus Power Management Inter-
face spec. Rev 1.0
• Support full and half duplex operations in both 100
Base-TX and 10 Base-T mode
• Magic PacketTM mode to support Remote-Wake-Up
and Remote-Power-On
• 100/10 Base-T NWAY auto negotiation function
• Large on-chip FIFOs for both transmit and receive
operations without external local memory
• Bus master architecture with linked host buffers deliv-
ers the most optimized performance
• 32-bit bus master DMA channel provides ultra low
CPU utilization, best fit in server and windows appli-
cation.
• Proprietary Adaptive Network Throughput Control
(ANTC) technology to optimize data integrity and
throughput
• Support up to 64K bytes boot ROM interface
• Three levels of loopback diagnositic capability
• Support a variety of flexible address filtering modes
with 16 CAM address and 512 bits hash
• MicroWire interface to EEPROM for customer's IDs
and configuration data
• Single +5V power supply, CMOS technology, 128-pin
PQFP package/LQPF package
( Magic P ack et Technology is a trademark of Advanced
Micro De vice Corp. )
2. GENERAL DESCRIPTIONS
The MX98715A controller is an IEEE802.3u compliant
single chip 32-bit full duplex, 10/100Mbps highly inte-
grated Fast Ethernet combo solution, designed to ad-
dress high performance local area networking (LAN)
system application requirements.
MX98715A's PCI bus master architecture delivers the
optimized performance for future high speed and pow-
erful processor technologies. In other words, the
MX98715A not only keeps CPU utilization low while
maximizing data throughput, but it also optimizes the
PCI bandwidth providing the highest PCI bandwidth uti-
lization. To further reduce maintenance costs the
MX98715A uses drivers that are bac kward compatible
with the original MXIC MX98713 series controllers.
The MX98715A contains a PCI local bus glueless inter-
face, a Direct Memor y Access (DMA) buffer manage-
ment unit, an IEEE802.3u-compliant Media Access Con-
troller (MAC), large Transmit and Receive FIFOs, and
an on-chip 10 Base-T and 100 Base-TX transceiver sim-
plifying system design and improving high speed signal
quality. Full-duple x oper ation are supported in both 10
Base-T and 100 Base-TX modes that increases the
controller's operating bandwidth up to 200Mbps.
Equipped with intelligent IEEE802.3u-compliant auto-
negotiation, the MX98715A-based adapter allows a
single RJ-45 connector to link with the other IEEE802.3u-
compliant de vice without re-configuration.
In MX98715A, an innovative and proprietary design
"Adaptive Network Throughput Control" (ANTC) is built-
in to configure itself automatically by MXIC's driver based
on the PCI burst throughput of different PCs. With this
proprietary design, MX98715A can alwa ys optimiz e its
operating bandwidth, network data integrity and through-
put f or diff erent PCs .
The MX98715A features Remote-Power-On and Re-
mote-W ake-Up capability and is compliant with the Ad-
vanced Configuration and Power Interface version 1.0
(A CPI). This support enab les a wide range of wak e-up
capabilities, including the ability to customize the con-
tent of specified pack et which PC should be responded
to , e ven when it is in a lo w-power state. PCs and work-
stations could take advantage of these capabilities of
being waked up and served simultaneously over the net-
work by remote server or workstation. It helps organi-
zations reduce their maintenance cost of PC network.
The 32-bit multiplex ed bus interface unit of MX98715A
provides a direct interf ace to a PCI local bus , simplifing
the design of an Ethernet adapter in a PC system. With
its on-chip support for both little and big endian byte
alignment, MX98715A can also address non-PC appli-
cations.
1
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
SINGLE CHIP FAST ETHERNET NIC CONTROLLER
PRELIMINARY
INDEX
2
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
3. PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
BPA4
BPA3
BPA2
BPA1(EEDI)
BPA0(EECK)
EECS
BPD0(EED0)
BPD1
BPD2
BPD3
BPD4
BPD5
BPD6
BPD7
GND
VDD
AD0
AD1
GND
AD2
AD3
VDD
AD4
AD5
GND
AD6
VDD
GND
GND
VDD
GND
VCC
GND
PMEB
INTAB
RSTB
PCICLK
GNTB
REQB
AD31
AD30
GND
AD29
AD28
VDD
AD27
GND
AD26
AD25
GND
AD24
CBEB3
IDSEL
GND
AD23
AD22
GND
AD21
AD20
VDD
AD19
AD18
GND
AD17
AD16
CBEB2
FRAMEB
GND
IRDYB
TRDYB
DEVSELSB
STOPB
VDD
PERRB
SERRB
PAR
CBEB1
AD15
GND
AD14
AD13
VDD
AD12
AD11
AD10
GND
AD9
AD8
CBEB0
AD7
RTX
RTX2EQ
CPK
GND
TXOP
TXON
VDD
GND
GND
VDD
RXIP
RXIN
VDD
GND
VDD
GND
GND
CKREF
VDD
RDA
GND
VDD
LED1
LED0
BPA15
BPA14
BPA13
GND
VDD
BPA12
BPA11
BPA10
BPA9
BOEB
BPA8
BPA7
BPA6
BPA5
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
MX98715A
INDEX
3
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
4. PIN DESCRIPTION ( 128 PIN PQFP )
( T/S : tri-state, S/T/S : sustended tri-state, I : input, O : output, O/D : open drain )
Pin Name Type Pin No 128 Pin Function and Driver
AD[31:0] T/S 116, 117 PCI address/data bus: shared PCI address/data bus lines. Little or big endian
119,120, byte ordering are supported.
122,124,
125,127,
3,4,6,7,9,
10,12,13,
26,28,29,
31-33,35,
36,38,39,
41,42,44,
45,47,48
CBE[3:0] T/S 128,14 PCI command and byte enab le bus: shared PCI command b yte enable b us,
25,37 during the address phase of the transaction, these four bits pro vide the b us
command. During the data phase, these f our bits provide the b yte enable .
FRAMEB S/T/S 15 PCI FRAMEB signal: shared PCI cycle start signal, asserted to indicate the
beginning of a bus tr ansaction. As long as FRAMEB is asserted, data
transf ers continue.
TRDYB S/T/S 18 PCI Target ready: issued b y the target agent, a data phase is completed on
the rising edge of PCICLK when both IRDYB and TRDYB are asserted.
IRDYB S/T/S 17 PCI Master ready: indicates the bus master's ability to complete the current
data phase of the transaction. A data phase is completed on any rising edge
of PCICLK when both IRDYB and TRDYB are asserted.
DEVSELB S/T/S 19 PCI slav e device select: asserted b y the target of the current b us access .
When 98715A is the initiator of current bus access , the target m ust assert
DEVSELB within 5 bus cycles , otherwise cycle is aborted.
IDSEL I 1 PCI initialization device select: target specific device select signal f or
configuration cycles issued by host.
PCICLK I 113 PCI bus cloc k input: PCI b us clock range from 16MHz to 33MHz.
RSTB I 112 PCI b us reset: host system hardw are reset.
LANW AKE O 110 Power Management Event:When high indicating a power management e vent
occures, such as detection of a Magic packet, a wake up frame, or link change.
INTAB O/D 111 PCI bus interrupt request signal: wired to INTAB line.
SERRB O/D 23 PCI bus system error signal: If an address parity error is detected and CFCS
bit 8 is enabled, SERRB and CFCS's bit 30 will be asserted.
PERRB S/T/S 22 PCI b us data error signal: As a bus master, when a data parity error is
detected and CFCS bit 8 is enabled, CFCS bit 24 and CSR5 bit 13 will be
asserted. As a bus target, a data parity error will cause PERRB to be
asserted.
INDEX
4
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
Pin Name Type Pin No 128 Pin Function and Driver
PAR T/S 24 PCI bus parity bit: shared PCI bus even parity bit for 32 bits AD bus and CBE
bus.
STOPB S/T/S 20 PCI T arget requested transfer stop signal: as bus master, assertion of STOPB
cause MX98715A either to retry, disconnect, or abort.
REQB T/S 1 15 PCI bus request signal: to initiate a bus master cycle request
GNTB I 114 PCI bus grant ac kno wledge signal: host asserts to inf orm MX98715A that
access to the bus is gr anted
BPA1 O 6 1 Boot PROM address bit 1(EECS=0): together with BPA[15:0] to access
(EEDI) e xternal boot PROM up to 256KB .
EEPROM data in(EECS=1): EEPROM serial data input pin.
BPA0 O 6 0 Boot PROM address bit 0(EECS=0): together with BPA[15:0] to access
(EECK) e xternal boot PROM up to 256KB.
EEPROM cloc k(EECS=1): EEPROM cloc k input pin
BPA[15:0] O 78-76,
73-70, Boot PROM address line .
68-60
BPD0 T/S 58 Boot PROM data line 0(EECS=0): boot PROM or flash data line 0.
(EEDO) EEPROM data out(EECS=1): EEPROM serial data outpin(during reset
initialization).
BPD[7:0] T/S 51-58 Boot PROM data lines: boot PR OM or flash data lines 7-0.
EECS O 59 EEPROM Chip Select pin.
BOEB O 6 9 Boot PROM Output Enable .
RD A O 8 3 Connecting an external resistor to ground, Resistor value=510 ohms
R TX O 1 02 Connecting an external resistor to ground, Resistor value=510 ohms
R TX2EQ O 101 No connection.
NC I 100 No Connection.
RXIP I 92 Twisted pair receiv e diff erential input: Support both 10 Base-T and 100
Base-TX receive diff erential input.
RXIN I 91 Twisted pair receiv e diff erential input: Support both 10 Base-T and 100
Base-TX receive diff erential input
TXOP O 98 Twisted pair transmit diff erential output: Support both 10 Base-T and 100
Base-TX transmit diff erential output
TXON O 97 Twisted pair transmit differential output: Support both 10 Base-T and 100
Base-TX transmit diff erential output
CKREF I 85 Ref erence cloc k: 25MHz oscillator cloc k input
LED0 O 79 Programmab le LED pin 0:
CSR9.28=1 Set the LED as Link Speed (10/100) LED.
CSR9.28=0 Set the LED as Activity LED.
Def ault is activity LED after reset.
INDEX
5
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
Pin Name Type Pin No 128 Pin Function and Driver
LED1 O 80 Programmab le LED pin 1:
CSR9.29=1 Set the LED as Link/Activity LED.
CSR9.29=0 Set the LED as Good Link LED.
Def ault is Good Link LED after reset.
VDD I 8,21,30,43, P o wer pins.
49,74,81,84,
88,90,93,96,
103,106,108,
121
GND I 2,5,11,16,27 Ground pins.
34,40,46,50
75,82,86,87
89,94,95,99
104,105,107
109,118,123,
126
INDEX
6
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5. PROGRAMMONG INTERFACE
5.1 PCI CONFIGURATION REGISTERS:
5.1.1 PCI ID REGISTER ( PFID ) ( Offset 03h-00h )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Device ID (bit 31:16)
Vendor ID (bit 15:0)
5.1.2 PCI COMMAND AND STATUS REGISTER ( PFCS ) ( Offset 07h-04h )
The bit content will be reset to 0 when a 1 is written to the corresponding bit location.
bit 0 : IO Space Access, set to 1 enable IO access
bit 1 : Memory Space Access, set to 1 to enable memory access
bit 2 : Master Operation, set to 1 to support b us master mode
bit 5-3 : not used
bit 6 : P arity Error Response, set to 1 to enab le assertion of CSR<13> bit if parity error detected.
bit 7 : not used
bit 8 : System Error Enab le, set to 1 to enab le SERR# when parity error is detected on address lines and CBE[3:0].
bit 20 : New capability. Set to support PCI power management.
bit 22-bit19 : not used
bit 23 : Fast Back-to back, alwa ys set to accept fast back-to-bac k tr ansactions that are not sent to the same b us
device.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Detect Party Error
Signal System Error
Data Parity Report
New Capability
Receive Master Abort
Receive Target Abort
Deceive Select Timing
Fast Back-to-back
System Error Enable
Parity Error Response
Master Operation
Memory Space Access
IO Space Access
This register can be loaded from exter nal serial EEPROM or use a MXIC preset value of "10D9" and "0531" for
vendor ID and device ID respectively. Word location 3Eh and 3Dh in serial EEPROM are used to configure customer's
vendor ID and device ID respectively. If location 3Eh contains"FFFF" value then MXIC'svendor ID and de vice ID will
be set in this register, otherwise both 3Eh and 3Dh will be loaded into this register from serial EEPROM.
INDEX
7
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.1.3 PCI REVISION REGISTER ( PFRV ) ( Offset 0Bh-08h )
bit 3 - 0 : Step Number, range from 0 to Fh.
bit 7 - 4 : Re vision Number, fix ed to 2h for MX98715A
bit 15 - 8 : not used
bit 23 - 16 : Subclass , fixed to 0h.
bit 31 - 24 : Base Class, fixed to 2h.
5.1.4 PCI LATENCY TIMER REGISTER ( PFLT ) (Offset 0Fh-0Ch)
bit 0 - bit 7 : System cache line size in units of 32 bit word, device driver should use this value to program CSR0<15:14>.
bit 8 - bit 15 : Configuration Latency Timer, when MX98715A assert FRAME#, it enab les its latency timer to count.
If MX98715A deasserts FRAME# prior to timer expiration, then timer is ignored. Otherwise, after timer expires,
MX98715A initiates transaction termination as soon as its GNT# is deasserted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Base Class
Step Number
Subclass
Revision Number
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Latency Timer
System cache line size
PFLT Register (0Fh-0Ch)
bit 24:Data parity Report, is set to 1 only if PERR# active and PFCS<6> is also set.
bit 26-25:De vice Select Timing of DEVSELB pin.
bit 27:not used
bit 28:Receive Target Abort, is set to indicate a transaction is terminated b y a target abort.
bit 29:Receive Master Abort, is set to indicate a master transaction with Master abort.
bit 30:Signal System Error, is set to indicate assertion of SERR#.
bit 31:Detected P arity Error, is set whene v er a parity error detected regardless of PFCS<6>.
INDEX
8
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.1.5 PCI B ASE IO ADDRESS REGISTER ( PBIO ) ( Offset 13h-10h )
bit 0 : IO/Memory Space Indicator, fix ed to 1 in this field will map into the IO space . This is a read only field.
bit 7 - 1 : not used, all 0 when read
bit 31 - 8 : Defines the address assignment mapping of MX98715A CSR registers.
5.1.6 PCI Base Memory Address Register ( PBMA ) ( Offset 17h-14h )
bit 0 : Memory Space Indicator, fix ed to 0 in this field will map into the memory space . This is a read only field.
bit 6 - 1 : not used, all 0 when read
bit 31 - 7 : Defines the address assignment mapping of MX98715A CSR registers.
5.1.7 PCI SUBSYSTEM ID REGISTER ( PSID ) ( Offset 2Ch-2Fh )
This register is used to uniquely identify the add-on board or subsystem where the NIC controller resides. V alues in
this register are loaded directly from e xternal serial EEPROM after system reset automatically. W ord location 36h of
EEPROM is subsystem vendor ID and location 35h is sub-system ID.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Base Memory Address
Memory Spec Indicator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Subsystem ID (31:16)
Subsystem Vendor ID (bit 15:0)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Configuration Base IO Address
IO/Memory Spec Indicator
INDEX
9
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.1.8 PCI B ASE EXPANSION ROM ADDRESS REGISTER ( PBER ) ( Offset 33h-30h )
bit 0 : Address Decode Enable, decoding will be enabled if only both enable bit in PFCS<1> and this expansion ROM
register are 1.
bit 10 - 1 : not use
bit 31 - 11 : Defines the upper 21 bits of expansion ROM base address.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Expansion ROM Base Address (upper 21 bit)
Address Decode Enable
0 0 0 0 0 0 0
5.1.10 INTERRUPT REGISTER ( PFIT ) ( Offset 3Fh-3Ch )
bit 7 - 0 : Interrupt Line, system BIOS will writes the routing information into this field, driver can use this information
to determine priority and interrupt vector .
bit 15 - 8 : Interrupt Pin, fixed to 01h which use INTA#.
bit 31 - 24 : Max_Lat which is a maximum period for a access to PCI bus.
bit 23 - 16 : Min_Gnt which is the maximum period that MX98715A needs to finish a brust PCI cycle.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Min-Gnt
Interrupt Pin
Max_Lat
0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0
Interrupt Line
5.1.9 PCI CAPABILITY POINTER REGISTER ( PFCP ) ( Offset 37h-34h )
bit 7- 0 : Capability pointer (Cap_Ptr) is set to 44h if PMEB is connected to PCI b us, otherwise 00.
bit 31- 8 : reserved
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Capability Pointer (Set to 44h)
INDEX
10
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.1.11 PCI DRIVER AREA REGISTER ( PFDA ) ( 43h-40h )
bit 31 : Sleep Mode, set to sleep mode which allo ws access to PCI configuration space, a hardware reset or reset to
this bit can exit from sleep mode. Magic packet can be received under sleep mode if CSR<22> (Magic Packet
Enable) is set.
bit 30 : not used
bit 29 : board type
bit 15 - 8 : driver is free to read and write this field for any purpose.
bit 7 - 0 : not used.
5.1.12 PCI POWER MANAGEMENT CAPABILITY REGISTER ( PPMC ) ( 47h-44h )
bit 31- 27 : PME_Support, read only indicates the pow er states in which the function may assert LANW AKE pin.
bit 31 ---- PME_D3cold (value=1)
bit 30 ---- PME_D3warm (value=1)
bit 29 ---- PME_D2 (v alue=1)
bit 28 ---- PME_D1 (v alue=1)
bit 27 ---- PME_D0 (v alue=1)
bit 26 : D2 mode support, read only, set to 1.
bit 25 : D1 mode support, read only, set to 1.
bit 24-22 : AUX_I bits. Auxiliary current field, set to 100.
bit 21 : DSI, read only, set to 0.
bit 20 : A uxiliary power source, set to 1. This bit only v alid when bit 15 is a '1'.
bit 19 : PME Clock, read only, set to 0.
bit 18-16 : PCI power management version, set to 001, read only.
bit 15-8 : Ne xt Pointer , all bits set to 0.
bit 7-0 : Capability ID, read only, a 1 indicates that the data structure currently being pointed to is the PCI po w er
managment data structure.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
D2_Support
D1_Support
PME_Support
0 0 0 0 0 0 0 0
AUX_I
DSI
Auxiliary Power Source
PME Clock
Version
Next Pointer
Capability ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Board Type
Sleep Type
Driver Special Use
INDEX
11
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.1.13 PCI POWER MANAGEMENT COMMAND AND STATUS REGISTER ( PPMCSR ) ( 4Bh-48h )
bit 1-0 : P o w er_State , read/write, D0 mode is 00, D1 mode is 01, D2 mode is 10, D3 hot mode is 11.
bit7-2 : all 0. Reserv ed.
bit8 : PME_EN, set 1 to enab le LANWAKE. Set 0 to disab le LANWAKE assertion.
bit 12-9 : Data_Select f or report in the Data register located at bit 31:24.
bit 14-13 : Data_Scale , read only.
bit 15 : PME_Status independent of the state of PME_EN.
When set, indicates a assertion of LANWAKE pin. (support D3 cold).
Write 1 to clear the LANW AKE signal. Write 0, no eff ect.
bit 21-16 : Reserv ed.
bit 22 : B2_B3#, B2_B3 support for D3 hot, meaningful only if BPCC_EN = 1, read only.
bit 23 : BPCC_EN, Bus Power/Cloc k Control Enab le , read only.
bit 31-24 : Data, read only.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bridge Extension Support
PME_Status
Data
Data_Scale
Data_Select
PME_EN
Reserved
Power State
0 0 0 0 0 0
INDEX
12
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.2 HOST INTERFACE REGISTERS
MX98715A CSRs are located in the host I/O or memory address space. The CSRs are doub le word aligned and 32
bits long. Definitions and address for all CSRs are as f ollo ws :
CSR Mapping
Register Meaning Offset from CSR Base
Address ( PBIO and PBMA )
CSR0 Bus mode 00
CSR1 Transmit poll demand 08h
CSR2 Receive poll demand 10h
CSR3 Receive list demand 18h
CSR4 Transmit list base address 20h
CSR5 Interrupt status 28h
CSR6 Operation mode 30h
CSR7 Interrupt enable 38h
CSR8 Missed frame counter 40h
CSR9 Serial ROM and MII management 48h
CSR10 Reserved 50h
CSR11 General Purpose timer 58h
CSR12 10 Base-T status port 60h
CSR13 SIA Reset Register 68h
CSR14 10 Base-T control port 70h
CSR15 Watchdog timer 78h
CSR16 Magic Pac ket Register 8 0h
CSR20 NWa y Status Register A0h
INDEX
13
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5. 2.1 BUS MODE REGISTER ( CSR0 )
Field Name Description
0 SWR Software Reset, when set, MX98715A resets all internal hardware with the e xception of
the configuration area and port selection.
1 BAR0 Internal bus arbitration scheme betw een receive and tr ansmit processes.
The receiv e channel usually has higher priority ov er transmit channel when receive FIFO
is partially full to a threshold. This threshold can be selected b y programming this bit. Set
f or low er threshold, reset for normal threshold.
6:2 DSL Descriptor Skip Length, specifies the number of longw ords to skip between two descrip-
tors.
7 BLE Big/Little Endian, set f or big endian b yte ordering mode, reset f or little endian byte order-
ing mode, this option only applies to data b uff ers
13:8 PBL Programmable Burst Length, specifies the maximum number of longwords to be trans-
f erred in one DMA transaction. default is 0 which means unlimited b urst length, possib le
v alues can be 1,2,4,8,16,32 and unlimited .
15:14 CAL Cache Alignment, programmab le address boundaries of data burst stop, MX98715A can
handle non-cache- aligned fragement as well as cache-aligned fr agment efficiently.
18:17 TAP Transmit Auto-Polling time inter val, defines the time inter val for MX98715A to performs
transmit poll command automatically at transmit suspended state .
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAP-Transmit Automatic Polling
0
ZERO-Must be zero
DSL-Descriptor Skip Length
SWR-Software Reset
CAL-Cache Alignment
PBL-Programmable Burst Length
BLE-Big/Little Endian
BAR-Bus Arbitration
TABLE 5.2.0 TRANSMIT AUTO POLLING BITS
CSR<18:17> Time Interv al
00 No transmit auto-polling, a write to CSR1 is required to poll
01 auto-poll e v ery 200 us
10 auto-poll e v ery 800 us
11 auto-poll e very 1.6 ms
INDEX
14
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.2.2 TRANSMIT POLL COMMAND ( CSR1 )
Field Name Description
31:0 TPC Write only, when written with an y v alue , MX98715A read transmit descriptor list in host
memory pointed by CSR4 and processes the list.
5.2.3 RECEIVE POLL COMMAND ( CSR2 )
Field Name Description
31:0 RPC Write only, when written with an y v alue, MX98715A read receive descriptor list in host
memory pointed by CSR4 and processes the list.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Transmit Poll command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Receive Poll command
5.2.4 DESCRIPT OR LIST ADDRESS ( CSR3, CSR4 )
CSR3 Receive List Base Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start of Receive List Address
CSR4 Traansmit List Base Address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start of Transmit List Address
INDEX
15
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.2.5 STATUS REGISTER ( CSR5 )
Field Name Description
28 WKUPI W ak e Up e v ent interrupt. Valid only if CSR16<22> bit is set.
27 LC 100 Base-TX link status has changed either from pass to fail or f ail to pass .
Read CSR12<1> f or 100 Base-TX link status.
25:23 EB Error Bits, read only, indicating the type of error that casued fatal b us error.
22:20 TS Transmit Process State, read only bits indicating the state of transmit process .
19:17 RS Receive Process State, read only bits indicating the state of receive process .
16 NIS Normal Interrupt Summary, is the logical OR of CSR5<0>, CSR5<2> and CSR5<6> and
CSR5<28>.
15 AIS Abnormal Interrupt Summary, is the logical OR of CSR5<1>, CSR5<3>, CSR5<5>,
CSR5<7>, CSR5<8>, CSR5<9>, CAR5<10>, CSR5<11> and CSR5<13>, CSR5<27>.
14 ERI Early receive interrupt, indicating the first b uffer has been filled in ring mode , or 64 bytes
has been received in chain mode .
13 FBE F atal Bus Error , indicating a system error occured, MX98715A will disable all bus access .
12 LF Link Fail, indicates a link fail state in 10 Base-T port. This bit is valid only when CSR6<18>=0,
CSR14<8>=1, and CSR13<3>=0.
11 GTE Gener al Purpose Timer Expired, indicating CSR11 counter has e xpired.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RS-Receive Process State
NIS-Normal Interrupt Summary
LF-Link Fail
ETI-Early Transmit Interrupt
AIS-Abnormal Interrupt Summary
ERI-Early Receive Interrupt
FBE-Fatal Bus Error
GTE-General Purpose Timer Expired
WKUPI-Wake Up event Interrupt
LC-Link Change
RPS-Receive Process Stopped
RI-Receive Interrupt
EB-Error Bits
TS-Transmit Process State
RWT-Receive Watchdog Timeout
RU-Receive Buffer Unavailable
LPANCI-Link Pass/Autonegotiation
Completed Interrupt
UNF-Transmit Underflow
TJT-Transmit Jabber Timeout
TU-Transmit Buffer Unavailable
TPS-Transmit Process Stopped
TI-Transmit Interrupt
INDEX
16
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
Field Name Description
10 ETI Early Transmit Interrupt, indicating the packet to be transmitted was fully transferred to
internal TX FIFO. CSR5<0> will automatically clears this bit.
9 RWT Receive Watchdog Timeout, reflects the network line status where receive watchdog timer
has e xpired while the other node is still activ e on the network.
8 RPS Write only, when written with any value, MX98715A reads receive descriptor list in host
memory pointed by CSR4 and processes the list.
7 R U Receive Buff er Unav ailable, the receiv e process is suspended due to the ne xt descriptor
in the receive list is owned by host. If no receive poll command is issued, the reception
process resumes when the ne xt recogniz ed incoming fr ame is received.
6 RI Receive Interrupt, indicating the completion of a frame reception.
5 UNF Transmit Underflow, indicating transmit FIFO has run empty before the completion of a
pack et transmission.
4 LPANCI When autonegotiation is not enabled ( CSR14<7>=0 ), this bit indicates that the 10 Base-
T link integrity test has completed successfully, after the link was down. This bit is also set
as as a result of writing 0 to CSR14<12> ( Link Test Enable ).
When Autonegotiation is enabled ( CSR14<7> =1 ) , this bit indicates that the autonegotiation
has completed ( CSR12<14:12>=5 ). CSR12 should then be read for a link status report.
This bit is only v alid when CSR6<18>=0, i.e. 10 Base-T port is selected Link F ail interrupt
( CSR5<12> ) will automatically clears this bit.
3 TJT Transmit Jabber Timeout, indicating the MX98715 has been excessiv ely active. The trans-
mit process is aborted and placed in the stopped state. TDES0<1> is also set.
2 TU Transmit Buffer Una v ailab le , transmit process is suspended due to the next descriptor in
the transmit list is o wned b y host.
1 TPS Transmit Process Stopped.
0 TI Transmit Interrupt. indicating a frame transmission w as completed.
INDEX
17
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
TABLE 5.2.1 FATAL BUS ERROR BITS
CSR5<25:23> Process State
000 parity error for either SERR# or PERR#, cleared by softw are reset.
00 1 master abort
010 target abort
011 reserved
1XX reserved
TABLE 5.2.2 TRANSMIT PROCESS STATE
CSR5<22:20> Process State
000 Stopped- reset or transmit jabber e xpired.
001 Fetching tr ansmit descriptor
010 W aiting f or end of transmission
011 filling transmit FIFO
100 reserved
101 Setup pack et
110 Suspended, either FIFO underflow or una vailab le tr ansmit descriptor
111 closing transmit descriptor
TABLE 5.2.3 RECEIVE PROCESS STATE
CSR5<19:17> Process State
000 Stopped- reset or stop receive command. Fetching receive descriptor
010 checking f or end of receiv e pac k et
011 W aiting f or receive pac k et
100 Suspended, receive b uff er unav ailable
101 closing receive descriptor
110 Purging the current frame from the receive FIFO due to una vailable receiv e b uffer
111 queuing the receive fr ame from the receiv e FIFO into host receiv e b uffer
INDEX
18
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.2.6 OPERATION MODE REGISTER ( CSR6 )
Field Name Description
24 SCR Scrambler Mode, default is set to enable scrambler function. Not affected by software
reset.
23 PCS Default is set to enable PCS functions. CSR6<18> must be set in order to operate in
symbol mode.
22 TTM Transmit Threshold Mode , set f or 10 Base-T and reset for 100 Base-TX.
21 SF Store and F orw ard, when set, transmission starts only if a full packet is in transmit FIFO.
the threshold values defined in CSR6<15:14> are ignored
19 HBD Heartbeat Disable , set to disable SQE function in 10 Base-T mode.
18 PS Port Select, deafult is 0 which is 10 Base-T mode, set f or 100 Base-TX mode .
A software reset does not affect this bit.
17 COE Collision Offset Enable, set to enable a modified backoff algorithm during low collision
situation, reset f or normal backoff algorithm.
15:14 TR Threshold Control Bits, these bits controls the selected threshold level for MX98715A's
transmit FIFO , transmission starts when frame size within the transmit FIFO is larger than
the selected threshold. Full frames with a length less than the threshold are also transmit-
ted.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
COE-Collision Offset Enable
FC-Force collision mode
LOM-Loopback Operation Mode
TR-Threshold Control Bits
ST-Start/Stop Transmission Command
TTM-Transmit Threshold Mode
SF-Store and Forward
PR-Promiscuous Mode
HBD-Hearbeat Disable
PS-Port Select
FD-Full Duplex Mode
PM-Pass All Multicast
SB-Start/Stop Backoff Counter
IF-Inverse Filtering
PB-Pass Bad Frame
HO-Hash-Only Filtering Mode
SR-Start/Stop Receive
HP-Hash/Perfect Receive Filtering Mode
PCS-PCS function
SCR-Scrambler Mode
INDEX
19
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
Field Name Description
13 ST Start/Stop Transmission Command, set to place transmission process in running state
and will try to transmit current descriptor in transmit list. When reset, tr ansmit process is
placed in stop state.
12 FC Force Collision Mode, used in collision logic test in inter nal loopback mode, set to force
collision during next transmission attempt. This can result in excessive collision reported
in TDES0<8> if 16 or more collision.
11:10 LOM Loopback Operation Mode , see table 5.2.6.
9 FD Full-Duplex Mode, set for simultaneous transmit and receiv e operation, heart beat check
is disabled, TDES0<7> should be ignored, and internal loopback is not allowed. This bit
controls the v alue of bit 6 of link code w ord .
7 PM P ass All Multicast, set to accept all incoming frames with a m ulticast destination address
are received. Incoming frames with physical address are filtered according to the CSR6<0>
bit.
6 PR Promiscuous Mode, any incoming valid frames are accepted, default is reset and not
aff ected by softw are reset.
5 SB Start/Stop Backoff Counter, when reset, the backoff timer is not affected by the network
carrier activity. Otherwise, timer will start counting when carrier drops .
4 IF Inverse Filtering, read only bit, set to operate in inverse filtering mode, only valid during
perf ect filtering mode.
3 PB Pass Bad Frames , set to pass bad frame mode , all incoming frames passed the address
filtering are accepted including runt frames, collided fragments, truncated frames caused
b y FIFO ov erflo w.
2 HO Hash-Only Filtering Mode , read only bit, set to operate in imperfect filtering mode for both
ph ysical and multicast addresses .
1 SR Start/Stop Receiv e, set to place receive process in running state where descriptor acqui-
sition is attempted from current position in the receive list. Reset to place the receive
process in stop state.
0 HP Hash/P erfect Receive Filtering Mode, read only bit, set to use hash table to filter multicast
incoming frames. If CSR6<2> is also set, then the physical addresses are imperfect ad-
dress filtered too. If CSR6<2> is reset, then physical addresses are perfect address fil-
tered, according to a single physical address as specified in setup frame.
INDEX
20
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
TABLE 5.2.4 TRANSMIT THRESHOLD
CSR6<21> CSR6<15:14> CSR6<22>=0 CSR6<22>=1 (Threshold bytes)
(for 100 Base-TX) (for 10 Base-T)
0 00 128 72
0 01 256 96
0 10 512 128
0 11 1024 160
1 XX ( Store and Forw ard )
TABLE 5.2.5 D ATA PORT SELECTION
CSR14<7> CSR6<18> CSR6<22> CSR6<23> CSR6<24> Port
1 0 X X 1 Nway Auto-negotiation
0 0 1 X 0 10 Base-T
0 1 0 1 X 100 Base-TX
TABLE 5.2.6 LOOPBACK OPERATION MODE
CSR6<11:10> Operation Mode
00 Normal
01 Internal loopback at FIFO port
11 Internal loopback at the PHY level
10 External loopback at the PMD le v el
TABLE 5.2.7 FILTERING MODE
CSR6<7> CSR6<6> CSR6<4> CSR6<2> CSR6<0> Filtering Mode
0 0 0 0 0 16 perfect filtering
0 0 0 0 1 512-bit hash + 1 perfect filtering
0 0 0 1 1 512-bit hash for multicast and
ph ysical addresses
0 0 1 0 0 Inverse filtering
X 1 0 0 X Promiscuous
0 1 0 1 1 Promiscuous
1 0 0 0 X P ass All Multicast
1 0 0 1 1 P ass All Multicast
INDEX
21
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.2.7 INTERRUPT MASK REGISTER ( CSR7 )
Field Name Description
28 WKUPIE W ak e Up Event Interrupt Enable , enables CSR5<28>.
27 LCE Link Changed Enable , enables CSR5<27>.
16 NIE Normal Interrupt Summary Enable, set to enab le CSR5<0>, CSR5<2>, CSR5<6>.
15 AIE Abnormal Interrupt Summary enab le, set to enbale CSR5<1>, CSR5<3>, CSR5<5>,
CSR5<7>, CSR5<8>, CSR5<9>, CSR5<11> and CSR5<13>.
14 ERIE Early Receive Interrupt Enable
13 FBE Fatal Bus Error Enab le , set together with with CSR7<15> enables CSR5<13>.
12 LFE Link F ail Interrupt Enable , enables CSR5<12>
11 GPTE General Purpose Timer Enable , set together with CSr7<15> enab les CSR5<11>.
10 ETIE Early Transmit Interrupt Enable , enables CSR5<10>
9 RWE Receiv e W atchdog Timeout Enab le, set together with CSR7<15> enab les CSR5<9>.
8 RSE Receive Stopped Enable , set together with CSR7<15> enables CSR5<8>.
7 R UE Receive Buff er Una v ailable Enab le, set together with CSR7<15> enables CSR5<7>.
6 RIE Receive Interrupt Enable, set together with CSR7<16> enab les CSR5<6>.
5 UNE Underflo w Interrupt Enable , set together with CSR7<15> enables CSR5<5>.
4 LPANCIE Link P ass/A utonegotiation Completed Interrupt Enab le
3 TJE Transmit Jabber Timeout Enab le, set together with CSR7<15> enab les CSR5<3>.
2 TUE Transmit Buffer Unav ailab le Enable , set together with CSR7<16> enab les CSR5<2>.
1 TSE Transmit Stop Enable , set together with CSR7<15> enables CSR5<1>.
0 TIE Transmit Interrupt Enab le, set together with CSR7<16> enab les CSR5<0>.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NIE-Normal interrupt Summary Enable
FBE-Fatal Bus Error Enable
LFE-Link Fail Enable
AIE-Abnormal Interrupt Summary Enable
ERIE-Early Receive Interrupt Enable
ETIE-Early Transmit Interrupt Enable
RIE-Receive Interrupt Enable
RWE-Receiv e W atchdog Enable
RSE-Receive Stopped Enable
GPTE-General-Purpose Timer Enable
RUE-Receive Buffer Unavailable Enable
UNE-Underflow Interrupt Enable
LPANCIE-Link Pass
/Nway Complete Interrupt Enable
TJE-Transmit Jabber Timeout Enable
TUE-Transmit Buffer Unavailable Enable
TSE-Transmit Stopped Enable
TIE-Transmit Interrupt Enable
LCE-Link Changed Enable
WKUPIE-Wake Up event interrupt Enable
INDEX
22
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.2.8 MISSED FRAME COUNTER ( CSR8 )
Field Name Description
16 MFO Missed Frame Ov erflow, set when missed frame counter ov erflo ws , reset when CSR8
is read.
15:0 MFC Missed Frame Counter, indicates the number of fr ames discarded because no host
receive descriptors w ere av ailab le.
5.2.9 NON-VOLATILE MEMOR Y CONTROL REGISTER ( CSR9 )
Field Name Description
29 LED1SEL 0:Def ault value . Set LED1 as Good Link LED.
1: Set LED1 as Link/Activity LED.
28 LED0SEL 0:Def ault value . Set LED0 as Activity LED.
1: Set LED0 as Link Speed (10/100) LED.
14 RD Boot ROM read oper ation when boot ROM is selected.
12 BR Boot ROM Select, set select serial ROM only if CSR9<11>=0.
11 SR Serial ROM Select, set to select serial R OM for either read or write operation.
7:0 Data If boot ROM is selected (CSR9<12> is set), this field contains the data to be read from
and written to the boot ROM. If ser ial ROM is selected, CSR9<3:0> are defined as fol-
lows:
Warning : CSR9<11> and CSR9<12> should be mutually exclusive f or correct operations.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Missed Frame Overflow
Missed Frame Counter
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR-Boot ROM Select
Data-Boot ROM data
or Serial ROM control
LED1SEL
LED0SEL
WKFCAT
RD-Read Operation
SR-Serial ROM Select
INDEX
23
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.2.10 GENERAL PURPOSE TIMER ( CSR11 )
Field Name Description
16 CON When set,the general purpose timer is in continuous operating mode. When reset, the
timer is in one-shot mode.
15:0 Timer Value contains the timer value in a cycle time of 204.8us.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CON-Continuous Mode
Timer V alue
5.2.11 10 B ASE-T STATUS Port ( CSR12 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LPC-Link Partner's Link Code Word
LPN-Link Partner Negotiable
ANS-Autonegotiation Arbitration State
TRF-Transmit Remote Fault
APS-Autopolarity State
LS10B-Link Status of 10 Base-T
LS100B-Link Status of 100 Base-TX
*Software reset has no effect on this register
Field Name Decription
31:16 LPC Link P artner's Link Code Word, where bit 16 is S0 ( selector field bit 0 ) and bit31 is NP
( Next Page ). Effective only when CSR12<15> is read as a logical 1.
15 LPN Link P artner Negotiable , set when link partner support NWAY algorithm and CSR14<7>
is set.
14:12 ANS A utonegotiation Arbitration State , arbitration states are defined
000 = A utonegotiation disable
001 = Transmit disable
010 = ability detect
011 = Ackno wledge detect
100 = Complete ackno wledge detect
101 = FLP link good; autonegotiation complete
110 = Link check
When autonegotiation is completed, an ANC interrupt ( CSR5<4>) is generated, write
001 into this field can restart the autonegotiation sequence if CSR14<7> is set.
Otherwise, these bits should be 0.
INDEX
24
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
Field Name Decription
11 TRF Transmit Remote F ault
3 APS Autopolarity State, set when polarity is positiv e. When reset, the 10Base-T polarity is
negative . The received bit stream is in v erted by the receiv er .
2 LS10B Set when link status of 10 Base-T port link test fail. Reset when 10 Base-T link test is in
pass state.
1 LS100B Link state of 100 Base-TX, this bit reflects the state of SD pin, eff ectiv e only when
CSR6<23>= 1 ( PCS is set ). Set to indicate a fail condition .i.e. SD=0.
5.2.12 SIA Reset Register (CSR13)
Field Name Decription
0 Nwa y Reset While writing 0 to this bit, resets the CSR12 & CSR14.
1 100Base-TX Reset Write a 1 will reset the internal 100 Base-TX PHY module
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
100 TX Reset-
100 Base-TX PHY level reset
Nway Reset-
Nway and 10 Base-T PHY level reset
5.2.13 10 Base-T Control PORT (CSR14)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T4-100 Base-T4 (link code word)
TXF-100 Base-TX full duplex
(link code word)
TXH-100 Base-TX half duplex
(link code word)
LTE-Link Test Enable
RSO-Receive Squelch Enable
ANE-Autonegotiation Enable
HDE-Half Duplex Enable)
PWD10B-Power down 10 Base-T
LBK-Loopback (MCC)
INDEX
25
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.2.14 W ATCHDOG TIMER ( CSR15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBZ-Must Be Zero
RWR-Receiv e W atchdog Release
PWD-Receive W atchdog Disable
JCK-Jabber Clock
HUJ-Host Unjabber
JAB-Jabber Disable
Field Name Description
5 RW R Defines the time interval no carrier from receive watchdog e xpir ation until reenabling the
receive channel. When set, the receiv e w atchdog is release 40-48 bit times from the last
carrier deassertion. When reset, the receiv e watchdog is released 16 to 24 bit times from
the last carrier deassertion.
4 RW D When set, the receiv e w atchdog counter is disable . When reset, receiv e carriers longer
than 2560 bytes are guaranted to cause the watchdog counter to time out. Packets shorter
than 2048 bytes are guaranted to pass .
2 JCK When set, transmission is cut off after a range of 2048 b ytes to 2560 bytes is transmitted,
When reset, transmission f or the 10 Base-T port is cut off after a range of 26 ms to 33ms .
When reset, transmission for the 100 Base-TX port is cut off after a range of 2.6ms to
3.3ms.
1 HUJ Defines the time interv al between transmit jab ber e xpiration until reenabling of the
transmit channel. When set, the transmit channel is released immediately after the jabber
expiration.
When reset, the jabber is released 365ms to 420 ms after jab ber expiration f or 10 Base-T
port. When reset, the jab ber is released 36.5ms to 42ms after the jabber e xpor ation f or
100 Base-TX port.
0 JBD Ja bber Disab le, set to disab le tr ansmit jabber function.
Field Name Decription
18 T4 Bit 9 of link code word for T4 mode.
17 TXF Bit 8 of link code word for 100 Base-TX full duplex mode.
16 TXH Bit 7 of link code word for 100 Base-TX half duplex mode. Meaningful only when CSR14<7>
( ANE ) is set.
12 LTE Link Test Enable , when set the 10 Base-T port link test function is enabled.
8 RSQ Receive Squelch Enab le f or 10 Base-T port. Set to enable .
7 ANE Autonegotiation Enable, .
6 HDE Half-Duplex Enable, this is the bit 5 of link code word, only meaningful when CSR14<7> is
set.
2 PWD10B Reset to power do wn 10 Base-T module, this will force both TX and RX port into tri-state
and pre v ent AC current path. Set for normal 10 Base T operation.
1 LBK Loop back enable f or 10 Base-T MCC.
INDEX
26
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.2.15 Magic P ac ket Register (CSR16)
Field Name Description
bit 31:23 reserved
bit 15:0 reserve d
bit 22 MPE Magic Pac k et Enable , set to enab le Magic Pack et Mode
Sleep mode and MPE mode can be used seperately. When Sleep and MPE are both set, the Sleep mode dominate
MPE, i.e. no magic packet can be detected since both TX and RX channel are shut off in sleep mode. On the
detection of magic packet, the MPI interrupt bit at CSR5<28> can be set to generate a PCI interrupt if CSR7<28>
MPIE is set.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPE (Magic Packet Enable)
5.2.16 Nway Status Register (CSR20)
Field Name Description
31 T4 T4 mode is accepted, read only
30 100TXF 100Base-TX full duple x is accepted, read only
29 100TXH 100Base-TX half duplex is accepted, read only
28 10TXF 10Base-T duplex is accepted, read only
27 10TXH 10Base-T half duplex is accepted, read only
16 PCITEST Default is 0 after Po wer-on reset. Reserv ed f or PCI b us test purpose, must be set
1 by softw are f or normal operation.
12 EQTEST Default is 0 after Power-on reset. Reserved for tranceiver equalization test pur-
pose, m ust be set 1 by software f or normal operation.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCITEST
EQTEST
100T4
100TXF
100TXH
10TXF
10TXH
INDEX
27
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
5.3 P o wer Management Functions :
MX98715A complies to ACPI Version 1.0, supports
D3cold state to generate PMEB . There are basically 3
power saving modes supported, namely Remote Power-
On, Remote Wake-Up, and Sleep mode. By default,
MX98715A will enable A CPI function with the f ollowing
registers setup :
PFCS<20> (Ne w Capability)=1
PFCP<7:0> (Capability P ointer)=44h
PPMC<7:0> (Capability ID)=1h
Please ref er to PCI configuration registers for more de-
tails.
5.3.1 Remote Power -On Mode :
When AC power cord of PC is plugged into the wall
outlet, MX98715A will load the network ID from
EEPROM and enter itself into Remote P ower-On mode
automatically. The host and PCI bus has no power at
this stage. As soon as a Magic packet addressed to
this network adaptor, PMEB will be asserted low to
pow er on the PC .
To set up the Remote P ower-On (PRO) mode, as long
as a 5.0V standby VDD is connected into the adaptor's
isolated VDD and MX98715A will set up itself to detect
Magic packet. No registers needed to be programmed.
Simply turn off the power switch or plug in the AC power
cord of the PC that support RPO and ev erything else is
set automatically.
5.3.2 Remote W ake-Up Mode :
When the PC is still turned on regardless of the status
of CPU and system's ststus, a Magic packet can be
detected if enabled. As soon as a Magic packet ad-
dressed to the network adaptor is detected, both INTA#
and PMEB can be asser ted low if registers set up as
f ollows :
CSR16<22> (PME)=1 and
PPMCSR<8> (PME_EN)=1
to enable PMEB assertion.
CSR16<22> (PME)=1 and
CSR7<28> (MPIE)=1 to enable INTA#
assertion
5.3.3 Sleep Mode :
Set PFDA<31> (Sleep)=1 will enter the chip into a sleep
mode where no TX nor RX activities can be processed.
Only PCI configuration can be accessed.
INDEX
28
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
6. AC/DC CHARACTERISTICS
6.1 BOOT ROM READ TIMING
TRC
BPA 15-0
TOES
TCE
BCEB
BOEB
(CE&OE is typical shorted)
TOH
BPD 7:0
TACC
TOOLZ
TCOLZ
TOH
INDEX
29
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
6.2 A C CHARACTERISTICS
SYMBOL DESCRIPTION MINIMUM TYPICAL MAXIMUM UNITS
TRC Read Cycle 8 - - PCI Cycle
TCE Chip Enab le Access Time - - 7 PCI Cycle
TA CC Address Access Time - - 7 PCI Cycle
T OES Output Enable Access Time - - 7 PCI Cycl
T OH Output Hold from Address, CEB , or OEB 0 - - ns
PCI cycle range:66ns (16MHz)~25ns (40MHz)
6.3 ABSOLUTE OPERATION CONDITION
Supply Voltage (VCC) -0.5V to +7.0V
DC Input Voltage (Vin) 4.75V to 5.25V
DC Output Voltage (Vout) -0.5V to VCC + 0.5V
Storage Temperature Range (Tstg) -55°C to +150°C
Operating T emperature Range 0°C to 70°C
P o wer Dissipation (PD) 750mW (Typ.)
Lead Temp. (TL) (Soldering, 10 sec) 26 0°C
ESD Rating (Rzap = 1.5k, Czap = 100pF) 1.0kV
Clamp Diode Current 20mA
6.4 DC CHARA CTERISTICS
Symbol Parameter Conditions Min Max Units
TTL/PCI Input/Output
Voh Minimum High Le vel Output Voltage Ioh = -3mA 2.4 V
Vol Maxim um Low Le v el Output Voltage Iol = +6mA 0.4 V
Vih Minim um High Le v el Input Voltage 2.0 V
Vil Maximum Lo w Lev el Input Voltage 0.8 V
Iin Input Current Vi = VCC or GND - 1.0 + 1.0 uA
Ioz Minimum TRI-STATE Output Leakage Current Vout = VCC or GND -10 +10 uA
LED output Dr iver
Vlol LED turn on Output Voltage Iol = 16mA 0.4 V
Supply
Idd A ver age Supply Current CKREF =25MHz 130 170 mA
PCICLK = 33MHz
Vdd A verage Supply Voltage 4.75V 5.25V V
INDEX
30
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
7.0 PACKAGE INFORMATION
128-Pin Plastic Quad Flat P ac k
A
eL
A1
L1
E3 aE
38
1
64
65
102
103
128 39
IH
D3
D
ZD
b
c
d
ZE
ITEM MILLIMETERS INCHES
a 14.00±.05 5.512±.002
b .20 [T yp .] .08 [Typ.]
c 20.00±.05 7.87±.002
d 1.346 .530
e .50 [T yp .] .20 [Typ.]
L1 1.60±.1 .63±.04
L .80±.1 .31±.04
ZE .75 [T yp .] .30 [T yp .]
E3 12.50 [Typ.] 4.92 [Typ.]
E 17.20±.2 6.77±.08
ZD .75 [T yp .] .30 [T yp .]
D3 18.50 [T y p.] 7.28 [Typ.]
D 23.20±.2 9.13±.08
A1 .25±.1 min. .01 ±.04 min.
A 3.40±.1 max. 1.34±.04 max.
Note Short Lead Short Lead
NOTE: Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material condi-
tion.
INDEX
31
P/N:PM0537 REV. 1.2, FEB. 24, 1999
MX98715A
REVISION HIST OR Y
Revision Destription Page Date
1.1 (1) re vise PFRV register bit 31-24 to be 2h P7 SEP/15/1998
(2) exchange description for PFIT register bit 7-0 and bit 15-8 P9
(3) revise ESD r ating in Section 6.3 from 1.5KV to 1.0KV P29
(4) add Power Dissipation in Section 6.3 to be 750mW (typ) P29
(5) add ldd value in Section 6.4 to be 130mA to 170mA P29
1.2 Change NW AY Status Register P26 FEB/24/1999
INDEX
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888
FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-747-2309
FAX:+65-748-4090
TAIPEI OFFICE:
TEL:+886-3-509-3300
FAX:+886-3-509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
32
MX98715A
INDEX
