DATA SH EET
Product specification
Supersedes data of 1998 Feb 23 2003 Jul 10
INTEGRATED CIRCUITS
74HC74; 74HCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
2003 Jul 10 2
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
FEATURES
Wide supply voltage range from 2.0 to 6.0 V
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
GENERAL DESCRIPTION
The 74HC/HCT74 is a high-speed Si-gate CMOS device
and is pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The74HC/HCT74aredualpositive-edgetriggered,D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (SD) and reset (RD) inputs; also complementary
Q and Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f=6ns
Notes
1. CPD is used to determine the dynamic power dissipation (PDin µW).
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. For 74HC74 the condition is VI= GND to VCC.
For 74HCT74 the condition is VI= GND to VCC 1.5 V.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
HC HCT
tPHL/tPLH propagation delay CL= 15 pF; VCC =5V
nCP to nQ, nQ1415ns
n
SD to nQ, nQ1518ns
n
RD to nQ, nQ1618ns
f
max maximum clock frequency 76 59 MHz
CIinput capacitance 3.5 3.5 pF
CPD power dissipation capacitance per flip-flop notes 1 and 2 24 29 pF
2003 Jul 10 3
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
FUNCTION TABLES
Table 1 See note 1
Table 2 See note 1
Note
1. H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
= LOW-to-HIGH CP transition;
Qn+1 = state after the next LOW-to-HIGH CP transition.
ORDERING INFORMATION
INPUT OUTPUT
SD RD CP D Q Q
LHXXHL
HLXXLH
LLXXHH
INPUT OUTPUT
SD RD CP D Qn+1 Qn+1
HHLLH
HHHHL
TYPE NUMBER PACKAGE
TEMPERATURE
RANGE PINS PACKAGE MATERIAL CODE
74HC74N 40 to +125 °C 14 DIP14 plastic SOT27-1
74HCT74N 40 to +125 °C 14 DIP14 plastic SOT27-1
74HC74D 40 to +125 °C 14 SO14 plastic SOT108-1
74HCT74D 40 to +125 °C 14 SO14 plastic SOT108-1
74HC74DB 40 to +125 °C 14 SSOP14 plastic SOT337-1
74HCT74DB 40 to +125 °C 14 SSOP14 plastic SOT337-1
74HC74PW 40 to +125 °C 14 TSSOP14 plastic SOT402-1
74HCT74PW 40 to +125 °C 14 TSSOP14 plastic SOT402-1
74HC74BQ 40 to +125 °C 14 DHVQFN14 plastic SOT762-1
74HCT74BQ 40 to +125 °C 14 DHVQFN14 plastic SOT762-1
2003 Jul 10 4
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
PINNING
PIN SYMBOL DESCRIPTION
11
RD asynchronous reset-direct input (active LOW)
2 1D data input
3 1CP clock input (LOW-to-HIGH, edge-triggered)
41
SD asynchronous set-direct input (active LOW)
5 1Q true flip-flop output
61
Q complement flip-flop output
7 GND ground (0 V)
82
Q complement flip-flop output
9 2Q true flip-flop output
10 2SD asynchronous set-direct input (active LOW)
11 2CP clock input (LOW-to-HIGH, edge-triggered)
12 2D data input
13 2RD asynchronous reset-direct input (active LOW)
14 VCC positive supply voltage
handbook, halfpage
MNA417
74
1
2
3
4
5
6
78
14
13
12
11
10
9
1RD
1D
1CP
1SD
1Q
1Q
GND 2Q
2Q
2SD
2CP
2D
2RD
VCC
Fig.1 Pin configuration DIP14, SO14 and
(T)SSOP14.
handbook, halfpage
114
GND(1)
1RD VCC
7
2
3
4
5
6
1D
1CP
1SD
1Q
1Q
13
12
11
10
9
2RD
2D
2CP
2SD
2Q
8
GND
Top view 2Q
MNB038
Fig.2 Pin configuration DHVQFN14.
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
2003 Jul 10 5
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
MNA418
handbook, halfpage
RD
FF
SD
410
Q1Q
2Q
1Q
2Q
5
9
2
12
3
11 6
8
Q
1SD
CP
2CP
1CP
2D
1D D
2SD
113
1RD 2RD
Fig.3 Logic symbol.
handbook, halfpage
MNA419
6
3
2C1
4S
1D
1R
5
8
11
12 C1
10 S
1D
13 R
9
Fig.4 IEC logic symbol.
handbook, halfpage
RD
FF
SD
4
Q1Q
1Q
5
2
3
6
Q
1SD
CP
1CP
1D D
11RD
MNA420
RD
FF
SD
10
Q2Q
2Q
9
12
11
8
Q
2SD
CP
2CP
2D D
13 2RD
Fig.5 Functional diagram.
2003 Jul 10 6
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
handbook, full pagewidth
MNA421
SD
CP
RD
D
C
C
Q
C
C
C
C
C
C
Q
C
C
Fig.6 Logic diagram (one flip-flop).
2003 Jul 10 7
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO14 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP14 and TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K.
For DIP14 packages: above 70 °C derate linearly with 12 mW/K.
SYMBOL PARAMETER CONDITIONS 74HC74 74HCT74 UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 VCC 0VCC V
VOoutput voltage 0 VCC 0VCC V
Tamb operating ambient
temperature 40 +25 +125 40 +25 +125 °C
tr,t
finput rise and fall
times VCC = 2.0 V −−1000 −−500 ns
VCC = 4.5 V 6.0 500 6.0 500 ns
VCC = 6.0 V −−400 −−500 ns
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage 0.5 +7.0 V
IIK input diode current VI<0.5 V or VI>V
CC + 0.5 V;
note 1 −±20 mA
IOK output diode current VO<0.5 V or VO>V
CC + 0.5 V;
note 1 −±20 mA
IOoutput source or sink current 0.5V<V
O<V
CC + 0.5 V; note 1 −±25 mA
ICC, IGND VCC or GND current −±100 mA
Tstg storage temperature 65 +150 °C
Ptot power dissipation Tamb =40 to +125 °C; note 2 500 mW
2003 Jul 10 8
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
DC CHARACTERISTICS
Family 74HC
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Note
1. All typical values are measured at Tamb =25°C.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =40 to +85 °C; note 1
VIH HIGH-level input
voltage 2.0 1.5 1.2 V
4.5 3.15 2.4 V
6.0 4.2 3.2 V
VIL LOW-level input voltage 2.0 0.8 0.5 V
4.5 2.1 1.35 V
6.0 2.8 1.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=4.0 mA 4.5 3.84 4.32 V
IO=5.2 mA 6.0 5.34 5.81 V
VOL LOW-level output
voltage VI=V
IH or VIL
IO= 4.0 mA 4.5 0.15 0.33 V
IO= 5.2 mA 6.0 0.16 0.33 V
ILI input leakage current VI=V
CC or GND 6.0 −−±1.0 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 6.0 −−40 µA
Tamb =40 to +125 °C
VIH HIGH-level input
voltage 2.0 1.5 −−V
4.5 3.15 −−V
6.0 4.2 −−V
V
IL LOW-level input voltage 2.0 −−0.5 V
4.5 −−1.35 V
6.0 −−1.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=4.0 mA 4.5 3.7 −−V
I
O
=5.2 mA 6.0 5.2 −−V
V
OL LOW-level output
voltage VI=V
IH or VIL
IO= 4.0 mA 4.5 −−0.4 V
IO= 5.2 mA 6.0 −−0.4 V
ILI input leakage current VI=V
CC or GND 6.0 −−±1.0 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 6.0 −−80 µA
2003 Jul 10 9
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
Family 74HCT
At recommended operating conditions; voltages are referenced to GND (ground=0V).
Note
1. All typical values are measured at Tamb =25°C.
Remark to HCT types
The value of additional quiescent supply current (ICC) for a unit load of 1 is given here. To determine ICC per input,
multiply this value by the unit load coefficient shown in the table.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =40 to +85 °C; note 1
VIH HIGH-level input
voltage 4.5 to 5.5 2.0 1.6 V
VIL LOW-level input voltage 4.5 to 5.5 1.2 0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL;
IO=4.0 mA 4.5 3.84 4.32 V
VOL LOW-level output
voltage VI=V
IH or VIL;
IO= 4.0 mA 4.5 0.33 0.15 V
ILI input leakage current VI=V
CC or GND 5.5 −−±1.0 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 5.5 −−40 µA
ICC additional quiescent
supply current per input VI=V
CC 2.1 V other
inputs at VCC or GND;
IO=0
4.5 to 5.5 100 450 µA
Tamb =40 to +125 °C
VIH HIGH-level input
voltage 4.5 to 5.5 2.0 −−V
V
IL LOW-level input voltage 4.5 to 5.5 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL;
IO=4.0 mA 4.5 3.7 −−V
V
OL LOW-level output
voltage VI=V
IH or VIL;
IO= 4.0 mA 4.5 −−0.4 V
ILI input leakage current VI=V
CC or GND 5.5 −−±1.0 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 5.5 −−80 µA
ICC additional quiescent
supply current per input VI=V
CC 2.1 V other
inputs at VCC or GND;
IO=0
4.5 to 5.5 −−490 µA
INPUT UNIT LOAD COEFFICIENT
nD 0.70
nRD 0.70
nSD 0.80
nCP 0.80
2003 Jul 10 10
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
AC CHARACTERISTICS
Family 74HC
GND = 0 V; tr=t
f= 6 ns; CL=50pF.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =40 to +85 °C
tPHL/tPLH propagation delay
nCP to nQ, nQ see Fig.7 2.0 47 220 ns
4.5 17 44 ns
6.0 14 37 ns
propagation delay
nSD to nQ, nQ see Fig.8 2.0 50 250 ns
4.5 18 50 ns
6.0 14 43 ns
propagation delay
nRD to nQ, nQ see Fig.8 2.0 52 250 ns
4.5 19 50 ns
6.0 15 43 ns
tTHL/tTLH output transition time see Fig.7 2.0 19 95 ns
4.5 719ns
6.0 616ns
t
Wclock pulse width
HIGH or LOW see Fig.7 2.0 100 19 ns
4.5 20 7 ns
6.0 17 6 ns
set or reset pulse width
LOW see Fig.8 2.0 100 19 ns
4.5 20 7 ns
6.0 17 6 ns
trem removal time set or
reset see Fig.8 2.0 40 3 ns
4.5 8 1 ns
6.0 7 1 ns
tsu set-up time nD to nCP see Fig.7 2.0 75 6 ns
4.5 15 2 ns
6.0 13 2 ns
thhold time nCP to nD see Fig.7 2.0 3 6ns
4.5 3 2ns
6.0 3 2ns
fmax maximum clock pulse
frequency see Fig.7 2.0 4.8 23 MHz
4.5 24 69 MHz
6.0 28 82 MHz
2003 Jul 10 11
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
Tamb =40 to +125 °C
tPHL/tPLH propagation delay
nCP to nQ, nQ see Fig.7 2.0 −−265 ns
4.5 −−53 ns
6.0 −−45 ns
propagation delay
nSD to nQ, nQ see Fig.8 2.0 −−300 ns
4.5 −−60 ns
6.0 −−51 ns
propagation delay
nRD to nQ, nQ see Fig.8 2.0 −−300 ns
4.5 −−60 ns
6.0 −−51 ns
tTHL/tTLH output transition time see Fig.7 2.0 −−110 ns
4.5 −−22 ns
6.0 −−19 ns
tWclock pulse width HIGH
or LOW see Fig.7 2.0 120 −−ns
4.5 24 −−ns
6.0 20 −−ns
tWset or reset pulse width
LOW see Fig.8 2.0 120 −−ns
4.5 24 −−ns
6.0 20 −−ns
trem removal time set or
reset see Fig.8 2.0 45 −−ns
4.5 9 −−ns
6.0 8 −−ns
tsu set-up time nD to nCP see Fig.7 2.0 90 −−ns
4.5 18 −−ns
6.0 15 −−ns
thhold time nCP to nD see Fig.7 2.0 3 −−ns
4.5 3 −−ns
6.0 3 −−ns
fmax maximum clock pulse
frequency see Fig.7 2.0 4.0 −−MHz
4.5 20 −−MHz
6.0 24 −−MHz
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
2003 Jul 10 12
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
Family 74HCT
GND = 0 V; tr=t
f= 6 ns; CL=50pF.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =40 to +85 °C
tPHL/tPLH propagation
delay nCP to nQ, nQ see Fig.7 4.5 18 44 ns
propagation
delay nSD to nQ, nQ see Fig.8 4.5 23 50 ns
propagation
delay nRD to nQ, nQ see Fig.8 4.5 24 50 ns
tTHL/tTLH output transition time see Fig.7 4.5 719ns
t
Wclock pulse width HIGH
or LOW see Fig.7 4.5 23 9 ns
set or reset pulse width
LOW see Fig.8 4.5 20 9 ns
trem removal time set or
reset see Fig.8 4.5 8 1 ns
tsu set-up time nD to nCP see Fig.7 4.5 15 5 ns
thhold time nCP to nD see Fig.7 4.5 +3 3ns
fmax maximum clock pulse
frequency see Fig.7 4.5 22 54 MHz
Tamb =40 to +125 °C
tPHL/tPLH propagation
delay nCP to nQ, nQ see Fig.7 4.5 −−53 ns
propagation
delay nSD to nQ, nQ see Fig.8 4.5 −−60 ns
propagation
delay nRD to nQ, nQ see Fig.8 4.5 −−60 ns
tTHL/tTLH output transition time see Fig.7 4.5 −−22 ns
tWclock pulse width HIGH
or LOW see Fig.7 4.5 27 −−ns
set or reset pulse width
LOW see Fig.8 4.5 24 −−ns
trem removal time set or
reset see Fig.8 4.5 9 −−ns
tsu set-up time nD to nCP see Fig.7 4.5 18 −−ns
thhold time nCP to nD see Fig.7 4.5 3 −−ns
fmax maximum clock pulse
frequency see Fig.7 4.5 18 −−MHz
2003 Jul 10 13
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
AC WAVEFORMS
handbook, full pagewidth
MNA422
th
tsu
th
tPHL
tPHL
tW
tPLH
tPLH
tsu
1/fmax
VM
VM
VM
VM
VI
GND
VI
GND
nCP input
nD input
VOH
VOL
nQ output
VOH
VOL
nQ output
Fig.7 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,
the nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
The shaded areas indicate when the input is permitted to change for predictable output performance.
74HC74: VM= 50%; VI= GND to VCC.
74HCT74: VM= 1.3 V; VI= GND to 3 V.
2003 Jul 10 14
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
handbook, full pagewidth
MNA423
trem
tPHL
tPHL
tW
tPLH
tPLH
VM
VM
VM
tW
VM
VM
VI
GND
VI
GND
nSD input
VI
GND
nRD input
nCP input
VOH
VOL
nQ output
VOH
VOL
nQ output
Fig.8 The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths
and the nRD, nRD to nCP removal time.
74HC74: VM= 50%; VI= GND to VCC.
74HCT74: VM= 1.3 V; VI= GND to 3 V.
2003 Jul 10 15
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
handbook, full pagewidth
open
GND
VCC
VCC
VIVO
MNA183
D.U.T.
CL
RT
RL =
1 k
PULSE
GENERATOR
S1
Fig.9 Load circuitry for switching times.
Definitions for test circuit:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
TEST S1
tPZH GND
tPZL VCC
tPHZ GND
tPLZ VCC
2003 Jul 10 16
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
PACKAGE OUTLINES
UNIT A
max. 1 2 (1) (1)
b1cD (1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1 99-12-27
03-02-13
A
min. A
max. bmax.
w
ME
e1
1.73
1.13 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 2.24.2 0.51 3.2
0.068
0.044 0.021
0.015 0.77
0.73
0.014
0.009 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0870.17 0.02 0.13
050G04 MO-001 SC-501-14
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
2003 Jul 10 17
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 8.75
8.55 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT108-1
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
7
8
1
14
y
076E06 MS-012
pin 1 index
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.35
0.34 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.024 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
99-12-27
03-02-19
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
2003 Jul 10 18
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25 0.2
7.9
7.6 1.03
0.63 0.9
0.7 1.4
0.9 8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
A
max.
2
2003 Jul 10 19
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger 74HC74; 74HCT74
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 5.1
4.9 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.72
0.38 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153 99-12-27
03-02-18
wM
bp
D
Z
e
0.25
17
14 8
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
A
max.
1.1
pin 1 index