Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference, I2C Interface AD5625R/AD5645R/AD5665R, AD5625/AD5665 FEATURES FUNCTIONAL BLOCK DIAGRAMS VDD The AD5625R/AD5645R/AD5665R have an on-chip reference. The LFCSP versions of the AD56x5R have a 1.25 V or 2.5 V, 10 ppm/C reference, giving a full-scale output range of 2.5 V or 5 V; the TSSOP versions of the AD56x5R have a 2.5 V, 5 ppm/C reference, giving a full-scale output range of 5 V. The on-chip reference is off at power-up, allowing the use of an external reference. The internal reference is enabled via a software write. The AD5625/AD5665 require an external reference voltage to set the output range of the DAC. The part incorporates a power-on reset circuit that ensures that the DAC output powers up to 0 V (POR = GND) or midscale (POR = VDD) and remains there until a valid write occurs. The on-chip precision output amplifier enables rail-to-rail output swing. 1.25V/2.5V REF INPUT REGISTER DAC REGISTER STRING DAC A INPUT REGISTER DAC REGISTER STRING DAC B INPUT REGISTER DAC REGISTER STRING DAC C INPUT REGISTER DAC REGISTER STRING DAC D VOUTA BUFFER SCL INTERFACE LOGIC ADDR2 VOUTB BUFFER SDA VOUTC BUFFER POWER-ON RESET VOUTD POWER-DOWN LOGIC 06341-001 LDAC CLR POR NOTES 1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE: ADDR2, LDAC, CLR, POR. Figure 1. AD5625R/AD5645R/AD5665R VDD GND VREFIN INPUT REGISTER DAC REGISTER STRING DAC A INPUT REGISTER DAC REGISTER STRING DAC B INPUT REGISTER DAC REGISTER STRING DAC C INPUT REGISTER DAC REGISTER STRING DAC D AD5625/AD5665 BUFFER ADDR1 VOUTA BUFFER SCL VOUTB BUFFER SDA VOUTC BUFFER POWER-ON RESET VOUTD POWER-DOWN LOGIC LDAC CLR POR NOTES 1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE: ADDR2, LDAC, CLR, POR. 06341-002 ADDR2 GENERAL DESCRIPTION The AD5625R/AD5645R/AD5665R and AD5625/AD5665 members of the nanoDAC(R) family are low power, quad, 12-/ 14-/16-bit, buffered voltage-out DACs with/without an on-chip reference. All devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and have an I2C-compatible serial interface. VREFIN/VREFOUT BUFFER ADDR1 APPLICATIONS Process control Data acquisition systems Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Programmable attenuators GND AD5625R/AD5645R/AD5665R INTERFACE LOGIC Low power, smallest pin-compatible, quad nanoDACs AD5625R/AD5645R/AD5665R 12-/14-/16-bit nanoDACs On-chip, 2.5 V, 5 ppm/C reference in TSSOP On-chip, 2.5 V, 10 ppm/C reference in LFCSP On-chip, 1.25 V, 10 ppm/C reference in LFCSP AD5625/AD5665 12-/16-bit nanoDACs External reference only 3 mm x 3 mm 10-lead LFCSP and 14-lead TSSOP 2.7 V to 5.5 V power supply Guaranteed monotonic by design Power-on reset to zero scale/midscale Per channel power-down Hardware LDAC and CLR functions I2C-compatible serial interface supports standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes Figure 2. AD5625/AD5665 The AD56x5R/AD56x5 use a 2-wire I2C-compatible serial interface that operates in standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes. Table 1. Related Devices Part No. AD5025/AD5045/AD5065 AD5624R/AD5644R/AD5664R, AD5624/AD5664 AD5627R/AD5647R/AD5667R, AD5627/AD5667 AD5666 Description Dual 12-/14-/16-bit DACs Quad SPI 12-/14-/16-bit DACs, with/without internal reference Dual I2C 12-/14-/16-bit DACs, with/without internal reference Quad SPI 16-bit DAC with internal reference Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2007-2009 Analog Devices, Inc. All rights reserved. AD5625R/AD5645R/AD5665R, AD5625/AD5665 TABLE OF CONTENTS Features .............................................................................................. 1 External Reference ..................................................................... 23 Applications ....................................................................................... 1 Serial Interface ............................................................................ 23 General Description ......................................................................... 1 Write Operation.......................................................................... 23 Functional Block Diagrams ............................................................. 1 Read Operation........................................................................... 23 Revision History ............................................................................... 2 High Speed Mode ....................................................................... 25 Specifications..................................................................................... 3 Input Shift Register .................................................................... 25 Specifications--AD5665R/AD5645R/AD5625R ..................... 3 Multiple Byte Operation ............................................................ 25 Specifications--AD5665/AD5625 ............................................. 5 Broadcast Mode .......................................................................... 27 AC Characteristics........................................................................ 7 LDAC Function .......................................................................... 27 2 I C Timing Specifications ............................................................ 8 Power-Down Modes .................................................................. 29 Absolute Maximum Ratings.......................................................... 10 Power-On Reset and Software Reset ....................................... 30 ESD Caution ................................................................................ 10 Internal Reference Setup (R Versions) .................................... 30 Pin Configurations and Function Descriptions ......................... 11 Applications Information .............................................................. 31 Typical Performance Characteristics ........................................... 12 Terminology .................................................................................... 20 Using a Reference as a Power Supply for the AD56x5R/AD56x5 ..................................................................... 31 Theory of Operation ...................................................................... 22 Bipolar Operation Using the AD56x5R/AD56x5 .................. 31 Digital-to-Analog Converter (DAC) ....................................... 22 Power Supply Bypassing and Grounding ................................ 31 Resistor String ............................................................................. 22 Outline Dimensions ....................................................................... 32 Output Amplifier ........................................................................ 22 Ordering Guide .......................................................................... 33 Internal Reference ...................................................................... 22 REVISION HISTORY 12/09--Rev. A to Rev. B Changes to Features Section, General Description Section, and Table 1 ......................................................................................... 1 Changes to Table 2 ............................................................................ 3 Changes to Internal Reference Section ........................................ 22 Updated Outline Dimensions ....................................................... 32 Changes to Ordering Guide .......................................................... 33 6/09--Rev. 0 to Rev. A Changes to Features and General Description Sections.............. 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 5 Changes to Digital-to-Analog Converter (DAC) Section, Added Figure 54 and Figure 55, Renumbered Subsequent Figures ..... 22 Changes to Ordering Guide .......................................................... 33 3/07--Revision 0: Initial Version Rev. B | Page 2 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 SPECIFICATIONS SPECIFICATIONS--AD5665R/AD5645R/AD5625R VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE 2 AD5665R Resolution Relative Accuracy Differential Nonlinearity AD5645R Resolution Relative Accuracy Differential Nonlinearity AD5625R Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk (External Reference) Min B Grade Typ Max 8 Unit Test Conditions/Comments 1 16 1 Bits LSB LSB Guaranteed monotonic by design 4 0.5 Bits LSB LSB Guaranteed monotonic by design 14 2 12 12 1 2 1 -0.1 0.1 2 2.5 -100 4 1 10 10 0.5 1.25 0.5 2 1 -0.1 0.1 2 2.5 -100 Bits LSB LSB mV mV % FSR % FSR V/C ppm dB 15 V 10 8 25 10 8 25 V/mA V V 20 10 20 10 V/mA V VDD 2x VREF 0 VDD 2x VREF 2 10 0.5 30 4 DC Output Impedance Short-Circuit Current Power-Up Time 1 0.25 10 10 0.5 1 15 0 0 Capacitive Load Stability REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance REFERENCE OUTPUT (1.25 V) Output Voltage Reference TC3 Output Impedance Min 16 DC Crosstalk (Internal Reference) OUTPUT CHARACTERISTICS 3 Output Voltage Range A Grade Typ Max 210 0.75 2 10 0.5 30 4 260 VDD 210 0.75 26 1.247 1.247 All 1s loaded to DAC register Of FSR/C DAC code = midscale; VDD = 5 V 10% Due to full-scale output change, RL = 2 k to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 k to GND or VDD Due to load current change Due to powering down (per channel) V Internal reference disabled Internal reference enabled nF nF mA s RL = RL = 2 k VDD = 5 V Coming out of power-down mode; VDD = 5 V 260 VDD A V k VREF = VDD = 5.5 V 1.253 V ppm/C k At ambient 26 1.253 10 7.5 Guaranteed monotonic by design All 0s loaded to DAC register 10 7.5 Rev. B | Page 3 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 Parameter REFERENCE OUTPUT (2.5 V) Output Voltage Reference TC3 Output Impedance LOGIC INPUTS (ADDRx, CLR, LDAC, POR)3 IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance VHYST, Input Hysteresis LOGIC INPUTS (SDA, SCL)3 IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance VHYST, Input Hysteresis Min A Grade Typ Max 2.495 2.505 B Grade Typ Max 2.495 10 7.5 5 7.5 1 0.15 x VDD 0.85 x VDD 2 0.1 x VDD 0.7 x VDD 2 0.1 x VDD 0.05 x VDD 1 0.3 x VDD A V V pF V V 2 5.5 2.7 V ppm/C k A V V pF V 0.4 0.6 1 2 Unit 1 0.15 x VDD 0.7 x VDD 2 0.1 x VDD 0.05 x VDD 0.4 0.6 1 2.7 2.505 10 0.85 x VDD 2 0.1 x VDD 1 0.3 x VDD LOGIC OUTPUTS (SDA)3 VOL, Output Low Voltage Floating-State Leakage Current Floating-State Output Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode)4 VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes)5 VDD = 2.7 V to 5.5 V VDD = 3.6 V to 5.5 V Min V V A Test Conditions/Comments1 VDD = 4.5 V to 5.5 V At ambient High speed mode Fast mode ISINK = 3 mA ISINK = 6 mA pF 5.5 V 1.0 0.9 1.9 1.4 1.16 1.05 2.14 1.59 1.0 0.9 1.9 1.4 1.16 1.05 2.14 1.59 mA mA mA mA VIH = VDD, VIL = GND, full-scale loaded Internal reference off Internal reference off Internal reference on Internal reference on 0.48 0.48 1 1 0.48 0.48 1 1 A A VIH = VDD, VIL = GND (LFCSP) VIH = VDD, VIL = GND (TSSOP) 1 Temperature range of A and B grades is -40C to +105C. Linearity calculated using a reduced code range: AD5665R (Code 512 to Code 65,024), AD5645R (Code 128 to Code 16,256), AD5625R (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. Power-down function is not available on 14-lead TSSOP parts when the part is powered with VDD < 3.6 V. 2 Rev. B | Page 4 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 SPECIFICATIONS--AD5665/AD5625 VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter STATIC PERFORMANCE 2 AD5665 Resolution Relative Accuracy Differential Nonlinearity AD5625 Resolution Relative Accuracy Differential Nonlinearity Zero-Code Error Offset Error Full-Scale Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio DC Crosstalk (External Reference) Min 16 8 DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUTS Reference Current Reference Input Range Reference Input Impedance LOGIC INPUTS (ADDRx, CLR, LDAC, POR)3 IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance VHYST, Input Hysteresis LOGIC INPUTS (SDA, SCL)3 IIN, Input Current VINL, Input Low Voltage VINH, Input High Voltage CIN, Pin Capacitance VHYST, Input Hysteresis 16 1 12 0.5 2 1 -0.1 0.1 2 2.5 -100 15 DC Crosstalk (Internal Reference) OUTPUT CHARACTERISTICS 3 Output Voltage Range Capacitive Load Stability B Grade Typ Max 1 0.25 10 10 0.5 1 Unit Test Conditions/Comments 1 Bits LSB LSB Guaranteed monotonic by design Bits LSB LSB mV mV % FSR % FSR V/C ppm dB V 10 8 25 V/mA V V 20 10 V/mA V 0 VDD 2 10 0.5 30 4 210 0.75 V nF nF mA s 260 VDD A V k 1 0.15 x VDD A V V pF V 1 0.3 x VDD A V V pF V V 26 0.85 x VDD 2 0.1 x VDD 0.7 x VDD 2 0.1 x VDD 0.05 x VDD Rev. B | Page 5 of 36 Guaranteed monotonic by design All 0s loaded to DAC register All 1s loaded to DAC register Of FSR/C DAC code = midscale; VDD = 5 V 10% Due to full-scale output change, RL = 2 k to GND or VDD Due to load current change Due to powering down (per channel) Due to full-scale output change, RL = 2 k to GND or VDD Due to load current change Due to powering down (per channel) RL = RL = 2 k VDD = 5 V Coming out of power-down mode; VDD = 5 V VREF = VDD = 5.5 V High speed mode Fast mode AD5625R/AD5645R/AD5665R, AD5625/AD5665 Parameter LOGIC OUTPUTS (SDA)3 VOL, Output Low Voltage Floating-State Leakage Current Floating-State Output Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 4 VDD = 4.5 V to 5.5 V VDD = 2.7 V to 3.6 V IDD (All Power-Down Modes) 5 VDD = 2.7 V to 5.5 V VDD = 3.6 V to 5.5 V Min B Grade Typ Max Unit Test Conditions/Comments 1 0.4 0.6 1 V V A pF ISINK = 3 mA ISINK = 6 mA 5.5 V 1.0 0.9 1.16 1.05 mA mA 0.48 0.48 1 1 A A 2 2.7 VIH = VDD, VIL = GND, full-scale loaded 1 VIH = VDD, VIL = GND (LFCSP) VIH = VDD, VIL = GND (TSSOP) Temperature range of B grade is -40C to +105C. Linearity calculated using a reduced code range: AD5665 (Code 512 to Code 65,024), AD5625 (Code 32 to Code 4064). Output unloaded. 3 Guaranteed by design and characterization; not production tested. 4 Interface inactive. All DACs active. DAC outputs unloaded. 5 All DACs powered down. Power-down function is not available on 14-lead TSSOP parts when the part is powered with VDD < 3.6 V. 2 Rev. B | Page 6 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 AC CHARACTERISTICS VDD = 2.7 V to 5.5 V; RL = 2 k to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. Table 4. Parameter 1,2 Output Voltage Settling Time AD5625R/AD5625 AD5645R AD5665R/AD5665 Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Reference Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion Output Noise Spectral Density Output Noise Min Typ Max Unit Test Conditions/Comments 3 3 3.5 4 1.8 4.5 5 7 s s s V/s 1/4 to 3/4 scale settling to 0.5 LSB 1/4 to 3/4 scale settling to 0.5 LSB 1/4 to 3/4 scale settling to 2 LSB 15 5 0.1 -90 0.1 1 4 1 4 340 -80 120 100 15 nV-s nV-s nV-s dB nV-s nV-s nV-s nV-s nV-s kHz dB nV/Hz nV/Hz V p-p 1 Guaranteed by design and characterization; not production tested. See the Terminology section. 3 Temperature range is -40C to +105C, typical @ 25C. 2 Rev. B | Page 7 of 36 1 LSB change around major carry LFCSP TSSOP VREF = 2 V 0.1 V p-p, frequency 10 Hz to 20 MHz External reference Internal reference External reference Internal reference VREF = 2 V 0.1 V p-p VREF = 2 V 0.1 V p-p, frequency = 10 kHz DAC code = midscale, 1 kHz DAC code = midscale, 10 kHz 0.1 Hz to 10 Hz AD5625R/AD5645R/AD5665R, AD5625/AD5665 I2C TIMING SPECIFICATIONS VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted. 1 Table 5. Parameter fSCL 3 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t11A Test Conditions 2 Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode Standard mode Fast mode Standard mode Fast mode High speed mode Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Min 4 0.6 60 120 4.7 1.3 160 320 250 100 10 0 0 0 0 4.7 0.6 160 4 0.6 160 4.7 Max 100 400 3.4 1.7 3.45 0.9 70 150 1.3 4 0.6 160 10 20 10 20 10 20 10 20 Unit kHz kHz MHz MHz s s ns ns s s ns ns ns ns ns s s ns ns s s ns s s ns s 1000 300 80 160 300 300 80 160 1000 300 40 80 1000 s s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns 300 80 160 ns ns ns Rev. B | Page 8 of 36 Description Serial clock frequency tHIGH, SCL high time tLOW, SCL low time tSU;DAT, data setup time tHD;DAT, data hold time tSU;STA, setup time for a repeated start condition tHD;STA, hold time (repeated) start condition tBUF, bus-free time between a stop and a start condition tSU;STO, setup time for a stop condition tRDA, rise time of SDA signal tFDA, fall time of SDA signal tRCL, rise time of SCL signal tRCL1, rise time of SCL signal after a repeated start condition and after an acknowledge bit AD5625R/AD5645R/AD5665R, AD5625/AD5665 Parameter t12 t13 t14 t15 tSP 4 Test Conditions 2 Standard mode Fast mode High speed mode, CB = 100 pF High speed mode, CB = 400 pF Standard mode Fast mode High speed mode Standard mode Min Fast mode High speed mode Standard mode Fast mode High speed mode Fast mode High speed mode 300 30 20 20 20 0 0 Max 300 300 40 80 10 20 10 10 10 300 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 50 10 Description tFCL, fall time of SCL signal LDAC pulse width low Falling edge of ninth SCL clock pulse of last byte of a valid write to LDAC falling edge CLR pulse width low Pulse width of spike suppressed 1 See Figure 3. High speed mode timing specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7. CB refers to the capacitance on the bus line. 3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC behavior of the part. 4 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode. 2 t11 t12 t6 t2 SCL t1 t6 t4 t5 t3 t8 t10 t9 SDA t7 P S S P t14 t15 CLR *ASYNCHRONOUS LDAC UPDATE MODE. Figure 3. 2-Wire Serial Interface Timing Diagram Rev. B | Page 9 of 36 06341-003 t13 LDAC* AD5625R/AD5645R/AD5665R, AD5625/AD5665 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 6. Parameter VDD to GND VOUT to GND VREFIN/VREFOUT to GND Digital Input Voltage to GND Operating Temperature Range, Industrial Storage Temperature Range Junction Temperature (TJ maximum) Power Dissipation JA Thermal Impedance LFCSP_WD (4-Layer Board) TSSOP Reflow Soldering Peak Temperature, RoHS Compliant Rating -0.3 V to +7 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -40C to +105C -65C to +150C 150C (TJ max - TA)/JA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 61C/W 150.4C/W 260C 5C Rev. B | Page 10 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VOUTA 4 TOP VIEW (Not to Scale) VOUTC 5 POR 6 VREFIN/VREFOUT 7 SCL 13 SDA VOUTA 1 12 GND VOUTB 2 11 VOUTB GND 3 10 VOUTD VOUTC 4 9 CLR VOUTD 5 8 ADDR2 14 SCL 13 SDA 12 GND 11 VOUTB 10 VOUTD POR 6 9 CLR VREFIN 7 8 ADDR2 2 AD5625/ AD5665 VDD 3 VOUTA 4 VOUTC 5 TOP VIEW (Not to Scale) VREFIN/VREFOUT 9 VDD 8 SDA 7 SCL 6 ADDR Figure 6. Pin Configuration (10-Lead LFCSP), R Suffix Version VOUTA 1 VOUTB 2 GND 3 VOUTC 4 VOUTD 5 06341-121 LDAC 1 TOP VIEW (Not to Scale) 10 EXPOSED PAD TIED TO GND. Figure 4. Pin Configuration (14-Lead TSSOP), R Suffix Version ADDR1 AD5625R/ AD5645R/ AD5665R 06341-122 AD5625R/ AD5645R/ AD5665R VDD 3 14 AD5625/ AD5665 TOP VIEW (Not to Scale) 10 VREFIN 9 VDD 8 SDA 7 SCL 6 ADDR EXPOSED PAD TIED TO GND. 06341-123 2 06341-120 LDAC 1 ADDR1 Figure 7. Pin Configuration (10-Lead LFCSP) Figure 5. Pin Configuration (14-Lead TSSOP) Table 7. Pin Function Descriptions Pin Number 14-Lead 10-Lead 1 N/A Mnemonic LDAC 2 N/A ADDR1 3 9 VDD 4 5 6 1 4 N/A VOUTA VOUTC POR 7 10 VREFIN/VREFOUT 8 9 N/A N/A ADDR2 CLR 10 11 12 13 5 2 3 8 VOUTD VOUTB GND SDA 14 7 SCL N/A 6 ADDR EPAD Description Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 9). Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Power-On Reset Pin. Tying the POR pin to GND powers up the part to 0 V. Tying the POR pin to VDD powers up the part to midscale. The AD56x5R have a common pin for reference input and reference output. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference input. (The internal reference and reference output are only available on R suffix versions.) The AD56x5 has a reference input pin only. Three-State Address Input. Sets Bit A3 and Bit A2 of the 7-bit slave address (see Table 9). Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits clear code mode on the falling edge of the ninth clock pulse of the last byte of the valid write. If CLR is activated during a write sequence, the write is aborted. If CLR is activated during high speed mode, the part exits high speed mode. Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor. Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input register. Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address (see Table 8). For the 10-lead LFCSP, the exposed pad must be tied to GND. Rev. B | Page 11 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 TYPICAL PERFORMANCE CHARACTERISTICS 8 0.6 4 0.4 DNL ERROR (LSB) 6 2 0 -2 -4 0.2 0 -0.2 -0.4 -6 -0.6 -8 -0.8 -10 0 VDD = VREF = 5V TA = 25C 0.8 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k CODE -1.0 06341-005 INL ERROR (LSB) 1.0 VDD = VREF = 5V TA = 25C 0 10k 40k 50k 60k 0.5 VDD = VREF = 5V TA = 25C 3 30k CODE Figure 11. DNL, AD5665, External Reference Figure 8. INL, AD5665, External Reference 4 20k 06341-007 10 VDD = VREF = 5V TA = 25C 0.4 0.3 DNL ERROR (LSB) INL ERROR (LSB) 2 1 0 -1 -2 0.2 0.1 0 -0.1 -0.2 -0.3 -3 0 2500 5000 7500 10000 CODE 12500 15000 -0.5 0 Figure 9. INL, AD5645R, External Reference 2500 5000 7500 10000 CODE 12500 15000 06341-008 -0.4 06341-006 -4 Figure 12. DNL, AD5645R, External Reference 1.0 0.20 VDD = VREF = 5V 0.8 TA = 25C VDD = VREF = 5V TA = 25C 0.15 0.6 0.10 DNL ERROR (LSB) 0.2 0 -0.2 -0.4 0.05 0 -0.05 -0.10 -0.6 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 Figure 10. INL, AD5625, External Reference -0.20 0 500 1000 1500 2000 2500 CODE 3000 3500 Figure 13. DNL, AD5625, External Reference Rev. B | Page 12 of 36 4000 06341-009 -0.15 -0.8 06341-100 INL ERROR (LSB) 0.4 AD5625R/AD5645R/AD5665R, AD5625/AD5665 1.0 0.6 65000 06341-013 60000 55000 50000 Figure 17. DNL, AD5665R, 2.5 V Internal Reference 4 0.5 VDD = 5V VREFOUT = 2.5V TA = 25C VDD = 5V VREFOUT = 2.5V TA = 25C 0.4 0.3 DNL ERROR (LSB) 2 INL ERROR (LSB) 45000 CODE Figure 14. INL, AD5665R, 2.5 V Internal Reference 3 40000 0 65000 CODE 06341-010 60000 55000 50000 45000 40000 35000 30000 25000 20000 15000 -1.0 5000 -0.8 10000 -8 -10 0 -0.6 35000 -0.4 -6 30000 -4 0 -0.2 25000 0 -2 0.2 20000 2 0.4 15000 4 DNL ERROR (LSB) INL ERROR (LSB) 6 VDD = 5V VREFOUT = 2.5V TA = 25C 0.8 10000 8 VDD = 5V VREFOUT = 2.5V TA = 25C 5000 10 1 0 -1 -2 0.2 0.1 0 -0.1 -0.2 -0.3 -3 -0.4 16250 06341-014 15000 13750 12500 11250 8750 7500 6250 5000 3750 2500 0 Figure 18. DNL, AD5645R, 2.5 V Internal Reference 1.0 0.20 VDD = 5V VREFOUT = 2.5V TA = 25C 0.8 0.6 VDD = 5V VREFOUT = 2.5V TA = 25C 0.15 0.10 DNL ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 0.05 0 -0.05 -0.10 -0.6 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 Figure 16. INL, AD5625R, 2.5 V Internal Reference -0.20 0 500 1000 1500 2000 2500 CODE 3000 3500 Figure 19. DNL, AD5625R, 2.5 V Internal Reference Rev. B | Page 13 of 36 4000 06341-015 -0.15 -0.8 06341-012 INL ERROR (LSB) 1250 CODE Figure 15. INL, AD5645R, 2.5 V Internal Reference -1.0 10000 CODE -0.5 06341-011 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 -4 AD5625R/AD5645R/AD5665R, AD5625/AD5665 1.0 0.6 -0.2 65000 CODE Figure 20. INL, AD5665R,1.25 V Internal Reference 06341-019 60000 55000 50000 0 65000 CODE 06341-016 60000 55000 50000 45000 40000 35000 30000 25000 20000 -1.0 15000 -0.8 10000 -8 -10 0 -0.6 5000 -6 45000 -0.4 40000 -4 0 35000 -2 0.2 30000 0 25000 2 0.4 20000 4 DNL ERROR (LSB) INL ERROR (LSB) 6 VDD = 3V VREFOUT = 1.25V TA = 25C 0.8 5000 8 15000 VDD = 3V VREFOUT = 1.25V TA = 25C 10000 10 Figure 23. DNL, AD5665R,1.25 V Internal Reference 4 0.5 VDD = 3V VREFOUT = 1.25V TA = 25C 3 VDD = 3V VREFOUT = 1.25V TA = 25C 0.4 0.3 DNL ERROR (LSB) INL ERROR (LSB) 2 1 0 -1 0.2 0.1 0 -0.1 -0.2 -2 -0.3 -3 -0.4 16250 15000 13750 12500 11250 10000 8750 7500 6250 5000 3750 2500 1250 0 CODE Figure 21. INL, AD5645R, 1.25 V Internal Reference 06341-020 CODE 06341-017 16250 15000 13750 12500 11250 8750 10000 7500 6250 5000 3750 2500 0 -0.5 1250 -4 Figure 24. DNL, AD5645R,1.25 V Internal Reference 1.0 0.20 VDD = 3V VREFOUT = 1.25V TA = 25C 0.8 0.6 VDD = 3V VREFOUT = 1.25V TA = 25C 0.15 DNL ERROR (LSB) 0.2 0 -0.2 -0.4 0.05 0 -0.05 -0.10 -0.6 -1.0 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 Figure 22. INL, AD5625R,1.25 V Internal Reference -0.20 0 500 1000 1500 2000 2500 CODE 3000 3500 Figure 25. DNL, AD5625R, 1.25 V Internal Reference Rev. B | Page 14 of 36 4000 06341-021 -0.15 -0.8 06341-018 INL ERROR (LSB) 0.10 0.4 AD5625R/AD5645R/AD5665R, AD5625/AD5665 8 0 6 VDD = VREF = 5V VDD = 5V -0.02 MAX INL -0.04 GAIN ERROR 4 ERROR (% FSR) 2 MAX DNL 0 MIN DNL -2 -0.08 -0.10 -0.12 -0.14 -4 FULL-SCALE ERROR -0.16 MIN INL -6 -0.18 -20 0 20 40 60 TEMPERATURE (C) 80 100 -0.20 -40 06341-022 -8 -40 Figure 26. INL Error and DNL Error vs. Temperature -20 0 20 40 60 TEMPERATURE (C) 80 100 06341-025 ERROR (LSB) -0.06 Figure 29. Gain Error and Full-Scale Error vs. Temperature 10 1.5 MAX INL 8 1.0 ZERO-SCALE ERROR 6 0.5 VDD = 5V TA = 25C ERROR (mV) ERROR (LSB) 4 2 MAX DNL 0 MIN DNL -2 0 -0.5 -1.0 -4 -1.5 OFFSET ERROR -6 MIN INL 1.75 2.25 2.75 3.25 VREF (V) 3.75 4.25 4.75 -2.5 -40 Figure 27. INL Error and DNL Error vs. VREF 0 20 40 60 TEMPERATURE (C) 80 100 Figure 30. Zero-Scale Error and Offset Error vs. Temperature 8 1.0 6 MAX INL TA = 25C 0.5 4 ERROR (% FSR) GAIN ERROR 2 MAX DNL 0 MIN DNL -2 0 FULL-SCALE ERROR -0.5 -1.0 -4 MIN INL -8 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 -2.0 2.7 3.2 3.7 4.2 VDD (V) 4.7 5.2 Figure 31. Gain Error and Full-Scale Error vs. Supply Figure 28. INL Error and DNL Error vs. Supply Rev. B | Page 15 of 36 06341-027 -1.5 -6 06341-024 ERROR (LSB) -20 06341-026 1.25 06341-023 -8 -10 0.75 -2.0 AD5625R/AD5645R/AD5665R, AD5625/AD5665 1.0 2.0 TA = 25C 1.8 VDD = 5.5V TA = 25C 0.5 ZERO-SCALE ERROR 1.6 VREFOUT = 2.5V 1.4 -0.5 IDD (mA) ERROR (mV) 0 -1.0 1.2 VREFIN = 5V 1.0 0.8 0.6 -1.5 0.4 OFFSET ERROR 3.2 3.7 4.2 VDD (V) 4.7 5.2 0 512 06341-028 -2.5 2.7 0.2 VDD = 5.5V 60512 15 0.6 10 0.4 5 0.2 06341-029 TA = 25C 0 2.7 3.2 4.7 5.2 1.2 VDD = 3.6V VDD = 5.5V VDD = VREF = 5V 1.0 20 0.8 IDD (mA) 15 VREFOUT = 1.25V 4.2 VDD (V) Figure 36. Supply Current vs. Supply Figure 33. IDD Histogram with External Reference 25 3.7 06341-061 IDD (mA) 0.8 IDD (mA) VREFOUT = 2.5V 10 VDD = VREF = 3V 0.6 0.4 5 0 -40 -20 0 20 40 60 TEMPERATURE (C) 80 Figure 37. Supply Current vs. Temperature Figure 34. IDD Histogram with Internal Reference Rev. B | Page 16 of 36 100 06341-063 IDD (mA) 06341-030 0 0.2 1.35 1.37 1.39 1.41 1.43 1.45 1.47 1.49 1.51 1.53 1.55 1.57 1.59 1.61 1.63 1.65 1.67 1.69 1.71 1.73 1.75 1.77 1.79 1.81 1.83 1.85 1.87 1.89 1.91 1.93 1.95 1.97 1.99 NUMBER OF DEVICES 50512 1.0 20 0 30512 40512 CODE 1.2 VDD = 3.6V 0.88 0.89 0.90 0.91 0.92 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 NUMBER OF DEVICES 25 20512 Figure 35. Supply Current vs. DAC Code Figure 32. Zero-Scale Error and Offset Error vs. Supply 30 10512 06341-060 -2.0 AD5625R/AD5645R/AD5665R, AD5625/AD5665 0.5 0.4 DAC LOADED WITH FULL-SCALE SOURCING CURRENT DAC LOADED WITH ZERO-SCALE SINKING CURRENT ERROR VOLTAGE (V) 0.3 0.2 0.1 VDD = VREF = 5V TA = 25C FULL-SCALE CODE CHANGE 0x0000 TO 0xFFFF OUTPUT LOADED WITH 2k AND 200pF TO GND VDD = 3V VREFOUT = 1.25V 0 -0.1 -0.2 VOUT = 909mV/DIV VDD = 5V VREFOUT = 2.5V -0.3 1 -8 -6 -4 -2 0 2 CURRENT (mA) 4 6 8 10 06341-048 -0.5 -10 06341-031 -0.4 TIME BASE = 4s/DIV Figure 41. Full-Scale Settling Time, 5 V Figure 38. Headroom at Rails vs. Source and Sink 6 5 VDD = 5V VREFOUT = 2.5V TA = 25C 3/4 SCALE 4 VOUT (V) VDD = VREF = 5V TA = 25C FULL SCALE 3 MIDSCALE VDD 2 1 1/4 SCALE 1 ZERO SCALE -20 -10 0 10 CURRENT (mA) 20 VOUT 30 06341-046 -1 -30 MAX(C2) 420.0mV 2 CH1 2.0V 4 VOUT (V) M100s 125MS/s A CH1 1.28V 8.0ns/pt Figure 42. Power-On Reset to 0 V Figure 39. AD56x5R with 2.5 V Reference, Source and Sink Capability 3 CH2 500mV 06341-049 0 SYNC VDD = 3V VREFOUT = 1.25V TA = 25C 1 FULL SCALE SLCK 3 3/4 SCALE 2 MIDSCALE 1 1/4 SCALE VOUT 0 ZERO SCALE VDD = 5V -20 -10 0 10 CURRENT (mA) 20 30 Figure 40. AD56x5R with 1.25 V Reference, Source and Sink Capability Rev. B | Page 17 of 36 CH1 5.0V CH3 5.0V CH2 500mV M400ns A CH1 Figure 43. Exiting Power-Down to Midscale 1.4V 06341-050 -1 -30 06341-047 2 VDD = VREF = 5V TA = 25C DAC LOADED WITH MIDSCALE VDD = VREF = 5V TA = 25C 5ns/SAMPLE NUMBER GLITCH IMPULSE = 9.494nV 1LSB CHANGE AROUND MIDSCALE (0x8000 TO 0x7FFF) 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 512 4s/DIV Figure 44. Digital-to-Analog Glitch Impulse (Negative) 2.498 1 Figure 47. 0.1 Hz to 10 Hz Output Noise Plot, External Reference VDD = 5V VREFOUT = 2.5V TA = 25C DAC LOADED WITH MIDSCALE VDD = VREF = 5V TA = 25C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 0.424nV 2.497 06341-051 2V/DIV 2.538 2.537 2.536 2.535 2.534 2.533 2.532 2.531 2.530 2.529 2.528 2.527 2.526 2.525 2.524 2.523 2.522 2.521 06341-058 VOUT (V) AD5625R/AD5645R/AD5665R, AD5625/AD5665 10V/DIV VOUT (V) 2.496 2.495 2.494 1 2.493 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 512 Figure 48. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference 5V/DIV VDD = 3V VREFOUT = 1.25V TA = 25C DAC LOADED WITH MIDSCALE VDD = 5V VREFOUT = 2.5V TA = 25C 5ns/SAMPLE NUMBER ANALOG CROSSTALK = 4.462nV 0 50 100 150 200 250 300 350 SAMPLE NUMBER 400 450 Figure 46. Analog Crosstalk, Internal Reference 512 06341-062 VOUT (V) Figure 45. Analog Crosstalk, External Reference 2.496 2.494 2.492 2.490 2.488 2.486 2.484 2.482 2.480 2.478 2.476 2.474 2.472 2.470 2.468 2.466 2.464 2.462 2.460 2.458 2.456 5s/DIV 06341-052 0 1 4s/DIV 06341-053 2.491 06341-059 2.492 Figure 49. 0.1 Hz to 10 Hz Output Noise Plot, 1.25 V Internal Reference Rev. B | Page 18 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 16 800 TA = 25C MIDSCALE LOADED VREF = VDD TA = 25C 14 600 VDD = 3V 12 TIME (s) 500 400 300 1k 10k FREQUENCY (Hz) 100k 1M 4 0 Figure 50. Noise Spectral Density, Internal Reference -30 4 5 6 7 CAPACITANCE (nF) 5 VDD = 5V TA = 25C DAC LOADED WITH FULL SCALE VREF = 2V 0.3V p-p 8 9 10 VDD = 5V TA = 25C 0 -5 BANDWIDTH (dB) -50 -60 -70 -80 -10 -15 -20 -25 -30 -90 -35 2k 4k 6k FREQUENCY (Hz) 8k 10k 06341-055 THD (dB) 3 Figure 52. Settling Time vs. Capacitive Load -40 -100 2 Figure 51. Total Harmonic Distortion -40 10k 100k 1M FREQUENCY (Hz) Figure 53. Multiplying Bandwidth Rev. B | Page 19 of 36 10M 06341-057 -20 1 06341-056 0 100 VDD = 5V 6 VDD = 3V VREFOUT = 1.25V 100 10 8 VDD = 5V VREFOUT = 2.5V 200 06341-054 OUTPUT NOISE (nV/Hz) 700 AD5625R/AD5645R/AD5665R, AD5625/AD5665 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a 1/4 to 3/4 full-scale input change, and it is measured from the rising edge of the stop condition. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FFF to 0x8000) (see Figure 44). Zero-Code Error Zero-code error is a measurement of the output error when zero scale (0x0000) is loaded to the DAC register. Ideally, the output should be 0 V. The zero-code error is always positive in the AD5665R because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero-code error is expressed in millivolts (mV). Full-Scale Error Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the output should be VDD - 1 LSB. Full-scale error is expressed as a percentage of full-scale range (FSR). Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from ideal expressed as a percentage of full-scale range (FSR). Zero-Code Error Drift Zero-code error drift is a measurement of the change in zero-code error with a change in temperature. It is expressed in microvolts per degrees Celsius (V/C). Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in parts per million (ppm) of full-scale range per degrees Celsius (FSR/C). Offset Error Offset error is a measure of the difference between VOUT (actual) and VOUT (ideal) expressed in mV in the linear region of the transfer function. Offset error is measured on the AD5665R with Code 512 loaded in the DAC register. It can be negative or positive. DC Power Supply Rejection Ratio (PSRR) DC PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to the change in VDD for full-scale output of the DAC. It is measured in decibels (dB). VREF is held at 2 V, and VDD is varied by 10%. Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in decibels (dB). Output Noise Spectral Density Output noise spectral density is a measurement of the internally generated random noise, which is characterized as a spectral density (nanovolts per square root of hertz frequency (nV/Hz)). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nanovolts per square root of hertz frequency (nV/Hz). A plot of noise spectral density is shown in Figure 50. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC kept at midscale. It is expressed in microvolts (V). DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has on another DAC kept at midscale. It is expressed in microvolts per milliampere (V/mA). Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nanovolts per second (nV-s). Rev. B | Page 20 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) and then executing a software LDAC and monitoring the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nanovolts per second (nV-s). DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nanovolts per second (nV-s). Multiplying Bandwidth The multiplying bandwidth is a measure of the finite bandwidth of the amplifiers within the DAC. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Total Harmonic Distortion (THD) THD is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measurement of the harmonics present on the DAC output. It is measured in decibels (dB). Rev. B | Page 21 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTER (DAC) RESISTOR STRING The AD56x5R/AD56x5 DACs are fabricated on a CMOS process. The AD56x5 does not have an internal reference, and the DAC architecture is shown in Figure 54. The AD56x5R does have an internal reference and can be configured for use with either an internal or external reference (see Figure 54 and Figure 55). The resistor string is shown in Figure 56. It is simply a string of resistors, each of value R. The code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. Because the input coding to the DAC is straight binary, the ideal output voltage when using an external reference is given by OUTPUT AMPLIFIER D VOUT = VREFIN x N 2 VREFIN/VREFOUT REF BUFFER REF (+) DAC REGISTER The output buffer amplifier can generate rail-to-rail voltages on its output, which gives an output range of 0 V to VDD. It can drive a load of 2 k in parallel with 1000 pF to GND. The source and sink capabilities of the output amplifier are shown in Figure 38 and Figure 39. The slew rate is 1.8 V/s with a 1/4 to 3/4 full-scale settling time of 7 s. OUTPUT AMPLIFIER GAIN = x2 RESISTOR STRING R VOUT R REF (-) TO OUTPUT AMPLIFIER 06341-034 R GND Figure 54. Internal Configuration When Using an External Reference R The ideal output voltage when using the internal reference is given by R 06341-033 D VOUT = 2 x V REFOUT x N 2 where: D is the decimal equivalent of the binary code that is loaded to the DAC register, as follows: 0 to 4095 for AD5625R/AD5625 (12-bit). 0 to 16,383 for AD5645R (14-bit). 0 to 65,535 for AD5665R/AD5665 (16-bit). N is the DAC resolution. REF (+) DAC REGISTER RESISTOR STRING OUTPUT AMPLIFIER GAIN = x2 VOUT BE OVERDRIVEN BY VREFIN/VREFOUT . GND 06341-035 REF (-) 1CAN INTERNAL REFERENCE The AD5625R/AD5645R/AD5665R feature an on-chip reference. Versions without the R suffix require an external reference. The on-chip reference is off at power-up and is enabled via a write to a control register. See the Internal Reference Setup section for details. Versions packaged in a 10-lead LFCSP have a 1.25 V reference or a 2.5 V reference, giving a full-scale output of 2.5 V or 5 V, depending on the model selected (see the Ordering Guide). These parts can be operated with a VDD supply of 2.7 V to 5.5 V. Versions packaged in a 14-lead TSSOP have a 2.5 V reference, giving a full-scale output of 5 V. Parts are functional with a VDD supply of 2.7 V to 5.5 V, but, with a VDD supply of less than 5 V, the output is clamped to VDD. See the Ordering Guide for a full list of models. The internal reference associated with each part is available at the VREFOUT pin (available on R suffix versions only). VREFIN/VREFOUT 1.25V INTERNAL REFERENCE 1 Figure 56. Resistor String Figure 55. Internal Configuration When Using the Internal Reference A buffer is required if the reference output is used to drive external loads. When using the internal reference, it is recommended that a 100 nF capacitor be placed between the reference output and GND for reference stability. Rev. B | Page 22 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 EXTERNAL REFERENCE The 2-wire serial bus protocol operates as follows: The VREFIN pin on the AD56x5R allows the use of an external reference if the application requires it. The default condition of the on-chip reference is off at power-up. All devices can be operated from a single 2.7 V to 5.5 V supply. 1. SERIAL INTERFACE The AD56x5R/AD56x5 have 2-wire I2C-compatible serial interfaces. The AD56x5R/AD56x5 can be connected to an I2C bus as a slave device, under the control of a master device. See Figure 3 for a timing diagram of a typical write sequence. The AD56x5R/AD56x5 support standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) data transfer modes. High speed operation is only available on selected models. See the Ordering Guide for a full list of models. Support is not provided for 10-bit addressing and general call addressing. The AD56x5R/AD56x5 each has a 7-bit slave address. The 10-lead versions of the part have a slave address whose five MSBs are 00011, and the two LSBs are set by the state of the ADDR address pin, which determines the state of the A0 and A1 address bits. The 14-lead versions of the part have a slave address whose three MSBs are 001, and the four LSBs are set by the ADDR1 and ADDR2 address pins, which determine the state of the A0 and A1 and A2 and A3 address bits, respectively. The facility to make hardwired changes to the ADDR pin allows the user to incorporate up to three of these devices on one bus, as outlined in Table 8. Table 8. ADDR Pin Settings (10-Lead Package) ADDR Pin Connection VDD NC GND A1 0 1 1 A0 0 0 1 The facility to make hardwired changes to the ADDR1 and the ADDR2 pins allows the user to incorporate up to nine of these devices on one bus, as outlined in Table 9. Table 9. ADDR1, ADDR2 Pin Settings (14-Pin Package) ADDR2 Pin Connection VDD VDD VDD NC NC NC GND GND GND ADDR1 Pin Connection VDD NC GND VDD NC GND VDD NC GND A3 0 0 0 1 1 1 1 1 1 A2 0 0 0 0 0 0 1 1 1 A1 0 1 1 0 1 1 0 1 1 A0 0 0 1 0 0 1 0 0 1 2. 3. The master initiates data transfer by establishing a start condition when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address. The slave address corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read or written, a stop condition is established. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master brings the SDA line low before the 10th clock pulse, and then high during the 10th clock pulse to establish a stop condition. WRITE OPERATION When writing to the AD56x5R/AD56x5, the user must begin with a start command followed by an address byte (R/W = 0), after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The AD5665 requires two bytes of data for the DAC and a command byte that controls various DAC functions. Three bytes of data must, therefore, be written to the DAC, the command byte followed by the most significant data byte and the least significant data byte, as shown in Figure 57 and Figure 58. After these data bytes are acknowledged by the AD56x5R/AD56x5, a stop condition follows. READ OPERATION When reading data back from the AD56x5R/AD56x5, the user begins with a start command followed by an address byte (R/W = 1), after which the DAC acknowledges that it is prepared to transmit data by pulling SDA low. Two bytes of data are then read from the DAC, which are both acknowledged by the master as shown in Figure 59 and Figure 60. A stop condition follows. Rev. B | Page 23 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 ACK. BY AD56x5 START BY MASTER ACK. BY AD56x5 FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 9 1 SCL (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB7 DB8 DB6 DB5 ACK. BY AD56x5 FRAME 3 MOST SIGNIFICANT DATA BYTE DB4 DB3 DB2 DB1 DB0 ACK. BY STOP BY AD56x5 MASTER FRAME 4 LEAST SIGNIFICANT DATA BYTE 06341-103 SDA (CONTINUED) Figure 57. I2C Write Operation (10-Lead Package) 1 9 1 9 SCL 0 SDA 0 1 A3 A2 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 ACK. BY AD56x5 START BY MASTER ACK. BY AD56x5 FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 9 1 SCL (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB7 DB8 DB6 DB5 ACK. BY AD56x5 FRAME 3 MOST SIGNIFICANT DATA BYTE DB4 DB3 DB2 DB1 DB0 ACK. BY STOP BY AD56x5 MASTER FRAME 4 LEAST SIGNIFICANT DATA BYTE 06341-104 SDA (CONTINUED) Figure 58. I2C Write Operation (14-Lead Package) 1 9 1 9 SCL 0 SDA 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 ACK. BY AD56x5 START BY MASTER DB16 ACK. BY MASTER FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 9 1 SCL (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 FRAME 3 MOST SIGNIFICANT DATA BYTE DB9 DB8 DB7 ACK. BY MASTER DB6 DB5 DB4 DB2 FRAME 4 LEAST SIGNIFICANT DATA BYTE Figure 59. I2C Read Operation (10-Lead Package) Rev. B | Page 24 of 36 DB3 DB1 DB0 NO ACK. STOP BY MASTER 06341-101 SDA (CONTINUED) AD5625R/AD5645R/AD5665R, AD5625/AD5665 1 9 1 9 SCL 0 SDA 0 1 A3 A2 A1 R/W A0 DB23 DB22 DB21 DB20 DB19 DB18 DB17 ACK. BY AD56x5 START BY MASTER DB16 ACK. BY MASTER FRAME 1 SLAVE ADDRESS FRAME 2 COMMAND BYTE 1 9 9 1 SCL (CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB7 DB8 DB6 DB5 DB4 ACK. BY MASTER FRAME 3 MOST SIGNIFICANT DATA BYTE DB3 DB2 DB1 DB0 NO ACK. STOP BY MASTER FRAME 4 LEAST SIGNIFICANT DATA BYTE 06341-102 SDA (CONTINUED) Figure 60. I2C Read Operation (14-Lead Package) FAST MODE HIGH-SPEED MODE 1 9 1 9 SCL 0 START BY MASTER 0 0 0 1 X X X 0 NO ACK. 0 1 A3 A2 A1 A0 SR R/W ACK. BY AD56x5 HS-MODE MASTER CODE SERIAL BUS ADDRESS BYTE 06341-105 SDA Figure 61. Placing the AD56x5RBRUZ-2/AD56x5RBRUZ-2REEL7 in High Speed Mode HIGH SPEED MODE INPUT SHIFT REGISTER Some models offer high speed serial communication with a clock frequency of 3.4 MHz. See the Ordering Guide for a full list of models. The input shift register is 24 bits wide. Data is loaded into the device as a 24-bit word under the control of a serial clock input, SCL. The timing diagram for this operation is shown in Figure 3. The eight MSBs make up the command byte. DB23 is reserved and should always be set to 0 when writing to the device. DB22 (S) is used to select multiple byte operation. The next three bits are the command bits (C2, C1, and C0) that control the mode of operation of the device. See Table 10 for details. The last three bits of the first byte are the address bits (A2, A1, and A0). See Table 11 for details. The rest of the bits are the 16-/14-/12-bit data-word. The data-word comprises the 16-/14-/12-bit input code followed by two or four don't care bits for the AD5645R and the AD5625R/AD5625, respectively (see Figure 64 through Figure 66). High speed mode communication commences after the master addresses all devices connected to the bus with the Master Code 00001XXX to indicate that a high speed mode transfer is to begin. No device connected to the bus is permitted to acknowledge the high speed master code; therefore, the code is followed by a no acknowledge. Next, the master must issue a repeated start followed by the device address. The selected device then acknowledges its address. All devices continue to operate in high speed mode until the master issues a stop condition. When the stop condition is issued, the devices return to standard/fast mode. The part also returns to standard/fast mode when CLR is activated while the part is in high speed mode. MULTIPLE BYTE OPERATION Multiple byte operation is supported on the AD56x5R/AD56x5. A 2-byte operation is useful for applications that require fast DAC updating and do not need to change the command byte. The S bit (DB22) in the command register can be set to 1 for 2-byte mode of operation (see Figure 63). For standard 3-byte and 4-byte operation, the S bit (DB22) in the command byte should be set to 0 (see Figure 62). Rev. B | Page 25 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 BLOCK 2 BLOCK n S=0 S=0 SLAVE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE BYTE DATA BYTE DATA BYTE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT STOP BYTE DATA BYTE DATA BYTE Figure 62. Multiple Block Write with Command Byte in Each Block (S = 0) BLOCK 2 BLOCK n S=1 S=1 SLAVE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT MOST SIGNIFICANT LEAST SIGNIFICANT ADDRESS BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE MOST SIGNIFICANT LEAST SIGNIFICANT STOP DATA BYTE DATA BYTE 06341-106 BLOCK 1 S=1 Figure 63. Multiple Block Write with Initial Command Byte Only (S = 1) S BYTE SELECTION C2 C1 C0 COMMAND A2 A1 A0 D15 D14 D13 DAC ADDRESS COMMAND BYTE D12 D11 D10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE 06341-108 R RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 Figure 64. AD5665R/AD5665 Input Shift Register (16-Bit DAC) S BYTE SELECTION C2 C1 C0 COMMAND A2 A1 A0 D13 D12 D11 DAC ADDRESS COMMAND BYTE D10 D9 D8 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D7 D6 D5 D4 D3 D2 D1 D0 X X DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE 06341-109 R RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 R S RESERVED BYTE SELECTION DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 C2 C1 C0 COMMAND COMMAND BYTE A2 A1 A0 DAC ADDRESS D11 D10 D9 D8 D7 D6 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 D5 D4 D3 D2 D1 D0 X X X X DAC DATA DAC DATA DATA HIGH BYTE DATA LOW BYTE Figure 66. AD5625R/AD5625 Input Shift Register (12-Bit DAC) Rev. B | Page 26 of 36 06341-110 Figure 65. AD5645R Input Shift Register (14-Bit DAC) 06341-107 BLOCK 1 S=0 AD5625R/AD5645R/AD5665R, AD5625/AD5665 BROADCAST MODE LDAC FUNCTION Broadcast addressing is supported on the AD56x5R/AD56x5 in write mode only. Broadcast addressing can be used to synchronously update or power down multiple AD56x5R/AD56x5 devices. When the broadcast address is used, the AD56x5R/ AD56x5 responds regardless of the states of the address pins. The AD56x5R/AD56x5 broadcast address is 00010000. The AD56x5R/AD56x5 DACs have double-buffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected directly to the input shift register, and the digital code is transferred to the relevant input register upon completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings. Table 10. Command Definition Access to the DAC registers is controlled by the LDAC pin. When the LDAC pin is high, the DAC registers are latched and the input registers can change state without affecting the contents of the DAC registers. When LDAC is brought low, however, the DAC registers become transparent and the contents of the input registers are transferred to them. The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. The user can write to one of the input registers individually and then, by bringing LDAC low when writing to the other DAC input register, all outputs update simultaneously. C2 0 0 0 C1 0 0 1 C0 0 1 0 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 Command Write to input Register n Update DAC Register n Write to input Register n, update all (software LDAC) Write to and update DAC Channel n Power up/power down Reset LDAC register setup Internal reference setup (on/off ) Table 11. DAC Address Command A2 0 0 0 0 1 A1 0 0 1 1 1 A0 0 1 0 1 1 ADDRESS (n) DAC A DAC B DAC C DAC D All DACs These parts each contain an extra feature whereby a DAC register is not updated unless its input register has been updated since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD56x5R/AD56x5, the DAC register updates only if the input register has changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. The outputs of all DACs can be simultaneously updated, using the hardware LDAC pin. . Rev. B | Page 27 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 Synchronous LDAC Table 12. LDAC Register Mode of Operation on the 10-Lead LFCSP (Load DAC Register) The DAC registers are updated after new data is read in. LDAC can be permanently low or pulsed. LDAC Bits (DB3 to DB0) 0 Asynchronous LDAC The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register. 1 The LDAC register gives the user full flexibility and control over the hardware LDAC pin (and software LDAC on the 10-lead parts that do not have the hardware LDAC pin--see Table 12). This register allows the user to select which combination of channels to simultaneously update when the hardware LDAC pin is executed. Setting the LDAC bit register to 0 for a DAC channel means that the update of this channel is controlled by the LDAC pin. If this bit is set to 1, this channel synchronously updates; that is, the DAC register is updated after new data is read in, regardless of the state of the LDAC pin. The device effectively sees the LDAC pin as being pulled low. See Table 13 for the LDAC register mode of operation. This flexibility is useful in applications when the user wants to simultaneously update select channels while the rest of the channels are synchronously updating. LDAC Mode of Operation Normal operation (default), DAC register update is controlled by the write command. The DAC registers are updated after new data is read in. Table 13. LDAC Register Mode of Operation on the 14-Lead TSSOP (Load DAC Register) LDAC Bits (DB3 to DB0) 0 1 LDAC Pin LDAC Operation 1/0 Determined by the LDAC pin. x = don't care The DAC registers are updated after new data is read in. S C2 C1 C0 A2 A1 A0 0 X 1 1 0 A2 A1 A0 DON'T CARE COMMAND DAC ADDRESS (DON'T CARE) DB15 DB14 DB13 DB12 DB11 DB10 X X X X X X DB9 DB8 DB7 DB6 DB5 DB4 X X X X X X DON'T CARE Figure 67. LDAC Setup Command Rev. B | Page 28 of 36 DON'T CARE DB3 DB2 DB1 DB0 DAC D DAC C DAC B DAC A DAC SELECT (0 = LDAC PIN ENABLED) 06341-115 R RESERVED Writing to the DAC using Command 110 loads the 4-bit LDAC register [DB3:DB0]. The default for each channel is 0; that is, the LDAC pin works normally. Setting the bits to 1 means that the DAC register is updated, regardless of the state of the LDAC pin. See Figure 67 for the contents of the input shift register during the LDAC register setup command. AD5625R/AD5645R/AD5665R, AD5625/AD5665 POWER-DOWN MODES Table 14. Modes of Operation for the AD56x5R/AD56x5 Command 100 is reserved for the power-up/power-down function. The power-up/power-down modes are programmed by setting Bit DB5 and Bit DB4. This defines the output state of the DAC amplifier, as shown in Table 14. Bit DB3 to Bit DB0 determine to which DAC or DACs the power-up/power-down command is applied. Setting one of these bits to 1 applies the power-up/power-down state defined by DB5 and DB4 to the corresponding DAC. If a bit is 0, the state of the DAC is unchanged. Figure 69 shows the contents of the input shift register for the power-up/power-down command. DB5 0 DB4 0 0 1 1 1 0 1 C2 C1 C0 A2 A1 A0 X 1 0 0 A2 A1 A0 Figure 68. Output Stage During Power-Down The bias generator, output amplifier, resistor string, and other associated linear circuitry are shut down when power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit powerdown is typically 4 s for VDD = 5 V or VDD = 3 V. RESERVED DON'T CARE COMMAND DAC ADDRESS (DON'T CARE) DB15 DB14 DB13 DB12 DB11 DB10 X X X RESISTOR NETWORK X X X DB9 DB8 DB7 DB6 DB5 DB4 X X X X PD1 PD0 DON'T CARE Figure 69. Power-Up/Power-Down Command Rev. B | Page 29 of 36 DON'T CARE POWERDOWN MODE DB3 DB2 DB1 DB0 DAC D DAC C DAC B DAC A DAC SELECT (1 = DAC SELECTED) 06341-116 S VOUT POWER-DOWN CIRCUITRY Note that the 14-lead TSSOP models offer the power-down function when the part is operated with a VDD of 3.6 V to 5.5 V. The 10-lead LFCSP models offer the power-down function when the part is powered with a VDD of 2.7 V to 5.5 V. 0 AMPLIFIER 06341-038 RESISTOR STRING DAC When Bit DB5 and Bit DB4 are set to 0, the part works normally with its normal power consumption of 1 mA at 5 V. However, for the three power-down modes, the supply current falls to 480 nA at 5 V. Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This allows the output impedance of the part to be known while the part is in power-down mode. The outputs can either be connected internally to GND through a 1 k or 100 k resistor or be left open-circuited (three-state) as shown in Figure 66. R Operating Mode Normal operation Power-down modes 1 k pull-down resistor to GND 100 k pull-down resistor to GND Three-state, high impedance AD5625R/AD5645R/AD5665R, AD5625/AD5665 POWER-ON RESET AND SOFTWARE RESET Table 15. Software Reset Modes for the AD56x5R/AD56x5 The AD56x5R/AD56x5 contain a power-on reset circuit that controls the output voltage during power-up. The 10-lead version of the device powers up to 0 V. The 14-lead version has a power-on reset (POR) pin that allows the output voltage to be selected. By connecting the POR pin to GND, the AD56x5R/ AD56x5 output powers up to 0 V; by connecting the POR pin to VDD, the AD56x5R/AD56x5 output powers up to midscale. The output remains powered up at this level until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC while it is in the process of powering up. DB0 0 1 (Power-On Reset) INTERNAL REFERENCE SETUP (R VERSIONS) The on-chip reference is off at power-up by default. It can be turned on by sending the reference setup command (111) and setting DB0 in the input shift register. Table 16 shows how the state of the bit corresponds to the mode of operation. Any events on LDAC or CLR during power-on reset are ignored. There is also a software reset function. Command 101 is the software reset command. The software reset command contains two reset modes that are software programmable by setting bit DB0 in the input shift register. Table 16. Reference Setup Command C2 C1 C0 A2 A1 A0 X 1 0 1 X X X RESERVED DON'T CARE DB15 DB14 DB13 DB12 DB11 DB10 X X X DAC ADDRESS (DON'T CARE) COMMAND X X DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X X X X X X RST X DON'T CARE RESET MODE S 0 Action Internal reference off (default) Internal reference on DON'T CARE 06341-113 DB0 0 1 Table 15 shows how the state of the bit corresponds to the software reset modes of operation of the devices. Figure 70 shows the contents of the input shift register during the software reset mode of operation. X Registers Reset to Zero DAC register Input shift register DAC register Input shift register LDAC register Power-down register Internal reference setup register C2 C1 C0 A2 A1 A0 X 1 1 1 X X X DON'T CARE COMMAND DAC ADDRESS (DON'T CARE) DB15 DB14 DB13 DB12 DB11 DB10 X X X X X X DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X X X X X X X X REF DON'T CARE Figure 71. Reference Setup Command Rev. B | Page 30 of 36 DON'T CARE 06341-114 S 0 REFERENCE MODE R RESERVED Figure 70. Reset Command AD5625R/AD5645R/AD5665R, AD5625/AD5665 APPLICATIONS INFORMATION R2 = 10k USING A REFERENCE AS A POWER SUPPLY FOR THE AD56x5R/AD56x5 +5V R1 = 10k 1 mA + (5 V/5 k) = 2 mA 15V 5V VDD SCL SDA AD5625R/ AD5645R/ AD5665R/ AD5625/ AD5665 VOUT = 0V TO 5V GND 06341-043 2-WIRE SERIAL INTERFACE VDD +5V 10F 0.1F VO 5V VOUT AD5625R/ AD5645R/ AD5665R/ AD5625/ AD5665 GND SCL -5V SDA 2-WIRE SERIAL INTERFACE Figure 73. Bipolar Operation with the AD56x5R/AD56x5 POWER SUPPLY BYPASSING AND GROUNDING The load regulation of the REF195 is typically 2 ppm/mA, resulting in a 4 ppm (20 V) error for the 2 mA current drawn from it. This corresponds to a 0.263 LSB error. REF195 AD820/ OP295 06341-044 Because the supply current required by the AD56x5R/AD56x5 is extremely low, an alternative option is to use a voltage reference to supply the required voltage to the part (see Figure 72). This is especially useful if the power supply is noisy or if the system supply voltages are at some value other than 5 V or 3 V, for example, 15 V. The voltage reference outputs a steady supply voltage for the AD56x5R/AD56x5. If the low dropout REF195 is used, it must supply 450 A of current to the AD56x5R/AD56x5 with no load on the output of the DAC. When the DAC output is loaded, the REF195 also must supply the current to the load. The total current required (with a 5 k load on the DAC output) is Figure 72. REF195 as Power Supply to the AD56x5R/AD56x5 BIPOLAR OPERATION USING THE AD56x5R/AD56x5 The AD56x5R/AD56x5 have been designed for single-supply operation, but a bipolar output range is also possible using the circuit shown in Figure 73. The circuit gives an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as follows: D R1 + R2 R2 VO = V DD x x - V DD x 65 , 536 R1 R1 where D represents the input code in decimal (0 to 65,535). If VDD = 5 V, R1 = R2 = 10 k, 10 x D VO = -5 V 65,536 When accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. The printed circuit board containing the AD56x5R/AD56x5 should have separate analog and digital sections, each having its own area of the board. If the AD56x5R/AD56x5 are in a system where other devices require an AGND-to-DGND connection, the connection should be made at one point only. This ground point should be as close as possible to the AD56x5R/AD56x5. The power supply to the AD56x5R/AD56x5 should be bypassed with 10 F and 0.1 F capacitors. The capacitors should be located as close as possible to the device, with the 0.1 F capacitor ideally right up against the device. The 10 F capacitor is the tantalum bead type. It is important that the 0.1 F capacitor have low effective series resistance (ESR) and low effective series inductance (ESI), for example, common ceramic types of capacitors. This 0.1 F capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. The power supply line itself should have as large a trace as possible to provide a low impedance path and to reduce glitch effects on the supply line. Clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. Avoid crossover of digital and analog signals if possible. When traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. The best board layout technique is the microstrip technique where the component side of the board is dedicated to the ground plane only, and the signal traces are placed on the solder side. However, this is not always possible with a 2-layer board. This is an output voltage range of 5 V, with 0x0000 corresponding to a -5 V output and 0xFFFF corresponding to a +5 V output. Rev. B | Page 31 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 OUTLINE DIMENSIONS 0.30 0.23 0.18 3.00 BSC SQ 0.50 BSC 10 6 PIN 1 INDEX AREA 1.74 1.64 1.49 *EXPOSED PAD (BOTTOM VIEW) 0.50 0.40 0.30 5 1 TOP VIEW 2.48 2.38 2.23 0.80 MAX 0.55 NOM 0.80 0.75 0.70 PIN 1 INDICATOR (R 0.20) 0.05 MAX 0.02 NOM SEATING PLANE 0.20 REF 031208-B *FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 74. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8 0 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 75. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters Rev. B | Page 32 of 36 0.75 0.60 0.45 061908-A 1.05 1.00 0.80 AD5625R/AD5645R/AD5665R, AD5625/AD5665 ORDERING GUIDE Model 1 AD5625BCPZ-R2 AD5625BCPZ-REEL7 AD5625BRUZ AD5625BRUZ-REEL7 AD5625RBCPZ-R2 AD5625RBCPZ-REEL7 AD5625RACPZ-REEL7 AD5625RACPZ-1RL7 AD5625RBRUZ-1 AD5625RBRUZ-1REEL7 AD5625RBRUZ-2 AD5625RBRUZ-2REEL7 AD5645RBCPZ-R2 AD5645RBCPZ-REEL7 AD5645RBRUZ AD5645RBRUZ-REEL7 AD5665BCPZ-R2 AD5665BCPZ-REEL7 AD5665BRUZ AD5665BRUZ-REEL7 AD5665RBCPZ-R2 AD5665RBCPZ-REEL7 AD5665RBRUZ-1 AD5665RBRUZ-1REEL7 AD5665RBRUZ-2 AD5665RBRUZ-2REEL7 EVAL-AD5665REBZ1 Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C Accuracy 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 4 LSB INL 4 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 1 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 4 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL 16 LSB INL On-Chip Reference None None None None 1.25 V 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V 2.5 V 1.25 V 1.25 V 2.5 V 2.5 V None None None None 1.25 V 1.25 V 2.5 V 2.5 V 2.5 V 2.5 V Maximum I2C Speed 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 3.4 MHz 3.4 MHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 400 kHz 3.4 MHz 3.4 MHz EVAL-AD5665REBZ2 1 Z = RoHS Compliant Part. Rev. B | Page 33 of 36 Package Description 10-Lead LFCSP_WD 10-Lead LFCSP_WD 14-Lead TSSOP 14-Lead TSSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 10-Lead LFCSP_WD 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 14-Lead TSSOP 14-Lead TSSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 14-Lead TSSOP 14-Lead TSSOP 10-Lead LFCSP_WD 10-Lead LFCSP_WD 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP 14-Lead TSSOP TSSOP Evaluation Board LFCSP Evaluation Board Package Option CP-10-9 CP-10-9 RU-14 RU-14 CP-10-9 CP-10-9 CP-10-9 CP-10-9 RU-14 RU-14 RU-14 RU-14 CP-10-9 CP-10-9 RU-14 RU-14 CP-10-9 CP-10-9 RU-14 RU-14 CP-10-9 CP-10-9 RU-14 RU-14 RU-14 RU-14 Branding D8V D8V D8S D8S DEU DFW D89 D89 D6U D6U DA2 DA2 AD5625R/AD5645R/AD5665R, AD5625/AD5665 NOTES Rev. B | Page 34 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 NOTES Rev. B | Page 35 of 36 AD5625R/AD5645R/AD5665R, AD5625/AD5665 NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06341-0-12/09(B) Rev. B | Page 36 of 36