Quad, 12-/14-/16-Bit nanoDACs with
5 ppm/°C On-Chip Reference, I2C Interface
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B
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FEATURES
Low power, smallest pin-compatible, quad nanoDACs
AD5625R/AD5645R/AD5665R
12-/14-/16-bit nanoDACs
On-chip, 2.5 V, 5 ppm/°C reference in TSSOP
On-chip, 2.5 V, 10 ppm/°C reference in LFCSP
On-chip, 1.25 V, 10 ppm/°C reference in LFCSP
AD5625/AD5665
12-/16-bit nanoDACs
External reference only
3 mm × 3 mm 10-lead LFCSP and 14-lead TSSOP
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale/midscale
Per channel power-down
Hardware LDAC and CLR functions
I2C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5625R/AD5645R/AD5665R and AD5625/AD5665
members of the nanoDAC® family are low power, quad, 12-/
14-/16-bit, buffered voltage-out DACs with/without an on-chip
reference. All devices operate from a single 2.7 V to 5.5 V supply,
are guaranteed monotonic by design, and have an I2C-compatible
serial interface.
The AD5625R/AD5645R/AD5665R have an on-chip reference.
The LFCSP versions of the AD56x5R have a 1.25 V or 2.5 V,
10 ppm/°C reference, giving a full-scale output range of 2.5 V or
5 V; the TSSOP versions of the AD56x5R have a 2.5 V, 5 ppm/°C
reference, giving a full-scale output range of 5 V. The on-chip
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a software write.
The AD5625/AD5665 require an external reference voltage to
set the output range of the DAC.
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V (POR = GND) or midscale
(POR = VDD) and remains there until a valid write occurs. The
on-chip precision output amplifier enables rail-to-rail output swing.
FUNCTIONAL BLOCK DIAGRAMS
INTERFACE
LOGIC
SDA
SCL
A
DDR1
A
DDR2
V
DD
GND
1.25V/2.5V REF
V
REFIN
/
V
REFOUT
AD5625R/AD5645R/AD5665R
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A V
OUT
A
BUFFER
LDAC CLR POR
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B V
OUT
B
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C V
OUT
C
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D V
OUT
D
BUFFER
NOTES
1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:
ADDR2, LDAC, CLR, POR.
06341-001
POWER-ON RESET POWER-DOWN LOGIC
Figure 1. AD5625R/AD5645R/AD5665R
0
6341-002
INTERFACE
LOGIC
SDA
SCL
ADDR1
ADDR2
V
DD
GND
V
REFIN
AD5625/AD5665
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A V
OUT
A
BUFFER
LDAC CLR POR
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B V
OUT
B
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C V
OUT
C
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D V
OUT
D
BUFFER
NOTES
1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:
ADDR2, LDAC, CLR, POR.
POWER-ON RESET POWER-DOWN LOGIC
Figure 2. AD5625/AD5665
The AD56x5R/AD56x5 use a 2-wire I2C-compatible serial
interface that operates in standard (100 kHz), fast (400 kHz),
and high speed (3.4 MHz) modes.
Table 1. Related Devices
Part No. Description
AD5025/AD5045/AD5065 Dual 12-/14-/16-bit DACs
AD5624R/AD5644R/AD5664R,
AD5624/AD5664
Quad SPI 12-/14-/16-bit DACs,
with/without internal reference
AD5627R/AD5647R/AD5667R,
AD5627/AD5667
Dual I2C 12-/14-/16-bit DACs,
with/without internal reference
AD5666 Quad SPI 16-bit DAC with
internal reference
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Specifications—AD5665R/AD5645R/AD5625R ..................... 3
Specifications—AD5665/AD5625 ............................................. 5
AC Characteristics ........................................................................ 7
I2C Timing Specifications ............................................................ 8
Absolute Maximum Ratings .......................................................... 10
ESD Caution ................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 22
Digital-to-Analog Converter (DAC) ....................................... 22
Resistor String ............................................................................. 22
Output Amplifier ........................................................................ 22
Internal Reference ...................................................................... 22
External Reference ..................................................................... 23
Serial Interface ............................................................................ 23
Write Operation.......................................................................... 23
Read Operation........................................................................... 23
High Speed Mode ....................................................................... 25
Input Shift Register .................................................................... 25
Multiple Byte Operation ............................................................ 25
Broadcast Mode .......................................................................... 27
LDAC Function .......................................................................... 27
Power-Down Modes .................................................................. 29
Power-On Reset and Software Reset ....................................... 30
Internal Reference Setup (R Versions) .................................... 30
Applications Information .............................................................. 31
Using a Reference as a Power Supply for the
AD56x5R/AD56x5 ..................................................................... 31
Bipolar Operation Using the AD56x5R/AD56x5 .................. 31
Power Supply Bypassing and Grounding ................................ 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 33
REVISION HISTORY
12/09—Rev. A to Rev. B
Changes to Features Section, General Description Section,
and Table 1 ......................................................................................... 1
Changes to Table 2 ............................................................................ 3
Changes to Internal Reference Section ........................................ 22
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 33
6/09—Rev. 0 to Rev. A
Changes to Features and General Description Sections .............. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Digital-to-Analog Converter (DAC) Section, Added
Figure 54 and Figure 55, Renumbered Subsequent Figures ..... 22
Changes to Ordering Guide .......................................................... 33
3/07—Revision 0: Initial Version
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 3 of 36
SPECIFICATIONS
SPECIFICATIONS—AD5665R/AD5645R/AD5625R
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1
STATIC PERFORMANCE2
AD5665R
Resolution 16 Bits
Relative Accuracy ±8 ±16 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5645R
Resolution 14 Bits
Relative Accuracy ±2 ±4 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
AD5625R
Resolution 12 12 Bits
Relative Accuracy ±1 ±4 ±0.5 ±1 LSB
Differential Nonlinearity ±1 ±0.25 LSB Guaranteed monotonic by design
Zero-Code Error 2 10 2 10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 ±1 ±10 mV
Full-Scale Error −0.1 ±0.5 −0.1 ±0.5 % FSR All 1s loaded to DAC register
Gain Error ±0.1 ±1.25 ±0.1 ±1 % FSR
Zero-Code Error Drift ±2 ±2 µV/°C
Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C
DC Power Supply Rejection
Ratio
−100 −100 dB DAC code = midscale; VDD = 5 V ± 10%
DC Crosstalk (External
Reference)
15 15 µV Due to full-scale output change,
RL = 2 kΩ to GND or VDD
10 10 µV/mA Due to load current change
8 8 µV Due to powering down (per channel)
DC Crosstalk (Internal
Reference)
25 25 µV Due to full-scale output change,
RL = 2 kΩ to GND or VDD
20 20 µV/mA Due to load current change
10 10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 VDD 0 VDD V Internal reference disabled
0
2 ×
VREF
2 ×
VREF
Internal reference enabled
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 30 30 mA VDD = 5 V
Power-Up Time 4 4 µs Coming out of power-down mode;
VDD = 5 V
REFERENCE INPUTS
Reference Current 210 260 210 260 µA VREF = VDD = 5.5 V
Reference Input Range 0.75 VDD 0.75 VDD V
Reference Input Impedance 26 26 kΩ
REFERENCE OUTPUT (1.25 V)
Output Voltage 1.247 1.253 1.247 1.253 V At ambient
Reference TC3
±10 ±10 ppm/°C
Output Impedance 7.5 7.5 kΩ
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 4 of 36
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1
REFERENCE OUTPUT (2.5 V) VDD = 4.5 V to 5.5 V
Output Voltage 2.495 2.505 2.495 2.505 V At ambient
Reference TC3 ±10 ±5 ±10 ppm/°C
Output Impedance 7.5 7.5 kΩ
LOGIC INPUTS (ADDRx, CLR,
LDAC, POR)3
IIN, Input Current ±1 ±1 μA
VINL, Input Low Voltage 0.15 × VDD 0.15 × VDD V
VINH, Input High Voltage 0.85 × VDD 0.85 × VDD V
CIN, Pin Capacitance 2 2 pF
VHYST, Input Hysteresis 0.1 × VDD 0.1 × VDD V
LOGIC INPUTS (SDA, SCL)3
IIN, Input Current ±1 ±1 μA
VINL, Input Low Voltage 0.3 × VDD 0.3 × VDD V
VINH, Input High Voltage 0.7 × VDD 0.7 × VDD V
CIN, Pin Capacitance 2 2 pF
VHYST, Input Hysteresis 0.1 × VDD 0.1 × VDD V High speed mode
0.05 × VDD 0.05 × VDD V Fast mode
LOGIC OUTPUTS (SDA)3
VOL, Output Low Voltage 0.4 0.4 V ISINK = 3 mA
0.6 0.6 V ISINK = 6 mA
Floating-State Leakage
Current
±1 ±1 μA
Floating-State Output
Capacitance
2 2 pF
POWER REQUIREMENTS
VDD 2.7 5.5 2.7 5.5 V
IDD (Normal Mode)4 V
IH = VDD, VIL = GND, full-scale loaded
VDD = 4.5 V to 5.5 V 1.0 1.16 1.0 1.16 mA Internal reference off
VDD = 2.7 V to 3.6 V 0.9 1.05 0.9 1.05 mA Internal reference off
VDD = 4.5 V to 5.5 V 1.9 2.14 1.9 2.14 mA Internal reference on
VDD = 2.7 V to 3.6 V 1.4 1.59 1.4 1.59 mA Internal reference on
IDD (All Power-Down Modes)5
VDD = 2.7 V to 5.5 V 0.48 1 0.48 1 μA VIH = VDD, VIL = GND (LFCSP)
VDD = 3.6 V to 5.5 V 0.48 1 0.48 1 μA VIH = VDD, VIL = GND (TSSOP)
1 Temperature range of A and B grades is −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5665R (Code 512 to Code 65,024), AD5645R (Code 128 to Code 16,256), AD5625R (Code 32 to Code 4064). Output
unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down. Power-down function is not available on 14-lead TSSOP parts when the part is powered with VDD < 3.6 V.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 5 of 36
SPECIFICATIONS—AD5665/AD5625
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Grade
Parameter Min Typ Max Unit Test Conditions/Comments1
STATIC PERFORMANCE2
AD5665
Resolution 16 Bits
Relative Accuracy ±8 ±16 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5625
Resolution 12 Bits
Relative Accuracy ±0.5 ±1 LSB
Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design
Zero-Code Error 2 10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 mV
Full-Scale Error −0.1 ±0.5 % FSR All 1s loaded to DAC register
Gain Error ±0.1 ±1 % FSR
Zero-Code Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 5 V ± 10%
DC Crosstalk (External Reference) 15 µV Due to full-scale output change,
RL = 2 kΩ to GND or VDD
10 µV/mA Due to load current change
8 µV Due to powering down (per channel)
DC Crosstalk (Internal Reference) 25 µV Due to full-scale output change,
RL = 2 kΩ to GND or VDD
20 µV/mA Due to load current change
10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 VDD V
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
DC Output Impedance 0.5 Ω
Short-Circuit Current 30 mA VDD = 5 V
Power-Up Time 4 µs Coming out of power-down mode; VDD = 5 V
REFERENCE INPUTS
Reference Current 210 260 µA VREF = VDD = 5.5 V
Reference Input Range 0.75 VDD V
Reference Input Impedance 26 kΩ
LOGIC INPUTS (ADDRx, CLR, LDAC, POR)3
IIN, Input Current ±1 µA
VINL, Input Low Voltage 0.15 × VDD V
VINH, Input High Voltage 0.85 × VDD V
CIN, Pin Capacitance 2 pF
VHYST, Input Hysteresis 0.1 × VDD V
LOGIC INPUTS (SDA, SCL)3
IIN, Input Current ±1 µA
VINL, Input Low Voltage 0.3 × VDD V
VINH, Input High Voltage 0.7 × VDD V
CIN, Pin Capacitance 2 pF
VHYST, Input Hysteresis 0.1 × VDD V High speed mode
0.05 × VDD V Fast mode
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 6 of 36
B Grade
Parameter Min Typ Max Unit Test Conditions/Comments1
LOGIC OUTPUTS (SDA)3
VOL, Output Low Voltage 0.4 V ISINK = 3 mA
0.6 V ISINK = 6 mA
Floating-State Leakage Current ±1 µA
Floating-State Output Capacitance 2 pF
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD (Normal Mode)4 V
IH = VDD, VIL = GND, full-scale loaded
VDD = 4.5 V to 5.5 V 1.0 1.16 mA
VDD = 2.7 V to 3.6 V 0.9 1.05 mA
IDD (All Power-Down Modes)5
VDD = 2.7 V to 5.5 V 0.48 1 µA VIH = VDD, VIL = GND (LFCSP)
VDD = 3.6 V to 5.5 V 0.48 1 µA VIH = VDD, VIL = GND (TSSOP)
1 Temperature range of B grade is −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5665 (Code 512 to Code 65,024), AD5625 (Code 32 to Code 4064). Output unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down. Power-down function is not available on 14-lead TSSOP parts when the part is powered with VDD < 3.6 V.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 7 of 36
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1,2 Min Typ Max Unit Test Conditions/Comments3
Output Voltage Settling Time
AD5625R/AD5625 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5645R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5665R/AD5665 4 7 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 1.8 V/µs
Digital-to-Analog Glitch Impulse 1 LSB change around major carry
15 nV-s LFCSP
5 nV-s TSSOP
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dB VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
Digital Crosstalk 0.1 nV-s
Analog Crosstalk 1 nV-s External reference
4 nV-s Internal reference
DAC-to-DAC Crosstalk 1 nV-s External reference
4 nV-s Internal reference
Multiplying Bandwidth 340 kHz VREF = 2 V ± 0.1 V p-p
Total Harmonic Distortion −80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz
100 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 15 µV p-p 0.1 Hz to 10 Hz
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical @ 25°C.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 8 of 36
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1
Table 5.
Parameter Test Conditions2Min Max Unit Description
fSCL3Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
High speed mode, CB = 100 pF 3.4 MHz
High speed mode, CB = 400 pF 1.7 MHz
t1 Standard mode 4 s tHIGH, SCL high time
Fast mode 0.6 s
High speed mode, CB = 100 pF 60 ns
High speed mode, CB = 400 pF 120 ns
t2 Standard mode 4.7 s tLOW, SCL low time
Fast mode 1.3 s
High speed mode, CB = 100 pF 160 ns
High speed mode, CB = 400 pF 320 ns
t3 Standard mode 250 ns tSU;DAT, data setup time
Fast mode 100 ns
High speed mode 10 ns
t4 Standard mode 0 3.45 s tHD;DAT, data hold time
Fast mode 0 0.9 s
High speed mode, CB = 100 pF 0 70 ns
High speed mode, CB = 400 pF 0 150 ns
t5 Standard mode 4.7 s tSU;STA, setup time for a repeated start condition
Fast mode 0.6 s
High speed mode 160 ns
t6 Standard mode 4 s tHD;STA, hold time (repeated) start condition
Fast mode 0.6 s
High speed mode 160 ns
t7 Standard mode 4.7 s tBUF, bus-free time between a stop and a start
condition
Fast mode 1.3 s
t8 Standard mode 4 s tSU;STO, setup time for a stop condition
Fast mode 0.6 s
High speed mode 160 ns
t9 Standard mode 1000 ns tRDA, rise time of SDA signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
t10 Standard mode 300 ns tFDA, fall time of SDA signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
t11 Standard mode 1000 ns tRCL, rise time of SCL signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 40 ns
High speed mode, CB = 400 pF 20 80 ns
t11A Standard mode 1000 ns
tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 9 of 36
Parameter Test Conditions2Min Max Unit Description
t12 Standard mode 300 ns tFCL, fall time of SCL signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 40 ns
High speed mode, CB = 400 pF 20 80 ns
t13 Standard mode 10 ns
LDAC pulse width low
Fast mode 10 ns
High speed mode 10 ns
t14 Standard mode 300 ns
Falling edge of ninth SCL clock pulse of last byte
of a valid write to LDAC falling edge
Fast mode 300 ns
High speed mode 30 ns
t15 Standard mode 20 ns
CLR pulse width low
Fast mode 20 ns
High speed mode 20 ns
tSP4Fast mode 0 50 ns Pulse width of spike suppressed
High speed mode 0 10 ns
1 See Figure 3. High speed mode timing specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7.
2 CB refers to the capacitance on the bus line.
3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
4 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.
SCL
SDA
PS S P
t8
t6
t5
t3t10 t9
t4
t6t1
t2
t11 t12
t14
CLR
t13
t15
LDAC*
t7
*ASYNCHRONOUS LDAC UPDATE MODE.
06341-003
Figure 3. 2-Wire Serial Interface Timing Diagram
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 10 of 36
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to GND −0.3 V to +7 V
VOUT to GND −0.3 V to VDD + 0.3 V
VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range, Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ maximum) 150°C
Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance
LFCSP_WD (4-Layer Board) 61°C/W
TSSOP 150.4°C/W
Reflow Soldering Peak Temperature,
RoHS Compliant
260°C ± 5°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 11 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
LDAC
14
SCL
2
ADDR1
13
SDA
3
V
DD 12
GND
4
V
OUT
A
11
V
OUT
B
5
V
OUT
C
10
V
OUT
D
6
POR
9
CLR
7
V
REFIN
/V
REFOUT 8
ADDR2
AD5625R/
AD5645R/
AD5665R
TOP VIEW
(Not to Scale)
06341-120
Figure 4. Pin Configuration (14-Lead TSSOP), R Suffix Version
1
LDAC
14
SCL
2
ADDR1
13
SDA
3
V
DD 12
GND
4
V
OUT
A
11
V
OUT
B
5
V
OUT
C
10
V
OUT
D
6
POR
9
CLR
7
V
REFIN 8
ADDR2
AD5625/
AD5665
TOP VIEW
(Not to Scale)
0
6341-121
Figure 5. Pin Configuration (14-Lead TSSOP)
1
V
OUT
A
10
V
REFIN
/V
REFOUT
2
V
OUT
B
9
V
DD
3
GND
8
SDA
4
V
OUT
C
7
SCL
5
V
OUT
D
6
ADDR
AD5625R/
AD5645R/
AD5665R
TOP VIEW
(Not to Scale)
EXPOSED PAD TIED TO GND.
06341-122
Figure 6. Pin Configuration (10-Lead LFCSP), R Suffix Version
1
V
OUT
A
10
V
REFIN
2
V
OUT
B
9
V
DD
3
GND
8
SDA
4
V
OUT
C
7
SCL
5
V
OUT
D
6
ADDR
AD5625/
AD5665
TOP VIEW
(Not to Scale)
EXPOSED PAD TIED TO GND.
06341-123
Figure 7. Pin Configuration (10-Lead LFCSP)
Table 7. Pin Function Descriptions
Pin Number
14-Lead 10-Lead Mnemonic Description
1 N/A LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently
low.
2 N/A ADDR1 Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address
(see Table 9).
3 9 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND.
4 1 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5 4 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
6 N/A POR Power-On Reset Pin. Tying the POR pin to GND powers up the part to 0 V. Tying the POR pin to VDD
powers up the part to midscale.
7 10 VREFIN/VREFOUT The AD56x5R have a common pin for reference input and reference output. When using the internal
reference, this is the reference output pin. When using an external reference, this is the reference
input pin. The default for this pin is as a reference input. (The internal reference and reference output
are only available on R suffix versions.) The AD56x5 has a reference input pin only.
8 N/A ADDR2 Three-State Address Input. Sets Bit A3 and Bit A2 of the 7-bit slave address (see Table 9).
9 N/A CLR Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses
are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the
output to 0 V. The part exits clear code mode on the falling edge of the ninth clock pulse of the last
byte of the valid write. If CLR is activated during a write sequence, the write is aborted. If CLR is
activated during high speed mode, the part exits high speed mode.
10 5 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
11 2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
12 3 GND Ground Reference Point for All Circuitry on the Part.
13 8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit
input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an
external pull-up resistor.
14 7 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit
input register.
N/A 6 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address
(see Table 8).
EPAD For the 10-lead LFCSP, the exposed pad must be tied to GND.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 12 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL ERROR (LSB)
10
4
6
8
0
2
–6
–10
–8
–2
–4
0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
V
DD
= V
REF
= 5V
T
A
= 25°C
06341-005
Figure 8. INL, AD5665, External Reference
CODE
INL ERROR (LSB)
4
–4
0 2500 5000 7500 10000 12500 15000
–3
–2
–1
0
1
2
3
V
DD
= V
REF
= 5V
T
A
= 25°C
06341-006
Figure 9. INL, AD5645R, External Reference
CODE
INL ERROR (LSB)
1.0
–1.0
0 500 1000 1500 2000 2500 3000 3500 4000
–0.8
–0.6
–0.4
0
0.4
0.2
–0.2
0.6
0.8
V
DD
= V
REF
= 5V
T
A
= 25°C
06341-100
Figure 10. INL, AD5625, External Reference
CODE
DNL ERROR (LSB)
1.0
0.6
0.4
0.2
0.8
0
–0.4
–0.2
–0.6
–1.0
–0.8
0 10k 20k 30k 40k 50k 60k
V
DD
= V
REF
= 5V
T
A
= 25°C
0
6341-007
Figure 11. DNL, AD5665, External Reference
DNL ERROR (LSB)
0.5
0.3
0.2
0.1
0.4
0
–0.2
–0.1
–0.3
–0.5
–0.4
V
DD
= V
REF
= 5V
T
A
= 25°C
CODE
02500 5000 7500 10000 12500 15000
0
6341-008
Figure 12. DNL, AD5645R, External Reference
DNL ERROR (LSB)
0.20
0.10
0.05
0.15
0
–0.05
–0.10
–0.20
–0.15
CODE
0500 1000 1500 2000 2500 3000 3500 4000
V
DD
= V
REF
= 5V
T
A
= 25°C
0
6341-009
Figure 13. DNL, AD5625, External Reference
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 13 of 36
CODE
INL ERROR (LSB)
10
8
0
–10
–6
–8
–4
6
–2
4
2
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
06341-010
Figure 14. INL, AD5665R, 2.5 V Internal Reference
CODE
INL ERROR (LSB)
4
3
–4
–3
–2
2
–1
1
0
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
V
DD
=5V
V
REFOUT
=2.5V
T
A
= 25°C
06341-011
Figure 15. INL, AD5645R, 2.5 V Internal Reference
CODE
INL ERROR (LSB)
1.0
0.8
0
–1.0
–0.8
–0.6
0.6
–0.4
–0.2
0.4
0.2
0 1000500 20001500 350030002500 4000
V
DD
=5V
V
REFOUT
=2.5V
T
A
=25°C
06341-012
Figure 16. INL, AD5625R, 2.5 V Internal Reference
CODE
DNL ERROR (LSB)
1.0
0.8
0
–1.0
–0.6
–0.8
–0.4
0.6
–0.2
0.4
0.2
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
=5V
V
REFOUT
=2.5V
T
A
=25°C
06341-013
Figure 17. DNL, AD5665R, 2.5 V Internal Reference
CODE
DNL ERROR (LSB)
0.5
0.4
0
–0.5
–0.3
–0.4
–0.2
0.3
–0.1
0.2
0.1
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
0
6341-014
Figure 18. DNL, AD5645R, 2.5 V Internal Reference
CODE
DNL ERROR (LSB)
0.20
0.15
0
–0.20
–0.15
–0.10
0.10
–0.05
0.05
01000500 20001500 350030002500 4000
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
0
6341-015
Figure 19. DNL, AD5625R, 2.5 V Internal Reference
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 14 of 36
CODE
INL ERROR (LSB)
10
8
4
6
2
0
–4
–2
–6
–8
–10
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06341-016
Figure 20. INL, AD5665R,1.25 V Internal Reference
CODE
INL ERROR (LSB)
4
–4
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
3
2
1
0
–1
–2
–3
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06341-017
Figure 21. INL, AD5645R, 1.25 V Internal Reference
CODE
INL ERROR (LSB)
1.0
–1.0
0 500 1000 1500 2000 2500 3000 3500 4000
0
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06341-018
Figure 22. INL, AD5625R,1.25 V Internal Reference
CODE
DNL ERROR (LSB)
1.0
0.8
0.4
0.6
0.2
0
–0.4
–0.2
–0.6
–0.8
–1.0
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
06341-019
Figure 23. DNL, AD5665R,1.25 V Internal Reference
CODE
DNL ERROR (LSB)
0.5
–0.5
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
0
0.4
0.3
0.2
0.1
–0.1
–0.2
–0.3
–0.4
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
06341-020
Figure 24. DNL, AD5645R,1.25 V Internal Reference
CODE
DNL ERROR (LSB)
0.20
–0.20
0 500 1000 1500 2000 2500 3000 3500 4000
0
0.15
0.10
0.05
–0.05
–0.10
–0.15
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
06341-021
Figure 25. DNL, AD5625R, 1.25 V Internal Reference
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 15 of 36
TEMPERATURE (°C)
ERROR (LSB)
8
6
4
2
–6
–4
–2
0
–8
–40 –20 40200 1008060
MIN DNL
MAX DNL
MAX INL
MIN INL
VDD = VREF = 5V
06341-022
Figure 26. INL Error and DNL Error vs. Temperature
V
REF
(V)
ERROR (LSB)
10
4
6
8
2
0
–8
–6
–4
–2
–10
0.75 1.25 1.75 2.25 4.253.753.252.75 4.75
MIN DNL
MAX DNL
MAX INL
MIN INL
V
DD
= 5V
T
A
= 25°C
06341-023
Figure 27. INL Error and DNL Error vs. VREF
V
DD
(V)
ERROR (LSB)
8
6
4
2
–6
–4
–2
0
–8
2.7 3.2 3.7 4.74.2 5.2
MIN DNL
MAX DNL
MAX INL
MIN INL
T
A
= 25°C
06341-024
Figure 28. INL Error and DNL Error vs. Supply
TEMPERATURE (°C)
ERROR (% FSR)
0
–0.04
–0.02
–0.06
–0.08
–0.10
–0.18
–0.16
–0.14
–0.12
–0.20
–40 –20 40200 1008060
V
DD
= 5V
GAIN ERROR
FULL-SCALE ERROR
06341-025
Figure 29. Gain Error and Full-Scale Error vs. Temperature
TEMPERATURE (°C)
ERROR (mV)
1.5
1.0
0.5
0
–2.0
–1.5
–1.0
–0.5
–2.5
–40 –20 40200860 1000
OFFSET ERROR
ZERO-SCALE ERROR
06341-026
Figure 30. Zero-Scale Error and Offset Error vs. Temperature
V
DD
(V)
ERROR (% FSR)
1.0
–1.5
–1.0
–0.5
0
0.5
–2.0
2.7 3.2 3.7 4.74.2 5.2
GAIN ERROR
FULL-SCALE ERROR
06341-027
Figure 31. Gain Error and Full-Scale Error vs. Supply
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 16 of 36
V
DD
(V)
ERROR (mV)
1.0
0.5
0
–2.0
–1.5
–1.0
–0.5
–2.5
2.7 3.2 4.23.7 5.24.7
ZERO-SCALE ERROR
OFFSET ERROR
T
A
= 25°C
06341-028
Figure 32. Zero-Scale Error and Offset Error vs. Supply
I
DD
(mA)
NUMBER OF DEVICES
0
30
25
20
15
10
5
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
V
DD
= 3.6V
V
DD
= 5.5V
06341-029
Figure 33. IDD Histogram with External Reference
I
DD
(mA)
NUMBER OF DEVICES
0
25
20
15
10
5
1.35
1.37
1.39
1.41
1.43
1.45
1.47
1.49
1.51
1.53
1.55
1.57
1.59
1.61
1.63
1.65
1.67
1.69
1.71
1.73
1.75
1.77
1.79
1.81
1.83
1.85
1.87
1.89
1.91
1.93
1.99
1.95
1.97
V
DD
= 3.6V
V
DD
= 5.5V
06341-030
V
REFOUT
= 1.25V V
REFOUT
= 2.5V
Figure 34. IDD Histogram with Internal Reference
CODE
I
DD
(mA)
0
2.0
1.6
1.8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
512 10512 20512 30512 40512 50512 60512
T
A
= 25°C
V
DD
= 5.5V
V
REFOUT
= 2.5V
V
REFIN
= 5V
0
6341-060
Figure 35. Supply Current vs. DAC Code
V
DD
(V)
I
DD
(mA)
0
0.2
0.4
0.8
0.6
1.0
1.2
3.22.7 3.74.24.75.2
T
A
= 25°C
0
6341-061
Figure 36. Supply Current vs. Supply
TEMPERATURE (°C)
I
DD
(mA)
1.2
0.2
0.4
1.0
0.6
0.8
0
–40–200 20406080100
06341-063
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 3V
Figure 37. Supply Current vs. Temperature
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 17 of 36
CURRENT (mA)
ERROR VOLTAGE (V)
0.5
0.4
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
–10 –8 –6 –4 –2 0 2 4 8610
V
DD
= 3V
V
REFOUT
= 1.25V
V
DD
= 5V
V
REFOUT
= 2.5V
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
0
6341-031
Figure 38. Headroom at Rails vs. Source and Sink
CURRENT (mA)
V
OUT
(V)
6
5
4
3
2
1
–1
0
–30 –20 –10 0 10 20 30
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
ZERO SCALE
FULL SCALE
MIDSCALE
1/4 SCALE
3/4 SCALE
0
6341-046
Figure 39. AD56x5R with 2.5 V Reference, Source and Sink Capability
CURRENT (mA)
V
OUT
(V)
4
–1
0
1
2
3
–30 –20 –10 0 10 20 30
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
ZERO SCALE
FULL SCALE
MIDSCALE
1/4 SCALE
3/4 SCALE
0
6341-047
Figure 40. AD56x5R with 1.25 V Reference, Source and Sink Capability
TIME BASE = 4µs/DIV
V
DD
= V
REF
= 5V
T
A
= 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
V
OUT
= 909mV/DIV
1
06341-048
Figure 41. Full-Scale Settling Time, 5 V
CH1 2.0V CH2 500mV M100µs 125MS/s
A CH1 1.28V
8.0ns/pt
V
DD
= V
REF
= 5V
T
A
= 25°C
V
OUT
V
DD
1
2
MAX(C2)
420.0mV
06341-049
Figure 42. Power-On Reset to 0 V
VDD = 5V
SYNC
SLCK
VOUT
1
3
CH1 5.0V
CH3 5.0V
CH2 500mV M400ns A CH1 1.4V
2
0
6341-050
Figure 43. Exiting Power-Down to Midscale
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 18 of 36
SAMPLE NUMBER
V
OUT
(V)
2.521
2.522
2.523
2.524
2.525
2.526
2.527
2.528
2.529
2.530
2.531
2.532
2.533
2.534
2.535
2.536
2.537
2.538
0 50 100 150 350 400200 250 300 450 512
V
DD
= V
REF
= 5V
T
A
= 25°C
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
0
6341-058
Figure 44. Digital-to-Analog Glitch Impulse (Negative)
SAMPLE NUMBER
V
OUT
(V)
2.491
2.492
2.493
2.494
2.495
2.496
2.497
2.498
0 50 100 150 350 400200 250 300 450 512
V
DD
= V
REF
= 5V
T
A
= 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
0
6341-059
Figure 45. Analog Crosstalk, External Reference
SAMPLE NUMBER
V
OUT
(V)
2.456
2.458
2.460
2.462
2.464
2.466
2.468
2.470
2.472
2.474
2.476
2.478
2.480
2.482
2.484
2.486
2.488
2.490
2.492
2.494
2.496
0 50 100 150 350 400200 250 300 450 512
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 4.462nV
0
6341-062
Figure 46. Analog Crosstalk, Internal Reference
1
V
DD
= V
REF
= 5V
T
A
= 25°C
DAC LOADED WITH MIDSCALE
4s/DIV
2µV/DI
V
06341-051
Figure 47. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
5s/DIV
10µV/DI
V
1
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
DAC LOADED WITH MIDSCALE
06341-052
Figure 48. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
4s/DIV
5µV/DI
V
1
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
DAC LOADED WITH MIDSCALE
06341-053
Figure 49. 0.1 Hz to 10 Hz Output Noise Plot, 1.25 V Internal Reference
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 19 of 36
CAPACITANCE (nF)
TIME (µs)
16
14
12
10
8
6
4
012 34567 981
FREQUENCY (Hz)
OUTPUT NOISE (nV/√Hz)
800
0
100
200
300
400
500
600
700
100 10k1k 100k 1M
V
DD
= 3V
V
REFOUT
= 1.25V
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
MIDSCALE LOADED
0
6341-054
Figure 50. Noise Spectral Density, Internal Reference
FREQUENCY (Hz)
THD (dB)
–
20
–50
–80
–30
–40
–60
–70
–90
–100
2k 4k 6k 8k 10k
V
DD
= 5V
T
A
= 25°C
DAC LOADED WITH FULL SCALE
V
REF
= 2V ± 0.3V p-p
0
6341-055
0
V
REF
= V
DD
T
A
= 25°C
V
DD =
5V
V
DD =
3V
0
6341-056
Figure 52. Settling Time vs. Capacitive Load
FREQUENCY (Hz)
BANDWIDTH (dB)
5
–40
10k 100k 1M 10M
–35
–30
–25
–20
–15
–10
–5
0
V
DD
= 5V
T
A
= 25°C
06341-057
Figure 51. Total Harmonic Distortion Figure 53. Multiplying Bandwidth
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 20 of 36
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC
transfer function.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic
by design.
Zero-Code Error
Zero-code error is a measurement of the output error when zero
scale (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5665R because the output of the DAC cannot go below 0 V
due to a combination of the offset errors in the DAC and the out-
put amplifier. Zero-code error is expressed in millivolts (mV).
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed as a
percentage of full-scale range (FSR).
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed as a percentage of full-scale range (FSR).
Zero-Code Error Drift
Zero-code error drift is a measurement of the change in
zero-code error with a change in temperature. It is expressed in
microvolts per degrees Celsius (µV/°C).
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in parts
per million (ppm) of full-scale range per degrees Celsius
(FSR/°C).
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5665R
with Code 512 loaded in the DAC register. It can be negative or
positive.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to the change in VDD for full-scale output of the DAC. It is
measured in decibels (dB). VREF is held at 2 V, and VDD is varied
by ±10%.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change, and it is measured from the rising edge
of the stop condition.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 44).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC
but is measured when the DAC output is not updated. It is
specified in nV-s and is measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in decibels (dB).
Output Noise Spectral Density
Output noise spectral density is a measurement of the internally
generated random noise, which is characterized as a spectral
density (nanovolts per square root of hertz frequency (nV/√Hz)).
It is measured by loading the DAC to midscale and measuring
noise at the output. It is measured in nanovolts per square root
of hertz frequency (nV/√Hz). A plot of noise spectral density is
shown in Figure 50.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC
in response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC
kept at midscale. It is expressed in microvolts (V).
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has on
another DAC kept at midscale. It is expressed in microvolts per
milliampere (V/mA).
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nanovolts per
second (nV-s).
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 21 of 36
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa) and then executing
a software LDAC and monitoring the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nanovolts per second (nV-s).
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
to all 1s and vice versa) with LDAC low while monitoring the
output of the victim channel that is at midscale. The energy of
the glitch is expressed in nanovolts per second (nV-s).
Multiplying Bandwidth
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in
decibels (dB).
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 22 of 36
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
The AD56x5R/AD56x5 DACs are fabricated on a CMOS
process. The AD56x5 does not have an internal reference, and
the DAC architecture is shown in Figure 54. The AD56x5R does
have an internal reference and can be configured for use with
either an internal or external reference (see Figure 54 and
Figure 55).
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
⎟
⎠
⎞
⎜
⎝
⎛
×= N
REFIN
OUT
D
VV 2
REF
BUFFER
OUTPUT
AMPLIFIER
GAIN = ×2
DAC
REGISTER
V
REFIN
/V
REFOUT
V
OUT
06341-034
GND
REF (+)
REF (–)
RESISTOR
STRING
Figure 54. Internal Configuration When Using an External Reference
The ideal output voltage when using the internal reference is
given by
⎟
⎠
⎞
⎜
⎝
⎛
××= N
REFOUTOUT
D
VV 2
2
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register, as follows:
0 to 4095 for AD5625R/AD5625 (12-bit).
0 to 16,383 for AD5645R (14-bit).
0 to 65,535 for AD5665R/AD5665 (16-bit).
N is the DAC resolution.
OUTPUT
AMPLIFIER
GAIN = ×2
DAC
REGISTER
REF (+)
V
REFIN
/V
REFOUT
V
OUT
REF (–)
RESISTOR
STRING
GND
06341-035
1.25V INTERNAL
REFERENCE
1
1
CAN BE OVERDRIVEN
BY V
REFIN
/V
REFOUT
.
Figure 55. Internal Configuration When Using the Internal Reference
RESISTOR STRING
The resistor string is shown in Figure 56. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on its
output, which gives an output range of 0 V to VDD. It can drive a
load of 2 k in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier are shown in Figure 38
and Figure 39. The slew rate is 1.8 V/µs with a ¼ to ¾ full-scale
settling time of 7 µs.
R
R
R
R
RTO OUTPUT
AMPLIFIER
06341-033
Figure 56. Resistor String
INTERNAL REFERENCE
The AD5625R/AD5645R/AD5665R feature an on-chip reference.
Versions without the R suffix require an external reference. The
on-chip reference is off at power-up and is enabled via a write to a
control register. See the Internal Reference Setup section for details.
Versions packaged in a 10-lead LFCSP have a 1.25 V reference
or a 2.5 V reference, giving a full-scale output of 2.5 V or 5 V,
depending on the model selected (see the Ordering Guide). These
parts can be operated with a VDD supply of 2.7 V to 5.5 V. Versions
packaged in a 14-lead TSSOP have a 2.5 V reference, giving a
full-scale output of 5 V. Parts are functional with a VDD supply
of 2.7 V to 5.5 V, but, with a VDD supply of less than 5 V, the
output is clamped to VDD. See the Ordering Guide for a full list
of models. The internal reference associated with each part is
available at the VREFOUT pin (available on R suffix versions only).
A buffer is required if the reference output is used to drive
external loads. When using the internal reference, it is recom-
mended that a 100 nF capacitor be placed between the reference
output and GND for reference stability.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 23 of 36
EXTERNAL REFERENCE
The VREFIN pin on the AD56x5R allows the use of an external
reference if the application requires it. The default condition of
the on-chip reference is off at power-up. All devices can be
operated from a single 2.7 V to 5.5 V supply.
SERIAL INTERFACE
The AD56x5R/AD56x5 have 2-wire I2C-compatible serial inter-
faces. The AD56x5R/AD56x5 can be connected to an I2C bus as
a slave device, under the control of a master device. See Figure 3
for a timing diagram of a typical write sequence.
The AD56x5R/AD56x5 support standard (100 kHz), fast
(400 kHz), and high speed (3.4 MHz) data transfer modes.
High speed operation is only available on selected models. See
the Ordering Guide for a full list of models. Support is not
provided for 10-bit addressing and general call addressing.
The AD56x5R/AD56x5 each has a 7-bit slave address. The
10-lead versions of the part have a slave address whose five
MSBs are 00011, and the two LSBs are set by the state of the
ADDR address pin, which determines the state of the A0 and
A1 address bits. The 14-lead versions of the part have a slave
address whose three MSBs are 001, and the four LSBs are set by
the ADDR1 and ADDR2 address pins, which determine the
state of the A0 and A1 and A2 and A3 address bits, respectively.
The facility to make hardwired changes to the ADDR pin allows
the user to incorporate up to three of these devices on one bus,
as outlined in Table 8.
Table 8. ADDR Pin Settings (10-Lead Package)
ADDR Pin Connection A1 A0
VDD 0 0
NC 1 0
GND 1 1
The facility to make hardwired changes to the ADDR1 and the
ADDR2 pins allows the user to incorporate up to nine of these
devices on one bus, as outlined in Table 9.
Table 9. ADDR1, ADDR2 Pin Settings (14-Pin Package)
ADDR2 Pin
Connection
ADDR1 Pin
Connection A3 A2 A1 A0
VDD V
DD 0 0 0 0
VDD NC 0 0 1 0
VDD GND 0 0 1 1
NC VDD 1 0 0 0
NC NC 1 0 1 0
NC GND 1 0 1 1
GND VDD 1 1 0 0
GND NC 1 1 1 0
GND GND 1 1 1 1
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the ninth clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to or read from its shift register.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
3. When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA line
remains high). The master brings the SDA line low before
the 10th clock pulse, and then high during the 10th clock
pulse to establish a stop condition.
WRITE OPERATION
When writing to the AD56x5R/AD56x5, the user must begin
with a start command followed by an address byte (R/W = 0),
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The AD5665 requires two bytes of
data for the DAC and a command byte that controls various
DAC functions. Three bytes of data must, therefore, be written
to the DAC, the command byte followed by the most significant
data byte and the least significant data byte, as shown in
and . After these data bytes are acknowledged by the
AD56x5R/AD56x5, a stop condition follows.
Figure 57
Figure 58
READ OPERATION
When reading data back from the AD56x5R/AD56x5, the
user begins with a start command followed by an address byte
(R/W = 1), after which the DAC acknowledges that it is prepared
to transmit data by pulling SDA low. Two bytes of data are then
read from the DAC, which are both acknowledged by the master
as shown in and . A stop condition follows. Figure 59 Figure 60
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 24 of 36
FRAME 2
COMMAND BYTE
FRAME 1
SLAVE ADDRESS
19 91
SCL
START BY
MASTER
ACK. BY
AD56x5
ACK. BY
AD56x5
SDA R/W DB23A0A11000 1 DB22 DB21 DB20 DB19 DB18 DB17 DB16
191
ACK. BY
AD56x5
ACK. BY
AD56x5
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
FRAME 3
MOST SIGNIFICANT
DATA BYTE
9
STOP BY
MASTER
SCL
(
CONTINUED)
SDA
(CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
6341-103
Figure 57. I2C Write Operation (10-Lead Package)
FRAME 2
COMMAND BYTE
FRAME 1
SLAVE ADDRESS
19 91
SCL
START BY
MASTER
ACK. BY
AD56x5
ACK. BY
AD56x5
SDA R/W DB23A0A1A2100 A3 DB22 DB21 DB20 DB19 DB18 DB17 DB16
191
ACK. BY
AD56x5
ACK. BY
AD56x5
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
FRAME 3
MOST SIGNIFICANT
DATA BYTE
9
STOP BY
MASTER
SCL
(
CONTINUED)
SDA
(CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
6341-104
Figure 58. I2C Write Operation (14-Lead Package)
FRAME 2
COMMAND BYTE
FRAME 1
SLAVE ADDRESS
19 91
SCL
START BY
MASTER
ACK. BY
AD56x5
ACK. BY
MASTER
SDA R/W DB23A0A11000 1 DB22 DB21 DB20 DB19 DB18 DB17 DB16
191
ACK. BY
MASTER
NO ACK.
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
FRAME 3
MOST SIGNIFICANT
DATA BYTE
9
STOP BY
MASTER
SCL
(
CONTINUED)
SDA
(CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
6341-101
Figure 59. I2C Read Operation (10-Lead Package)
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 25 of 36
FRAME 2
COMMAND BYTE
FRAME 1
SLAVE ADDRESS
19 91
SCL
START BY
MASTER
ACK. BY
AD56x5
ACK. BY
MASTER
SDA R/W DB23A0A1A2100 A3 DB22 DB21 DB20 DB19 DB18 DB17 DB16
191
ACK. BY
MASTER
NO ACK.
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
FRAME 3
MOST SIGNIFICANT
DATA BYTE
9
STOP BY
MASTER
SCL
(
CONTINUED)
SDA
(CONTINUED) DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0
6341-102
Figure 60. I2C Read Operation (14-Lead Package)
0
6341-105
SCL
00001XXX 001A3A2A1A0R/W
SDA
1919
NO ACK. SR
START BY
MASTER
ACK. BY
AD56x5
HS-MODE
MASTER CODE SERIAL BUS
ADDRESS BYTE
FAST MODE HIGH-SPEED MODE
Figure 61. Placing the AD56x5RBRUZ-2/AD56x5RBRUZ-2REEL7 in High Speed Mode
HIGH SPEED MODE INPUT SHIFT REGISTER
Some models offer high speed serial communication with a
clock frequency of 3.4 MHz. See the Ordering Guide for a full
list of models.
The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock
input, SCL. The timing diagram for this operation is shown in
Figure 3. The eight MSBs make up the command byte. DB23
is reserved and should always be set to 0 when writing to the
device. DB22 (S) is used to select multiple byte operation.
The next three bits are the command bits (C2, C1, and C0)
that control the mode of operation of the device. See Table 10
for details. The last three bits of the first byte are the address bits
(A2, A1, and A0). See Table 11 for details. The rest of the bits
are the 16-/14-/12-bit data-word. The data-word comprises the
16-/14-/12-bit input code followed by two or four don’t care bits
for the AD5645R and the AD5625R/AD5625, respectively (see
Figure 64 through Figure 66).
High speed mode communication commences after the master
addresses all devices connected to the bus with the Master Code
00001XXX to indicate that a high speed mode transfer is to
begin. No device connected to the bus is permitted to acknowl-
edge the high speed master code; therefore, the code is followed
by a no acknowledge. Next, the master must issue a repeated
start followed by the device address. The selected device then
acknowledges its address. All devices continue to operate in
high speed mode until the master issues a stop condition. When
the stop condition is issued, the devices return to standard/fast
mode. The part also returns to standard/fast mode when CLR is
activated while the part is in high speed mode. MULTIPLE BYTE OPERATION
Multiple byte operation is supported on the AD56x5R/AD56x5.
A 2-byte operation is useful for applications that require fast
DAC updating and do not need to change the command byte.
The S bit (DB22) in the command register can be set to 1 for
2-byte mode of operation (see Figure 63). For standard 3-byte
and 4-byte operation, the S bit (DB22) in the command byte
should be set to 0 (see Figure 62).
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 26 of 36
SLAVE
ADDRESS
COMMAND
BYTE
MOST SIGNIFICANT
DATA BYTE
COMMAND
BYTE
LEAST SIGNIFICANT
DATA BYTE
MOST SIGNIFICANT
DATA BYTE
LEAST SIGNIFICANT
DATA BYTE
S = 0
BLOCK 1
S = 0
BLOCK 2
MOST SIGNIFICANT
DATA BYTE
COMMAND
BYTE
LEAST SIGNIFICANT
DATA BYTE STOP
S = 0
BLOCK n
06341-107
Figure 62. Multiple Block Write with Command Byte in Each Block (S = 0)
SLAVE
ADDRESS
COMMAND
BYTE
MOST SIGNIFICANT
DATA BYTE
MOST SIGNIFICANT
DATA BYTE
LEAST SIGNIFICANT
DATA BYTE
LEAST SIGNIFICANT
DATA BYTE
S = 1
BLOCK 1
S = 1
BLOCK 2
MOST SIGNIFICANT
DATA BYTE
LEAST SIGNIFICANT
DATA BYTE STOP
S = 1
BLOCK n
06341-106
Figure 63. Multiple Block Write with Initial Command Byte Only (S = 1)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R S
RESERVED
BYTE
SELECTION
C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
COMMAND DAC ADDRESS DAC DATA DAC DATA
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE
06341-108
Figure 64. AD5665R/AD5665 Input Shift Register (16-Bit DAC)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R S
RESERVED
BYTE
SELECTION
C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
COMMAND DAC ADDRESS DAC DATA DAC DATA
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE
0
6341-109
Figure 65. AD5645R Input Shift Register (14-Bit DAC)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
R S
RESERVED
BYTE
SELECTION
C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
COMMAND DAC ADDRESS DAC DATA DAC DATA
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE
06341-110
Figure 66. AD5625R/AD5625 Input Shift Register (12-Bit DAC)
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 27 of 36
BROADCAST MODE
Broadcast addressing is supported on the AD56x5R/AD56x5
in write mode only. Broadcast addressing can be used to synchro-
nously update or power down multiple AD56x5R/AD56x5
devices. When the broadcast address is used, the AD56x5R/
AD56x5 responds regardless of the states of the address pins.
The AD56x5R/AD56x5 broadcast address is 00010000.
Table 10. Command Definition
C2 C1 C0 Command
0 0 0 Write to input Register n
0 0 1 Update DAC Register n
0 1 0 Write to input Register n, update all
(software LDAC)
0 1 1 Write to and update DAC Channel n
1 0 0 Power up/power down
1 0 1 Reset
1 1 0 LDAC register setup
1 1 1 Internal reference setup (on/off )
Table 11. DAC Address Command
A2 A1 A0 ADDRESS (n)
0 0 0 DAC A
0 0 1 DAC B
0 1 0 DAC C
0 1 1 DAC D
1 1 1 All DACs
LDAC FUNCTION
The AD56x5R/AD56x5 DACs have double-buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The input registers are connected directly to the input
shift register, and the digital code is transferred to the relevant
input register upon completion of a valid write sequence. The
DAC registers contain the digital code used by the resistor strings.
Access to the DAC registers is controlled by the LDAC pin.
When the LDAC pin is high, the DAC registers are latched
and the input registers can change state without affecting the
contents of the DAC registers. When LDAC is brought low,
however, the DAC registers become transparent and the contents of
the input registers are transferred to them. The double-buffered
interface is useful if the user requires simultaneous updating of
all DAC outputs. The user can write to one of the input registers
individually and then, by bringing LDAC low when writing to
the other DAC input register, all outputs update simultaneously.
These parts each contain an extra feature whereby a DAC register
is not updated unless its input register has been updated since
the last time LDAC was brought low. Normally, when LDAC is
brought low, the DAC registers are filled with the contents of the
input registers. In the case of the AD56x5R/AD56x5, the DAC
register updates only if the input register has changed since the
last time the DAC register was updated, thereby removing
unnecessary digital crosstalk.
The outputs of all DACs can be simultaneously updated, using
the hardware LDAC pin.
.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 28 of 36
Synchronous LDAC
The DAC registers are updated after new data is read in. LDAC
can be permanently low or pulsed.
Asynchronous LDAC
The outputs are not updated at the same time that the input
registers are written to. When LDAC goes low, the DAC
registers are updated with the contents of the input register.
The LDAC register gives the user full flexibility and control over
the hardware LDAC pin (and software LDAC on the 10-lead
parts that do not have the hardware LDAC pin—see ).
This register allows the user to select which combination of
channels to simultaneously update when the hardware
Table 12
LDAC
pin is executed. Setting the LDAC bit register to 0 for a DAC
channel means that the update of this channel is controlled by
the LDAC pin. If this bit is set to 1, this channel synchronously
updates; that is, the DAC register is updated after new data is
read in, regardless of the state of the LDAC pin. The device
effectively sees the LDAC pin as being pulled low. See
for the
Table 13
LDAC register mode of operation. This flexibility is
useful in applications when the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
Writing to the DAC using Command 110 loads the 4-bit LDAC
register [DB3:DB0]. The default for each channel is 0; that is,
the LDAC pin works normally. Setting the bits to 1 means that
the DAC register is updated, regardless of the state of the LDAC
pin. See for the contents of the input shift register
during the
Figure 67
LDAC register setup command.
Table 12. LDAC Register Mode of Operation on the 10-Lead
LFCSP (Load DAC Register)
LDAC Bits
(DB3 to DB0) LDAC Mode of Operation
0 Normal operation (default), DAC register
update is controlled by the write command.
1 The DAC registers are updated after new data
is read in.
Table 13. LDAC Register Mode of Operation on the 14-Lead
TSSOP (Load DAC Register)
LDAC Bits
(DB3 to DB0) LDAC Pin LDAC Operation
0 1/0
Determined by the LDAC pin.
1 x = don’t
care
The DAC registers are updated
after new data is read in.
R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 X
RESERVED
DON’T
CARE
110A2 A1 A0 XXXXXXXXXXXX
DAC D DAC C DAC B DAC A
COMMAND DAC ADDRESS
(DON’T CARE) DON’T CARE DON’T CARE DAC SELECT
(0 = LDAC PIN ENABLED)
06341-115
Figure 67. LDAC Setup Command
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 29 of 36
POWER-DOWN MODES
Command 100 is reserved for the power-up/power-down
function. The power-up/power-down modes are programmed
by setting Bit DB5 and Bit DB4. This defines the output state of
the DAC amplifier, as shown in Table 14. Bit DB3 to Bit DB0
determine to which DAC or DACs the power-up/power-down
command is applied. Setting one of these bits to 1 applies the
power-up/power-down state defined by DB5 and DB4 to the
corresponding DAC. If a bit is 0, the state of the DAC is
unchanged. Figure 69 shows the contents of the input shift
register for the power-up/power-down command.
When Bit DB5 and Bit DB4 are set to 0, the part works normally
with its normal power consumption of 1 mA at 5 V. However,
for the three power-down modes, the supply current falls to
480 nA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This allows the
output impedance of the part to be known while the part is in
power-down mode. The outputs can either be connected
internally to GND through a 1 k or 100 k resistor or be left
open-circuited (three-state) as shown in Figure 66.
Note that the 14-lead TSSOP models offer the power-down
function when the part is operated with a VDD of 3.6 V to 5.5 V.
The 10-lead LFCSP models offer the power-down function
when the part is powered with a VDD of 2.7 V to 5.5 V.
Table 14. Modes of Operation for the AD56x5R/AD56x5
DB5 DB4 Operating Mode
0 0 Normal operation
Power-down modes
0 1 1 kΩ pull-down resistor to GND
1 0 100 kΩ pull-down resistor to GND
1 1 Three-state, high impedance
RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC
POWER-DOWN
CIRCUITRY
AMPLIFIER
06341-038
Figure 68. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-
down is typically 4 µs for VDD = 5 V or VDD = 3 V.
R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 X
RESERVED
DON’T
CARE
100A2 A1 A0 XXXXXXXXXXPD1 PD0
DAC D DAC C DAC B DAC A
COMMAND DAC ADDRESS
(DON’T CARE) DON’T CARE DON’T CARE POWER-
DOWN MODE
DAC SELECT
(1 = DAC SELECTED)
06341-116
Figure 69. Power-Up/Power-Down Command
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 30 of 36
POWER-ON RESET AND SOFTWARE RESET
The AD56x5R/AD56x5 contain a power-on reset circuit that
controls the output voltage during power-up. The 10-lead
version of the device powers up to 0 V. The 14-lead version has
a power-on reset (POR) pin that allows the output voltage to
be selected. By connecting the POR pin to GND, the AD56x5R/
AD56x5 output powers up to 0 V; by connecting the POR pin to
VDD, the AD56x5R/AD56x5 output powers up to midscale. The
output remains powered up at this level until a valid write sequence
is made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
in the process of powering up.
Any events on LDAC or CLR during power-on reset are ignored.
There is also a software reset function. Command 101 is the
software reset command. The software reset command contains
two reset modes that are software programmable by setting bit
DB0 in the input shift register.
Table 15 shows how the state of the bit corresponds to the
software reset modes of operation of the devices. Figure 70
shows the contents of the input shift register during the
software reset mode of operation.
Table 15. Software Reset Modes for the AD56x5R/AD56x5
DB0 Registers Reset to Zero
0 DAC register
Input shift register
1 (Power-On Reset) DAC register
Input shift register
LDAC register
Power-down register
Internal reference setup register
INTERNAL REFERENCE SETUP (R VERSIONS)
The on-chip reference is off at power-up by default. It can be
turned on by sending the reference setup command (111) and
setting DB0 in the input shift register. Table 16 shows how the
state of the bit corresponds to the mode of operation.
Table 16. Reference Setup Command
DB0 Action
0 Internal reference off (default)
1 Internal reference on
X S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 X
RESERVED
DON’T
CARE
10 1XXXXXXXXXXXXXXXXXXRST
COMMAND DAC ADDRESS
(DON’T CARE) DON’T CARE DON’T CARE
RESET
MODE
06341-113
Figure 70. Reset Command
R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 X
RESERVED
DON’T
CARE
11 1XXXXXXXXXXXXXXXXXXREF
COMMAND DAC ADDRESS
(DON’T CARE) DON’T CARE DON’T CARE
REFERENCE
MODE
06341-114
Figure 71. Reference Setup Command
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 31 of 36
APPLICATIONS INFORMATION
USING A REFERENCE AS A POWER SUPPLY FOR
THE AD56x5R/AD56x5
Because the supply current required by the AD56x5R/AD56x5 is
extremely low, an alternative option is to use a voltage reference
to supply the required voltage to the part (see Figure 72). This is
especially useful if the power supply is noisy or if the system
supply voltages are at some value other than 5 V or 3 V, for
example, 15 V. The voltage reference outputs a steady supply
voltage for the AD56x5R/AD56x5. If the low dropout REF195 is
used, it must supply 450 µA of current to the AD56x5R/AD56x5
with no load on the output of the DAC. When the DAC output
is loaded, the REF195 also must supply the current to the load.
The total current required (with a 5 kΩ load on the DAC
output) is
1 mA + (5 V/5 k) = 2 mA
The load regulation of the REF195 is typically 2 ppm/mA,
resulting in a 4 ppm (20 µV) error for the 2 mA current drawn
from it. This corresponds to a 0.263 LSB error.
2-WIRE
SERIAL
INTERFACE
SCL
SDA
5V
V
OUT
= 0V TO 5V
V
DD
GND
15
V
REF195
AD5625R/
AD5645R/
AD5665R/
AD5625/
AD5665
06341-043
Figure 72. REF195 as Power Supply to the AD56x5R/AD56x5
BIPOLAR OPERATION USING THE
AD56x5R/AD56x5
The AD56x5R/AD56x5 have been designed for single-supply
operation, but a bipolar output range is also possible using the
circuit shown in Figure 73. The circuit gives an output voltage
range of ±5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as follows:
⎥
⎦
⎤
⎢
⎣
⎡⎟
⎠
⎞
⎜
⎝
⎛
×−
⎟
⎠
⎞
⎜
⎝
⎛+
×
⎟
⎠
⎞
⎜
⎝
⎛
×=
R1
R2
V
R1
R2R1D
VV DDDD
O536,65
where D represents the input code in decimal (0 to 65,535).
If VDD = 5 V, R1 = R2 = 10 kΩ,
V5
536,65
10 −
⎟
⎠
⎞
⎜
⎝
⎛×
=D
VO
This is an output voltage range of ±5 V, with 0x0000 corre-
sponding to a −5 V output and 0xFFFF corresponding to a
+5 V output.
2-WIRE
SERIAL
INTERFACE
R2 = 10kΩ
+5V
–5V
AD820/
OP295
AD5625R/
AD5645R/
AD5665R/
AD5625/
AD5665
VDD VOUT
R1 = 10kΩ
±5V
VO
0.1µF10µF
+5
V
SDASCLGND
06341-044
Figure 73. Bipolar Operation with the AD56x5R/AD56x5
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD56x5R/AD56x5
should have separate analog and digital sections, each having its
own area of the board. If the AD56x5R/AD56x5 are in a system
where other devices require an AGND-to-DGND connection,
the connection should be made at one point only. This ground
point should be as close as possible to the AD56x5R/AD56x5.
The power supply to the AD56x5R/AD56x5 should be bypassed
with 10 µF and 0.1 µF capacitors. The capacitors should be
located as close as possible to the device, with the 0.1 µF capaci-
tor ideally right up against the device. The 10 µF capacitor is
the tantalum bead type. It is important that the 0.1 µF capacitor
have low effective series resistance (ESR) and low effective
series inductance (ESI), for example, common ceramic types of
capacitors. This 0.1 µF capacitor provides a low impedance path
to ground for high frequencies caused by transient currents due
to internal logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 32 of 36
OUTLINE DIMENSIONS
031208-B
TOP VIEW
10
1
6
5
0.30
0.23
0.18
*EXPOSED
PAD
(BOTTOM VIEW)
PIN 1 INDEX
AREA
3.00
BSC SQ
SEATING
PLANE
0.80
0.75
0.70
0.20 REF
0.05 MAX
0.02 NOM
0.80 MAX
0.55 NOM
1.74
1.64
1.49
2.48
2.38
2.23
0.50
0.40
0.30
0.50 BSC
PIN 1
INDICATOR
(R 0.20)
*FOR PROPER CONNECTION OF THE EXPOSED PAD PLEASE REFER TO
THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION
OF THIS DATA SHEET.
Figure 74. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
061908-A
8°
0°
4.50
4.40
4.30
14 8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65 BSC
0.15
0.05 0.30
0.19
1.20
MAX
1.05
1.00
0.80 0.20
0.09 0.75
0.60
0.45
COPLANARITY
0.10
SEATING
PLANE
Figure 75. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 33 of 36
ORDERING GUIDE
Model1
Temperature
Range Accuracy
On-Chip
Reference
Maximum
I2C Speed
Package
Description
Package
Option Branding
AD5625BCPZ-R2 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 D8V
AD5625BCPZ-REEL7 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 D8V
AD5625BRUZ −40°C to +105°C ±1 LSB INL None 400 kHz 14-Lead TSSOP RU-14
AD5625BRUZ-REEL7 −40°C to +105°C ±1 LSB INL None 400 kHz 14-Lead TSSOP RU-14
AD5625RBCPZ-R2 −40°C to +105°C ±1 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D8S
AD5625RBCPZ-REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D8S
AD5625RACPZ-REEL7 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 DEU
AD5625RACPZ-1RL7 −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 10-Lead LFCSP_WD CP-10-9 DFW
AD5625RBRUZ-1 −40°C to +105°C ±1 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14
AD5625RBRUZ-1REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14
AD5625RBRUZ-2 −40°C to +105°C ±1 LSB INL 2.5 V 3.4 MHz 14-Lead TSSOP RU-14
AD5625RBRUZ-2REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 3.4 MHz 14-Lead TSSOP RU-14
AD5645RBCPZ-R2 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D89
AD5645RBCPZ-REEL7 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D89
AD5645RBRUZ −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14
AD5645RBRUZ-REEL7 −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14
AD5665BCPZ-R2 −40°C to +105°C ±16 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 D6U
AD5665BCPZ-REEL7 −40°C to +105°C ±16 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 D6U
AD5665BRUZ −40°C to +105°C ±16 LSB INL None 400 kHz 14-Lead TSSOP RU-14
AD5665BRUZ-REEL7 −40°C to +105°C ±16 LSB INL None 400 kHz 14-Lead TSSOP RU-14
AD5665RBCPZ-R2 −40°C to +105°C ±16 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 DA2
AD5665RBCPZ-REEL7 −40°C to +105°C ±16 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 DA2
AD5665RBRUZ-1 −40°C to +105°C ±16 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14
AD5665RBRUZ-1REEL7 −40°C to +105°C ±16 LSB INL 2.5 V 400 kHz 14-Lead TSSOP RU-14
AD5665RBRUZ-2 −40°C to +105°C ±16 LSB INL 2.5 V 3.4 MHz 14-Lead TSSOP RU-14
AD5665RBRUZ-2REEL7 −40°C to +105°C ±16 LSB INL 2.5 V 3.4 MHz 14-Lead TSSOP RU-14
EVAL-AD5665REBZ1 TSSOP Evaluation
Board
EVAL-AD5665REBZ2 LFCSP Evaluation
Board
1 Z = RoHS Compliant Part.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 34 of 36
NOTES
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 35 of 36
NOTES
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 36 of 36
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2007-2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06341-0-12/09(B)
