Quad, 12-/14-/16-Bit nanoDACs with
5 ppm/°C On-Chip Reference, I2C Interface
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B
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FEATURES
Low power, smallest pin-compatible, quad nanoDACs
AD5625R/AD5645R/AD5665R
12-/14-/16-bit nanoDACs
On-chip, 2.5 V, 5 ppm/°C reference in TSSOP
On-chip, 2.5 V, 10 ppm/°C reference in LFCSP
On-chip, 1.25 V, 10 ppm/°C reference in LFCSP
AD5625/AD5665
12-/16-bit nanoDACs
External reference only
3 mm × 3 mm 10-lead LFCSP and 14-lead TSSOP
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale/midscale
Per channel power-down
Hardware LDAC and CLR functions
I2C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5625R/AD5645R/AD5665R and AD5625/AD5665
members of the nanoDAC® family are low power, quad, 12-/
14-/16-bit, buffered voltage-out DACs with/without an on-chip
reference. All devices operate from a single 2.7 V to 5.5 V supply,
are guaranteed monotonic by design, and have an I2C-compatible
serial interface.
The AD5625R/AD5645R/AD5665R have an on-chip reference.
The LFCSP versions of the AD56x5R have a 1.25 V or 2.5 V,
10 ppm/°C reference, giving a full-scale output range of 2.5 V or
5 V; the TSSOP versions of the AD56x5R have a 2.5 V, 5 ppm/°C
reference, giving a full-scale output range of 5 V. The on-chip
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a software write.
The AD5625/AD5665 require an external reference voltage to
set the output range of the DAC.
The part incorporates a power-on reset circuit that ensures that
the DAC output powers up to 0 V (POR = GND) or midscale
(POR = VDD) and remains there until a valid write occurs. The
on-chip precision output amplifier enables rail-to-rail output swing.
FUNCTIONAL BLOCK DIAGRAMS
INTERFACE
LOGIC
SDA
SCL
A
DDR1
A
DDR2
V
DD
GND
1.25V/2.5V REF
V
REFIN
/
V
REFOUT
AD5625R/AD5645R/AD5665R
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A V
OUT
A
BUFFER
LDAC CLR POR
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B V
OUT
B
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C V
OUT
C
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D V
OUT
D
BUFFER
NOTES
1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:
ADDR2, LDAC, CLR, POR.
06341-001
POWER-ON RESET POWER-DOWN LOGIC
Figure 1. AD5625R/AD5645R/AD5665R
0
6341-002
INTERFACE
LOGIC
SDA
SCL
ADDR1
ADDR2
V
DD
GND
V
REFIN
AD5625/AD5665
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A V
OUT
A
BUFFER
LDAC CLR POR
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B V
OUT
B
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C V
OUT
C
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D V
OUT
D
BUFFER
NOTES
1. THE FOLLOWING PINS ARE AVAILABLE ONLY ON 14-LEAD PACKAGE:
ADDR2, LDAC, CLR, POR.
POWER-ON RESET POWER-DOWN LOGIC
Figure 2. AD5625/AD5665
The AD56x5R/AD56x5 use a 2-wire I2C-compatible serial
interface that operates in standard (100 kHz), fast (400 kHz),
and high speed (3.4 MHz) modes.
Table 1. Related Devices
Part No. Description
AD5025/AD5045/AD5065 Dual 12-/14-/16-bit DACs
AD5624R/AD5644R/AD5664R,
AD5624/AD5664
Quad SPI 12-/14-/16-bit DACs,
with/without internal reference
AD5627R/AD5647R/AD5667R,
AD5627/AD5667
Dual I2C 12-/14-/16-bit DACs,
with/without internal reference
AD5666 Quad SPI 16-bit DAC with
internal reference
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 2 of 36
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams ............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Specifications—AD5665R/AD5645R/AD5625R ..................... 3
Specifications—AD5665/AD5625 ............................................. 5
AC Characteristics ........................................................................ 7
I2C Timing Specifications ............................................................ 8
Absolute Maximum Ratings .......................................................... 10
ESD Caution ................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 22
Digital-to-Analog Converter (DAC) ....................................... 22
Resistor String ............................................................................. 22
Output Amplifier ........................................................................ 22
Internal Reference ...................................................................... 22
External Reference ..................................................................... 23
Serial Interface ............................................................................ 23
Write Operation.......................................................................... 23
Read Operation........................................................................... 23
High Speed Mode ....................................................................... 25
Input Shift Register .................................................................... 25
Multiple Byte Operation ............................................................ 25
Broadcast Mode .......................................................................... 27
LDAC Function .......................................................................... 27
Power-Down Modes .................................................................. 29
Power-On Reset and Software Reset ....................................... 30
Internal Reference Setup (R Versions) .................................... 30
Applications Information .............................................................. 31
Using a Reference as a Power Supply for the
AD56x5R/AD56x5 ..................................................................... 31
Bipolar Operation Using the AD56x5R/AD56x5 .................. 31
Power Supply Bypassing and Grounding ................................ 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 33
REVISION HISTORY
12/09—Rev. A to Rev. B
Changes to Features Section, General Description Section,
and Table 1 ......................................................................................... 1
Changes to Table 2 ............................................................................ 3
Changes to Internal Reference Section ........................................ 22
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 33
6/09—Rev. 0 to Rev. A
Changes to Features and General Description Sections .............. 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Digital-to-Analog Converter (DAC) Section, Added
Figure 54 and Figure 55, Renumbered Subsequent Figures ..... 22
Changes to Ordering Guide .......................................................... 33
3/07—Revision 0: Initial Version
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 3 of 36
SPECIFICATIONS
SPECIFICATIONS—AD5665R/AD5645R/AD5625R
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1
STATIC PERFORMANCE2
AD5665R
Resolution 16 Bits
Relative Accuracy ±8 ±16 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5645R
Resolution 14 Bits
Relative Accuracy ±2 ±4 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
AD5625R
Resolution 12 12 Bits
Relative Accuracy ±1 ±4 ±0.5 ±1 LSB
Differential Nonlinearity ±1 ±0.25 LSB Guaranteed monotonic by design
Zero-Code Error 2 10 2 10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 ±1 ±10 mV
Full-Scale Error −0.1 ±0.5 −0.1 ±0.5 % FSR All 1s loaded to DAC register
Gain Error ±0.1 ±1.25 ±0.1 ±1 % FSR
Zero-Code Error Drift ±2 ±2 µV/°C
Gain Temperature Coefficient ±2.5 ±2.5 ppm Of FSR/°C
DC Power Supply Rejection
Ratio
−100 −100 dB DAC code = midscale; VDD = 5 V ± 10%
DC Crosstalk (External
Reference)
15 15 µV Due to full-scale output change,
RL = 2 kΩ to GND or VDD
10 10 µV/mA Due to load current change
8 8 µV Due to powering down (per channel)
DC Crosstalk (Internal
Reference)
25 25 µV Due to full-scale output change,
RL = 2 kΩ to GND or VDD
20 20 µV/mA Due to load current change
10 10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 VDD 0 VDD V Internal reference disabled
0
2 ×
VREF
2 ×
VREF
Internal reference enabled
Capacitive Load Stability 2 2 nF RL = ∞
10 10 nF RL = 2 kΩ
DC Output Impedance 0.5 0.5
Short-Circuit Current 30 30 mA VDD = 5 V
Power-Up Time 4 4 µs Coming out of power-down mode;
VDD = 5 V
REFERENCE INPUTS
Reference Current 210 260 210 260 µA VREF = VDD = 5.5 V
Reference Input Range 0.75 VDD 0.75 VDD V
Reference Input Impedance 26 26 kΩ
REFERENCE OUTPUT (1.25 V)
Output Voltage 1.247 1.253 1.247 1.253 V At ambient
Reference TC3
±10 ±10 ppm/°C
Output Impedance 7.5 7.5 kΩ
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 4 of 36
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments1
REFERENCE OUTPUT (2.5 V) VDD = 4.5 V to 5.5 V
Output Voltage 2.495 2.505 2.495 2.505 V At ambient
Reference TC3 ±10 ±5 ±10 ppm/°C
Output Impedance 7.5 7.5
LOGIC INPUTS (ADDRx, CLR,
LDAC, POR)3
IIN, Input Current ±1 ±1 μA
VINL, Input Low Voltage 0.15 × VDD 0.15 × VDD V
VINH, Input High Voltage 0.85 × VDD 0.85 × VDD V
CIN, Pin Capacitance 2 2 pF
VHYST, Input Hysteresis 0.1 × VDD 0.1 × VDD V
LOGIC INPUTS (SDA, SCL)3
IIN, Input Current ±1 ±1 μA
VINL, Input Low Voltage 0.3 × VDD 0.3 × VDD V
VINH, Input High Voltage 0.7 × VDD 0.7 × VDD V
CIN, Pin Capacitance 2 2 pF
VHYST, Input Hysteresis 0.1 × VDD 0.1 × VDD V High speed mode
0.05 × VDD 0.05 × VDD V Fast mode
LOGIC OUTPUTS (SDA)3
VOL, Output Low Voltage 0.4 0.4 V ISINK = 3 mA
0.6 0.6 V ISINK = 6 mA
Floating-State Leakage
Current
±1 ±1 μA
Floating-State Output
Capacitance
2 2 pF
POWER REQUIREMENTS
VDD 2.7 5.5 2.7 5.5 V
IDD (Normal Mode)4 V
IH = VDD, VIL = GND, full-scale loaded
VDD = 4.5 V to 5.5 V 1.0 1.16 1.0 1.16 mA Internal reference off
VDD = 2.7 V to 3.6 V 0.9 1.05 0.9 1.05 mA Internal reference off
VDD = 4.5 V to 5.5 V 1.9 2.14 1.9 2.14 mA Internal reference on
VDD = 2.7 V to 3.6 V 1.4 1.59 1.4 1.59 mA Internal reference on
IDD (All Power-Down Modes)5
VDD = 2.7 V to 5.5 V 0.48 1 0.48 1 μA VIH = VDD, VIL = GND (LFCSP)
VDD = 3.6 V to 5.5 V 0.48 1 0.48 1 μA VIH = VDD, VIL = GND (TSSOP)
1 Temperature range of A and B grades is −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5665R (Code 512 to Code 65,024), AD5645R (Code 128 to Code 16,256), AD5625R (Code 32 to Code 4064). Output
unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down. Power-down function is not available on 14-lead TSSOP parts when the part is powered with VDD < 3.6 V.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 5 of 36
SPECIFICATIONS—AD5665/AD5625
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
B Grade
Parameter Min Typ Max Unit Test Conditions/Comments1
STATIC PERFORMANCE2
AD5665
Resolution 16 Bits
Relative Accuracy ±8 ±16 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5625
Resolution 12 Bits
Relative Accuracy ±0.5 ±1 LSB
Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design
Zero-Code Error 2 10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 mV
Full-Scale Error −0.1 ±0.5 % FSR All 1s loaded to DAC register
Gain Error ±0.1 ±1 % FSR
Zero-Code Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 dB DAC code = midscale; VDD = 5 V ± 10%
DC Crosstalk (External Reference) 15 µV Due to full-scale output change,
RL = 2 kΩ to GND or VDD
10 µV/mA Due to load current change
8 µV Due to powering down (per channel)
DC Crosstalk (Internal Reference) 25 µV Due to full-scale output change,
RL = 2 kΩ to GND or VDD
20 µV/mA Due to load current change
10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS3
Output Voltage Range 0 VDD V
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
DC Output Impedance 0.5
Short-Circuit Current 30 mA VDD = 5 V
Power-Up Time 4 µs Coming out of power-down mode; VDD = 5 V
REFERENCE INPUTS
Reference Current 210 260 µA VREF = VDD = 5.5 V
Reference Input Range 0.75 VDD V
Reference Input Impedance 26 kΩ
LOGIC INPUTS (ADDRx, CLR, LDAC, POR)3
IIN, Input Current ±1 µA
VINL, Input Low Voltage 0.15 × VDD V
VINH, Input High Voltage 0.85 × VDD V
CIN, Pin Capacitance 2 pF
VHYST, Input Hysteresis 0.1 × VDD V
LOGIC INPUTS (SDA, SCL)3
IIN, Input Current ±1 µA
VINL, Input Low Voltage 0.3 × VDD V
VINH, Input High Voltage 0.7 × VDD V
CIN, Pin Capacitance 2 pF
VHYST, Input Hysteresis 0.1 × VDD V High speed mode
0.05 × VDD V Fast mode
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 6 of 36
B Grade
Parameter Min Typ Max Unit Test Conditions/Comments1
LOGIC OUTPUTS (SDA)3
VOL, Output Low Voltage 0.4 V ISINK = 3 mA
0.6 V ISINK = 6 mA
Floating-State Leakage Current ±1 µA
Floating-State Output Capacitance 2 pF
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD (Normal Mode)4 V
IH = VDD, VIL = GND, full-scale loaded
VDD = 4.5 V to 5.5 V 1.0 1.16 mA
VDD = 2.7 V to 3.6 V 0.9 1.05 mA
IDD (All Power-Down Modes)5
VDD = 2.7 V to 5.5 V 0.48 1 µA VIH = VDD, VIL = GND (LFCSP)
VDD = 3.6 V to 5.5 V 0.48 1 µA VIH = VDD, VIL = GND (TSSOP)
1 Temperature range of B grade is −40°C to +105°C.
2 Linearity calculated using a reduced code range: AD5665 (Code 512 to Code 65,024), AD5625 (Code 32 to Code 4064). Output unloaded.
3 Guaranteed by design and characterization; not production tested.
4 Interface inactive. All DACs active. DAC outputs unloaded.
5 All DACs powered down. Power-down function is not available on 14-lead TSSOP parts when the part is powered with VDD < 3.6 V.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 7 of 36
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1,2 Min Typ Max Unit Test Conditions/Comments3
Output Voltage Settling Time
AD5625R/AD5625 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5645R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5665R/AD5665 4 7 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 1.8 V/µs
Digital-to-Analog Glitch Impulse 1 LSB change around major carry
15 nV-s LFCSP
5 nV-s TSSOP
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dB VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
Digital Crosstalk 0.1 nV-s
Analog Crosstalk 1 nV-s External reference
4 nV-s Internal reference
DAC-to-DAC Crosstalk 1 nV-s External reference
4 nV-s Internal reference
Multiplying Bandwidth 340 kHz VREF = 2 V ± 0.1 V p-p
Total Harmonic Distortion −80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz
100 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 15 µV p-p 0.1 Hz to 10 Hz
1 Guaranteed by design and characterization; not production tested.
2 See the Terminology section.
3 Temperature range is −40°C to +105°C, typical @ 25°C.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 8 of 36
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1
Table 5.
Parameter Test Conditions2Min Max Unit Description
fSCL3Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
High speed mode, CB = 100 pF 3.4 MHz
High speed mode, CB = 400 pF 1.7 MHz
t1 Standard mode 4 s tHIGH, SCL high time
Fast mode 0.6 s
High speed mode, CB = 100 pF 60 ns
High speed mode, CB = 400 pF 120 ns
t2 Standard mode 4.7 s tLOW, SCL low time
Fast mode 1.3 s
High speed mode, CB = 100 pF 160 ns
High speed mode, CB = 400 pF 320 ns
t3 Standard mode 250 ns tSU;DAT, data setup time
Fast mode 100 ns
High speed mode 10 ns
t4 Standard mode 0 3.45 s tHD;DAT, data hold time
Fast mode 0 0.9 s
High speed mode, CB = 100 pF 0 70 ns
High speed mode, CB = 400 pF 0 150 ns
t5 Standard mode 4.7 s tSU;STA, setup time for a repeated start condition
Fast mode 0.6 s
High speed mode 160 ns
t6 Standard mode 4 s tHD;STA, hold time (repeated) start condition
Fast mode 0.6 s
High speed mode 160 ns
t7 Standard mode 4.7 s tBUF, bus-free time between a stop and a start
condition
Fast mode 1.3 s
t8 Standard mode 4 s tSU;STO, setup time for a stop condition
Fast mode 0.6 s
High speed mode 160 ns
t9 Standard mode 1000 ns tRDA, rise time of SDA signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
t10 Standard mode 300 ns tFDA, fall time of SDA signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
t11 Standard mode 1000 ns tRCL, rise time of SCL signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 40 ns
High speed mode, CB = 400 pF 20 80 ns
t11A Standard mode 1000 ns
tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 9 of 36
Parameter Test Conditions2Min Max Unit Description
t12 Standard mode 300 ns tFCL, fall time of SCL signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 40 ns
High speed mode, CB = 400 pF 20 80 ns
t13 Standard mode 10 ns
LDAC pulse width low
Fast mode 10 ns
High speed mode 10 ns
t14 Standard mode 300 ns
Falling edge of ninth SCL clock pulse of last byte
of a valid write to LDAC falling edge
Fast mode 300 ns
High speed mode 30 ns
t15 Standard mode 20 ns
CLR pulse width low
Fast mode 20 ns
High speed mode 20 ns
tSP4Fast mode 0 50 ns Pulse width of spike suppressed
High speed mode 0 10 ns
1 See Figure 3. High speed mode timing specification applies only to the AD5625RBRUZ-2/AD5625RBRUZ-2REEL7 and AD5665RBRUZ-2/AD5665RBRUZ-2REEL7.
2 CB refers to the capacitance on the bus line.
3 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on the EMC
behavior of the part.
4 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or less than 10 ns for high speed mode.
SCL
SDA
PS S P
t8
t6
t5
t3t10 t9
t4
t6t1
t2
t11 t12
t14
CLR
t13
t15
LDAC*
t7
*ASYNCHRONOUS LDAC UPDATE MODE.
06341-003
Figure 3. 2-Wire Serial Interface Timing Diagram
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 10 of 36
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to GND −0.3 V to +7 V
VOUT to GND −0.3 V to VDD + 0.3 V
VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range, Industrial −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ maximum) 150°C
Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance
LFCSP_WD (4-Layer Board) 61°C/W
TSSOP 150.4°C/W
Reflow Soldering Peak Temperature,
RoHS Compliant
260°C ± 5°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 11 of 36
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
LDAC
14
SCL
2
ADDR1
13
SDA
3
V
DD 12
GND
4
V
OUT
A
11
V
OUT
B
5
V
OUT
C
10
V
OUT
D
6
POR
9
CLR
7
V
REFIN
/V
REFOUT 8
ADDR2
AD5625R/
AD5645R/
AD5665R
TOP VIEW
(Not to Scale)
06341-120
Figure 4. Pin Configuration (14-Lead TSSOP), R Suffix Version
1
LDAC
14
SCL
2
ADDR1
13
SDA
3
V
DD 12
GND
4
V
OUT
A
11
V
OUT
B
5
V
OUT
C
10
V
OUT
D
6
POR
9
CLR
7
V
REFIN 8
ADDR2
AD5625/
AD5665
TOP VIEW
(Not to Scale)
0
6341-121
Figure 5. Pin Configuration (14-Lead TSSOP)
1
V
OUT
A
10
V
REFIN
/V
REFOUT
2
V
OUT
B
9
V
DD
3
GND
8
SDA
4
V
OUT
C
7
SCL
5
V
OUT
D
6
ADDR
AD5625R/
AD5645R/
AD5665R
TOP VIEW
(Not to Scale)
EXPOSED PAD TIED TO GND.
06341-122
Figure 6. Pin Configuration (10-Lead LFCSP), R Suffix Version
1
V
OUT
A
10
V
REFIN
2
V
OUT
B
9
V
DD
3
GND
8
SDA
4
V
OUT
C
7
SCL
5
V
OUT
D
6
ADDR
AD5625/
AD5665
TOP VIEW
(Not to Scale)
EXPOSED PAD TIED TO GND.
06341-123
Figure 7. Pin Configuration (10-Lead LFCSP)
Table 7. Pin Function Descriptions
Pin Number
14-Lead 10-Lead Mnemonic Description
1 N/A LDAC Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently
low.
2 N/A ADDR1 Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address
(see Table 9).
3 9 VDD Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND.
4 1 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5 4 VOUTC Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
6 N/A POR Power-On Reset Pin. Tying the POR pin to GND powers up the part to 0 V. Tying the POR pin to VDD
powers up the part to midscale.
7 10 VREFIN/VREFOUT The AD56x5R have a common pin for reference input and reference output. When using the internal
reference, this is the reference output pin. When using an external reference, this is the reference
input pin. The default for this pin is as a reference input. (The internal reference and reference output
are only available on R suffix versions.) The AD56x5 has a reference input pin only.
8 N/A ADDR2 Three-State Address Input. Sets Bit A3 and Bit A2 of the 7-bit slave address (see Table 9).
9 N/A CLR Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses
are ignored. When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the
output to 0 V. The part exits clear code mode on the falling edge of the ninth clock pulse of the last
byte of the valid write. If CLR is activated during a write sequence, the write is aborted. If CLR is
activated during high speed mode, the part exits high speed mode.
10 5 VOUTD Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
11 2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
12 3 GND Ground Reference Point for All Circuitry on the Part.
13 8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit
input register. It is a bidirectional, open-drain data line that should be pulled to the supply with an
external pull-up resistor.
14 7 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit
input register.
N/A 6 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address
(see Table 8).
EPAD For the 10-lead LFCSP, the exposed pad must be tied to GND.
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 12 of 36
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL ERROR (LSB)
10
4
6
8
0
2
–6
–10
–8
–2
–4
0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
V
DD
= V
REF
= 5V
T
A
= 25°C
06341-005
Figure 8. INL, AD5665, External Reference
CODE
INL ERROR (LSB)
4
–4
0 2500 5000 7500 10000 12500 15000
–3
–2
–1
0
1
2
3
V
DD
= V
REF
= 5V
T
A
= 25°C
06341-006
Figure 9. INL, AD5645R, External Reference
CODE
INL ERROR (LSB)
1.0
–1.0
0 500 1000 1500 2000 2500 3000 3500 4000
–0.8
–0.6
–0.4
0
0.4
0.2
–0.2
0.6
0.8
V
DD
= V
REF
= 5V
T
A
= 25°C
06341-100
Figure 10. INL, AD5625, External Reference
CODE
DNL ERROR (LSB)
1.0
0.6
0.4
0.2
0.8
0
–0.4
–0.2
–0.6
–1.0
–0.8
0 10k 20k 30k 40k 50k 60k
V
DD
= V
REF
= 5V
T
A
= 25°C
0
6341-007
Figure 11. DNL, AD5665, External Reference
DNL ERROR (LSB)
0.5
0.3
0.2
0.1
0.4
0
–0.2
–0.1
–0.3
–0.5
–0.4
V
DD
= V
REF
= 5V
T
A
= 25°C
CODE
02500 5000 7500 10000 12500 15000
0
6341-008
Figure 12. DNL, AD5645R, External Reference
DNL ERROR (LSB)
0.20
0.10
0.05
0.15
0
–0.05
–0.10
–0.20
–0.15
CODE
0500 1000 1500 2000 2500 3000 3500 4000
V
DD
= V
REF
= 5V
T
A
= 25°C
0
6341-009
Figure 13. DNL, AD5625, External Reference
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 13 of 36
CODE
INL ERROR (LSB)
10
8
0
–10
–6
–8
–4
6
–2
4
2
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
06341-010
Figure 14. INL, AD5665R, 2.5 V Internal Reference
CODE
INL ERROR (LSB)
4
3
–4
–3
–2
2
–1
1
0
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
V
DD
=5V
V
REFOUT
=2.5V
T
A
= 25°C
06341-011
Figure 15. INL, AD5645R, 2.5 V Internal Reference
CODE
INL ERROR (LSB)
1.0
0.8
0
–1.0
–0.8
–0.6
0.6
–0.4
–0.2
0.4
0.2
0 1000500 20001500 350030002500 4000
V
DD
=5V
V
REFOUT
=2.5V
T
A
=25°C
06341-012
Figure 16. INL, AD5625R, 2.5 V Internal Reference
CODE
DNL ERROR (LSB)
1.0
0.8
0
–1.0
–0.6
–0.8
–0.4
0.6
–0.2
0.4
0.2
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
=5V
V
REFOUT
=2.5V
T
A
=25°C
06341-013
Figure 17. DNL, AD5665R, 2.5 V Internal Reference
CODE
DNL ERROR (LSB)
0.5
0.4
0
–0.5
–0.3
–0.4
–0.2
0.3
–0.1
0.2
0.1
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
0
6341-014
Figure 18. DNL, AD5645R, 2.5 V Internal Reference
CODE
DNL ERROR (LSB)
0.20
0.15
0
–0.20
–0.15
–0.10
0.10
–0.05
0.05
01000500 20001500 350030002500 4000
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25°C
0
6341-015
Figure 19. DNL, AD5625R, 2.5 V Internal Reference
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 14 of 36
CODE
INL ERROR (LSB)
10
8
4
6
2
0
–4
–2
–6
–8
–10
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06341-016
Figure 20. INL, AD5665R,1.25 V Internal Reference
CODE
INL ERROR (LSB)
4
–4
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
3
2
1
0
–1
–2
–3
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06341-017
Figure 21. INL, AD5645R, 1.25 V Internal Reference
CODE
INL ERROR (LSB)
1.0
–1.0
0 500 1000 1500 2000 2500 3000 3500 4000
0
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25°C
06341-018
Figure 22. INL, AD5625R,1.25 V Internal Reference
CODE
DNL ERROR (LSB)
1.0
0.8
0.4
0.6
0.2
0
–0.4
–0.2
–0.6
–0.8
–1.0
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
06341-019
Figure 23. DNL, AD5665R,1.25 V Internal Reference
CODE
DNL ERROR (LSB)
0.5
–0.5
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
0
0.4
0.3
0.2
0.1
–0.1
–0.2
–0.3
–0.4
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
06341-020
Figure 24. DNL, AD5645R,1.25 V Internal Reference
CODE
DNL ERROR (LSB)
0.20
–0.20
0 500 1000 1500 2000 2500 3000 3500 4000
0
0.15
0.10
0.05
–0.05
–0.10
–0.15
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
06341-021
Figure 25. DNL, AD5625R, 1.25 V Internal Reference
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 15 of 36
TEMPERATURE (°C)
ERROR (LSB)
8
6
4
2
–6
–4
–2
0
–8
–40 –20 40200 1008060
MIN DNL
MAX DNL
MAX INL
MIN INL
VDD = VREF = 5V
06341-022
Figure 26. INL Error and DNL Error vs. Temperature
V
REF
(V)
ERROR (LSB)
10
4
6
8
2
0
–8
–6
–4
–2
–10
0.75 1.25 1.75 2.25 4.253.753.252.75 4.75
MIN DNL
MAX DNL
MAX INL
MIN INL
V
DD
= 5V
T
A
= 25°C
06341-023
Figure 27. INL Error and DNL Error vs. VREF
V
DD
(V)
ERROR (LSB)
8
6
4
2
–6
–4
–2
0
–8
2.7 3.2 3.7 4.74.2 5.2
MIN DNL
MAX DNL
MAX INL
MIN INL
T
A
= 25°C
06341-024
Figure 28. INL Error and DNL Error vs. Supply
TEMPERATURE (°C)
ERROR (% FSR)
0
–0.04
–0.02
–0.06
–0.08
–0.10
–0.18
–0.16
–0.14
–0.12
–0.20
–40 –20 40200 1008060
V
DD
= 5V
GAIN ERROR
FULL-SCALE ERROR
06341-025
Figure 29. Gain Error and Full-Scale Error vs. Temperature
TEMPERATURE (°C)
ERROR (mV)
1.5
1.0
0.5
0
–2.0
–1.5
–1.0
–0.5
–2.5
–40 –20 40200860 1000
OFFSET ERROR
ZERO-SCALE ERROR
06341-026
Figure 30. Zero-Scale Error and Offset Error vs. Temperature
V
DD
(V)
ERROR (% FSR)
1.0
–1.5
–1.0
–0.5
0
0.5
–2.0
2.7 3.2 3.7 4.74.2 5.2
GAIN ERROR
FULL-SCALE ERROR
06341-027
Figure 31. Gain Error and Full-Scale Error vs. Supply
AD5625R/AD5645R/AD5665R, AD5625/AD5665
Rev. B | Page 16 of 36
V
DD
(V)
ERROR (mV)
1.0
0.5
0
–2.0
–1.5
–1.0
–0.5
–2.5
2.7 3.2 4.23.7 5.24.7
ZERO-SCALE ERROR
OFFSET ERROR
T
A
= 25°C
06341-028
Figure 32. Zero-Scale Error and Offset Error vs. Supply
I
DD
(mA)
NUMBER OF DEVICES
0
30
25
20
15
10
5
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
V
DD
= 3.6V
V
DD
= 5.5V
06341-029
Figure 33. IDD Histogram with External Reference
I
DD
(mA)
NUMBER OF DEVICES
0
25
20
15
10
5
1.35
1.37
1.39
1.41
1.43
1.45
1.47
1.49
1.51
1.53
1.55
1.57
1.59
1.61
1.63
1.65
1.67
1.69
1.71
1.73
1.75
1.77
1.79
1.81
1.83
1.85
1.87
1.89
1.91
1.93
1.99
1.95
1.97
V
DD
= 3.6V
V
DD
= 5.5V
06341-030
V
REFOUT
= 1.25V V
REFOUT
= 2.5V
Figure 34. IDD Histogram with Internal Reference
CODE
I
DD
(mA)
0
2.0
1.6
1.8
1.4
1.2
1.0
0.8
0.6
0.4
0.2
512 10512 20512 30512 40512 50512 60512
T
A
= 25°C
V
DD
= 5.5V
V
REFOUT
= 2.5V
V
REFIN
= 5V
0
6341-060
Figure 35. Supply Current vs. DAC Code
V
DD
(V)
I
DD
(mA)
0
0.2
0.4
0.8
0.6
1.0
1.2
3.22.7 3.74.24.75.2
T
A
= 25°C
0
6341-061
Figure 36. Supply Current vs. Supply
TEMPERATURE (°C)
I
DD
(mA)
1.2
0.2
0.4
1.0
0.6
0.8
0
40200 20406080100
06341-063
V
DD
= V
REF
= 5V
V
DD
= V
REF
= 3V
Figure 37. Supply Current vs. Temperature