PAC1921 High-Side Power/Current Monitor with Analog Output Features Description * Configurable Measurement Type Output: Power, Current or Bus Voltage * Configurable Voltage Output (3V, 2V, 1.5V, 1V) - All output values also available over SMBus * New Device Topology - Provides integrated average power measurement - Power measurements provided to microcontroller with ADC inputs - Unique lossless integrating architecture allows operation at low sense voltages - Output voltage proportional to selected measurement * High-Side Current Sensor - 100 mV full-scale current sense voltage range - Second-order delta-sigma ADC with 11-bit or 14-bit resolution - Selectable current binary gain ranges: 1x through 128x * 1% Power Measurement Accuracy * Auto-Zero Offset * Auto Sleep State - Automatically shifts to low-power state (3.5 A) * Power Supply - VDD = 3.3V nominal (operational range 3.0V to 5.5V) * Bus Range 0V to 32V * No Input Filters Required * Available in a 10-pin 3 mm x 3 mm VDFN RoHS Compliant Package The PAC1921 is a dedicated power-monitoring device with a configurable analog output that can present power, current or voltage. The PAC1921 is designed for power measurement and diagnostic systems that cannot allow for latency when performing high-speed power management. Measurements are accumulated in large lossless registers, allowing for integration periods of 500 s to 2.9 seconds. The measurement is averaged and presented on the analog output with a full scale range of 3V, 2V, 1.5V or 1.0V. Applications * * * * * Diagnostic Equipment Servers Power Supplies Industrial and Power Management Systems Notebook and Desktop Computers 2012-2016 Microchip Technology Inc. The PAC1921 has a READ/INT pin for host control of the measurement integration period. This pin can be used to synchronize readings of multiple buses between several devices. Alternatively, PAC1921 is able to provide outputs in a free-running mode. Information is provided on the OUT pin and is available via SMBus if desired. Data sampling and output attributes, such as the internal ADC resolution (11-bit or 14-bit) and sample rate, are configurable. The SMBus interface has more selections for user-configurable options. The PAC1921 is a 1% accurate power measurement device that measures and cancels the zero offset from the input pins. The PAC1921 was designed to monitor power rails from 0-32V with a full-scale capability of 100 mV across the sense resistor. No input filters are required for this device. Package Types PAC1921 3x3 VDFN* VDD 1 SENSE + 2 SENSE - 3 OUT 4 GND 5 10 SM_CLK EP 11 9 SM_DATA 8 READ/INT 7 RESERVED 6 ADDR_SEL *Includes Exposed Thermal Pad (EP), see Table 3-1 DS20005293D-page 1 PAC1921 Device Block Diagram VDD ADDR_SEL SENSE+ SENSE- DS20005293D-page 2 GND 10-bit DAC Resistor Decoder V Buffer/ Divider Diff Current Amplifier 11-bit or 14-bit ADC and MUX OUT READ/INT SM_CLK Digital Control SM_DATA RESERVED 2012-2016 Microchip Technology Inc. PAC1921 1.0 ELECTRICAL CHARACTERISTICS 1.1 Electrical Specifications Absolute Maximum Ratings() VDD pin............................................................................................................................................................-0.3 to 6.0V Voltage on SENSE- and SENSE+ pins............................................................................................................-0.3 to 42V Voltage on ADDR_SEL pin .............................................................................................................................-0.3 to 2.6V Voltage on any other pin to GND ....................................................................................................................-0.3 to 6.0V Voltage between Sense pins (|(SENSE+ - SENSE-)|) ...............................................................................................40V Input current to any pin except VDD ...................................................................................................................... 10 mA Output short circuit current.............................................................................................................................. Continuous Package Power Dissipation (Note) ...............................................................................................0.5W up to TA = +85C Junction to Ambient (JA) ....................................................................................................................................+78C/W Operating Ambient Temperature Range ....................................................................................................... -40 to +85C Storage Temperature Range ....................................................................................................................... -55 to +150C ESD Rating - All pins - HBM ...................................................................................................................................2000V Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. Note: The Package Power Dissipation specification assumes a recommended thermal via design consisting of a 2 x 2 matrix of 0.3 mm (12 mil) vias at 1.0 mm pitch connected to the ground plane with a 1.6 mm x 2.3 mm thermal landing 2012-2016 Microchip Technology Inc. DS20005293D-page 3 PAC1921 TABLE 1-1: ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40C to +85C, VDD = 3V to 5.5V, VBUS = 0V to 32V; typical values are at TA = +25C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ - SENSE-) = 0V Characteristic Sym. Min. Typ. Max. Unit Conditions VDD Range VDD 3.0 -- 5.5 V VDD Integrate Current IDD -- 450 900 A Output unloaded VDD Read Current IREAD -- 300 450 A Output unloaded VDD Sleep Current ISLEEP -- 3.5 15 A VDD_RISE 0.05 -- 1000 V/ms Power Supply VDD Rise Rate 0 to 3V in 60 ms Analog Input Characteristics Bus Voltage Range VBUS 0 -- 32 V VSENSE Differential Input Voltage Range VSENSE_DIF 0 -- 100 mV ADC Data Resolution ADC_RES -- -- 14 bits VSENSE_LSB -- 6.1 -- V 14-bit resolution -- 48.8 -- V 11-bit resolution -- 1.95 -- mV 14-bit resolution -- 15.6 -- mV 11-bit resolution VSENSE_ GAIN_ERR -- 0.2 0.4 % Gain = 1 VSENSE_ OFFSET_ERR -- 25 100 V 14-bit resolution VBUS Gain Accuracy VBUS_GAIN_ERR -- -- 0.4 % Measured at ADC output, Gain = 1 SENSE+, SENSEPin Leakage Current ISENSE +, ISENSE- -- -- 1.0 A VBUS = 24V, VSENSE = 0V Sleep state SENSE+, SENSEPin Leakage Current ISENSE +, ISENSE- -- -- 1.0 A VDD = 0V SENSE+ Pin Bias Current ISENSE+_BIAS -- 34 -- A VBUS = 24V, VSENSE = 100 mV Integrate state, Power measurement SENSE- Pin Bias Current ISENSE-_BIAS -- -- 1.0 A VBUS = 24V, VSENSE = 0 to 100 mV Integrate state VSENSE LSB Step Size VBUS LSB Step Size VSENSE Gain Accuracy VSENSE Offset Accuracy, Referenced to Input DS20005293D-page 4 VBUS_LSB Common-mode voltage on SENSE pins, referenced to ground 2012-2016 Microchip Technology Inc. PAC1921 TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40C to +85C, VDD = 3V to 5.5V, VBUS = 0V to 32V; typical values are at TA = +25C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ - SENSE-) = 0V Characteristic Sym. Min. Typ. Max. Unit Conditions VOUT 0 3.0 VDD-0.15 V 3V FSR maximum equation in effect when VDD falls below 3.15V OUTGAIN_ERR -- -- 0.2 % Output Offset Error, Referenced to Output OUTOFFSET_ ERR -- 3 6 mV 3V FSR Output Settling Time tSETTLE -- -- 42 s Output swing from 0V to 3.0V driving up to 50 pF Output Load COUT -- -- 50 pF Output Current Drive IOUT -- -- 3 mA DC IOUT_SHORT -- -- 20 mA Device cannot be damaged when OUT pin is short circuited to GND OUTPSRR_DC -- 69 -- dB tINT_T -- 14.25 20 ms Time after power-up before ready to begin communications and measurement tUPDATE 1.25 -- 9.2 s READ/INT pin low pulse width range to guarantee transfer of digital value to DAC and not enter Read state Read Pulse tREAD 9.8 -- -- s READ/INT pin minimum low pulse width to guarantee entry into Read state Read State Time for Auto-Sleep State tSLEEP 1.088 1.14 1.203 s Transition From Sleep State to Start of Integration Period tSLEEP_TO_INT -- -- 86 s Transition From Read State to Start of Integration Period tREAD_TO_INT -- -- 30 s DAC and OUT Amplifier Characteristics Output Voltage Swing Output Gain Error OUT Short Circuit OUT Power Supply Rejection Ratio, DC, Referenced to Input Integration and Read Timing Time to First Communications Update Pulse 2012-2016 Microchip Technology Inc. DS20005293D-page 5 PAC1921 TABLE 1-1: ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40C to +85C, VDD = 3V to 5.5V, VBUS = 0V to 32V; typical values are at TA = +25C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ - SENSE-) = 0V Characteristic Sym. Min. Typ. Max. Unit Conditions Digital I/O Pins (READ/INT, SMBus pins) Output Low Voltage VOL -- -- 0.4 V Input High Voltage VIH 2.0 -- -- V Input Low Voltage VIL -- -- 0.8 V Leakage Current ILEAK -5 -- 5 A TABLE 1-2: Sinking 8 mA Powered or unpowered, TA < +85C maximum SMBUS MODULE SPECIFICATIONS Electrical Characteristics: Unless otherwise specified, maximum values are at TA = -40C to +85C, VDD = 3V to 5.5V, VBUS = 0V to 32V; typical values are at TA = +25C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ - SENSE-) = 0V Characteristic Sym. Min. Typ. Max. Units Conditions CIN -- 4 10 pF fSMB 10 -- 400 kHz Spike Suppression tSP 0 -- 50 ns Bus Free Time Stop to Start tBUF 1.3 -- -- s Start Setup Time tSU:STA 0.6 -- -- s Start Hold Time tHD:STA 0.6 -- -- s Stop Setup Time tSU:STO 0.6 -- -- s Data Hold Time tHD:DAT 0 -- -- s When transmitting to the master Data Hold Time tHD:DAT 0.3 -- -- s When receiving from the master SMBus Interface Input Capacitance SMBus Timing Clock Frequency Pulse width of spikes that must be suppressed by the input filter Data Setup Time tSU:DAT 0.6 -- -- s Clock Low Period tLOW 1.3 -- -- s Clock High Period tHIGH 0.6 -- -- s Clock/Data Fall Time tFALL -- -- 300 ns Minimum = 20 + 0.1 CLOAD ns tRISE -- -- 300 ns Minimum = 20 + 0.1 CLOAD ns CLOAD -- -- 400 pF Total per bus line Clock/Data Rise Time Capacitive Load Time Out tTIMEOUT 25 -- 35 ms Disabled by default Idle Reset tIDLE_RESET 350 -- -- s Disabled by default (see Section 5.2 "SMBus Timeout") DS20005293D-page 6 2012-2016 Microchip Technology Inc. PAC1921 TLOW THIGH THD:STA TRISE SMCLK T THD:STA HD:DAT TSU:STO TFALL TSU:DA TSU:STA T SMDATA TBUF P FIGURE 1-1: S S - Start Condition S P - Stop Condition P SMBus Timing. 2012-2016 Microchip Technology Inc. DS20005293D-page 7 PAC1921 NOTES: DS20005293D-page 8 2012-2016 Microchip Technology Inc. PAC1921 2.0 TYPICAL OPERATING CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 500 480 460 440 420 400 380 360 340 320 300 38 +85C 37 +25C ISENSE+ (A) IDD (A) Note: Unless otherwise specified, maximum values are at TA = -40C to 85C, VDD = 3V to 5.5V, VBUS = 0V to 32V; typical values are at TA = 25C, VDD = 3.3V, VBUS = 24V, VSENSE = (SENSE+ - SENSE-) = 0V -40C +85C 36 +25C 35 -40C 34 33 32 3.0 3.5 4.0 4.5 5.0 5.5 0 20 40 60 VSENSE FSR (%) VDD (V) 0.50 400 380 360 340 320 300 280 260 240 220 200 0.40 +85 C +25 C -40 C 0.30 0.20 -40C +25C +85C 0.10 0.00 3.0 3.5 4.0 4.5 VDD (V) 5.0 +85 C +25 C -40 C 3.0 3.5 4.0 4.5 5.0 VDD (V) FIGURE 2-3: Sleep State IDD vs. VDD (VBUS = 24, VSENSE = 0V). 2012-2016 Microchip Technology Inc. 20 40 60 VSENSE FSR (%) 80 100 FIGURE 2-5: ISENSE- Input Current vs. VSENSE - Integrate State (VBUS = 24V, VSENSE = 100 mV). ISENSE+ (A) 20 18 16 14 12 10 8 6 4 2 0 0 5.5 FIGURE 2-2: Read State IDD vs. VDD (VBUS = 24, VSENSE = 0V). IDD (A) 100 FIGURE 2-4: ISENSE+ Input Current vs. VSENSE - Integrate State. ISENSE- (A) IDD (A) FIGURE 2-1: Integrate State IDD vs. VDD (VBUS = 24V, VSENSE = 0V). 80 5.5 44 40 36 32 28 24 20 16 12 8 4 0 -40C +25C +85C VDD = 3.3V Crossover Point 0 4 8 12 16 VBUS (V) 20 24 28 32 FIGURE 2-6: ISENSE+ Input Current vs. Common-Mode Voltage (VBUS) Integrate State (VDD = 3.3V, VSENSE = 100 mV). DS20005293D-page 9 10 0.20 5 0.15 0 0.10 -5 -10 -15 -20 Output Offset Input Offset -25 Error (%) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 Input VOFFSET (V) Output VOFFSET (mV) PAC1921 -25 -10 5 20 35 50 Temperature (C) 65 0.00 -0.05 -0.10 -0.15 -0.20 -30 -40 0.05 -40 80 FIGURE 2-7: Current Sense Offset vs. Temperature (VBUS = 24V, VSENSE = 100 mV). 3,000 0.30 2,500 2,000 VOUT (mV) Gain Error (%) 0.20 0.00 -0.10 -0.20 60 85 3V Range 2V Range 1.5V Range 1V Range 1,500 1,000 500 -0.30 -0.40 -40 -15 10 35 60 85 0 0.000 Temperature (C) FIGURE 2-8: Current Sense Gain Error vs. Temperature (VBUS = 24V, VSENSE = 98 mV). VBUS Error (%) 10 35 Temperature (C) FIGURE 2-10: Current Sense Offset vs. Temperature (VBUS = 32V, VSENSE = 98 mV). 0.40 0.10 -15 0.5 0.4 0.3 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 0.020 0.040 0.060 VSENSE (V) 0.080 0.100 FIGURE 2-11: VOUT vs. VSENSE (VDD = 3.3V, VBUS = 24V). -40C +25C +85C 0 4 8 12 16 VBUS (V) 20 24 28 32 FIGURE 2-9: VBUS Voltage Measurement Accuracy vs. Temperature (VDD = 3.3V, VSENSE = 98 mV). DS20005293D-page 10 FIGURE 2-12: DAC Setting Time. 2012-2016 Microchip Technology Inc. PAC1921 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PAC1921 3x3 VDFN PIN DESCRIPTION Symbol Type (See Table 3-2) 1 VDD Power Positive Power Supply Voltage 2 SENSE+ AIO40 VBUS/VSENSE+ input 3 SENSE- AIO40 VSENSE- input 4 OUT AIO5 Measurement Output Voltage 5 GND Power Ground 6 ADDR_SEL AIO2 Selects SMBus/I2C Address 7 RESERVED DI (5V) Reserved for future use. Connect to VDD for SMBus functionality. 8 READ/INT DI 9 SM_DATA DIOD SM_DATA: SMBus/I2C Data - requires pull-up resistor 10 SM_CLK DI (5V) SM_CLK: SMBus/I2C Clock - requires pull-up resistor 11 EP - Not internally connected, but recommend grounding. TABLE 3-2: Pin Type PIN TYPES DESCRIPTION Description Power This pin is used to power to the device. AIO40 Analog Input/Output - this pin is used as an I/O for analog signals. Maximum voltage is 40V. AIO5 Analog Input Output - this pin is used as an I/O for analog signals. Maximum voltage is 5V. AIO2 DI DIOD 3.1 Function Analog Input/Output - this pin is used as an I/O for analog signals. Maximum voltage is 2V. Digital Input - this pin is used for digital inputs. Digital Input/Output Open-Drain - this pin is used for digital I/O and is open-drain. Positive Power Supply Voltage (VDD) Controls power states 3.3 Measurement Output Voltage (Out) The OUT pin provides an analog voltage based on the upper 10 bits of the latest calculation. This pin can be programmed for 1.0, 1.5, 2.0 and 3.0V output swings. 3.4 Ground (GND) System ground. 3.5 SMBus/I2C Address (ADDR_SEL) Address selection for the SMBus Slave address, based on the pull-down resistor. 3.6 COMM_SEL Reserved for future use, connect to VDD for SMBus operability. 3.7 Power States (READ/INT) This pin controls the current state of the device, either in the INTEGRATE state, or in the READ state. Power supply input Voltage ranging from 3.0 to 5.5 VDC. 3.8 3.2 This is the bidirectional SMBus data pin. This pin is open-drain and requires a pull-up resistor. VBUS/VSENSE+ Input/VSENSE- Input (SENSE+/SENSE-) These two pins form the differential input for measuring voltage across a sense resistor in the application. The positive input (Sense+) also acts as the input pin for bus voltage. 3.9 SMBus/I2C Data (SM_DATA) SMBus/I2C Clock (SM_CLK) This is the SMBus clock pin. This pin is open-drain and requires a pull-up resistor. 3.10 Exposed Thermal Pad (EP) This pad should be connected to ground for noise immunity. 2012-2016 Microchip Technology Inc. DS20005293D-page 11 PAC1921 NOTES: DS20005293D-page 12 2012-2016 Microchip Technology Inc. PAC1921 4.0 GENERAL DESCRIPTION measures the voltage (VSENSE) developed across an external sense resistor to represent the high-side supply current. The full-scale range of VSENSE is from 0 mV to 100 mV. For power, the current and voltage data is multiplied and accumulated, scaled with two digital gain parameters, then applied to the OUT pin through a 10-bit DAC and a gain output buffer for the output FSR. The PAC1921 is a dedicated power monitoring device with a configurable output: Power, Current, or Voltage. The OUT pin supplies data for systems that cannot tolerate the latencies inherent in embedded communications buses. MCU-based systems equipped with ADC inputs can sample the value presented on the OUT pin for immediate use in thermal or power control algorithms. Output values are also available in a digital format via the SMBus interface. The PAC1921 contains a high-side precision current-sensing circuit and a precision bus voltage measurement circuit. The current-sensing circuit contains a differential amplifier that continuously 3.0V to 5.5V ISENSE RSENSE VBUS = 0V to 32V VBUS The integration time is variable depending on the measurement type, the resolution setting (11-bit or 14-bit), the post filter settings and the number of samples. A system diagram using the PAC1921 in SMBus mode is shown in Figure 4-1. Load SENSE+ SENSE- 3.0V to 5.5V VDD PAC1921 SM_CLK SMCLK SM_DATA SM_DATA RESERVED READ/INT GPIO ADDR_SEL OUT MCU ADC GND FIGURE 4-1: 4.1 PAC1921 System Diagram - SMBus Mode. VDD Pin RC Filter For optimal rejection of AC power supply noise, an RC filter comprised of a 100 resistor and a 1 F capacitor is required on the 3.3V VDD pin. 4.2 4.3 Use Cases The following examples illustrate application of the PAC1921 device. Figure 4-2 demonstrates how to synchronize the power measurement of multiple supply rails using a single GPIO to control the READ/INT pins. OUT Pin RC Filter To minimize the effect of circuit noise induced on the OUT signal trace between the PAC1921 and the receiving ADC, an RC filter comprised of a 100-150 resistor and a 1 nF capacitor is recommended on the OUT pin. This RC filter should ideally be placed near the measurement ADC input. 2012-2016 Microchip Technology Inc. DS20005293D-page 13 PAC1921 28V DC-DC Load 12V DC-DC Load PAC 1921 3.3V DC-DC PAC 1921 Load PAC 1921 VDD MCU SM_CLK SM_DATA READ# / INT PWR_OUT3 PWR_OUT2 PWR_OUT1 FIGURE 4-2: SMCLK SMDATA GPIO ADC ADC ADC Usage Model. Figure 4-3 shows some of the math when filling the registers with maximum values. VBUS 32V VBUS = 0V to 32V 3.0V to 5.5V RSENSE = 0.01 SENSE+ SENSE- ISENSE IBUS 10A 3.0V to 5.5V VDD PAC1921 SMCLK SM_CLK SM_DATA SM_DATA RESERVED READ/INT GPIO ADDR_SEL OUT MCU ADC GND IMAX = VSENSE = 0.01 x 10A = 0.10V = 100 mV (max ILOAD) VSENSE Result Registers (12h, 13h) = FF80h VMAX = 32V VBUS = 32V (max VBUS) VBUS Result Registers (10h, 11h) = FF80h 10A x 32V = 320W Power = VPOWER Result Registers (1Dh, 1Eh) = FF80h (Upper 10 bits of VPOWER Result) OUT Pin (3V FSR) = VPOWER Result 65472 x OUT Pin FSR = FF80h/65472 x 3.0V Calculated Power using OUT pin FIGURE 4-3: DS20005293D-page 14 10A = 2.997V = OUT Pin/OUT Pin FSR x IMAX x VMAX = 2.997/3.0 x 10 x 32 = 319.68W Maximum Value Example. 2012-2016 Microchip Technology Inc. PAC1921 Figure 4-4 illustrates dynamic operating conditions by changing the DI_GAIN value. VBUS 24V VBUS = 0V to 32V 3.0V to 5.5V ISENSE RSENSE = 0.02 SENSE+ IBUS (X)A SENSE- 3.0V to 5.5V VDD PAC1921 SMCLK SM_CLK SM_DATA SM_DATA RESERVED READ/INT GPIO ADDR_SEL OUT MCU ADC GND IMAX = 50A VMAX = 32V PMAX = 1600W OUT FSR = 3V VBUS = 24V OUT Pin ILOAD 1.8V 1.8V 1.8V 1.8V ILOAD = 40A ILOAD = 10A ILOAD = 2.5A ILOAD = 0.625A VPOWER Result represents 9973h 960W 9973h 9973h 9973h (265Ch without DI_GAIN) (997h without DI_GAIN) (265h without DI_GAIN) 240W 60W 15W READ/INT Pin DI_GAIN FIGURE 4-4: 00h (1X) 02h (4X) 04h (16X) 06h (64X) DI_GAIN Effects on OUT Voltage. In this example, the load current decreases from 40A to less than 1A over time. The user is notified of a change through the change in the OUT voltage. The DI_GAIN value is then adjusted to center the measurements again. In this example, the changes in current were factors of four apart. Using the DI_GAIN parameter to adjust the Full Scale value, the analog output maintains good resolution throughout the entire range. 2012-2016 Microchip Technology Inc. DS20005293D-page 15 PAC1921 4.4 Power States tSETTLE The PAC1921 has three power states, as described in the following paragraphs. 4.4.1 READ OUT Pin 0V INTEGRATE STATE In the Integrate state, the device is fully active and integrating in one of two modes: pin-controlled or free-run (see Section 4.7 "Integration"). When the READ/INT pin is driven high, the device is in the Integrate state. Alternatively, when using SMBus, the device can be placed in the Integrate state by enabling the pin override (READ/INT_OVR = 1) and setting the INT_EN bit to `1'. FIGURE 4-5: 4.4.2 4.5 READ STATE The Read state is a lower-power state. When the READ/INT pin is driven low for at least tREAD time (see Section 1.0 "Electrical Characteristics"), the device is in the Read state. When using SMBus, the device can also be placed in the Read state by enabling the pin override (READ/INT_OVR = 1) and setting the INT_EN bit to `0'. The Read state terminates integration, starts the internal sleep timer, transfers the selected measurement to the output DAC, and places the device in a low-power state. The OUT pin will output the latest measurement voltage in the voltage range defined by VOUT until the next time the device enters the Read state (next falling edge of READ/INT, or INT_EN set to `1' and then back to `0') or until the sleep timer expires and the device enters the Sleep state. 4.4.3 0V Internal Intergrator Sleep State READ/INT Pin tSLEEP tSLEEP_TO_INT Sleep State Timing. Measurement Modes The PAC1921 can measure the source-side voltage, VBUS, and the voltage across an external current sense resistor, VSENSE. The device can be configured to perform one of three sets of calculations: Power (see Section 4.5.1 "Power Measurement"), VSENSE (see Section 4.5.2 "VSENSE Measurement") or VBUS (see Section 4.5.3 "VBUS Measurement"). The results of these digital calculations are applied to the analog OUT pin as well as stored in registers available via the communications bus. Figure 4-6 shows the data flow. SLEEP STATE The Sleep state is the lowest-power state. While in this state, the device will draw a supply current of ISLEEP from the VDD pin. By default, the device enters the Sleep state automatically when the READ/INT pin (or INT_EN bit if READ/INT_OVR = 1) is held low for longer than tSLEEP. In SMBus mode, the device can also be put in the Sleep state by setting the SLEEP bit (see Register 6-3). When entering the Sleep state, the device will reset all measurement registers and turn off unnecessary internal biasing and drive circuits to reduce quiescent current to ISLEEP. The device will stay in the Sleep state until it is placed in the Integrate state. The device will transition from Sleep to the start of integration in tSLEEP_TO_INT and start accumulating current and voltage information again. An example of the timing required to enter the Sleep state is shown in Figure 4-5. DS20005293D-page 16 2012-2016 Microchip Technology Inc. PAC1921 I V 40-bit PSUM Accumulator Registers 26-bit ISUM Accumulator Registers 26-bit VSUM Accumulator Registers X DI_GAIN X DV_GAIN X DI_GAIN X DV_GAIN VPOWER Average (divide by # samples) VSENSE Average (divide by # samples) VBUS Average (divide by # samples) 10-bit Power Result Registers (10 MSBs) 10-bit VSENSE Result Registers (10 MSBs) 10-bit VBUS Result Registers (10 MSBs) Measurement Type = Power? Measurement Type = VSENSE? Measurement Type = VBUS? Digital Multiply Yes Yes Yes 10-bit DAC OUT Pin Note: FIGURE 4-6: 4.5.1 Registers not required for the selected measurement type are not populated. PAC1921 Data Flow. POWER MEASUREMENT VBUS and VSENSE are sampled and multiplied during the integration period, resulting in the sum of power for all samples. The power full-scale range is defined in Equation 4-1. The instantaneous values are summed over the integration period. The summed value is then divided by the number of samples, and stored in the VPOWER Results registers. The VPOWER Results registers result can be converted directly to watts using the conversion described in Equation 4-2 for 1 LSB. This result is also sent to the DAC which drives the proportional voltage output on the OUT pin, if it is the selected output. 2012-2016 Microchip Technology Inc. EQUATION 4-1: POWER FSR CALCULATION 0.1V R 32V PowerFSR = ----------------------------- --------------------------- DI_GAIN DV_GAIN Where: 0.1V = Maximum VSENSE voltage input R = RSENSE resistor value DI_GAIN = Digital current gain 32V = Maximum device bus voltage input DV_GAIN = Digital voltage gain DS20005293D-page 17 PAC1921 EQUATION 4-2: 1 LSB Where: POWER LSB WEIGHT 32V 0.1V ------------------------------------- --------------------------DV_GAIN DI GAIN R = -----------------------------------------------------------------------6 1023 2 0.1V = Maximum VSENSE voltage input R = RSENSE resistor value DI_GAIN = Digital current gain 32V/DV_GAIN = Maximum device bus voltage input DV_GAIN = Digital voltage gain 4.5.3 VBUS MEASUREMENT When VBUS is selected as the measurement type, free-run integration is used (see Section 4.7.3 "Free-Run Integration"). The VBUS voltage is digitized and summed in the VSUM Accumulator Registers. The average is taken at the end of the integration period and digital gain is applied by adjusting the parameter DV_GAIN. The upper 10-bit resultant value represents the average VBUS voltage measured and is used to drive the DAC. The PAC1921 should be kept in the Integrate state for continuous output in this mode. The value of one LSB in volts can be calculated according to Equation 4-5. EQUATION 4-5: 4.5.2 VBUS LSB VALUE IN VOLTS VSENSE MEASUREMENT When VSENSE is selected as the measurement type, free-run integration is used (see Section 4.7.3 "Free-Run Integration"). The VSENSE voltage is digitized and summed in the ISUM Accumulator Registers, The average is then taken at the end of the integration period. Finally, digital gain is applied by adjusting the parameter DI_GAIN. The upper 10-bit resultant value represents the average VSENSE voltage measured and is used to drive the DAC. The PAC1921 should be kept in the Integrate state for continuous output in this mode. The value of one LSB in amps can be calculated according to Equation 4-3. EQUATION 4-3: 1 LSB VSENSE LSB VALUE IN AMPS 0.1V --------------------------------------R DI_GAIN = ---------------------------------------6 1023 2 Where: 0.1V = Maximum VSENSE voltage input R = RSENSE resistor value DI_GAIN = Digital current gain 1023 x 26 1 LSB 32V -------------------------DV_GAIN = --------------------------6 1023 2 Where: 1LSB = LSB value in volts 32/DV_GAIN = Maximum voltage 1023 x 26 = FSR shifted 6 bits 4.6 OUT Pin and Measurement Type The OUT pin is driven by a buffered 10-bit DAC. The OUT pin signal is typically sent to an MCU with ADC inputs to supply data for algorithms that cannot tolerate the latencies inherent in embedded communications buses. After a DAC update, the OUT pin can be polled after tSETTLE. The output voltage can also be expressed as a result of the DAC, as shown in Equation 4-6. EQUATION 4-6: OUT PIN VALUE DAC OUT = -----------------------6 OUTFSR 1023 2 = FSR x scale offset Where: The value of one LSB in volts can be calculated according to Equation 4-4. EQUATION 4-4: 1 LSB VSENSE LSB VALUE IN VOLTS 0.1V -----------------------DI_GAIN = ------------------------6 1023 2 OUT = Output on OUT pin DAC = value of the selected measurement result registers 1023 x 26 = FSR x scale offset OUTFSR = Output FSR Where: 0.1V = Maximum VSENSE voltage input DI_GAIN = Digital current gain 1023 x 26 = FSR x scale offset DS20005293D-page 18 2012-2016 Microchip Technology Inc. PAC1921 The OUT Pin can represent Power, Voltage or Current. This measurement type is selected by the MXSL<1:0> bits shown in Table 4-1. TABLE 4-1: MUX_SEL MULTIPLEXER DECODE MXSL<1:0> Selected Output 1 0 0 0 VPOWER pin-controlled (default) 0 1 VSENSE free-run 1 0 VBUS free-run 1 1 VPOWER free-run 4.7.1 PIN-CONTROLLED INTEGRATION In pin-controlled integration mode, the integration period is the time the PAC1921 is in the Integrate state less the state transition time, as shown in Figure 4-7. The power integration period can be any time between ~0.9 ms and ~1s with 11-bit resolution and between ~2.7 ms and ~2.9s with 14-bit resolution. When the PAC1921 is placed in the Read state, measurement is stopped, calculations are made, and the result is latched into the DAC. tREAD_TO_INT To change the MUX_SEL parameter, see Section 4.7.8 "Changing Integration Parameter Settings". The OUT buffer FSR is configurable. The OUT FSR is set by the OFSR<1:0> bits in Control Register 02h, as shown in Table 4-2. TABLE 4-2: OFSR DECODE - SMBUS MODE OFSR<1:0> 4.7 FSR for OUT Pin 1 0 0 0 0 to 3V (default) 0 1 0 to 2V 1 0 0 to 1.5V 1 1 0 to 1V Samples < 2048 Read State Integration Period DAC Updated FIGURE 4-7: Period. Pin-Controlled Integration To obtain an update to the DAC without entering the Read state, the READ/INT pin can be held low for tUPDATE. This eliminates the tREAD_TO_INT delay at the start of the next integration period which occurs when transitioning from Read to Integrate, as shown in Figure 4-8. tREAD_TO_INT or tSLEEP_TO_INT Integration The PAC1921 has two Integrate state (see Section 4.4.1 "Integrate State") operating modes: pin-controlled and free-run. In pin-controlled mode, the measurement type is Power. In free-run mode, the measurement type is Power by default and can be changed in SMBus mode to Voltage or Current. If pin-controlled integration mode is selected, the OUT pin will update to the latest Power value when the PAC1921 is placed in the Read state or when the READ/INT pin is held low for tUPDATE. If free-run is chosen, the OUT pin will update at the conclusion of each integration period. The integration mode is selected by the MXSL<1:0> bits (see Table 4-1). TABLE 4-3: Integrate State (Pin-Controlled Mode) INT_SEL PIN DECODE INT_SEL Pin Voltage Integration Mode GND Pin-controlled VDD Free-run 2012-2016 Microchip Technology Inc. READ/INT Pin tUPDATE Integration Period Integration Period DAC Updated FIGURE 4-8: Pin-Controlled Measurement Time. 4.7.2 MAXIMUM SAMPLES The number of samples is limited to 2048. When the Samples Registers reach their maximum value (2048), integration stops, the calculations are performed, the registers are updated and the results are sent to the OUT pin. DS20005293D-page 19 PAC1921 FREE-RUN INTEGRATION 4.7.4 In free-run integration mode, the integration period is controlled by the selected measurement type, resolution, filtering, and number of samples (see Section 4.7.4 "ADC Resolution, Filtering and Sampling"). The number of samples is controlled by the SMPL bits in the configuration register. The legend for these bits is shown in Table 4-4. SAMPLES IN FREE-RUN MODE Number of Samples 3 2 1 0 0 0 0 0 1 (default) 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 512 1 0 1 0 1024 1 0 1 1 2048 1 1 0 0 2048 1 1 0 1 2048 1 1 1 0 2048 1 1 1 1 2048 In free-run integration, the number of samples is selectable. In free-run SMBus mode, the number of samples is set by the SMPL<3:0> bits (see Register 6-2). The free-run integration period is determined by the selected measurement type, number of samples, resolution and filtering as shown in Table 4-5. 11-bit resolution is recommended if the fastest integration time is required. 14-bit resolution will provide more accurate and highly averaged measurements. TABLE 4-5: DAC Updated DAC Updated Integrate State (Free-Run Mode) Samples Samples Samples Samples Discarded Read State Integration Period FIGURE 4-9: DS20005293D-page 20 Integration Period Integration Period Incomplete Integration Time. Integration Period VSENSE or VBUS Measurement 11-Bit ADC Post Filters Off DAC Updated Integration Period Power measurement 14-bit ADC Post Filters On When the device enters the Read state during an integration period, that data is discarded, as shown in Figure 4-9. FREE RUN INTEGRATION PERIODS Mixed ADC Post Filter On After each integration period is completed, the output value is calculated and the result is latched into the DAC. As long as the device is still in the Integrate state, the next integration period starts after the calculations are complete. Integration is disabled whenever the device enters the Read state. tREAD_TO_INT When Power is selected as the OUT measurement type, the bus voltage and sense resistor voltage are sampled an equal number of times during the integration period in a round-robin scheme (e.g., a VBUS measurement is taken and then a VSENSE measurement is taken for each power sample). When VBUS or VSENSE is selected as the OUT measurement type, only the selected channel is sampled and digitized. 11-Bit ADC Post Filter Off SMPL<3:0> ADC post filtering improves signal quality and increases conversion time by 50%. In SMBus mode, ADC post filtering can be enabled or disabled by using the VSFEN and VBFEN bits (see Register 6-2). 14-bit ADC Post Filter On TABLE 4-4: ADC RESOLUTION, FILTERING AND SAMPLING ADC resolution can be specified at 11 or 14 bits. In SMBus mode, the resolution is set independently for VSENSE and VBUS by using the I_RES and V_RES bits (see Register 6-1). Samples 4.7.3 1 2.72 ms 0.93 ms 2.1 ms 1.41 ms 0.51 ms 2 4.05 ms 1.46 ms 3.1 ms 2.02 ms 0.72 ms 4 6.79 ms 2.41 ms 5.1 ms 3.43 ms 1.24 ms 8 12.2 ms 4.32 ms 9.2 ms 6.06 ms 2.08 ms 16 23 ms 8.05 ms 17.5 ms 11.5 ms 3.95 ms 32 46 ms 16.1 ms 34.9 ms 22.9 ms 7.89 ms 64 92 ms 32.1 ms 70 ms 45.7 ms 15.7 ms 128 184 ms 64.2 ms 139 ms 91.3 ms 31.4 ms 256 368 ms 128.3 ms 278 ms 183 ms 62.7 ms 512 736 ms 257 ms 556 ms 365 ms 126 ms 1024 1471 ms 513 ms 1112 ms 730 ms 251 ms 2048 1026 ms 2223 ms 1460 ms 502 ms 2941ms 2012-2016 Microchip Technology Inc. PAC1921 4.7.5 DI_GAIN SETTING 4.7.7 The DI_GAIN parameter acts as a digital multiplier to control the effective current gain, as described in Equation 4-3. DI_GAIN 1X is the setting for the full-scale range. DI_GAIN can be increased when the system is designed for a lower VSENSE range. It can also be used to provide a larger signal when the system is in a low-power mode. TABLE 4-6: DI_GAIN DECODE DI_GAIN<2:0> DI_GAIN Multiplier Effective VSENSE Range 2 1 0 0 0 0 1X (default) 0 to 100 mV (default) 0 0 1 2X 0 to 50 mV 0 1 0 4X 0 to 25 mV 0 1 1 8X 0 to 12.5 mV 1 0 0 16X 0 to 6.25 mV 1 0 1 32X 0 to 3.125 mV 1 1 0 64X 0 to 1.56 mV 1 1 1 128X 0 to 0.78 mV DI_GAIN is set in the Gain Configuration Register (see Register 6-1) based on Table 4-6. 4.7.6 DI_GAIN OVERFLOW If DI_GAIN is set too high for the input magnitude when VSENSE or VPOWER is selected as the measurement type, it will cause an overflow in the results registers (PSUM_GAINED and IAVG). To provide an indication that the selected gain is too high, the following occurs: Overflow status register 1Ch bit 2 (VSOV) is set to 1b and bit 0 (VPOV) is set to 1b if the power calculation overflowed, too. VSENSE Result Registers are set to the maximum value (12h is set to FFh and 13h is set to C0h). VPOWER Result Registers are set to the maximum value (1Dh is set to FFh and 1Eh is set to C0h). The values in the ISUM Accumulator Registers and PSUM Accumulator Registers will be accurate. In SMBus mode, change the DI_GAIN selection (see Register 6-1), set the RDAC bit (see Register 6-3) and check the results until an effective current gain is selected. 2012-2016 Microchip Technology Inc. DV_GAIN SETTING The DV_GAIN parameter acts as a digital multiplier to control the effective bus voltage gain. DV_GAIN 1X is the setting for the full-scale voltage range. DV_GAIN can be increased when the system is designed for a lower VBUS range. It can also be used to provide a larger signal when the system is in a low-power mode. TABLE 4-7: DV_GAIN DECODE DV_GAIN<2:0> DV_GAIN Multiplier Effective VBUS Range 0 1X (default) 0 to 32V (default) 0 1 2X 0 to 16V 1 0 4X 0 to 8V 0 1 1 8X 0 to 4V 1 0 0 16X 0 to 2V 1 0 1 32X 0 to 1V 1 1 0 32X 0 to 1V 1 1 1 32X 0 to 1V 2 1 0 0 0 0 0 DV_GAIN is set in the Gain Configuration Register (see Register 6-1) as shown in Table 4-7. 4.7.7.1 DV_GAIN Overflow If DV_GAIN is too high for the range being measured when VBUS or VPOWER is selected as the measurement type, it will cause an overflow in the results registers. To provide an indication that the selected gain is too high, the following occurs: Overflow status register 1Ch bit 1 (VBOV) is set to 1b and bit 0 (VPOV) is set to 1b if the power calculation overflowed, too. VBUS Result Register 10h is set to FFh and VBUS Result Register 11h is set to C0h. VPOWER Result Register 1Dh is set to FFh and VPOWER Result Register 1Eh is set to C0h. The values in the VSUM Accumulator Registers and PSUM Accumulator Registers will be accurate. In SMBus mode, change the DV_GAIN selection in Register 6-1 to match the range of the bus being measured. Set the RDAC bit in the same register and check the results. DS20005293D-page 21 PAC1921 4.7.8 CHANGING INTEGRATION PARAMETER SETTINGS The integration parameter settings I_RES, V_RES, SMPL, VSFEN and VBFEN can be changed by first putting the device in the Read state (see Section 4.4 "Power States"), then changing the applicable registers. If one of these parameters is changed while the device is in the Integrate state, the change will not take effect until after the device has been placed into the Read state and then back into the Integrate state. DI_GAIN and DV_GAIN can also be updated in the Read state; however, the effects can be seen while in Read by setting the RDAC bit to recalculate the last measurement using the new gain settings. If the integration mode is changed from VPOWER pin-controlled while the device is in the Integrate state, the device will terminate the Power measurement, update the OUT pin and then switch to the new measurement/integration mode. If the integration mode is changed from VPOWER free-run, VSENSE or VBUS while the device is in the Integrate state, the device will complete the integration period, update the OUT pin and then switch to the new measurement/integration mode. DS20005293D-page 22 2012-2016 Microchip Technology Inc. PAC1921 5.0 COMMUNICATIONS PROTOCOL The PAC1921 communicates with a host controller, such as an PIC MCU, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 1-1. For the first 15 ms after power-up, the device may not respond to SMBus communications. 5.1 SMBus Control Bits The interaction between clock and data creates special function bits within the data stream. 5.1.1 SMBUS START BIT The SMBus Start bit is defined as a transition of the SMBus Data line from a logic `1' state to a logic `0' state while the SMBus Clock line is in a logic `1' state. 5.1.2 SMBUS ADDRESS AND RD/WR BIT The SMBus Address Byte consists of the 7-bit client address followed by the RD/WR indicator bit. If this RD/WR bit is a logic `0', the SMBus Host is writing data to the client device. If this RD/WR bit is a logic `1', the SMBus Host is reading data from the client device. The PAC1921 SMBus address is determined by a single pull-down resistor connected between ground and the ADDR_SEL pin as shown in Table 5-1. TABLE 5-1: ADDR_SEL RESISTOR SETTING Resistor (5%) SMBus Address 0 1001_100(r/w) 120 1001_101(r/w) 220 1001_110(r/w) 330 1001_111(r/w) 470 1001_000(r/w) 620 1001_001(r/w) 820 1001_010(r/w) 1000 1001_011(r/w) 1300 0101_000(r/w) 1800 0101_001(r/w) 2200 0101_010(r/w) 3000 0101_011(r/w) 4300 0101_100(r/w) 6800 0101_101(r/w) 12000 0101_110(r/w) open 0011_000((r/w) 2012-2016 Microchip Technology Inc. 5.1.3 SMBUS DATA BYTES All SMBus Data bytes are sent most significant bit first and composed of eight bits of information. 5.1.4 SMBUS ACK AND NACK BITS The SMBus client will acknowledge all data bytes that it receives. This is done by the client device pulling the SMBus data line low after the 8th bit of each byte that is transmitted. The host will NACK (not acknowledge) the last data byte to be received from the client by holding the SMBus data line high after the 8th data bit has been sent. 5.1.5 SMBUS STOP BIT The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic `0' state to a logic `1' state while the SMBus clock line is in a logic `1' state. When the device detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its client interface and prepare to receive further communications. 5.2 SMBus Timeout The PAC1921 supports SMBus Timeout. If the clock line is held low for longer than tTIMEOUT, the device will reset its SMBus protocol. This function can be enabled by setting the TIMEOUT bit (see Register 6-3). 5.3 SMBus and I2C Compatibility The PAC1921 is compatible with SMBus and I2C. The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus 2.0 and I2C specifications. For information on using the PAC1921 in an I2C system, refer to AN 14.0 - "Microchip Dedicated Slave Devices in I2C Systems" (DS00001853). * PAC1921 supports I2C fast mode at 400 kHz. This covers the SMBus max time of 100 kHz. * Minimum frequency for SMBus communications is 10 kHz. * The SMBus client protocol will reset if the clock is held at a logic `0' for longer than 30 ms. This timeout functionality is disabled by default in the PAC1921 and can be enabled by writing to the TIMEOUT bit. I2C does not have a time out. * I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). * I2C devices support Block Read and Block Write differently. I2C protocol allows for an unlimited number of bytes to be sent in either direction. The SMBus protocol requires that an additional data byte indicating number of bytes to read/write is transmitted. The PAC1921 supports I2C formatting only. DS20005293D-page 23 PAC1921 Attempting to communicate with the PAC1921 SMBus interface with an invalid slave address or invalid protocol will result in no response from the device and will not affect its register contents. Stretching of the SMCLK signal is supported, provided other devices on the SMBus control the timing. 5.4 SMBus Protocols The device supports Send Byte, Read Byte, Write Byte, Receive Byte, and the Alert Response Address as valid protocols as shown below. All of the below protocols use the convention in Table 5-2. TABLE 5-2: PROTOCOL FORMAT Data Sent to Device Data Sent to the Host # of bits sent # of bits sent 5.4.1 WRITE BYTE The Write Byte is used to write one byte of data to the registers, as shown in Table 5-3. TABLE 5-3: WRITE BYTE PROTOCOL START Slave Address WR ACK Register Address ACK Register Data ACK STOP 10 YYYY_YYY 0 0 XXh 0 XXh 0 01 5.4.2 READ BYTE The Read Byte protocol is used to read one byte of data from the registers as shown in Table 5-4. TABLE 5-4: READ BYTE PROTOCOL START Slave Address WR ACK Register Address ACK START Slave Address RD ACK Register Data NACK STOP 1 0 YYYY_YYY 0 0 XXh 0 10 YYYY_YYY 1 0 XXh 1 01 5.4.3 SEND BYTE The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 5-5. TABLE 5-5: SEND BYTE PROTOCOL START Slave Address WR ACK Register Address ACK STOP 10 YYYY_YYY 0 0 XXh 0 01 DS20005293D-page 24 2012-2016 Microchip Technology Inc. PAC1921 5.4.4 RECEIVE BYTE The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 5-6. TABLE 5-6: RECEIVE BYTE PROTOCOL START Slave Address RD ACK Register Data NACK STOP 10 YYYY_YYY 1 0 XXh 1 01 I2C Protocols 5.5 The PAC1921 supports I2C Block Read and Block Write. The protocols listed below use the convention in Table 5-2. 5.5.1 BLOCK WRITE The Block Write protocol is used to write multiple data bytes to a group of contiguous registers, as shown in Table 5-7. TABLE 5-7: BLOCK WRITE PROTOCOL START Slave Address WR ACK Register Address ACK Register Data ACK 10 YYYY_YYY 0 0 XXh 0 XXh 0 Register Data ACK Register Data ACK Register Data ACK STOP XXh 0 XXh 0 XXh 0 01 5.5.2 BLOCK READ The Block Read protocol is used to read multiple data bytes from a group of contiguous registers, as shown in Table 5-8. TABLE 5-8: BLOCK READ PROTOCOL START Slave Address WR ACK Register Address 10 YYYY_YYY ACK Register Data 0 XXh 0 0 ACK Register Data 0 XXh 2012-2016 Microchip Technology Inc. ACK START Slave Address XXh 0 10 YYYY_YYY ACK Register Data 0 RD ACK Register Data 1 0 XXh ACK Register Data NACK STOP 0 XXh 1 01 DS20005293D-page 25 PAC1921 NOTES: DS20005293D-page 26 2012-2016 Microchip Technology Inc. PAC1921 6.0 REGISTER DESCRIPTION The registers shown in Table 6-1 are accessible through the SMBus. In the individual register tables that follow, an entry of `--' indicates that the bit is not used and will always read `0'. Register Address TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER Register Name BIT 7 BIT 6 BIT 5 BIT 4 V_RES DIGN2 DIGN1 BIT 3 BIT 2 00h Gain Configuration I_RES 01h Integration Configuration SMPL3 SMPL2 SMPL1 SMPL0 VSFEN VBFEN 02h Control MXSL1 MXSL0 OFSR1 OFSR0 10h VBUS Result High Byte VBR9 VBR8 VBR7 VBR6 VBR5 VBR4 11h VBUS Result Low Byte VBR1 VBR0 -- -- -- 12h VSENSE Result High Byte VSR9 VSR8 VSR7 VSR6 13h VSENSE Result Low Byte VSR1 VSR0 -- -- 14h VSUM Accumulator High Byte 15h BIT 1 BIT 0 DIGN0 DVGN2 DVGN1 DVGN0 00h INTEN 0Ch RDAC 00h VBR3 VBR2 00h -- -- -- 00h VSR5 VSR4 VSR3 VSR2 00h -- -- -- -- 00h VSM24 VSM23 VSM22 VSM21 VSM20 VSM19 VSM18 VSM17 00h VSUM Accumulator Middle High Byte VSM16 VSM15 VSM14 VSM13 VSM12 VSM11 VSM10 VSM9 00h 16h VSUM Accumulator Middle Low Byte VSM8 VSM7 VSM6 VSM5 VSM4 VSM3 VSM2 VSM1 00h 17h VSUM Accumulator Low Byte VSM0 -- -- -- -- -- -- -- 00h 18h ISUM Accumulator High Byte ISM24 ISM23 ISM22 ISM21 ISM20 ISM19 ISM18 ISM17 00h 19h ISUM Accumulator Mid-high Byte ISM16 ISM15 ISM14 ISM13 ISM12 ISM11 ISM10 ISM9 00h 1Ah ISUM Accumulator Mid-low Byte ISM8 ISM7 ISM6 ISM5 ISM4 ISM3 ISM2 ISM1 00h 1Bh ISUM Accumulator Low Byte ISM0 -- -- -- -- -- -- -- 00h 1Ch Overflow Status -- -- -- -- -- VSOV VBOV VPOV 00h 1Dh VPOWER Result High Byte VPR9 VPR8 VPR7 VPR6 VPR5 VPR4 VPR3 VPR2 00h 1Eh VPOWER Result Low Byte VPR1 VPR0 -- -- -- -- -- -- 00h 21h Samples High Byte SMP11 SMP10 SMP9 SMP8 SMP7 SMP6 SMP5 SMP4 00h SMP2 SMP1 SMP0 -- -- -- TOUT RIOV Default Value SLEEP SLPOV 22h Samples Low Byte SMP3 -- 00h 23h PSUM Accumulator High Byte PSM38 PSM37 PSM36 PSM35 PSM34 PSM33 PSM32 PSM31 00h 24h PSUM Accumulator Middle-High Byte PSM30 PSM29 PSM28 PSM27 PSM26 PSM25 PSM24 PSM23 00h 2012-2016 Microchip Technology Inc. DS20005293D-page 27 PAC1921 Register Address TABLE 6-1: REGISTER SET IN HEXADECIMAL ORDER (CONTINUED) Register Name BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Default Value 25h PSUM Accumulator Middle Byte PSM22 PSM21 PSM20 PSM19 PSM18 PSM17 PSM16 PSM15 00h 26h PSUM Accumulator Middle-Low Byte PSM14 PSM13 PSM12 PSM11 PSM10 PSM9 PSM8 PSM7 00h 27h PSUM Accumulator Low Byte PSM6 PSM3 PSM1 PSM0 -- 00h PSM5 PSM4 PSM2 FDh Product ID PID7 PID6 PID5 PID4 PID3 PID2 PID1 PID0 5Bh FEh Manufacturer ID MID7 MID6 MID5 MID4 MID3 MID2 MID1 MID0 5Dh FFh Revision RID7 RID6 RID5 RID4 RID3 RID2 RID1 RID0 82h 6.1 Read Multiple Data Bytes Data represented by multiple byte data registers are guaranteed to be synchronized and stable in the Read and Sleep states after transitioning from the Integrate state and waiting for tSETTLE time (see Table 1-2). During the Integrate state, the data bytes will be changing dynamically. DS20005293D-page 28 2012-2016 Microchip Technology Inc. PAC1921 6.2 Detailed Register Description REGISTER 6-1: R/W-0 I_RES bit 7 GAIN CONFIGURATION REGISTER (ADDRESS 00H) R/W-0 V_RES bit 6 bit 5-3 bit 2-0 R/W-0 DI_GAIN<2:0> R/W-0 R/W-0 R/W-0 DV_GAIN<2:0> R/W-0 bit 0 Legend: R = Read bit -n = Value at POR bit 7 R/W-0 W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown I_RES: Sets the VSENSE ADC measurement resolution 1 = VSENSE ADC measurement resolution is 11-bit 0 = VSENSE ADC measurement resolution is 14-bit V_RES: Sets the VBUS ADC measurement resolution 1 = VBUS ADC measurement resolution is 11-bit 0 = VBUS ADC measurement resolution is 14-bit DI_GAIN<2:0>: Selects the digital current gain, 000b = 1x 001b = 2x 010b = 4x 011b = 8x 100b = 16x 101b = 32x 110b = 64x 111b = 128x DV_GAIN<2:0>: Selects the digital bus voltage gain. 000b = 1x 001b = 2x 010b = 4x 011b = 8x 100b = 16x 101b = 32x 110b = 32x 111b = 32x 2012-2016 Microchip Technology Inc. DS20005293D-page 29 PAC1921 REGISTER 6-2: R/W-0 INTEGRATION CONFIGURATION REGISTER (ADDRESS 01H) R/W-0 R/W-0 SMPL<3:0> bit 7 Legend: RC = Read-then-clear bit -n = Value at POR bit 7-4 bit 3 bit 2 bit 1 bit 0 W = Writable bit `1' = bit is set R/W-0 R/W-1 VSFEN R/W-1 VBFEN R/W-0 RIOV R/W-0 INTEN bit 0 U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SMPL<3:0>: Controls the number of samples of the selected measurement type. 0000b = 1 0001b = 2 0010b = 4 0011b = 8 0100b = 16 0101b = 32 0110b = 64 0111b = 128 1000b = 256 1001b = 512 1010b = 1024 1011b = 2048 1100b = 2048 1101b = 2048 1110b = 2048 1111b = 2048 VSFEN: enables the ADC post filter for VSENSE samples. When the filter is enabled, conversion time is increased by 50% 1 = Filter enabled 0 = Filter disabled VBFEN: enables the ADC post filter for VBUS samples. When the filter is enabled, conversion time is increased by 50% 1 = Filter enabled 0 = Filter disabled RIOV: enables the INT_EN bit to override the READ/INT pin. 1 = Override enabled 0 = Override not enabled INTEN: forces the device into integrate mode, overriding the READ/INT pin. 1 = Forced Integrate mode 0 = Forced Read State DS20005293D-page 30 2012-2016 Microchip Technology Inc. PAC1921 REGISTER 6-3: CONTROL REGISTER (ADDRESS 02H) R/W-0 R/W-0 MXSL<1:0> bit 7 Legend: RC = Read-then-clear bit -n = Value at POR bit 7-6 bit 5-4 bit 3 bit 2 bit 1 bit 0 R/W-0 R/W-0 OFSR<1:0> W = Writable bit `1' = bit is set R/W-0 TOUT R/W-0 SLEEP R/W-0 SLPOV R/W-0 RDAC bit 0 U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown MXSL<1:0>: Selects which digital value is used for input to the OUT DAC and the integration mode 00 = VPOWER pin-controlled (default) 01 = VSENSE free-run 10 = VBUS free-run 11 = VPOWER free-run OFSR<1:0>: Determines the OUT pin full-scale range 00b = 3V FSR 01b = 2V FSR 10b = 1.5V FSR 11b = 1.0V FSR TOUT: Enables the time out and idle reset functionality of the communications protocol (see Section 5.2 "SMBus Timeout"). 1 = Time out enabled 0 = Time out disabled SLEEP: When the device is in the Read state, writing this bit to a `1' places the device in Sleep state. 1 = Sleep State 0 = Normal operation SLPOV: Sleep override. Writing a `1' disables the Sleep state timer, allowing the PAC1921 to remain in the Read state after tSLEEP. 1 = Forced Read mode 0 = Normal operation RDAC: Forces the device to recalculate the selected measurement, and output immediately to the DAC 1 = Forced recalculate/DAC update mode 0 = Normal operation REGISTER 6-4: R-0 VBUS RESULT REGISTER (ADDRESSES 10H AND 11H) R-0 R-0 R-0 R-0 R-0 R-0 R-0 VBR<9:2> bit 15 bit 8 R-0 R-0 VBR<1:0> U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 U-0 -- W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown VBR<9:0>: These registers contain the most recent digitized value of the average of VBUS samples. Unimplemented: Read as `0' 2012-2016 Microchip Technology Inc. DS20005293D-page 31 PAC1921 REGISTER 6-5: R-0 VSENSE RESULT REGISTER (ADDRESSES 12H AND 13H) R-0 R-0 R-0 R-0 R-0 R-0 R-0 VSR<9:2> bit 15 bit 8 R-0 R-0 VSR<1:0> U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown VBR<9:0>: These registers contain the most recent digitized value of the average of VSENSE samples Unimplemented: Read as `0' REGISTER 6-6: R-0 VSUM ACCUMULATOR REGISTER (ADDRESSES 14H THROUGH 17H) R-0 R-0 R-0 R-0 VSM<24:17> R-0 R-0 bit 31 R-0 bit 24 R-0 R-0 R-0 R-0 R-0 VSM<16:9> R-0 R-0 bit 23 R-0 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 VSM<8:1> bit 15 bit 8 R-0 VSM0 bit 7 U-0 -- bit 6-0 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0 Legend: R = Readable bit -n = Value at POR bit 31-7 U-0 -- W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown VSM<24:0>: These registers contain the accumulated sum of VBUS samples (VSUM) This is the number of 14-bit ADC counts. For 11-bit ADC resolution, the bits are shifted left by 3, so 1 count has a bit weighting of 8 and the lowest 3 bits will not be populated. The register value is only valid in the Read state. Unimplemented: Read as `0' DS20005293D-page 32 2012-2016 Microchip Technology Inc. PAC1921 REGISTER 6-7: R-0 ISUM ACCUMULATOR REGISTER (ADDRESSES 18H THROUGH 1BH) R-0 R-0 R-0 R-0 ISM<24:17> R-0 R-0 R-0 bit 31 bit 24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ISM<16:9> bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ISM<8:1> bit 15 bit 8 R-0 ISM0 bit 7 U-0 -- bit 6-0 U-0 -- W = Writable bit `1' = bit is set U-0 -- Legend: R = Readable bit -n = Value at POR bit 0 U-0 -- U-0 -- U-0 -- U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown OVERFLOW STATUS REGISTER (ADDRESS 1CH) U-0 -- bit 7 bit 1 U-0 -- ISM<24:0>: These registers contain the accumulated sum of VSENSE samples (ISUM). This is the number of 14-bit ADC counts. For 11-bit ADC resolution, the bits are shifted left by 3, so 1 count has a bit weighting of 8 and the lowest 3 bits will not be populated. The register value is only valid in the Read state. Unimplemented: Read as `0' REGISTER 6-8: bit 7-3 bit 2 U-0 -- bit 0 Legend: R = Readable bit -n = Value at POR bit 31-7 U-0 -- W = Writable bit `1' = bit is set U-0 -- U-0 -- R-0 VSOV R-0 VBOV R-0 VPOV bit 0 U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' VSOV: This bit is set to `1' when the DI_GAIN setting causes the VSENSE Result register to overflow 1 = Overflow occurred 0 = Normal operation VBOV: This bit is set to `1' when the DV_GAIN setting causes the VBUS Result register to overflow. 1 = Overflow occurred 0 = Normal operation VPOV: This bit is set to `1' when the DI_GAIN and/or DV_GAIN settings cause the VPOWER Result register to overflow 1 = Overflow occurred 0 = Normal operation 2012-2016 Microchip Technology Inc. DS20005293D-page 33 PAC1921 REGISTER 6-9: R-0 VPOWER RESULT REGISTER (ADDRESSES 1DH AND 1EH) R-0 R-0 R-0 R-0 R-0 R-0 R-0 VPR<9:2> bit 15 bit 8 R-0 R-0 U-0 -- VPR<1:0> U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown VPR<9:0>: These registers store the digitized value of the latest representation of the power relative to maximum power. Unimplemented: Read as `0' REGISTER 6-10: R-0 SAMPLES REGISTERS (ADDRESSES 21H AND 22H) R-0 R-0 R-0 R-0 SMP<11:4> R-0 R-0 R-0 bit 15 bit 8 R-0 R-0 R-0 SMP<3:0> R-0 U-0 -- U-0 -- U-0 -- U-0 -- bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3-0 W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown SMP<11:0>: These register values indicate the number of voltage samples (pairs of samples for power) taken during the integration period. Unimplemented: Read as `0' DS20005293D-page 34 2012-2016 Microchip Technology Inc. PAC1921 REGISTER 6-11: R-0 PSUM ACCUMULATOR REGISTER (ADDRESSES 23H THROUGH 27H) R-0 R-0 R-0 R-0 PSM<38:31> R-0 R-0 bit 39 R-0 bit 32 R-0 R-0 R-0 R-0 R-0 PSM<30:23> R-0 R-0 bit 31 R-0 bit 24 R-0 R-0 R-0 R-0 R-0 PSM<22:15> R-0 R-0 bit 23 R-0 bit 16 R-0 R-0 R-0 R-0 R-0 PSM<14:7> R-0 R-0 R-0 bit 15 bit 8 R-0 U-0 U-0 U-0 PSM<5:1> U-0 U-0 U-0 U-0 -- bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 39-1 bit 0 W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PSM<38:1>: These registers contain the accumulated sum of power samples (PSUM). This is the number of 14-bit ADC counts. For 11-bit ADC resolution, the bits are shifted left by 6, so 1 count has a bit weighting of 64 and the lowest 6 bits will not be populated. The register value is only valid in the Read state. Unimplemented: Read as `0' REGISTER 6-12: R-0 PRODUCT ID REGISTER (ADDRESS FDH) R-1 R-0 R-1 R-1 R-0 R-1 R-1 PID<7:0> bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown PID<7:0>: This register contains the Product ID for the PAC1921. 2012-2016 Microchip Technology Inc. DS20005293D-page 35 PAC1921 REGISTER 6-13: R-0 MANUFACTURER ID REGISTER (ADDRESS FEH) R-1 R-0 R-1 R-1 R-1 R-0 R-1 MID<7:0> bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown MID<7:0>: The Manufacturer ID register identifies Microchip as the manufacturer of the PAC1921 REGISTER 6-14: R-1 REVISION ID REGISTER (ADDRESS FFH) R-0 R-0 R-0 R-0 R-0 R-1 R-0 RID<7:0> bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit `1' = bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown RID<7:0>: The Revision register identifies the die revision. DS20005293D-page 36 2012-2016 Microchip Technology Inc. PAC1921 7.0 PACKAGING INFORMATION 7.1 Package Marking Information 10-Lead VDFN (3x3x0.9 mm) Example 1C03 256A 1CWW NNNA e4 e4 PIN 1 PIN 1 Legend: Y WW NNN <R> <COO> Note: Year code (last digit of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Package Country of origin In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2012-2016 Microchip Technology Inc. DS20005293D-page 37 PAC1921 10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D 1 A B 2 NOTE 1 E (DATUM B) (DATUM A) 2X 0.10 C N 2X TOP VIEW 0.10 C 0.10 C A1 C A SEATING PLANE 10X (A3) SIDE VIEW 0.05 C D2 N E2 NOTE 1 L 1 K 2 10X b 0.10 0.05 e C A B C BOTTOM VIEW Microchip Technology Drawing C04-206A Sheet 1 of 2 DS20005293D-page 38 2012-2016 Microchip Technology Inc. PAC1921 10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Terminals e Pitch A Overall Height Standoff A1 (A3) Terminal Thickness Overall Length D Exposed Pad Length D2 Overall Width E Exposed Pad Width E2 b Terminal Width L Terminal Length K Terminal-to-Exposed-Pad MIN 0.80 0.00 2.20 1.50 0.18 0.35 0.25 MILLIMETERS NOM 10 0.50 BSC 0.85 0.02 0.20 REF 3.00 BSC 2.30 3.00 BSC 1.60 0.25 0.40 0.30 MAX 0.90 0.05 2.40 1.70 0.30 0.45 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-206A Sheet 2 of 2 2012-2016 Microchip Technology Inc. DS20005293D-page 39 PAC1921 10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C 2X CH OV 1 10 2 VX X1 X2 E G1 VY SILK SCREEN (G2) Y2 Y1 RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width Y2 Optional Center Pad Length X2 Contact Pad Spacing C Center Pad Chamfer CH Contact Pad Width (X10) X1 Contact Pad Length (X10) Y1 Contact Pad to Contact Pad (X8) G1 Contact Pad to Center Pad (X10) G2 Thermal Via Diameter V Thermal Via Pitch VX Thermal Via Pitch VY MIN MILLIMETERS NOM 0.50 BSC MAX 1.70 2.40 3.00 0.28 0.30 0.80 0.20 0.25 REF 0.30 1.00 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerances, for reference only. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2206A DS20005293D-page 40 2012-2016 Microchip Technology Inc. PAC1921 APPENDIX A: REVISION HISTORY Revision D (October 2016) * Fixed minor typographical errors. Revision C (June 2016) The following is the list of modifications: * Modified the matrix description from the note in Section "Absolute Maximum Ratings()" * Fixed various typographical errors for consistency. Revision B (April 2015) The following is the list of modifications: 1. 2. 3. 4. The document has been restructured to comply with the latest Microchip data sheet standards. Removed notes from Section 1.1 "Electrical Specifications". Created separate Section 2.0 "Typical Operating Curves" chapter; updated plots. Fixed minor typographical errors. Revision A (May 2014) Replaced former SMSC version 1.2 (12-21-12). * All sections updated to Microchip format. * References to "stand-alone mode" removed. * References to "lead-free" removed. Rev 1.2 (December 2012) * Modified under features in "Ordering Information" section. Rev. 1.0 (April 2012) * Initial document release. 2012-2016 Microchip Technology Inc. DS20005293D-page 41 PAC1921 NOTES: DS20005293D-page 42 2012-2016 Microchip Technology Inc. PAC1921 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X -XXX Device SMBus Address Package -XX Tape and Reel Device: PAC1921: High-side power/current monitor with analog output SMBus Address: -1 Package: AIA = 10-lead 3 mm x 3 mm VDFN Tape and Reel Option: TR Examples: a) PAC1921-1-AIA-TR: High-side current monitor 3 x 3 VDFN-8 package, Tape and Reel = selectable address =4,000 piece Tape and Reel 2012-2016 Microchip Technology Inc. DS20005293D-page 43 PAC1921 NOTES: DS20005293D-page 44 2012-2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2012-2016 Microchip Technology Inc. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2012-2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. 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