3.5 GSPS Direct Digital Synthesizer with 12-Bit DAC AD9914 Data Sheet FUNCTIONAL BLOCK DIAGRAM 3.5 GSPS internal clock speed Integrated 12-bit DAC Frequency tuning resolution to 190 pHz 16-bit phase tuning resolution 12-bit amplitude scaling Programmable modulus Automatic linear and nonlinear frequency sweeping capability 32-bit parallel datapath interface 8 frequency/phase offset profiles Phase noise: -128 dBc/Hz (1 kHz offset at 1396 MHz) Wideband SFDR < -50 dBc Serial or parallel input/output control 1.8 V/3.3 V power supplies Software and hardware controlled power-down 88-lead LFCSP package PLL REF CLK multiplier Phase modulation capability Amplitude modulation capability AD9914 HIGH SPEED PARALLEL MODULATION PORT LINEAR SWEEP BLOCK 3.5GSPS DDS CORE REF CLK MULTIPLIER TIMING AND CONTROL SERIAL OR PARALLEL DATA PORT 12-BIT DAC 10836-001 FEATURES Figure 1. APPLICATIONS Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers Polar modulator Fast frequency hopping Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2012-2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9914 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 12-Bit DAC Output .................................................................... 20 Applications ....................................................................................... 1 DAC Calibration Output ........................................................... 20 Functional Block Diagram .............................................................. 1 Reconstruction Filter ................................................................. 20 Revision History ............................................................................... 2 Clock Input (REF_CLK/REF_CLK) ........................................ 21 General Description ......................................................................... 3 PLL Lock Indication .................................................................. 22 Specifications..................................................................................... 4 Output Shift Keying (OSK) ....................................................... 22 DC Specifications ......................................................................... 4 Digital Ramp Generator (DRG) ............................................... 23 AC Specifications.......................................................................... 5 Power-Down Control ................................................................ 27 Absolute Maximum Ratings ............................................................ 8 Programming and Function Pins ................................................. 28 Thermal Performance .................................................................. 8 Serial Programming ....................................................................... 31 ESD Caution .................................................................................. 8 Control Interface--Serial Input/Output ................................. 31 Pin Configuration and Function Descriptions ............................. 9 General Serial Input/Output Operation.................................. 31 Typical Performance Characteristics ........................................... 12 Instruction Byte .......................................................................... 31 Equivalent Circuits ......................................................................... 16 Serial Input/Output Port Pin Descriptions ............................. 31 Theory of Operation ...................................................................... 17 Serial Input/Output Timing Diagrams .................................... 32 Single Tone Mode ....................................................................... 17 MSB/LSB Transfers .................................................................... 32 Profile Modulation Mode .......................................................... 17 Parallel Programming (8-/16-Bit) ................................................ 33 Digital Ramp Modulation Mode .............................................. 17 Register Map and Bit Descriptions .............................................. 34 Parallel Data Port Modulation Mode....................................... 17 Register Bit Descriptions ........................................................... 39 Programmable Modulus Mode ................................................. 17 Outline Dimensions ....................................................................... 45 Mode Priority .............................................................................. 18 Ordering Guide .......................................................................... 45 Functional Block Detail ................................................................. 19 DDS Core..................................................................................... 19 REVISION HISTORY 6/2016--Rev. E to Rev. F Changes to Figure 19 ...................................................................... 14 1/2016--Rev. D to Rev. E Changes to DDS Core Section ...................................................... 19 Change to Figure 30 ....................................................................... 19 Updated Outline Dimensions ....................................................... 45 1/2014--Rev. C to Rev. D Changes to Digital Timing Specifications Parameter, Table 2.... 5 Changes to Figure 23 ...................................................................... 15 Change to DAC Calibration Output Section .............................. 20 Change to Address 0x02, Table 14................................................ 34 Changes to Table 17 ........................................................................ 41 11/2013--Rev. B to Rev. C Changes to Table 2 ............................................................................ 5 Change to Programming and Function Pins Section ................ 30 7/2013--Rev. A to Rev. B Change to CMOS Logic Outputs Parameter, Table 1 ...................4 Changes to Table 2.............................................................................7 Changes to DDS Core Section ...................................................... 19 Changes to Phase-Locked Loop (PLL) Multiplier Section ....... 21 Changed PLL Charge Pump Section to PLL Charge Pump/ Total Feedback Divider Section; Changes to Table 8, PLL Loop Filter Components Section, and Figure 34 ....................... 22 Change to Table 14 ......................................................................... 34 Changes to Bits [15:8], Table 17 ................................................... 42 8/2012--Rev. 0 to Rev. A Changes to Features Section ............................................................1 Changed Differential Input Voltage Unit from mV p-p to V p-p .....4 Changes to Table 14 ....................................................................... 34 Changes to Table 16 ....................................................................... 40 Changes to Table 28 ....................................................................... 44 Updated Outline Dimensions ....................................................... 45 7/2012--Revision 0: Initial Version Rev. F | Page 2 of 45 Data Sheet AD9914 GENERAL DESCRIPTION parallel input/output port. The AD9914 also supports a user defined linear sweep mode of operation for generating linear swept waveforms of frequency, phase, or amplitude. A high speed, 32-bit parallel data input port is included, enabling high data rates for polar modulation schemes and fast reprogramming of the phase, frequency, and amplitude tuning words. The AD9914 is a direct digital synthesizer (DDS) featuring a 12-bit DAC. The AD9914 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency-agile analog output sinusoidal waveform at up to 1.4 GHz. The AD9914 enables fast frequency hopping and fine tuning resolution (64-bit capable using programmable modulus mode). The AD9914 also offers fast phase and amplitude hopping capability. The frequency tuning and control words are loaded into the AD9914 via a serial or The AD9914 is specified to operate over the extended industrial temperature range (see the Absolute Maximum Ratings section). AD9914 OUTPUT SHIFT KEYING OSK DRCTL DRHOLD 2 DIGITAL RAMP GENERATOR DROVER 3 PS[2:0] I/O_UPDATE 32 INTERNAL PROGRAMMING REGISTERS DDS DAC_RSET AMPLITUDE (A) A Acos (t + ) PHASE () DATA ROUTE FREQUENCY () Asin (t + ) AND PARTITION CONTROL CLOCK DAC 12-BIT SYSCLK AOUT AOUT REF_CLK REF_CLK INTERNAL CLOCK TIMING AND CONTROL PLL D0 TO D31 4 F0 TO F3 POWERDOWN CONTROL MULTICHIP SYNCHRONIZATION Figure 2. Detailed Block Diagram Rev. F | Page 3 of 45 10836-002 MASTER_RESET LOOP_FILTER SYNC_IN SYNC_OUT EXT_PWR_DWN SYNC_CLK AD9914 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V 5%, AVDD (3.3 V) and DVDD_I/O (3.3 V) = 3.3 V 5%, TA = 25C, RSET = 3.3 k, IOUT = 20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE DVDD_I/O DVDD AVDD (3.3 V) 3.135 1.71 3.135 3.30 1.80 3.30 3.465 1.89 3.465 V V V 1.71 1.80 1.89 V 20 433 640 mA mA mA 178 mA Pin 16, Pin 83 Pin 6, Pin 23, Pin 73 Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52, Pin 53, Pin 60 Pin 32, Pin 56, Pin 57 See also the total power dissipation specifications Pin 16, Pin 83 Pin 6, Pin 23, Pin 73 Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52, Pin 53, Pin 60 Pin 32, Pin 56, Pin 57 AVDD (1.8 V) SUPPLY CURRENT IDVDD_I/O IDVDD IAVDD(3.3V) IAVDD(1.8V) TOTAL POWER DISSIPATION Base DDS Power, PLL Disabled 2392 3091 mW Base DDS Power, PLL Enabled 2237 2627 mW Linear Sweep Additional Power Modulus Additional Power Amplitude Scaler Additional Power Full Power-Down Mode 28 20 138 400 616 mW mW mW mW CMOS LOGIC INPUTS Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IINH, IINL) Maximum Input Capacitance (CIN) CMOS LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) REF CLK INPUT CHARACTERISTICS REF CLK Multiplier Bypassed Input Capacitance Input Resistance Internally Generated DC Bias Voltage Differential Input Voltage REF CLK Multiplier Enabled Input Capacitance Input Resistance Internally Generated DC Bias Voltage Differential Input Voltage 2.0 60 3 2.7 V V A pF DVDD_I/O 0.4 V V IOH = 1 mA IOL = 1 mA REF CLK inputs must always be ac-coupled (both single-ended and differential) pF k V Single-ended, each pin Differential 1.5 1 1.4 2 0.8 Manual or automatic Using either the power-down and enable register or the EXT_PWR_DWN pin DVDD_I/O 0.8 200 1 1.4 2 0.8 3.5 GHz, single-tone mode, modules disabled, linear sweep disabled, amplitude scaler disabled 2.5 GHz, single-tone mode, modules disabled, linear sweep disabled, amplitude scaler disabled V p-p pF k V 1.5 At VIN = 0 V and VIN = DVDD_I/O V p-p Rev. F | Page 4 of 45 Single-ended, each pin Differential Data Sheet AD9914 AC SPECIFICATIONS AVDD (1.8V) and DVDD (1.8V) = 1.8 V 5%, AVDD3 (3.3V) and DVDD_I/O (3.3V) = 3.3 V 5%, TA = 25C, RSET = 3.3 k, IOUT = 20 mA, external reference clock frequency = 3.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted. Table 2. Parameter REF CLK INPUT REF CLK Multiplier Bypassed Input Frequency Range Duty Cycle Minimum Differential Input Level System Clock (SYSCLK) PLL Enabled VCO Frequency Range VCO Gain (KV) Maximum PFD Rate CLOCK DRIVERS SYNC_CLK Output Driver Frequency Range Duty Cycle Rise Time/Fall Time (20% to 80%) SYNC_OUT Output Driver Frequency Range Duty Cycle Rise Time (20% to 80%) Fall Time (20% to 80%) DAC OUTPUT CHARACTERISTICS Output Frequency Range (1st Nyquist Zone) Output Resistance Output Capacitance Full-Scale Output Current Gain Error Output Offset Voltage Compliance Range Min Typ 500 45 632 2400 Max Unit Test Conditions/Comments Input frequency range 3500 55 MHz % mV p-p Maximum fOUT is 0.4 x fSYSCLK 2500 60 125 45 50 650 Equivalent to 316 mV swing on each leg MHz MHz/V MHz 146 55 MHz % ps 9.1 66 MHz % ps ps 1750 MHz 10 pF load 33 1350 1670 0 50 1 20.48 +10 0.6 AVDD + 0.50 -10 AVDD - 0.50 pF mA % FS A V Wideband SFDR 101.1 MHz Output 427.5 MHz Output 696.5 MHz Output 1396.5 MHz Output Narrow-Band SFDR -66 -65 -57 -52 dBc dBc dBc dBc 100.5 MHz Output 427.5 MHz Output 696.5 MHz Output 1396.5 MHz Output -95 -95 -95 -92 dBc dBc dBc dBc Rev. F | Page 5 of 45 CFR2 register, Bit 9 = 1 10 pF load 10 pF load Single-ended (each pin internally terminated to AVDD (3.3 V)) Range depends on DAC RSET resistor See the Typical Performance Characteristics section 0 MHz to 1750 MHz 0 MHz to 1750 MHz 0 MHz to 1750 MHz 0 MHz to 1750 MHz See the Typical Performance Characteristics section 500 kHz 500 kHz 500 kHz 500 kHz AD9914 Parameter DIGITAL TIMING SPECIFICATIONS Time Required to Enter Power-Down Time Required to Leave Power-Down Minimum Master Reset time Maximum DAC Calibration Time (tCAL) Data Sheet Min DATA PORT TIMING D[31:0] Setup Time to SYNC_CLK D[31:0] Hold Time to SYNC_CLK F[3:0] Setup Time to SYNC_CLK F[3:0] Hold Time to SYNC_CLK IO_UPDATE Pin Setup Time to SYNC_CLK IO_UPDATE Pin Hold Time to SYNC_CLK Profile Pin Setup Time to SYNC_CLK Profile Pin Hold Time to SYNC_CLK DR_CTL/DR_HOLD Setup Time to SYNC_CLK DR_CTL/DR_HOLD Hold Time to SYNC_CLK Unit Test Conditions/Comments 45 ns 250 ns SYSCLK cycles s Power-down mode loses DAC/PLL calibration settings Must recalibrate DAC/PLL 135 16 8 2 Maximum Profile Toggle Rate SERIAL PORT TIMING SCLK Clock Rate (1/tCLK ) SCLK Pulse Width High, tHIGH SCLK Pulse Width Low, tLOW SDIO to SCLK Setup Time, tDS SDIO to SCLK Hold Time, tDH SCLK Falling Edge to Valid Data on SDIO/SDO, tDV CS to SCLK Setup Time, tS CS to SCLK Hold Time, tH CS Minimum Pulse Width High, tPWH Max 24 Maximum PLL Calibration Time (tREF_CLK) PARALLEL PORT TIMING Write Timing Address Setup Time to WR Active Address Hold Time to WR Inactive Data Setup Time to WR Inactive Data Hold Time to WR Inactive WR Minimum Low Time WR Minimum High Time Minimum WR Time Read Timing Address to Data Valid Address Hold to RD Inactive RD Active to Data Valid RD Inactive to Data Tristate RD Minimum Low Time RD Minimum High Time Typ 1 ms ms SYNC_CLK period 0 2.1 3.8 10.5 ns ns ns ns ns ns ns 92 0 69 50 69 50 ns ns ns ns ns ns 80 MHz ns ns ns ns ns 0 3.8 1.5 5.1 4.9 0 78 4 0 4 2 0 2 0 2 ns ns ns ns ns ns ns ns 0 ns 0 ns ns ns 0 ns 2 2 Rev. F | Page 6 of 45 See the DAC Calibration Output section for formula PFD rate = 25 MHz PFD rate = 50 MHz SCLK duty cycle = 50% Data Sheet Parameter DATA LATENCY (PIPELINE DELAY) Single Tone Mode or Profile Mode (Matched Latency Disabled) Frequency Phase Amplitude Single Tone Mode or Profile Mode (Matched Latency Enabled) Frequency Phase Amplitude Modulation Mode with 32-Bit Parallel Port (Matched Latency Disabled) Frequency Phase Amplitude Modulation Mode with 32-Bit Parallel Port (Matched Latency Enabled) Frequency Phase Amplitude Sweep Mode (Match Latency Disabled) Frequency Phase Amplitude Sweep Mode (Match Latency Enabled) Frequency Phase Amplitude AD9914 Min Typ Max Unit Test Conditions/Comments SYSCLK cycles = fS = system clock frequency in GHz 318 342 294 318 102 SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles OSK disabled OSK enabled OSK disabled OSK enabled OSK enabled 318 342 318 342 342 SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles OSK disabled OSK enabled OSK disabled OSK enabled OSK enabled 318 342 294 318 102 SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles OSK disabled OSK enabled OSK disabled OSK enabled OSK enabled 318 342 318 342 342 SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles OSK disabled OSK enabled OSK disabled OSK enabled OSK enabled 342 366 318 342 126 SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles OSK disabled OSK enabled OSK disabled OSK enabled OSK enabled 342 366 342 366 366 SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles SYSCLK cycles OSK disabled OSK enabled OSK disabled OSK enabled OSK enabled Rev. F | Page 7 of 45 AD9914 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL PERFORMANCE Table 3. Parameter AVDD (1.8 V), DVDD (1.8 V) Supplies AVDD (3.3 V), DVDD_I/O (3.3 V) Supplies Digital Input Voltage Digital Output Current Storage Temperature Range Operating Temperature Range Maximum Junction Temperature Lead Temperature (10 sec Soldering) Rating 2V 4V -0.7 V to +4 V 5 mA -65C to +150C -40C to +85C 150C 300C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 4. Symbol TJA TJMA TJMA TJB <JB TJC <JT 1 Description Junction-to-ambient thermal resistance (still air) per JEDEC JESD51-2 Junction-to-ambient thermal resistance (1.0 m/sec airflow) per JEDEC JESD51-6 Junction-to-ambient thermal resistance (2.0 m/sec air flow) per JEDEC JESD51-6 Junction-to-board thermal resistance (still air) per JEDEC JESD51-8 Junction-to-board characterization parameter (still air) per JEDEC JESD51-6 Junction-to-case thermal resistance Junction-to-top-of-package characterization parameter (still air) per JEDEC JESD51-2 Value1 24.1 Unit C/W 21.3 C/W 20.0 C/W 13.3 C/W 12.8 C/W 2.21 0.23 C/W C/W Results are from simulations. PCB is JEDEC multilayer. Thermal performance for actual applications requires careful inspection of the conditions in the application to determine if they are similar to those assumed in these calculations. ESD CAUTION Rev. F | Page 8 of 45 Data Sheet AD9914 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 D18 D19 I/O_UPDATE MASTER_RESET DGND DVDD_I/O (3.3V) SYNC_CLK D20 D21 D22 D23 D24 D25 D26 DGND DVDD (1.8V) D27 D28 D29 D30 D31 EXT_PWR_DWN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 AD9914 TOP VIEW (Not to Scale) 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 OSK DROVER DRHOLD DRCTL SYNC_IN SYNC_OUT AVDD (3.3V) REF LOOP_FILTER AVDD (1.8V) AVDD (1.8V) REF CLK REF CLK AVDD (3.3V) AVDD (3.3V) AGND AVDD (3.3V) AGND DAC_RSET AVDD (3.3V) AGND DAC_BP NOTES 1. THE EPAD MUST BE SOLDERED TO GROUND. 10836-003 DVDD (1.8V) DGND PS0 PS1 PS2 F0 F1 F2 F3 AVDD (1.8V) AGND AVDD (3.3V) AGND AVDD (3.3V) AGND AGND AVDD (3.3V) AVDD (3.3V) AOUT AOUT AVDD (3.3V) AGND 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 D17 D16 D15/A7 D14/A6 D13/A5 DVDD (1.8V) DGND D12/A4 D11/A3 D10/A2 D9/A1 D8/A0 D7 D6 D5 DVDD_I/O (3.3V) DGND D4/SYNCIO D3/SDO D2/SDIO/WR D1/SCLK/RD D0/CS/PWD Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 2, 13 to 15, 68 to 72, 75 to 81, 87, 88 Mnemonic D5 to D7, D16 to D31, D27 to D31 I/O1 I/O 3 D15/A7 I/O 4 D14/A6 I/O 5 D13/A5 I/O 8 D12/A4 I/O 9 D11/A3 I/O 10 D10/A2 I/O 11 D9/A1 I/O Description Parallel Port Pins. The 32-bit parallel port offers the option for serial or parallel programming of the internal registers. In addition, the parallel port can be configured to provide direct FSK, PSK, or ASK (or combinations thereof ) modulation data. The 32-bit parallel port configuration is set by the state of the four function pins (F0 to F3). Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins (F0 to F3). The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. Parallel Port Pin/Address Line. Multipurpose pin depending on the state of the function pins (F0 to F3). The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. Rev. F | Page 9 of 45 AD9914 Data Sheet Pin No. 12 Mnemonic D8/A0 I/O1 I/O 18 D4/SYNCIO I 19 D3/SDO I/O 20 D2/SDIO/WR I/O 21 D1/SCLK/RD I 22 D0/CS/PWD I 6, 23, 73 7, 17, 24, 74, 84 16, 83 32, 56, 57 33, 35, 37, 38, 44, 46, 49, 51 34, 36, 39, 40, 43, 47, 50, 52, 53, 60 25, 26, 27 DVDD (1.8V) DGND DVDD_I/O (3.3V) AVDD (1.8V) AGND I I I I I Description Parallel Port Pin/Address Line. The state of the F0 to F3 function pins determines if this pin acts as a line for direct FSK, PSK, or ASK data or as an address line for programming the internal registers. Parallel Port Pin/Serial Port Synchronization Pin. This pin is D4 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0 to F3, this pin resets the serial port. Parallel Port Pin/Serial Data Output. This pin is D3 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0 to F3, this pin is used for readback mode for serial operation. Parallel Port Pin/Serial Data Input and Output/Write Input. This pin is D2 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0 to F3, this pin is used for the SDIO for serial operation. If parallel mode is enabled, this pin is writes to change the values of the internal registers. Parallel Port Pin/Serial Clock/Read Input. This pin is D1 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0 to F3, this pin is used for SCLK for serial operation. If parallel mode is enabled, this pin reads back the value of the internal registers. Parallel Port Pin/Chip Select/Parallel Width. This pin is D0 for direct FSK, PSK, or ASK data. If serial mode is invoked via F0 to F3, this pin is used for the chip select for serial operation. If parallel mode is enabled, this pin sets either 8-bit data or16-bit data. Digital Core Supplies (1.8 V). Digital Ground. Digital Input/Output Supplies (3.3 V). Analog Core Supplies (1.8 V). Analog Ground. AVDD (3.3V) I Analog DAC Supplies (3.3 V). PS0 to PS2 I 28, 29, 30, 31 F0 to F3 I 41 AOUT O 42 AOUT O 45 DAC_BP I 48 DAC_RSET O 54 55 58 59 61 62 63 64 65 REF_CLK REF_CLK LOOP_FILTER REF SYNC_OUT SYNC_IN DRCTL DRHOLD DROVER I I O O O I I I O 66 OSK I Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the current contents of all input/output buffers to the corresponding registers. State changes must be set up on the SYNC_CLK pin (Pin 82). Function Pins. Digital inputs. The state of these pins determines if a serial or parallel interface is used. In addition, the function pins determine how the 32-bit parallel data-word is partitioned for FSK, PSK, or ASK modulation mode. DAC Complementary Output Source. Analog output (voltage mode). Internally connected through a 50 resistor to AVDD (3.3 V). DAC Output Source. Analog output (voltage mode). Internally connected through a 50 resistor to AVDD (3.3 V). DAC Bypass Pin. Provides access to the common control node of the DAC current sources. Connecting a capacitor between this pin and ground can improve noise performance at the DAC output. Analog Reference. This pin programs the DAC output full-scale reference current. Connect a 3.3 k resistor to AGND. Complementary Reference Clock Input. Analog input. Reference Clock Input. Analog input. External PLL Loop Filter Node. Local PLL Reference Supply. Typically at 2.05 V. Digital Synchronization Output. This pin synchronizes multiple chips. Digital Synchronization Input. This pin synchronizes multiple chips. Ramp Control. Digital input (active high). This pin controls the sweep direction (up/down). Ramp Hold. Digital input (active high). Pauses the sweep when active. Ramp Over. Digital output (active high). This pin switches to Logic 1 when the digital ramp generator reaches the programmed upper or lower limit. Output Shift Keying. Digital input (active high). When the OSK features are placed in either manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles the multiplier between 0 (low) and the programmed amplitude scale factor (high). In automatic mode, a low sweeps the amplitude down to zero and a high sweeps the amplitude up to the amplitude scale factor. Rev. F | Page 10 of 45 Data Sheet AD9914 Pin No. 67 Mnemonic EXT_PWR_DWN I/O1 I 82 SYNC_CLK O 85 MASTER_RESET I 86 I/O_UPDATE I EPAD 1 Description External Power-Down. Digital input (active high). A high level on this pin initiates the currently programmed power-down mode. Clock Output. Digital output. Many of the digital inputs on the chip, such as I/O_UPDATE, PS[2:0], and the parallel data port (D0 to D31), must be set up on the rising edge of this signal. Master Reset. Digital input (active high). Clears all memory elements and sets registers to default values. Input/Output Update. Digital input (active high). A high on this pin transfers the contents of the input/output buffers to the corresponding internal registers. Exposed Pad. The EPAD must be soldered to ground. I = input, O = output. Rev. F | Page 11 of 45 AD9914 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 0 -10 -10 -20 -20 -30 -30 -40 -40 -50 -60 -50 -60 -70 -70 -80 -80 175MHz/DIV STOP 1.75GHz 0 -10 -20 -20 -30 -30 -40 -40 SFDR (dBc) 0 -10 -50 -60 -80 -80 -90 -90 175MHz/DIV STOP 1.75GHz -100 0 0 -10 -10 -20 -20 -30 -30 -40 -40 SFDR (dBc) SFDR (dBc) CENTER 427.5MHz 50kHz/DIV SPAN 500kHz Figure 8. Narrow-Band SFDR at 427.5 MHz, SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed) Figure 5. Wideband SFDR at 427.5 MHz SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed) -50 -60 -50 -60 -70 -70 -80 -80 -90 START 0Hz 175MHz/DIV STOP 1.75GHz 10836-006 -90 -100 SPAN 500kHz -60 -70 START 0Hz 50kHz/DIV -50 -70 -100 CENTER 171.5MHz Figure 7. Narrow-Band SFDR at 171.5 MHz, SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed) 10836-005 SFDR (dBc) Figure 4. Wideband SFDR at 171.5 MHz SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed) 10836-008 START 0Hz -90 -100 -100 Figure 6. Wideband SFDR at 696.5 MHz, SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed) CENTER 696.5MHz 50kHz/DIV SPAN 500kHz Figure 9. Narrow-Band SFDR at 696.5 MHz, SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed) Rev. F | Page 12 of 45 10836-009 -90 -100 10836-007 SFDR (dBc) 0 10836-004 SFDR (dBc) Nominal supply voltage; DAC RSET = 3.3 k, TA = 25C, unless otherwise noted. AD9914 0 0 -10 -10 -20 -20 -30 -30 -40 -40 SFDR (dBc) -50 -60 -50 -60 -70 -70 -80 -80 -90 -100 START 0Hz 175MHz/DIV STOP 1.75GHz 10836-010 -90 -100 50kHz/DIV CENTER 1396.5MHz SPAN 500kHz 10836-013 SFDR (dBc) Data Sheet Figure 13. Narrow-Band SFDR at 1396.5 MHz, SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed) Figure 10. Wideband SFDR at 1396.5 MHz, SYSCLK = 3.5 GHz (SYSCLK PLL Bypassed) -70 0 -80 -10 -90 PHASE NOISE (dBc/Hz) -30 -40 -50 -60 -110 -120 -130 SMA AND ADCLK925 -140 -150 SMA -160 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 fC/fS -10 -20 -30 -40 -50 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M -70 SYSCLK = 2.7GHz SYSCLK = 2.8GHz SYSCLK = 2.9GHz SYSCLK = 3.0GHz SYSCLK = 3.1GHz SYSCLK = 3.2GHz SYSCLK = 3.3GHz SYSCLK = 3.4GHz SYSCLK = 3.5GHz -80 -90 PHASE NOISE (dBc/Hz) SYSCLK = 1.5GHz SYSCLK = 1.6GHz SYSCLK = 1.7GHz SYSCLK = 1.8GHz SYSCLK = 1.9GHz SYSCLK = 2.0GHz SYSCLK = 2.1GHz SYSCLK = 2.2GHz SYSCLK = 2.3GHz SYSCLK = 2.4GHz SYSCLK = 2.5GHz SYSCLK = 2.6GHz 100 Figure 14. Absolute Phase Noise of REF CLK Source Driving AD9914 Rohde & Schwarz SMA100 Signal Generator at 3.5 GHz Buffered by Series ADCLK925 Figure 11. Wideband SFDR vs. Normalized fOUT SYSCLK = 3.5 GHz 0 -170 10 10836-011 -80 10836-014 -70 -100 -110 1396MHz -120 696MHz -130 -140 -60 -150 427MHz -70 -160 -80 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 fC/fS Figure 12. Wideband SFDR vs. Normalized fOUT, SYSCLK = 2.5 GHz to 3.5 GHz 0.40 -170 10 10836-012 SFDR (dBc) -100 171MHz 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 10836-015 SFDR (dBc) -20 Figure 15. Absolute Phase Noise Curves of DDS Output at 3.5 GHz Operation Rev. F | Page 13 of 45 AD9914 Data Sheet -70 -80 -80 -90 -100 PHASE NOISE (dBc/Hz) -100 -110 1396MHz -120 -130 -140 NORMALIZED REF CLK SOURCE -150 978MHz -120 -130 305MHz -140 122MHz -150 -160 -160 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M -170 10 10836-016 -170 10 497MHz -110 Figure 16. Absolute Phase Noise Curves of Normalized REF CLK Source to DDS Output at 1396 MHz (SYSCLK = 3.5 GHz) 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 10836-019 PHASE NOISE (dBc/Hz) -90 Figure 19. Absolute Phase Noise Curves of DDS Output Using Internal PLL at 2.5 GHz Operation -60 -60 -70 -70 -80 PHASE NOISE (dBc/Hz) -100 -110 -120 1396MHz -130 696MHz -140 -150 -160 -110 1396MHz ABSOLUTE -120 -130 1396MHz RESIDUAL 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M -160 10 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 10836-020 171MHz Figure 17. Residual Phase Noise Curves Figure 20. Residual PN vs. Absolute PN Measurement Curves at 1396 MHz 0.5 -60 3.3V ANALOG -70 -80 PHASE NOISE (dBc/Hz) 0.4 0.3 1.8V DIGITAL 0.2 1.8V ANALOG -90 -100 -110 1396MHz ABSOLUTE -120 -130 -140 -150 1396MHz RESIDUAL 0.1 -160 1000 1500 2000 2500 3000 3500 SYSTEM CLOCK (MHz) Figure 18. Power Supply Current vs. SYSCLK 4000 -180 10 100 1k 10k 100k 1M FREQUENCY OFFSET (Hz) 10M 100M 10836-021 -170 3.3V DIGITAL 0 500 10836-018 SUPPLY CURRENT (A) -100 -150 -170 -180 10 -90 -140 427MHz 10836-017 PHASE NOISE (dBc/Hz) -80 -90 Figure 21. Residual Phase Noise vs. Normalized Absolute REF CLK Source Phase Noise at 1396 MHz Rev. F | Page 14 of 45 Data Sheet AD9914 930 FREQUENCY (MHz) 920 1 910 900 890 M20.00ms A CH2 1.64V IT 40.0ps/pt 870 -6 -4 -2 0 2 4 6 TIME (ms) 10836-024 CH2 1.0V 10836-022 880 Figure 24. Measured Rising Linear Frequency Sweep Figure 22. SYNC_OUT (fSYSCLK/384) 930 1.0 0.9 920 0.8 FREQUENCY (MHz) TIME (ms) 0.7 0.6 0.5 0.4 0.3 0.2 910 900 890 880 1000 1500 2000 2500 SYSTEM CLOCK RATE (MHz) 3000 3500 Figure 23. DAC Calibration Time vs. SYSCLK Rate. See the DAC Calibration Output Section for Formula. Rev. F | Page 15 of 45 870 -6 -4 -2 0 2 4 TIME (ms) Figure 25. Measured Falling Linear Frequency Sweep 6 10836-025 0 500 10836-023 0.1 AD9914 Data Sheet EQUIVALENT CIRCUITS AGND IFS CURRENT SWITCH ARRAY SWITCH CONTROL CURRENT SWITCH ARRAY IFS/2 + ICODE DVDD (3.3V) IFS/2 - ICODE CODE 41 INTERNAL 50 10836-044 INTERNAL 50 AOUT AVDD (3.3V) 10836-045 AOUT 42 Figure 28. CMOS Input Figure 26. DAC Output AVDD (3.3V) DVDD (3.3V) 10836-043 REF_CLK 10836-048 REF_CLK Figure 29. CMOS Output Figure 27. REF CLK input Rev. F | Page 16 of 45 Data Sheet AD9914 THEORY OF OPERATION DIGITAL RAMP MODULATION MODE The AD9914 has five modes of operation. x Single tone x Profile modulation x Digital ramp modulation (linear sweep) x Parallel data port modulation x Programmable modulus mode In digital ramp modulation mode, the modulated DDS signal control parameter is supplied directly from the digital ramp generator (DRG). The ramp generation parameters are controlled through the serial or parallel input/output port. The modes define the data source supplies the DDS with the signal control parameters: frequency, phase, or amplitude. The partitioning of the data into different combinations of frequency, phase, and amplitude is established based on the mode and/or specific control bits and function pins. Although the various modes are described independently, they can be enabled simultaneously. This provides an unprecedented level of flexibility for generating complex modulation schemes. However, to avoid multiple data sources from driving the same DDS signal control parameter, the device has a built-in priority protocol. In single tone mode, the DDS signal control parameters come directly from the profile programming registers. In digital ramp modulation mode, the DDS signal control parameters are delivered by a digital ramp generator. In parallel data port modulation mode, the DDS signal control parameters are driven directly into the parallel port. The various modulation modes generally operate on only one of the DDS signal control parameters (two in the case of the polar modulation format via the parallel data port). The unmodulated DDS signal control parameters are stored in programming registers and automatically routed to the DDS based on the selected mode. A separate output shift keying (OSK) function is also available. This function employs a separate digital linear ramp generator that affects only the amplitude parameter of the DDS. The OSK function has priority over the other data sources that can drive the DDS amplitude parameter. As such, no other data source can drive the DDS amplitude when the OSK function is enabled. SINGLE TONE MODE In single tone mode, the DDS signal control parameters are supplied directly from the profile programming registers. A profile is an independent register that contains the DDS signal control parameters. Eight profile registers are available. Note that the profile pins must select the desired register. PROFILE MODULATION MODE Each profile is independently accessible. For FSK, PSK, or ASK modulation, use the three external profile pins (PS[2:0]) to select the desired profile. A change in the state of the profile pins with the next rising edge on SYNC_CLK updates the DDS with the parameters specified by the selected profile. Therefore, the profile change must meet the setup and hold times to the SYNC_CLK rising edge. Note that amplitude control must also be enabled using the OSK enable bit in the CFR1 register (0x00[8]). The ramp generation parameters allow the user to control both the rising and falling slopes of the ramp. The upper and lower boundaries of the ramp, the step size and step rate of the rising portion of the ramp, and the step size and step rate of the falling portion of the ramp are all programmable. The ramp is digitally generated with 32-bit output resolution. The 32-bit output of the DRG can be programmed to affect frequency, phase, or amplitude. When programmed for frequency, all 32 bits are used. However, when programmed for phase or amplitude, only the 16 MSBs or 12 MSBs, respectively, are used. The ramp direction (rising or falling) is externally controlled by the DRCTL pin. An additional pin (DRHOLD) allows the user to suspend the ramp generator in the present state. Note that amplitude control must also be enabled using the OSK enable bit in Register CFR1. PARALLEL DATA PORT MODULATION MODE In parallel data port modulation mode, the modulated DDS signal control parameter(s) are supplied directly from the 32-bit parallel data port. The function pins define how the 32-bit data-word is applied to the DDS signal control parameters. Formatting of the 32-bit data-word is unsigned binary, regardless of the destination. Parallel Data Clock (SYNC_CLK) The AD9914 generates a clock signal on the SYNC_CLK pin that runs at 1/24 of the DAC sample rate (the sample rate of the parallel data port). SYNC_CLK serves as a data clock for the parallel port. PROGRAMMABLE MODULUS MODE In programmable modulus mode, the DRG is used as an auxiliary accumulator to alter the frequency equation of the DDS core, making it possible to implement fractions that are not restricted to a power of 2 in the denominator. A standard DDS is restricted to powers of 2 as a denominator because the phase accumulator is a set of bits as wide as the frequency tuning word (FTW). When in programmable modulus mode, however, the frequency equation is: f0 = (fS)(FTW + A/B)/232 where f0/fS < 1/2, 0 FTW < 231, 2 B 232 - 1, and A < B. This equation implies a modulus of B x 232 (rather than 232, in the case of a standard DDS). Furthermore, because B is programmable, the result is a DDS with a programmable modulus. Rev. F | Page 17 of 45 AD9914 Data Sheet When in programmable modulus mode, the 32-bit auxiliary accumulator operates in a way that allows it to roll over at a value other than the full capacity of 232. That is, it operates with a modified modulus based on the programmable value of B. With each roll over of the auxiliary accumulator, a value of 1 LSB adds to the current accumulated value of the 32-bit phase accumulator. This behavior changes the modulus of the phase accumulator to B x 232 (instead of 232), allowing it to synthesize the desired f0. To determine the programmable modulus mode register values for FTW, A, and B, the user must first define f0/fS as a ratio of relatively prime integers, M/N. That is, having converted f0 and fS to integers, M and N, reduce the fraction, M/N, to the lowest terms. Then, divide M x 232 by N. The integer part of this division operation is the value of FTW (Register 0x04[31:0]). The remainder, Y, of this division operation is Y = (232 x M) - (FTW x N) The value of Y facilitates the determination of A and B by taking the fraction, Y/N, and reducing it to the lowest terms. Then, the numerator of the reduced fraction is A (Register 0x06[31:0]) and the denominator is the B (Register 0x05[31:0]). For example, synthesizing precisely 300 MHz with a 1 GHz system clock is not possible with a standard DDS. It is possible, however, using programmable modulus as follows. Reducing this fraction to lowest terms yields 3/10; therefore, M = 3 and N = 10. FTW is the integer part of (M x 232)/N, or (3 x 232)/10, which is 1,288,490,188 (0x4CCCCCCC in 32-bit hexadecimal notation). The remainder, Y, of (3 x 232)/10, is (232 x 3) - (1,288,490,188 x 10), which is 8. Therefore, Y/N is 8/10, which reduces to 4/5. Therefore, A = 4 and B = 5 (0x00000004 and 0x00000005 in 32-bit hexadecimal notation, respectively). Programming the AD9914 with these values of FTW, A, and B results in an output frequency that is exactly 3/10 of the system clock frequency. MODE PRIORITY The ability to activate each mode independently makes it possible to have multiple data sources attempting to drive the same DDS signal control parameter (frequency, phase, and amplitude). To avoid contention, the AD9914 has a built-in priority system. Table 6 summarizes the priority for each of the DDS modes. The data source column in Table 6 lists data sources for a particular DDS signal control parameter in descending order of precedence. For example, if the profile mode enable bit and the parallel data port enable bit (0x01[23:22]) are set to Logic 1 and both are programmed to source the frequency tuning word to DDS output, the profile modulation mode has priority over the parallel data port modulation mode. First, express f0/fS as a ratio of integers: 300,000,000/1,000,000,000 Table 6. Data Source Priority Priority Highest Priority Data Source Programmable modulus DRG Profiles Lowest Priority Parallel port DDS Signal Control Parameters Conditions If programmable modulus mode is used to output frequency only, no other data source can control the output frequency in this mode. Note that the DRG is used in conjunction with programmable modulus mode; therefore, the DRG cannot be used to sweep phase or amplitude in programmable modulus mode. If output phase offset control is desired, enable profile mode and use the profile registers and profile pins accordingly to control output phase adjustment. If output amplitude control is desired, enable profile mode and use the profile registers and profile pins accordingly to control output amplitude adjustment. Note that the OSK enable bit must be set to control the output amplitude. The digital ramp modulation mode is the next highest priority mode. If the DRG is enabled to sweep output frequency, phase, or amplitude, the two parameters not being swept can be controlled independently via the profile mode. The profile modulation mode is the next highest priority mode. Profile mode can control all three parameters independently, if desired. Parallel data port modulation has the lowest priority but the most flexibility as far as changing any parameter at the high rate. See the Programming and Function Pins section. Rev. F | Page 18 of 45 Data Sheet AD9914 FUNCTIONAL BLOCK DETAIL The relative phase of the DDS signal can be digitally controlled by means of a 16-bit phase offset word (POW). The phase offset is applied prior to the angle to amplitude conversion block internal to the DDS core. The relative phase offset () is given by DDS CORE The direct digital synthesizer (DDS) block generates a reference signal (sine or cosine based on Register 0x00, Bit 16, the enable sine output bit). The parameters of the reference signal (frequency, phase, and amplitude) are applied to the DDS at the frequency, phase offset, and amplitude control inputs, as shown in Figure 30. 'T The output frequency (fOUT) of the AD9914 is controlled by the frequency tuning word (FTW) at the frequency control input to the DDS. The relationship among fOUT, FTW, and fSYSCLK is given by where the upper quantity is for the phase offset expressed as radian units and the lower quantity as degrees. (1) To find the POW value necessary to develop an arbitrary , solve the preceding equation for POW and round the result (in a manner similar to that described previously for finding an arbitrary FTW). where FTW is a 32-bit integer ranging in value from 0 to 2,147,483,647 (231 - 1), which represents the lower half of the full 32-bit range. This range constitutes frequencies from dc to Nyquist (that is, 1/2 fSYSCLK). The relative amplitude of the DDS signal can be digitally scaled (relative to full scale) by means of a 12-bit amplitude scale factor (ASF). The amplitude scale value is applied at the output of the angle to amplitude conversion block internal to the DDS core. The amplitude scale is given by The FTW required to generate a desired value of fOUT is found by solving Equation 1 for FTW, as given in Equation 2. FTW f round 2 32 OUT (c) (c) f SYSCLK ** (2) where the round(x) function rounds the argument (the value of x) to the nearest integer. This is required because the FTW is constrained to be an integer value. For example, for fOUT = 41 MHz and fSYSCLK = 122.88 MHz, FTW = 1,433,053,867 (0x556AAAAB). Amplitude Scale ASF 20 log 12 * (c) 2 (3) where the upper quantity is amplitude expressed as a fraction of full scale and the lower quantity is expressed in decibels relative to full scale. Programming an FTW greater than 231 produces an aliased image that appears at a frequency given by f OUT ASF 212 1 FTW * f SYSCLK 232 (c) To find the ASF value necessary for a particular scale factor, solve Equation 3 for ASF and round the result (in a manner similar to that described previously for finding an arbitrary FTW). for FTW 231 When the AD9914 is programmed to modulate any of the DDS signal control parameters, the maximum modulation sample rate is 1/24 fSYSCLK. This means that the modulation signal exhibits images at multiples of 1/24 fSYSCLK. The impact of these images must be considered when using the device as a modulator. DDS SIGNAL CONTROL PARAMETERS AMPLITUDE CONTROL 12 PHASE OFFSET CONTROL 16 MSB ALIGNED 32-BIT ACCUMULATOR 32 FREQUENCY 32 CONTROL 32 DQ R DDS_CLK 12 16 17 32 17 (MSBs) ANGLE-TOAMPLITUDE 12 12 CONVERSION (SINE OR COSINE) TO DAC ACCUMULATOR RESET Figure 30. DDS Block Diagram Rev. F | Page 19 of 45 10836-026 f OUT FTW * f 32 SYSCLK (c) 2 POW 2 S 16 * (c) 2 POW 360 16 * (c) 2 AD9914 Data Sheet 12-BIT DAC OUTPUT RECONSTRUCTION FILTER The AD9914 incorporates an integrated 12-bit, current output DAC. The output current is delivered as a balanced signal using two outputs. The use of balanced outputs reduces the potential amount of common-mode noise present at the DAC output, offering the advantage of an increased signal-to-noise ratio. An external resistor (RSET) connected between the DAC_RSET pin and AGND establishes the reference current. The recommended value of RSET is 3.3 k. The DAC output signal appears as a sinusoid sampled at fS. The frequency of the sinusoid is determined by the frequency tuning word (FTW) that appears at the input to the DDS. The DAC output is typically passed through an external reconstruction filter that serves to remove the artifacts of the sampling process and other spurs outside the filter bandwidth. Because the DAC constitutes a sampled system, the output must be filtered so that the analog waveform accurately represents the digital samples supplied to the DAC input. The unfiltered DAC output contains the desired baseband signal, which extends from dc to the Nyquist frequency (fS/2). It also contains images of the baseband signal that theoretically extend to infinity. Notice that the odd numbered images (shown in Figure 31) are mirror images of the baseband signal. Furthermore, the entire DAC output spectrum is affected by a sin(x)/x response, which is caused by the sample-and-hold nature of the DAC output signal. Attention must be paid to the load termination to keep the output voltage within the specified compliance range; voltages developed beyond this range cause excessive distortion and can damage the DAC output circuitry. DAC CALIBRATION OUTPUT The DAC CAL enable bit in the CFR4 control register (0x03[24]) must be manually set and then cleared after each power-up and every time the REF CLK or internal system clock is changed. This initiates an internal calibration routine to optimize the setup and hold times for internal DAC timing. Failure to calibrate may degrade performance and even result in loss of functionality. The length of time to calibrate the DAC clock is calculated from the following equation: 469,632 fS Some applications operate from an image above the Nyquist frequency, and those applications use a band-pass filter instead of a low-pass filter. The design of the reconstruction filter has a significant impact on the overall signal performance. Therefore, good filter design and implementation techniques are important for obtaining the best possible jitter results. MAGNITUDE (dB) IMAGE 0 IMAGE 1 IMAGE 2 IMAGE 3 IMAGE 4 0 -20 -40 PRIMARY SIGNAL FILTER RESPONSE SIN(x)/x ENVELOPE -60 -80 SPURS f -100 fs/2 fs 3fs/2 2fs BASE BAND Figure 31. DAC Spectrum vs. Reconstruction Filter Response Rev. F | Page 20 of 45 5fs/2 10836-027 t CAL For applications using the fundamental frequency of the DAC output, the response of the reconstruction filter must preserve the baseband signal (Image 0), while completely rejecting all other images. However, a practical filter implementation typically exhibits a relatively flat pass band that covers the desired output frequency plus 20%, rolls off as steeply as possible, and then maintains significant (though not complete) rejection of the remaining images. Depending on how close unwanted spurs are to the desired signal, a third-, fifth-, or seventh-order elliptic low-pass filter is common. Data Sheet AD9914 CLOCK INPUT (REF_CLK/REF_CLK) REF_CLK/REF_CLK Overview The AD9914 supports a number of options for producing the internal SYSCLK signal (that is, the DAC sample clock) via the REF_CLK/REF_CLK input pins. The REF_CLK input can be driven directly from a differential or single-ended source. There is also an internal phase-locked loop (PLL) multiplier that can be independently enabled. However, the PLL limits the SYSCLK signal between 2.4 GHz and 2.5 GHz operation. A differential signal is recommended when the PLL is bypassed. A block diagram of the REF_CLK functionality is shown in Figure 32. Figure 32 also shows how the CFR3 control bits are associated with specific functional blocks. The REF_CLK/REF_CLK input resistance is ~2.5 k differential (~1.2 k single-ended). Most signal sources have relatively low output impedances. The REF_CLK/REF_CLK input resistance is relatively high; therefore, the effect on the termination impedance is negligible and can usually be chosen to be the same as the output impedance of the signal source. The bottom two examples in Figure 33 assume a signal source with a 50 output impedance. 0.1F DIFFERENTIAL SOURCE, DIFFERENTIAL INPUT PECL, LVPECL, OR LVDS DRIVER 54 REF_CLK 55 REF_CLK 54 REF_CLK 55 REF_CLK 54 REF_CLK TERMINATION BALUN (1:1) 0.1F 58 SINGLE-ENDED SOURCE, DIFFERENTIAL INPUT PLL ENABLE CFR3[18] REF_CLK 0.1F LOOP_FILTER DOUBLER ENABLE CFR3[19] 55 50 0.1F DOUBLER CLOCK EDGE CFR3[16] x2 / 1, 2, 4, 8 0.1F LOOP FILTER 1 0 IN PLL OUT CHARGE PUMP DIVIDE 1 SYSCLK SINGLE-ENDED SOURCE, SINGLE-ENDED INPUT 0 50 2 55 54 INPUT DIVIDER 2 7 RESET CFR3[22] N ICP CFR3[15:8] INPUT DIVIDER RATIO CFR3[21:20] CFR3[5:3] 0.1F Figure 33. Direct Connection Diagram 10836-028 REF_CLK 10836-029 ENABLE REF_CLK Figure 32. REF_CLK Block Diagram The PLL enable bit chooses between the PLL path or the direct input path. When the direct input path is selected, the REF_CLK/REF_CLK pins must be driven by an external signal source (single-ended or differential). Input frequencies up to 3.5 GHz are supported. Direct Driven REF_CLK/REF_CLK With a differential signal source, the REF_CLK/REF_CLK pins are driven with complementary signals and ac-coupled with 0.1 F capacitors. With a single-ended signal source, either a singleended-to-differential conversion can be employed or the REF_CLK input can be driven single-ended directly. In either case, 0.1 F capacitors ac couples both REF_CLK/ REF_CLK pins to avoid disturbing the internal dc bias voltage of ~1.35 V. See Figure 33 for more details. Phase-Locked Loop (PLL) Multiplier An internal PLL provides the option to use a reference clock frequency that is significantly lower than the system clock frequency. The PLL supports a wide range of programmable even frequency multiplication factors (20x to 510x) as well as a programmable charge pump current and external loop filter components (connected via the PLL LOOP_FILTER pin). These features add an extra layer of flexibility to the PLL, allowing optimization of phase noise performance and flexibility in frequency plan development. The PLL is also equipped with a PLL lock bit indicator (0x1B[24]). The PLL output frequency range (fSYSCLK) is constrained to the range of 2.4 GHz fSYSCLK 2.5 GHz by the internal VCO. VCO Calibration When using the PLL to generate the system clock, VCO calibration is required to tune the VCO appropriately and achieve good performance. When the reference input signal is stable, the VCO cal enable bit in the CFR1 register, 0x00[24], must be asserted. Subsequent VCO calibrations require that the VCO calibration bit be cleared prior to initiating another VCO calibration. VCO calibration must occur before DAC calibration to ensure optimal performance and functionality. Rev. F | Page 21 of 45 AD9914 Data Sheet PLL Charge Pump/Total Feedback Divider CZ = 560pF (RECOMMENDED) The charge pump current (ICP) value is automatically chosen via the VCO calibration process and N value (N = 10 to 255) stored in Feedback Divider N[7:0] in the CFR3 register (0x02[15:8]). N values below 10 must be avoided. 0.47F REF LOOP_FILTER 59 58 CP 50pF Note that the total PLL multiplication value for the PLL is always 2N due to the fixed divide by 2 element in the feedback path. This is shown in Figure 34. This fixed divide by 2 element forces only even PLL multiplication. RPZ (3.5k) REFCLK PLL PLL IN CP /N To manually override the charge pump current value, the manual ICP selection bit in CFR3 (0x02[6]) must be set to Logic 1. This provides the user with additional flexibility to optimize the PLL performance. Table 7 lists the bit settings vs. the nominal charge pump current. Table 7. PLL Charge Pump Current Charge Pump Current, ICP (A) 125 250 375 500 (default) 625 750 875 1000 /2 Figure 34. REF CLK PLL External Loop Filter PLL LOCK INDICATION When the PLL is in use, the PLL lock bit (0x1B[24])provides an active high indication that the PLL has locked to the REF CLK input signal. OUTPUT SHIFT KEYING (OSK) The OSK function (see Figure 35) allows the user to control the output signal amplitude of the DDS. The amplitude data generated by the OSK block has priority over any other functional block that is programmed to deliver amplitude data to the DDS. Therefore, the OSK data source, when enabled, overrides all other amplitude data sources. The operation of the OSK function is governed by two CFR1 register bits, OSK enable (0x00[8]) and external OSK enable (0x00[9]), the external OSK pin, the profile pins, and the 12 bits of amplitude scale factor found in one of eight profile registers. The profile pins select the profile register containing the desired amplitude scale factor. Table 8. N Divider vs. Charge Pump Current N Divider Range 10 to 15 16 to 23 24 to 35 36 to 43 44 to 55 56 to 63 64 to 79 80 to 100 PLL OUT Recommended Charge Pump Current, ICP (A) 125 250 375 500 625 750 875 1000 The primary control for the OSK block is the OSK enable bit (0x00[8]). When the OSK function is disabled, the OSK input controls and OSK pin are ignored. PLL Loop Filter Components The loop filter is mostly internal to the device, as shown in Figure 34. The recommended external capacitor value is 560 pF. Because CP and RPZ are integrated, it is not recommended to adjust the loop bandwidth via the external capacitor value. The better option is to adjust the charge pump current even though it is a coarse adjustment. The OSK pin functionality depends on the state of the external OSK enable bit and the OSK enable bit. When both bits are set to Logic 1 and the OSK pin is Logic 0, the output amplitude is forced to 0; otherwise, if the OSK pin is Logic 1, the output amplitude is set by the amplitude scale factor value in one of eight profile registers depending on the profile pin selection. PS0 PS1 PS2 25 For example, suppose the PLL is manually programmed such that ICP = 375 A, KV = 60 MHz/V, and N = 25. This produces a loop bandwidth of approximately 250 kHz. 26 OSK 27 66 OSK ENABLE EXTERNAL OSK ENABLE AMPLITUDE SCALE 12 FACTOR (1 OF 8 SELECTED PROFILE REGISTERS [27:16]) OSK 12 CONTROLLER DDS CLOCK Figure 35. OSK Block Diagram Rev. F | Page 22 of 45 TO DDS AMPLITUDE CONTROL PARAMETER 10836-031 ICP Bits (CFR3[5:3]) 000 001 010 011 100 101 110 111 VCO 10836-030 PFD Data Sheet AD9914 The output of the DRG is a 32-bit unsigned data bus that can be routed to any one of the three DDS signal control parameters, as controlled by the two digital ramp destination bits in Control Function Register 2 according to Table 9. The 32-bit output bus is MSB-aligned with the 32-bit frequency parameter, the 16-bit phase parameter, or the 12-bit amplitude parameter, as defined by the destination bits. When the destination is phase or amplitude, the unused LSBs are ignored. DIGITAL RAMP GENERATOR (DRG) DRG Overview DRCTL DRHOLD DROVER To sweep phase, frequency, or amplitude from a defined start point to a defined endpoint, a completely digital ramp generator is included in the AD9914. The DRG makes use of eight control register bits, three external pins, and five 32-bit registers (see Figure 36). 63 64 65 Table 9. Digital Ramp Destination Digital Ramp Destination Bits (CFR2[21:20]) 00 01 1x1 DIGITAL RAMP ENABLE 2 DIGITAL RAMP DESTINATION 2 DIGITAL RAMP NO-DWELL DDS Signal Control Parameter Frequency Phase Amplitude Bits Assigned to DDS Parameter 31:0 31:18 31:20 LOAD LRR AT I/O_UPDATE 1 CLEAR DIGITAL RAMP ACCUMULATOR AUTOCLEAR DIGITAL RAMP ACCUMULATOR The ramp characteristics of the DRG are fully programmable. This includes the upper and lower ramp limits, and independent control of the step size and step rate for both the positive and negative slope characteristics of the ramp. A detailed block diagram of the DRG is shown in Figure 37. 32 DIGITAL RAMP LOWER LIMIT REGISTER DIGITAL RAMP UPPER LIMIT REGISTER RISING DIGITAL RAMP STEP SIZE REGISTER FALLING DIGITAL RAMP STEP SIZE REGISTER 32 DIGITAL RAMP GENERATOR x = don't care. 32 TO DDS SIGNAL CONTROL PARAMETER The direction of the ramping function is controlled by the DRCTL pin. Logic 0 on this pin causes the DRG to ramp with a negative slope, whereas Logic 1 causes the DRG to ramp with a positive slope. 32 32 32 DIGITAL RAMP RATE REGISTER 10836-032 The DRG also supports a hold feature controlled via the DRHOLD pin. When this pin is set to Logic 1, the DRG is stalled at the last state; otherwise, the DRG operates normally. The DDS signal control parameters that are not the destination of the DRG are taken from the active profile. DDS CLOCK Figure 36. Digital Ramp Block Diagram The primary control for the DRG is the digital ramp enable bit (0x01[19]). When disabled, the other DRG input controls are ignored and the internal clocks are shut down to conserve power. 32 INCREMENT STEP SIZE DIGITAL RAMP ACCUMULATOR 0 32 32 1 32 32 D Q DRCTL 63 R 16 NEGATIVE SLOPE RATE 16 POSITIVE SLOPE RATE LOAD LRR AT I/O_UPDATE 32 32 UPPER LIMIT LOWER LIMIT TO DDS SIGNAL CONTROL PARAMETER 16 1 LOAD CONTROL LOGIC DRHOLD 64 DDS CLOCK 0 LIMIT CONTROL PRESET LOAD ACCUMULATOR RESET CONTROL LOGIC Q DIGITAL RAMP TIMER Figure 37. Digital Ramp Generator Detail Rev. F | Page 23 of 45 NO-DWELL CONTROL 2 NO DWELL CLEAR DIGITAL RAMP ACCUMULATOR AUTOCLEAR DIGITAL RAMP . ACC 10836-033 32 DECREMENT STEP SIZE AD9914 Data Sheet DRG Slope Control The core of the DRG is a 32-bit accumulator clocked by a programmable timer. The time base for the timer is the DDS clock, which operates at 1/24 fSYSCLK. The timer establishes the interval between successive updates of the accumulator. The positive (+t) and negative (-t) slope step intervals are independently programmable as given by 't 't 24P f SYSCLK 24 N f SYSCLK where P and N are the two 16-bit values stored in the 32-bit digital ramp rate register and control the step interval. N defines the step interval of the negative slope portion of the ramp. P defines the step interval of the positive slope portion of the ramp. The step size of the positive (STEPP) and negative (STEPN) slope portions of the ramp are 32-bit values programmed into the 32-bit rising and falling digital ramp step size registers (0x06 and 0x07). Program each of the step sizes as an unsigned integer (the hardware automatically interprets STEPN as a negative value). The relationship between the 32-bit step size values and actual units of frequency, phase, or amplitude depend on the digital ramp destination bits. Calculate the actual frequency, phase, or amplitude step size by substituting STEPN or STEPP for M in the following equations as required: Frequency Step Phase Step Phase Step SM M *f 32 SYSCLK (c) 2 (radians) 45M 229 (degrees) M *I 32 FS (c) 2 The phase and amplitude step size equations yield the average step size. Although the step size accumulates with 32-bit precision, the phase or amplitude destination exhibits only 16 bits or 12 bits, respectively. Therefore, at the destination, the actual phase or amplitude step is the accumulated 32-bit value truncated to 16 bits or 12 bits, respectively. As described previously, the step interval is controlled by a 16-bit programmable timer. There are three events that can cause this timer to be reloaded prior to the expiration. One event occurs when the digital ramp enable bit transitions from cleared to set, followed by an input/output update. A second event is a change of state in the DRCTL pin. The third event is enabled using the load LRR at input/output update bit (0x00[15]). DRG Limit Control The ramp accumulator is followed by limit control logic that enforces an upper and lower boundary on the output of the ramp generator. Under no circumstances does the output of the DRG exceed the programmed limit values while the DRG is enabled. The limits are set through the 64-bit digital ramp limit register. Note that the upper limit value must be greater than the lower limit value to ensure normal operation. DRG Accumulator Clear 231 Amplitude Step Note that the frequency units are the same as those that represent fSYSCLK (MHz, for example). The amplitude units are the same as those that represent IFS, the full-scale output current of the DAC (mA, for example). The ramp accumulator can be cleared (that is, reset to 0) under program control. When the ramp accumulator is cleared, it forces the DRG output to the lower limit programmed into the digital ramp limit register. With the limit control block embedded in the feedback path of the accumulator, resetting the accumulator is equivalent to presetting it to the lower limit value. Rev. F | Page 24 of 45 Data Sheet AD9914 P DDS CLOCK CYCLES N DDS CLOCK CYCLES 1 DDS CLOCK CYCLE NEGATIVE STEP SIZE +t POSITIVE STEP SIZE -t UPPER LIMIT DRG OUTPUT LOWER LIMIT DROVER DRHOLD AUTO CLEAR CLEAR DRCTL RELEASE DIGITAL RAMP ENABLE CLEAR DIGITAL RAMP ACCUMULATOR AUTOCLEAR DIGITAL RAMP ACCUMULATOR 1 2 3 4 5 6 7 8 9 11 10 13 12 10836-034 I/O_UPDATE Figure 38. Normal Ramp Generation Normal Ramp Generation Normal ramp generation implies that both no-dwell bits are cleared (see the No-Dwell Ramp Generation section for details). In Figure 38, a sample ramp waveform is depicted with the required control signals. The top trace is the DRG output. The next trace down is the status of the DROVER output pin (assuming that the DRG over output enable bit is set). The remaining traces are control bits and control pins. The pertinent ramp parameters are also identified (upper and lower limits plus step size and t for the positive and negative slopes). Along the bottom, circled numbers identify specific events. These events are referred to by number (Event 1 and so on) in the following paragraphs. In this example, the positive and negative slopes of the ramp are different to demonstrate the flexibility of the DRG. The parameters of both slopes can be programmed to make the positive and negative slopes the same. Event 1--The digital ramp enable bit is set, which has no effect on the DRG output because the bit is not effective until an input/output update occurs. Event 2--An input/output update registers the digital ramp enable bit. If DRCTL = 1 is in effect (the gray portion of the DRCTL trace), the DRG output immediately begins a positive slope (the gray portion of the DRG output trace). Otherwise, if DRCTL = 0, the DRG output is initialized to the lower limit. Event 3--DRCTL transitions to Logic 1 to initiate a positive slope at the DRG output. In this example, the DRCTL pin is held long enough to cause the DRG to reach the programmed upper limit. The DRG remains at the upper limit until the ramp accumulator is cleared (DRCTL = 0) or the upper limit is reprogrammed to a higher value. In the latter case, the DRG immediately resumes the previous positive slope profile. Event 4--DRCTL transitions to Logic 0 to initiate a negative slope at the DRG output. In this example, the DRCTL pin is held long enough to cause the DRG to reach the programmed lower limit. The DRG remains at the lower limit until DRCTL = 1, or until the lower limit is reprogrammed to a lower value. In the latter case, the DRG immediately resumes the previous negative slope profile. Event 5--DRCTL transitions to Logic 1 for the second time, initiating a second positive slope. Event 6--The positive slope profile is interrupted by DRHOLD transitioning to Logic 1. This stalls the ramp accumulator and freezes the DRG output at the last value. Event 7--DRHOLD transitions to Logic 0, releasing the ramp accumulator and reinstating the previous positive slope profile. Event 8--The clear digital ramp accumulator bit is set, which has no effect on the DRG because the bit is not effective until an input/output update is issued. Event 9--An input/output update registers that the clear digital ramp accumulator bit is set, resetting the ramp accumulator and forcing the DRG output to the programmed lower limit. The DRG output remains at the lower limit until the clear condition is removed. Event 10--The clear digital ramp accumulator bit is cleared, which has no effect on the DRG output because the bit is not effective until an input/output update is issued. Event 11--An input/output update registers that the clear digital ramp accumulator bit is cleared, releasing the ramp accumulator; and the previous positive slope profile restarts. Event 12--The autoclear digital ramp accumulator bit is set, which has no effect on the DRG output because the bit is not effective until an input/output update is issued. Rev. F | Page 25 of 45 AD9914 Data Sheet Event 13--An input/output update registers that the autoclear digital ramp accumulator bit is set, resetting the ramp accumulator. However, with an automatic clear, the ramp accumulator is held in reset for only a single DDS clock cycle. This forces the DRG output to the lower limit, but the ramp accumulator is immediately made available for normal operation. In this example, the DRCTL pin remains Logic 1; therefore, the DRG output restarts the previous positive ramp profile. tion between the limits. Likewise, if the DRG output is in the midst of a negative slope and the DRCTL pin transitions from Logic 0 to Logic 1, the DRG immediately switches to the positive slope parameters and resumes oscillation between the limits. No-Dwell Ramp Generation A no-dwell high DRG output waveform is shown in Figure 39. The waveform diagram assumes that the digital ramp no-dwell high bit is set and has been registered by an input/output update. The status of the DROVER pin is also shown with the assumption that the DRG over output enable bit has been set. When both no-dwell bits are set, the DROVER signal produces a positive pulse (two cycles of the DDS clock) each time the DRG output reaches either of the programmed limits (assuming that the DRG over output enable bit (0x01[13]) is set). The two no-dwell high and no-dwell low bits (0x01[18:17]) in CFR2 add to the flexibility of the DRG capabilities. During normal ramp generation, when the DRG output reaches the programmed upper or lower limit, it simply remains at the limit until the operating parameters dictate otherwise. However, during no-dwell operation, the DRG output does not necessarily remain at the limit. For example, if the digital ramp no-dwell high bit is set when the DRG reaches the upper limit, it automatically (and immediately) snaps to the lower limit (that is, it does not ramp back to the lower limit; it jumps to the lower limit). Likewise, when the digital ramp no-dwell low bit is set, and the DRG reaches the lower limit, it automatically (and immediately) snaps to the upper limit. The circled numbers in Figure 39 indicate specific events, which are explained as follows: Event 1--Indicates the instant that an input/output update registers that the digital ramp enable bit is set. Event 2--DRCTL transitions to Logic 1, initiating a positive slope at the DRG output. Event 3--DRCTL transitions to Logic 0, which has no effect on the DRG output. During no-dwell operation, the DRCTL pin is monitored for state transitions only; that is, the static logic level is immaterial. Event 4--Because the digital ramp no-dwell high bit is set, the moment that the DRG output reaches the upper limit, it immediately switches to the lower limit, where it remains until the next Logic 0 to Logic 1 transition of DRCTL. During no-dwell high operation, a positive transition of the DRCTL pin initiates a positive slope ramp, which continues uninterrupted (regardless of any further activity on the DRCTL pin) until the upper limit is reached. Event 5--DRCTL transitions from Logic 0 to Logic 1, which restarts a positive slope ramp. During no-dwell low operation, a negative transition of the DRCTL pin initiates a negative slope ramp, which continues uninterrupted (regardless of any further activity on the DRCTL pin) until the lower limit is reached. Event 6 and Event 7--DRCTL transitions are ignored until the DRG output reaches the programmed upper limit. Event 8--Because the digital ramp no-dwell high bit is set, the moment that the DRG output reaches the upper limit, it immediately switches to the lower limit, where it remains until the next Logic 0 to Logic 1 transition of DRCTL. Setting both no-dwell bits invokes a continuous ramping mode of operation; that is, the DRG output automatically oscillates between the two limits using the programmed slope parameters. Furthermore, the function of the DRCTL pin is slightly different. Instead of controlling the initiation of the ramp sequence, it only serves to change the direction of the ramp; that is, if the DRG output is in the midst of a positive slope and the DRCTL pin transitions from Logic 1 to Logic 0, the DRG immediately switches to the negative slope parameters and resumes oscilla- Operation with the digital ramp no-dwell low bit set (instead of the digital ramp no-dwell high bit) is similar, except that the DRG output ramps in the negative direction on a Logic 1 to Logic 0 transition of DRCTL and jumps to the upper limit upon reaching the lower limit. P DDS CLOCK CYCLES POSITIVE STEP SIZE +t UPPER LIMIT DRG OUTPUT LOWER LIMIT DROVER 1 2 3 4 5 6 Figure 39. No-Dwell High Ramp Generation Rev. F | Page 26 of 45 7 8 10836-035 DRCTL Data Sheet AD9914 DROVER Pin POWER-DOWN CONTROL The DROVER pin provides an external signal to indicate the status of the DRG. Specifically, when the DRG output is at either of the programmed limits, the DROVER pin is Logic 1; otherwise, it is Logic 0. In the special case of both no-dwell bits set, the DROVER pin pulses positive for two DDS clock cycles each time the DRG output reaches either of the programmed limits. The AD9914 offers the ability to independently power down three specific sections of the device. Power-down functionality applies to the following: Frequency Jumping Capability in DRG Mode Another feature of the AD9914 allows the user to skip a predefined range of frequencies during a normal sweep. The frequency jump enable bit in CFR2 (0x01[14]) enables this functionality. When this bit is set, the sweeping logic monitors the instantaneous frequency. When it reaches the frequency point defined in the lower frequency jump register (0x09) on the next accumulation cycle, instead of accumulating a delta tuning word as in normal sweeping, it skips directly to the frequency value set in the upper frequency jump register (0x0A), and vice versa. Figure 40 shows how this feature works. A second frequency jump can also be allowed if the frequency jump registers are reprogrammed before the sweeping is complete. The following rules apply when this feature is enabled. x x The frequency jump values must lie between the lower limit and upper limit of the frequency sweep range. The lower frequency jump register value must be lower than that of the upper frequency jump register value. UPPER LIMIT 0x09 A power-down of the digital core disables the ability to update the serial/parallel input/output port. However, the digital power-down bit (0x00[7]) can still be cleared to prevent the possibility of a nonrecoverable state. Software power-down is controlled via three independent power-down bits in CFR1. Software control requires that the EXT_PWR_DWN pin be forced to a Logic 0 state. In this case, setting the desired power-down bits (0x00[7:5]) via the serial input/output port powers down the associated functional block, whereas clearing the bits restores the function. Alternatively, all three functions can be simultaneously powered down via external hardware control through the EXT_PWR_DWN pin. When this pin is forced to Logic 1, all four circuit blocks are powered down regardless of the state of the power-down bits; that is, the independent power-down bits in CFR1 are ignored and overridden when EXT_PWR_DWN is Logic 1. 10836-036 0x0A t Digital core DAC Input REF CLK clock circuitry Based on the state of the external power-down control bit, the EXT_PWR_DWN pin produces either a full power-down or a fast recovery power-down. The fast recovery power-down mode maintains power to the DAC bias circuitry and the PLL, VCO, and input clock circuitry. Although the fast recovery power-down does not conserve as much power as the full power-down, it allows the device to awaken very quickly from the power-down state. FREQUENCY LOWER LIMIT x x x Figure 40. Frequency vs. Time Rev. F | Page 27 of 45 AD9914 Data Sheet PROGRAMMING AND FUNCTION PINS The state of the external function pins (F0 to F3) determines how the 32-bit parallel port is configured. Pin 28 to Pin 31 are the function pins. Refer to Table 10 for possible configurations. The AD9914 is equipped with a 32-bit parallel port. The 32-bit port is for programming the internal registers of the device in either serial mode or parallel mode as well as allowing for direct modulation control of frequency (FTW), phase (POW), and amplitude (AMP). Note that the OSK enable bit, CFR1[8], must be set to enable amplitude control, as shown in Table 10. Table 10. Parallel Port Configurations Function Pins, F[3:0]1 0000 Mode Description Parallel programming mode Bits[31:24] Data[15:8] (optional) 0001 Serial programming mode Not used 0010 Full 32 bits of direct frequency tuning word control. MSB and LSB aligned to parallel port pins Full 32 bits of direct frequency tuning word control with different parallel port pin assignments Full 16 bits of direct phase offset control and full 12 bits of direct amplitude control Full 12 bits of direct amplitude control and full 16 bits of direct phase offset control 24 bits of partial FTW control and 8 bits of partial amplitude control 24 bits of partial FTW control and 8 bits of partial phase offset control 24 bits of partial FTW control and 8 bits of partial amplitude control 24 bits of partial FTW control and 8 bits of partial phase offset control 24 bits of partial FTW control and 8 bits of partial amplitude control 24 bits of partial FTW control and 8 bits of partial phase offset control 24 bits of partial FTW control and 8 bits of partial amplitude control 24 bits of partial FTW control and 8 bits of partial phase offset control FTW[31:24] 32-Bit Parallel Port Pin Assignment Bits[23:16]3 Bits[15:8]4 Bits[7:0]5 Data[7:0] Address[7:0] Controls writes, reads, and 8-bit or 16-bit data-word. See the Parallel Programming section for details. Not used Not used Controls SCLK, SDIO, SDO, CS, and SYNCIO. See the Serial Programming section for details. FTW[23:16] FTW[15:8] FTW[7:0] FTW[15:8] FTW[7:0] FTW[31:24] FTW[23:16] POW[15:8] POW[7:0] AMP[11:8] AMP[7:0] AMP[11:8] AMP[7:0] POW[15:8] POW[7:0] FTW[31:24] FTW[23:16] FTW[15:8] AMP[15:8] FTW[31:24] FTW[23:16] FTW[15:8] POW[15:8] FTW[31:24] FTW[23:16] FTW[15:8] AMP[7:0] FTW[31:24] FTW[23:16] FTW[15:8] POW[7:0] FTW[23:16] FTW[15:8] FTW[7:0] AMP[15:8] FTW[23:16] FTW[15:8] FTW[7:0] POW[15:8] FTW[23:16] FTW[15:8] FTW[7:0] AMP[7:0] FTW[23:16] FTW[15:8] FTW[7:0] POW[7:0] Not used Not used Not used Not used Not used Not used Not used Not used 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 2 1 Pin 31 to Pin 28. Pin 68 to Pin 72, Pin 75 to 77. Pin 78 to Pin 81, Pin 87, Pin 88, Pin 1, Pin 2. 4 Pin 3 to Pin 5, Pin 8 to Pin 12. 5 Pin 13 to Pin 15, Pin 18 to Pin 22. 2 3 Rev. F | Page 28 of 45 Data Sheet FUNCTION PINS AD9914 4 F[3:0] DECODE DDS DIRECT MODES PARALLEL PORT PINS 32 32 BITS[31:0] 32 32 ROUTING LOGIC DQ CK SYNC_CLK FTW FREQUENCY POW PHASE AMP AMPLITUDE 16 12 32 FUNCTION PINS AND DIRECT MODE BITS[31:0] VS. FTW, POW, AMP F[3:0] BITS[31:24] BITS[23:16] BITS[15:8] 0000 0001 PARALLEL CONTROL BITS[7:0] 27 PARALLEL MODE SERIAL MODE FTW[31:24] FTW[23:16] FTW[15:8] 8 BITS[31:24] 8 BITS[23:16] 8 DIRECT MODE 0010 BITS[15:8] FTW[7:0] BIT 2 0011 FTW[15:8] FTW[7:0] FTW[31:24] FTW[23:16] BIT 1 0100 POW[15:8] POW[7:0] AMP[11:8] BIT 0 AMP[7:0] AMP[7:0] 0101 AMP[11:8] POW[15:8] POW[7:0] 0110 FTW[31:24] FTW[23:16] FTW[15:8] AMP[15:8] 0111 FTW[31:24] FTW[23:16] FTW[15:8] POW[15:8] 1000 FTW[31:24] FTW[23:16] FTW[15:8] AMP[7:0] OSK ENABLE PARALLEL MODE D[15:8] SYSTEM CLOCK PROGRAMMING REGISTERS D[7:0] A[7:0] WR IO_UPDATE RD 16 BITS/8 BITS SERIAL MODE SERIAL CONTROL 5 BIT 4 FTW[31:24] FTW[23:16] FTW[15:8] POW[7:0] 1010 FTW[23:16] FTW[15:8] FTW[7:0] AMP[15:8] BIT 3 1011 FTW[23:16] FTW[15:8] FTW[7:0] POW[15:8] BIT 2 1100 FTW[23:16] FTW[15:8] FTW[7:0] AMP[7:0] BIT 1 1101 FTW[23:16] FTW[15:8] FTW[7:0] POW[7:0] BIT 0 SYNCIO SDO SDIO SCLK CS 10836-046 1001 NOTES 1. AMP[11:0] CONTROLS AMPLITUDE. AMP[15:12] UNUSED. Figure 41. Parallel Port Block Diagram The 32-pin parallel port of the AD9914 works in conjunction with an independent set of four function pins that control the functionality of the parallel port. The 32 pins of the parallel port constitute a 32-bit word designated by Bits[31:0] (31 indicating the most significant bit (MSB) and 0 indicating the least significant bit (LSB)), with the four function pins designated as F[3:0]. The relationship between the function pins, the 32-pin parallel port, the internal programming registers, and the DDS control parameters (frequency, phase, and amplitude) is illustrated in Figure 41. Note that the parallel port operates in three different modes as defined by the function pins. The parallel mode is in effect when the logic levels applied to the function pins are F[3:0] = 0000. This allows the parallel port to function as a parallel interface providing access to all of the device programming registers. In parallel mode, the 32-pin port (Bits[31:0]) is subdivided into three groups with Bits[31:16] constituting 16 data bits, Bits[15:8] constituting eight address bits, and Bits[2:0] constituting three control bits. The address bits target a specific device register, whereas the data bits constitute the register content. The control bits establish read or write functionality as well as set the width of the data bus. That is, the user can select whether the data bus spans 16 bits (Bits[31:16]) or eight bits (Bits[23:16]). The parallel mode allows the user to write to the device registers at rates of up to 200 MBps using 16-bit data (or 100 MBps using 8-bit data). The serial mode is in effect when the logic levels applied to the function pins are F[3:0] = 0001. This allows the parallel port to function as a serial interface providing access to all of the device programming registers. In this mode, only five pins of the 32-pin parallel port are functional (Bits[4:0]). These pins provide chip select (CS), serial clock (SCLK), and input/output synchronization (SYNCIO) functionality for the serial interface, as well as two serial data lines (SDO and SDIO). The serial mode supports data rates of up to 80 Mbps. When the logic levels applied to the function pins are F[3:0] = 0010 to 1101 (note that 1110 and 1111 are unused), the parallel port functions as a high speed interface with direct access to the 32-bit frequency, 16-bit phase, and 12-bit amplitude parameters of the DDS core. The table in Figure 41 shows the segmentation of the 32-pin parallel port by identifying Bits[31:0] with the frequency (FTW[31:0]), phase (POW[15:0]), and amplitude (AMP[15:0]) parameters of the DDS. Note, however, that although AMP[15:0] indicate 16-bit resolution, the actual amplitude resolution is 12 bits. Therefore, only AMP[11:0] provide amplitude control (that is, AMP[15:12] are not used). Rev. F | Page 29 of 45 AD9914 Data Sheet Furthermore, to make use of amplitude control, the user must be sure to program the OSK enable bit in the CFR1 register (0x00[8]) to Logic 1. The combination of the F[3:0] pins and Bits[31:0] provides the AD9914 with unprecedented modulation capability by allowing the user direct control of the DDS parameters (frequency, phase, amplitude, or various combinations thereof). Furthermore, the parallel port operates at a sample rate equal to 1/24 of the system sample clock. This allows for updates of the DDS parameters at rates of up to 145 MSPS (assuming a 3.5 GHz system clock) allowing the AD9914 to accommodate applications with wideband modulation requirements. Be aware that the frequency, phase, and amplitude changes applied at the parallel port travel to the DDS core over different paths, experiencing different propagation times (latency). Therefore, modulating more than one DDS parameter necessitates setting the matched latency enable bit in the CFR2 register (0x01[15]) of the device, which equalizes the latency of each DDS parameter as it propagates from the parallel port to the DDS core. Note that high speed modulation requires a DAC reconstruction filter with sufficient bandwidth to accommodate the instantaneous time domain transitions. Because direct access to the DDS parameters occurs via the FTW, POW, and AMP registers, the IO_UPDATE pin (see Figure 41) adds another layer of flexibility. To accommodate this functionality, the AD9914 provides a register control bit, parallel port streaming enable (0x00[17]). When this bit is set to Logic 1, the parallel port operates without the need for an input/output update. When this bit is Logic 0, however, the device delivers the parallel port data to the appropriate registers (FTW, POW, AMP), but not to the DDS core. Data does not transfer to the DDS core until the user asserts the IO_UPDATE pin. For example, suppose that an application requires frequency and amplitude modulation with full 32-bit frequency resolution and full 12-bit amplitude resolution. Note that none of the F[3:0] pin combinations supports such modulation capability directly. To circumvent this problem, set the parallel port streaming enable bit (0x00[17]) to Logic 0. This allows for the use of two direct mode cycles of the 32-pin parallel port, each with a different function pin setting, without affecting the DDS core until assertion of the IO_UPDATE pin. That is, during the first direct mode cycle, set the function pins to F[3:0] = 0010, which routes all 32 bits to the FTW register (frequency). On the next direct mode cycle, set the function pins to F[3:0] = 0100, which provides full 12-bit access to the AMP register (amplitude). Be aware, however, this also provides access to the POW register (phase); therefore, be sure keep the phase bits static. Next, toggle the IO_UPDATE pin, which synchronously transfers the new frequency and phase values from the FTW and POW registers to the DDS core. This mode of operation reduces the overall modulation rate by a factor of three because it requires two separate operations on the parallel port followed by an IO_UPDATE. However, this still allows for modulation sample rates as high as ~49 MSPS. Rev. F | Page 30 of 45 Data Sheet AD9914 SERIAL PROGRAMMING To enable SPI operations, set Pin 28 (F0) to logic high and Pin 29 to Pin 31 (F1 to F3) to logic low. To program the AD9914 with a parallel interface, see the Parallel Programming section. CONTROL INTERFACE--SERIAL INPUT/OUTPUT The AD9914 serial port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The serial input/output is compatible with most synchronous transfer formats. The interface allows read/write access to all registers that configure the AD9914. MSB-first or LSB-first transfer formats are supported. In addition, the serial interface port can be configured as a single pin input/output (SDIO) allowing a 2-wire interface, or it can be configured as two unidirectional pins for input/output (SDIO and SDO), enabling a 3-wire interface. Two optional pins (I/O_SYNC and CS) enable greater flexibility for designing systems with the AD9914. Table 11. Serial Input/Output Pin Description Pin No. 18 19 20 21 22 Mnemonic D4/SYNCIO D3/SDO D2/SDIO/WR D1/SCLK/RD D0/CS/PWD Serial Input/Output Description SYNCIO SDO SDIO SCLK CS--chip select GENERAL SERIAL INPUT/OUTPUT OPERATION There are two phases to a serial communications cycle. The first is the instruction phase to write the instruction byte into the AD9914. The instruction byte contains the address of the register to be accessed and defines whether the upcoming data transfer is a write or read operation. For a write cycle, Phase 2 represents the data transfer between the serial port controller to the serial port buffer. The number of bytes transferred is a function of the register being accessed. For example, when accessing Control Function Register 2 (Address 0x01), Phase 2 requires that four bytes be transferred. Each bit of data is registered on each corresponding rising edge of SCLK. The serial port controller expects that all bytes of the register be accessed; otherwise, the serial port controller is put out of sequence for the next communication cycle. However, one way to write fewer bytes than required is to use the SYNCIO pin feature. The SYNCIO pin function can abort an input/output operation and reset the pointer of the serial port controller. After a SYNCIO, the next byte is the instruction byte. Note that every completed byte written prior to a SYNCIO is preserved in the serial port buffer. Partial bytes written are not preserved. At the completion of any communication cycle, the AD9914 serial port controller expects the next eight rising SCLK edges to be the instruction byte for the next communication cycle. After a write cycle, the programmed data resides in the serial port buffer and is inactive. I/O_UPDATE transfers data from the serial port buffer to active registers. The input/output update can be sent either after each communication cycle or when all serial operations are complete. In addition, a change in profile pins can initiate an input/output update. For a read cycle, Phase 2 is the same as the write cycle with the following differences: data is read from the active registers, not the serial port buffer, and data is driven out on the falling edge of SCLK. Note that, to read back any profile register (0x0B to 0x1A), the three external profile pins must be used. For example, if the profile register is Profile 5 (0x15), the PS[0:2] pins must equal 101.This is not required to write to the profile registers. INSTRUCTION BYTE The instruction byte contains the following information as shown in the instruction byte information bit map. Instruction Byte Information Bit Map MSB LSB I7 I6 I5 I4 I3 I2 I1 I0 R/W X A5 A4 A3 A2 A1 A0 R/W--Bit 7 of the instruction byte determines whether a read or write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation. X--Bit 6 of the instruction byte is don't care. A5, A4, A3, A2, A1, A0--Bit 5, Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle. SERIAL INPUT/OUTPUT PORT PIN DESCRIPTIONS SCLK--Serial Clock The serial clock pin synchronizes data to and from the AD9914 and to run the internal state machines. CS--Chip Select Bar CS is an active low input that allows more than one device on the same serial communications line. The SDO and SDIO pins go to a high impedance state when this input is high. If driven high during any communications cycle, that cycle is suspended until CS is reactivated low. Chip select (CS) can be tied low in systems that maintain control of SCLK. SDIO--Serial Data Input/Output Data is always written into the AD9914 on this pin. However, this pin can be used as a bidirectional data line. Bit 1 of CFR1 (0x00) controls the configuration of this pin. The default is Logic 0, which configures the SDIO pin as bidirectional. Rev. F | Page 31 of 45 AD9914 Data Sheet SDO--Serial Data Out SERIAL INPUT/OUTPUT TIMING DIAGRAMS Data is read from this pin for protocols that use separate lines for transmitting and receiving data. When the AD9914 operates in single bidirectional input/output mode, this pin does not output data and is set to a high impedance state. Figure 42 through Figure 45 provide basic examples of the timing relationships between the various control signals of the serial input/output port. Most of the bits in the register map are not transferred to the internal destinations until assertion of an input/output update, which is not included in the timing diagrams that follow. SYNCIO--Input/Output Reset SYNCIO synchronizes the input/output port state machines without affecting the contents of the addressable registers. An active high input on the SYNCIO pin causes the current communication cycle to abort. After SYNCIO returns low (Logic 0), another communication cycle can begin, starting with the instruction byte write. Note that the SCLK stall condition between the instruction byte cycle and data transfer cycle in Figure 42 to Figure 45 is not required. MSB/LSB TRANSFERS The AD9914 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by Bit 0 in CFR1 (0x00). The default format is MSB first. If LSB first is active, all data, including the instruction byte, must follow LSB-first convention. Note that the highest number found in the bit range column for each register is the MSB, and the lowest number is the LSB for that register. I/O_UPDATE--Input/Output Update The input/output update initiates the transfer of written data from the serial or parallel input/output port buffer to active registers. I/O_UPDATE is active on the rising edge, and the pulse width must be greater than one SYNC_CLK period. INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO I6 I7 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 10836-037 SCLK D0 Figure 42. Serial Port Write Timing, Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK I6 I7 I5 I4 I3 I2 I1 I0 DON'T CARE DO7 SDO DO5 DO6 DO4 DO3 DO2 DO1 DO0 10836-038 SDIO Figure 43. 3-Wire Serial Port Read Timing, Clock Stall Low INSTRUCTION CYCLE DATA TRANSFER CYCLE CS I7 I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0 10836-039 SDIO DO0 10836-040 SCLK Figure 44. Serial Port Write Timing, Clock Stall High INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK SDIO I7 I6 I5 I4 I3 I2 I1 I0 DO7 DO6 DO5 DO4 Figure 45. 2-Wire Serial Port Read Timing, Clock Stall High Rev. F | Page 32 of 45 DO3 DO2 DO1 Data Sheet AD9914 PARALLEL PROGRAMMING (8-/16-BIT) The state of the external function pins (F0 to F3) determine the type of interface used by the AD9914. Pin 28 to Pin 31 are dedicated function pins. To enable the parallel mode interface set Pin 28 to Pin 31 to logic low. Parallel programming consists of eight address lines and either eight or 16 bidirectional data lines for read/write operations. The logic state on Pin 22 determines the width of the data lines used. A logic low on Pin 22 sets the data width to eight bits, and logic high sets the data width to 16 bits. In addition, parallel mode has dedicated write/read control inputs. If 16-bit mode is used, the upper byte, Bits[15:8], goes to the addressed register and the lower byte, Bits[7:0], goes to the adjacent lower address. Parallel input/output operation allows write access to each byte of any register in a single input/output operation. Readback capability for each register is included to ease designing with the AD9914. A[7:0] D[7:0] OR D[15:0] A1 D1 tRDHIGH Table 12. Parallel Port Read Timing (See Figure 46) Parameter tADV tAHD Value 92 0 Unit ns max ns min tRDLOV tRDHOZ tRDLOW tRDHIGH 69 50 69 50 ns max ns max ns max ns max Test Conditions/Comments Address to data valid time Address hold time to RD signal inactive RD low to output valid RD high to data three-state RD signal minimum low time RD signal minimum high time Table 13. Parallel Port Write Timing (See Figure 47) Parameter tASU Value 1 Unit ns tDSU 3.8 ns tAHD 0 ns tDHD 0 ns tWRLOW tWRHIGH tWR 2.1 3.8 10.5 ns ns ns Test Conditions/Comments Address setup time to WR signal active Data setup time to WR signal active Address hold time to WR signal inactive Data hold time to WR signal inactive WR signal minimum low time WR signal minimum high time Minimum write time A2 A3 D2 D3 tRDLOW RD tRDLOV 10836-041 tRDHOZ tADV tAHD Figure 46. Parallel Port Read Timing Diagram tWR D[7:0] OR D[15:0] A1 A2 D1 A3 D2 WR tASU tWRHIGH tDSU tWRLOW D3 tAHD tDHD Figure 47. Parallel Port Write Timing Diagram Rev. F | Page 33 of 45 10836-042 A[7:0] AD9914 Data Sheet REGISTER MAP AND BIT DESCRIPTIONS Table 14. Register Map Register Name (Serial Address) CFR1-- Control Function Register 1 (0x00) Bit Range (Parallel Address) [7:0] (0x00) [15:8] (0x01) Bit 7 (MSB) Digital powerdown Load LRR at input/ output update Bit 6 DAC powerdown Autoclear digital ramp accumulator Bit 5 REF CLK input powerdown Autoclear phase accumulator [23:16] (0x02) CFR2-- Control Function Register 2 (0x01) [31:24] (0x03) [7:0] (0x04) [15:8] (0x05) [23:16] (0x06) CFR3-- Control Function Register 3 (0x02) CFR4-- Control Function Register 4 (0x03) Digital Ramp Lower Limit Register (0x04) [31:24] (0x07) [7:0] (0x08) [15:8] (0x09) [23:16] (0x0A) [31:24] (0x0B) [7:0] (0x0C) [15:8] (0x0D) [23:16] (0x0E) [31:24] (0x0F) [7:0] (0x10) [15:8] (0x11) [23:16] (0x12) [31:24] (0x13) Bit 4 Open Bit 3 External power-down control Bit 2 Open Bit 1 SDIO input only Clear digital ramp accumulator Clear phase accumulator Open External OSK enable OSK enable 0x00 Parallel port streaming enable Enable sine output VCO cal enable 0x01 Open Open Open Matched latency enable Profile mode enable Frequency jump enable Parallel data port enable DRG over Open output enable Digital ramp destination Manual ICP selection SYNC_CLK enable SYNC_CLK invert Reserved Open 0x09 Digital ramp enable Digital ramp nodwell high Digital ramp nodwell low Program modulus enable 0x00 0x00 Lock detect enable ICP[2:0] Minimum LDW[1:0] Feedback Divider N[7:0] Open Input divider reset Input divider[1:0] 0x00 0x00 Open Open Default Value (Hex)1 0x08 Bit 0 (LSB) LSB first mode Doubler enable 0x1C 0x19 PLL enable PLL input divider enable Doubler clock edge 0x00 Open 0x00 Requires register default value settings (0x20) 0x20 Requires register default value settings (0x21) 0x21 Requires register default value settings (0x05) 0x05 Auxiliary divider powerdown Open DAC CAL clock powerdown DAC CAL enable2 0x00 Digital ramp lower limit[7:0] 0x00 Digital ramp lower limit[15:8] 0x00 Digital ramp lower limit[23:16] 0x00 Digital ramp lower limit[31:24] 0x00 Rev. F | Page 34 of 45 Data Sheet Register Name (Serial Address) Digital Ramp Upper Limit Register (0x05) Rising Digital Ramp Step Size Register (0x06) Falling Digital Ramp Step Size Register (0x07) Digital Ramp Rate Register (0x08) Lower Frequency Jump Register (0x09) Upper Frequency Jump Register (0x0A) Profile 0 (P0) Frequency Tuning Word 0 Register (0x0B) Bit Range (Parallel Address) [7:0] (0x14) [15:8] (0x15) [23:16] (0x16) [31:24] (0x17) [7:0] (0x18) [15:8] (0x19) [23:16] (0x1A) [31:24] (0x1B) [7:0] (0x1C) [15:8] (0x1D) [23:16] (0x1E) [31:24] (0x1F) [7:0] (0x20) [15:8] (0x21) [23:16] (0x22) [31:24] (0x23) [7:0] (0x24) [15:8] (0x25) [23:16] (0x26) [31:24] (0x27) [7:0] (0x28) [15:8] (0x29) [23:16] (0x2A) [31:24] (0x2B) [7:0] (0x2C) [15:8] (0x2D) [23:16] (0x2E) [31:24] (0x2F) AD9914 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Digital ramp upper limit[7:0] Bit 1 Bit 0 (LSB) Default Value (Hex)1 0x00 Digital ramp upper limit[15:8] 0x00 Digital ramp upper limit[23:16] 0x00 Digital ramp upper limit[31:24] 0x00 Rising digital ramp increment step size[7:0] N/A Rising digital ramp increment step size[15:8] N/A Rising digital ramp increment step size[23:16] N/A Rising digital ramp increment step size[31:24] N/A Falling digital ramp decrement step size[7:0] N/A Falling digital ramp decrement step size[15:8] N/A Falling digital ramp decrement step size[23:16] N/A Falling digital ramp decrement step size[31:24] N/A Digital ramp positive slope rate[7:0] N/A Digital ramp positive slope rate[15:8] N/A Digital ramp negative slope rate[7:0] N/A Digital ramp negative slope rate[15:8] N/A Lower frequency jump point[7:0] 0x00 Lower frequency jump point[15:8] 0x00 Lower frequency jump point[23:16] 0x00 Lower frequency jump point[31:24] 0x00 Upper frequency jump point[7:0] 0x00 Upper frequency jump point[15:8] 0x00 Upper frequency jump point[23:16] 0x00 Upper frequency jump point[31:24] 0x00 Frequency Tuning Word 0[7:0] 0x00 Frequency Tuning Word 0[15:8] 0x00 Frequency Tuning Word 0[23:16] 0x00 Frequency Tuning Word 0[31:24] 0x00 Rev. F | Page 35 of 45 AD9914 Register Name (Serial Address) Profile 0 (P0) Phase/ Amplitude Register (0x0C) Profile 1 (P1) Frequency Tuning Word 1 Register (0x0D) Profile 1 (P1) Phase/ Amplitude Register (0x0E) Profile 2 (P2) Frequency Tuning Word 2 Register (0x0F) Profile 2 (P2) Phase/ Amplitude Register (0x10) Profile 3 (P3) Frequency Tuning Word 3 Register (0x11) Profile 3 (P3) Phase/ Amplitude Register (0x12) Data Sheet Bit Range (Parallel Address) [7:0] (0x30) [15:8] (0x31) [23:16] (0x32) [31:24] (0x33) [7:0] (0x34) [15:8] (0x35) [23:16] (0x36) [31:24] (0x37) [7:0] (0x38) [15:8] (0x39) [23:16] (0x3A) [31:24] (0x3B) [7:0] (0x3C) [15:8] (0x3D) [23:16] (0x3E) [31:24] (0x3F) [7:0] (0x40) [15:8] (0x41) [23:16] (0x42) [31:24] (0x43) [7:0] (0x44) [15:8] (0x45) [23:16] (0x46) [31:24] (0x47) [7:0] (0x48) [15:8] (0x49) [23:16] (0x4A) [31:24] (0x4B) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Phase Offset Word 0[7:0] Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex)1 0x00 Phase Offset Word 0[15:8] 0x00 Amplitude Scale Factor 0[7:0] 0x00 Open Amplitude Scale Factor 0[11:8] 0x00 Frequency Tuning Word 1[7:0] N/A Frequency Tuning Word 1[15:8] N/A Frequency Tuning Word 1[23:16] N/A Frequency Tuning Word 1[31:24] N/A Phase Offset Word 1[7:0] N/A Phase Offset Word 1[15:8] N/A Amplitude Scale Factor 1[7:0] N/A Open Amplitude Scale Factor 1[11:8] N/A Frequency Tuning Word 2[7:0] N/A Frequency Tuning Word 2[15:8] N/A Frequency Tuning Word 2[23:16] N/A Frequency Tuning Word 2[31:24] N/A Phase Offset Word 2[7:0] N/A Phase Offset Word 2[15:8] N/A Amplitude Scale Factor 2[7:0] N/A Open Amplitude Scale Factor 2[11:8] N/A Frequency Tuning Word 3[7:0] N/A Frequency Tuning Word 3[15:8] N/A Frequency Tuning Word 3[23:16] N/A Frequency Tuning Word 3[31:24] N/A Phase Offset Word 3[7:0] N/A Phase Offset Word 3[15:8] N/A Amplitude Scale Factor 3[7:0] N/A Open Amplitude Scale Factor 3[11:8] Rev. F | Page 36 of 45 N/A Data Sheet Register Name (Serial Address) Profile 4 (P4) Frequency Tuning Word 4 Register (0x13) Profile 4 (P4) Phase/ Amplitude Register (0x14) Profile 5 (P5) Frequency Tuning Word 5 Register (0x15) Profile 5 (P5) Phase/ Amplitude Register (0x16) Profile 6 (P6) Frequency Tuning Word 6 Register (0x17) Profile 6 (P6) Phase/ Amplitude Register (0x18) Profile 7 (P7) Frequency Tuning Word 7 Register (0x19) Bit Range (Parallel Address) [7:0] (0x4C) [15:8] (0x4D) [23:16] (0x4E) [31:24] (0x4F) [7:0] (0x50) [15:8] (0x51) [23:16] (0x52) [31:24] (0x53) [7:0] (0x54) [15:8] (0x55) [23:16] (0x56) [31:24] (0x57) [7:0] (0x58) [15:8] (0x59) [23:16] (0x5A) [31:24] (0x5B) [7:0] (0x5C) [15:8] (0x5D) [23:16] (0x5E) [31:24] (0x5F) [7:0] (0x60) [15:8] (0x61) [23:16] (0x62) [31:24] (0x63) [7:0] (0x64) [15:8] (0x65) [23:16] (0x66) [31:24] (0x67) AD9914 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Frequency Tuning Word 4[7:0] Bit 1 Bit 0 (LSB) Default Value (Hex)1 N/A Frequency Tuning Word 4[15:8] N/A Frequency Tuning Word 4[23:16] N/A Frequency Tuning Word 4[31:24] N/A Phase Offset Word 4[7:0] N/A Phase Offset Word 4[15:8] N/A Amplitude Scale Factor 4[7:0] N/A Open Amplitude Scale Factor 4[11:8] N/A Frequency Tuning Word 5[7:0] N/A Frequency Tuning Word 5[15:8] N/A Frequency Tuning Word 5[23:16] N/A Frequency Tuning Word 5[31:24] N/A Phase Offset Word 5[7:0] N/A Phase Offset Word 5[15:8] N/A Amplitude Scale Factor 5[7:0] N/A Open Amplitude Scale Factor 5[11:8] N/A Frequency Tuning Word 6[7:0] N/A Frequency Tuning Word 6[15:8] N/A Frequency Tuning Word 6[23:16] N/A Frequency Tuning Word 6[31:24] N/A Phase Offset Word 6[7:0] N/A Phase Offset Word 6[15:8] N/A Amplitude Scale Factor 6[7:0] N/A Open Amplitude Scale Factor 6[11:8] n/a Frequency Tuning Word 7[7:0] N/A Frequency Tuning Word 7[15:8] N/A Frequency Tuning Word 7[23:16] N/A Frequency Tuning Word 7[31:24] N/A Rev. F | Page 37 of 45 AD9914 Register Name (Serial Address) Profile 7 (P7) Phase/ Amplitude Register (0x1A) USR0 (0x1B) 1 2 Data Sheet Bit Range (Parallel Address) [7:0] (0x68) [15:8] (0x69) [23:16] (0x6A) [31:24] (0x6B) [7:0] (0x6C) [15:8] (0x6D) [23:16] (0x6E) [31:24] (0x6F) Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Phase Offset Word 7[7:0] Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex)1 N/A Phase Offset Word 7[15:8] N/A Amplitude Scale Factor 7[7:0] N/A Open Amplitude Scale Factor 7[11:8] N/A Requires register default value settings (0x00) 0x00 Requires register default value settings (0x08) 0x08 Requires register default value settings (0x00) 0x00 Open PLL lock Read only A master reset is required after power up. The master reset returns the internal registers to the default values. The DAC CAL enable bit must be manually set and then cleared after each power-up and every time REF CLK or the internal system clock is changed. This initiates an internal calibration routine to optimize the setup and hold times for internal DAC timing. Failure to calibrate degrades ac performance or makes the device nonfunctional. Rev. F | Page 38 of 45 Data Sheet AD9914 REGISTER BIT DESCRIPTIONS The serial input/output port registers span an address range of 0 to 27 (0x00 to 0x1B in hexadecimal notation). This represents a total of 28 individual serial registers. If programming in parallel mode, the number of parallel registers increases to 112 individual parallel registers. Additionally, the registers are assigned names according to the functionality. In some cases, a register is given a mnemonic descriptor. For example, the register at Serial Address 0x00 is named Control Function Register 1 and is assigned the mnemonic CFR1. This section provides a detailed description of each bit in the AD9914 register map. For cases in which a group of bits serves a specific function, the entire group is considered a binary word and is described in aggregate. optional register mnemonic (in parentheses). Also given is the serial address in hexadecimal format and the number of bytes assigned to the register. Following each subheading is a table containing the individual bit descriptions for that particular register. The location of the bit(s) in the register is indicated by a single number or a pair of numbers separated by a colon; that is, a pair of numbers (A:B) indicates a range of bits from the most significant (A) to the least significant (B). For example, [5:2] implies Bit Position 5 to Bit Position 2, inclusive, with Bit 0 identifying the LSB of the register. Unless otherwise stated, programmed bits are not transferred to the internal destinations until the assertion of the I/O_UPDATE pin or a profile pin change. This section is organized in sequential order of the serial addresses of the registers. Each subheading includes the register name and Control Function Register 1 (CFR1)--Address 0x00 Table 15. Bit Description for CFR1 Bits [31:25] 24 Mnemonic Open VCO cal enable [23:18] 17 Open Parallel port streaming enable 16 Enable sine output 15 Load LRR at input/output update 14 Autoclear digital ramp accumulator 13 Autoclear phase accumulator 12 Clear digital ramp accumulator 11 Clear phase accumulator 10 Open Description 1 = initializes the auto internal PLL calibration. The calibration is required if the PLL is to provide the internal system clock. Must first be reset to Logic 0 before another calibration can be issued. Open. 0 = the 32 bit parallel port needs an input/output update to activate or register any FTW, POW, or AMP data presented to the 32-bit parallel port. 1 = the parallel port continuously samples data on the 32 input pins using SYNC_CLK and multiplexes the value of FTW/POW/AMP accordingly, per the configuration of the F0 to F3 pins, without the need of an input/output update. Data must meet the setup and hold times of the SYNC_CLK rising edge. If the function pins are used dynamically to alter data between parameters, they must also meet the timing of the SYNC_CLK edge. 0 = cosine output of the DDS is selected. 1 = sine output of the DDS is selected (default). Ineffective unless CFR2[19] = 1. 0 = normal operation of the digital ramp timer (default). 1 = interrupts the digital ramp timer operation to load a new linear ramp rate (LRR) value any time I/O_UPDATE is asserted or a PS[2:0] change occurs. 0 = normal operation of the DRG accumulator (default). 1 = the digital ramp accumulator is reset for one cycle of the DDS clock (SYNC_CLK), after which the accumulator automatically resumes normal operation. As long as this bit remains set, the ramp accumulator is momentarily reset each time an input/output update is asserted or a PS[2:0] change occurs. This bit is synchronized with either an input/output update or a PS[2:0] change and the next rising edge of SYNC_CLK. 0 = normal operation of the DDS phase accumulator (default). 1 = synchronously resets the DDS phase accumulator anytime I/O_UPDATE is asserted or a profile change occurs. 0 = normal operation of the digital ramp generator (default). 1 = asynchronous, static reset of the DRG accumulator. The ramp accumulator remains reset as long as this bit remains set. This bit is synchronized with either an input/output update or a PS[2:0] change and the next rising edge of SYNC_CLK. 0 = normal operation of the DDS phase accumulator (default). 1 = asynchronous, static reset of the DDS phase accumulator as long as this bit is set. This bit is synchronized with either an input/output update or a PS[2:0] change and the next rising edge of SYNC_CLK. Open. Rev. F | Page 39 of 45 AD9914 Bits 9 Mnemonic External OSK enable 8 OSK enable 7 Digital power-down 6 DAC power-down 5 REFCLK input power-down 4 3 Open External power-down control 2 1 Open SDIO input only 0 LSB first mode Data Sheet Description 0 = manual OSK enabled (default). 1 = automatic OSK enabled. Ineffective unless CFR1[8] = 1. 0 = OSK disabled (default). 1 = OSK enabled. To engage any digital amplitude adjust using DRG, profile, or direct mode via the 32-bit parallel port, or OSK pin, this bit must be set. This bit is effective without the need for an input/output update. 0 = clock signals to the digital core are active (default). 1 = clock signals to the digital core are disabled. 0 = DAC clock signals and bias circuits are active (default). 1 = DAC clock signals and bias circuits are disabled. This bit is effective without the need for an input/output update. 0 = REFCLK input circuits and PLL are active (default). 1 = REFCLK input circuits and PLL are disabled. Open. 0 = assertion of the EXT_PWR_DWN pin affects power-down. 1 = assertion of the EXT_PWR_DWN pin affects fast recovery power-down. Open. 0 = configures the SDIO pin for bidirectional operation; 2-wire serial programming mode (default). 1 = configures the serial data input/output pin (SDIO) as an input only pin; 3-wire serial programming mode. 0 = configures the serial input/output port for MSB-first format (default). 1 = configures the serial input/output port for LSB-first format. Control Function Register 2 (CFR2)--Address 0x01 Table 16. Bit Descriptions for CFR2 Bit(s) [31:24] 23 Mnemonic Open Profile mode enable 22 Parallel data port enable [21:20] 19 Digital ramp destination Digital ramp enable 18 Digital ramp no-dwell high 17 Digital ramp no-dwell low 16 Programmable modulus enable 15 Matched latency enable 14 Frequency jump enable Description Open. 0 = disables profile mode functionality (default). 1 = enables profile mode functionality. Profile pins select the desired profile. See the Parallel Data Port Modulation Mode section for more details. 0 = disables parallel data port modulation functionality (default). 1 = enables parallel data port modulation functionality. See Table 9 for details. Default is 00. See the Digital Ramp Generator (DRG) section for more details. 0 = disables digital ramp generator functionality (default). 1 = enables digital ramp generator functionality. See the Digital Ramp Generator (DRG) section for details. 0 = disables no-dwell high functionality (default). 1 = enables no-dwell high functionality. See the Digital Ramp Generator (DRG) section for details. 0 = disables no-dwell low functionality (default). 1 = enables no-dwell low functionality. 0 = disables programmable modulus. 1 = enables programmable modulus. 0 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at the output in the order listed in Table 2 under data latency (pipe line delay)(default). 1 = simultaneous application of amplitude, phase, and frequency changes to the DDS arrive at the output simultaneously. 0 = disables frequency jump. 1 = enables frequency jump mode. Must have the digital generator DRG enabled for this feature. Rev. F | Page 40 of 45 Data Sheet Bit(s) 13 Mnemonic DRG over output enable 12 11 Open SYNC_CLK enable 10 SYNC_CLK invert 9 [8:0] Reserved Open AD9914 Description 0 = disables the DROVER output. 1 = enables the DROVER output. Open. 0 = the SYNC_CLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate and provide timing to the data assembler. 1 = the internal SYNC_CLK signal appears at the SYNC_CLK pin (default). 0 = normal SYNC_CLK polarity; Q data associated with Logic 1, I data with Logic 0 (default). 1 = inverted SYNC_CLK polarity. Keep logic 0. Open. Control Function Register 3 (CFR3)--Address 0x02 Table 17. Bit Descriptions for CFR3 Bit(s) [31:23] 22 Mnemonic Open Input divider reset [21:20] Input divider 19 Doubler enable 18 PLL enable 17 PLL input divider enable 16 Doubler clock edge [15:8] Feedback divider N 7 6 Open Manual ICP selection [5:3] 2 ICP Lock detect enable [1:0] Minimum LDW Description Open. 0 = disables input divider reset function. 1 = initiates an input divider reset. Divides the input REF CLK signal by one of four values (1, 2, 4, 8). Bit 17 must be set to Logic 1 to enable the PLL input divider. 00 = divide by 1. 01 = divide by 2. 10 = divide by 4. 11 = divide by 8. 0 = disables the doubler feature. 1 = enables the doubler feature. Must have the doubler clock edge bit set to Logic 1 to utilize this feature. 0 = disables the internal PLL. 1 = the internal PLL is enabled and the output generates the system clock. The PLL must be calibrated when enabled via VCO calibration in Register CFR1, Bit 24. 0 = disables the PLL input divider function. 1 = enables the PLL input divider function. 0 = disables the internal doubler circuit. 1 = enables the doubler circuit. Must have doubler enable bit set to Logic 1 to utilize this feature. The N divider value in Bits[15:8] is one part of the total PLL multiplication available. The second part is the fixed divide by two element in the feedback path. Therefore, the total PLL multiplication value is 2N. The valid N divider range is 10x to 255x. The default N value for Bits[15:8] = 25. This sets the total default PLL multiplication to 50x or 2N. Open. 0 = the internal charge pump current is chosen automatically during the VCO calibration routine (default). 1 = the internal charge pump is set manually per Table 7. Manual charge pump current selection. See Table 7. 0 = disables PLL lock detection. 1 = enables PLL lock detection. Selects the number of REF CLK cycles that the phase error (at the PFD inputs) must remain within before a PLL lock condition can be read back via Bit 24 in Register 0x00. 00 = 128 REF CLK cycles. 01 = 256 REF CLK cycles. 10 = 512 REF CLK cycles. 11 = 1024 REF CLK cycles. Rev. F | Page 41 of 45 AD9914 Data Sheet Control Function Register 4 (CFR4)--Address 0x03 Table 18. Bit Descriptions for DAC Bit(s) [31:27] 26 Mnemonic Open Auxiliary divider power-down 25 DAC CAL clock power-down 24 DAC CAL enable [23:0] (See description) Description Open 0 = enables the SYNC OUT circuitry. 1 = disables the SYNC OUT circuitry 0 = enables the DAC CAL clock if Bit 26 in Register 0x03 is Logic 0. 1 = disables the DAC CAL clock. 1 = initiates an auto DAC calibration. The DAC CAL calibration is required at power-up and any time the internal system clock is changed. These bits must always be programmed with the default values listed in the default column in Table 14. Digital Ramp Lower Limit Register--Address 0x04 This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section for details. Table 19. Bit Descriptions for Digital Ramp Lower Limit Register Bit(s) [31:0] Mnemonic Digital ramp lower limit Description 32-bit digital ramp lower limit value. Digital Ramp Upper Limit Register--Address 0x05 This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section for details. Table 20. Bit Descriptions for Digital Ramp Limit Register Bit(s) [31:0] Mnemonic Digital ramp upper limit Description 32-bit digital ramp upper limit value. Rising Digital Ramp Step Size Register--Address 0x06 This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section for details. Table 21. Bit Descriptions for Rising Digital Ramp Step Size Register Bit(s) [31:0] Mnemonic Rising digital ramp increment step size Description 32-bit digital ramp increment step size value. Falling Digital Ramp Step Size Register--Address 0x07 This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section for details. Table 22. Bit Descriptions for Falling Digital Ramp Step Size Register Bit(s) [31:0] Mnemonic Falling digital ramp decrement step size Description 32-bit digital ramp decrement step size value. Rev. F | Page 42 of 45 Data Sheet AD9914 Digital Ramp Rate Register--Address 0x08 This register is effective only if the digital ramp enable bit in the CFR2 register (0x01[19]) = 1. See the Digital Ramp Generator (DRG) section for details. Table 23. Bit Descriptions for Digital Ramp Rate Register Bit(s) [31:16] [15:0] Mnemonic Digital ramp negative slope rate Digital ramp positive slope rate Description 16-bit digital ramp negative slope value that defines the time interval between decrement values. 16-bit digital ramp positive slope value that defines the time interval between increment values. Lower Frequency Jump Register--Address 0x09 This register is effective only if the digital ramp enable bit (0x01[19]) = 1 and the frequency jump enable bit (0x01[14]) = 1 in the CFR2 register. See the Digital Ramp Generator (DRG) section for details. Table 24. Bit Descriptions for Lower Frequency Jump Register Bit(s) [31:0] Mnemonic Lower frequency jump point Description 32-bit digital lower frequency jump value. Any time the lower frequency jump value is reached during a frequency sweep, the output frequency jumps to the upper frequency value instantaneously and continues frequency sweeping in a phase-continuous manner. Upper Frequency Jump Register--Address 0x0A This register is effective only if the digital ramp enable bit (0x01[19]) = 1 and the frequency jump enable bit (0x01[14]) = 1 in the CFR2 register. See the Digital Ramp Generator (DRG) section for details. Table 25. Bit Descriptions for Upper Frequency Jump Register Bit(s) [31:0] Mnemonic Upper frequency jump point Description 32-bit digital upper frequency jump value. Any time the upper frequency jump value is reached during a frequency sweep, the output frequency jumps to the lower frequency value instantaneously and continues frequency sweeping in a phase-continuous manner. Rev. F | Page 43 of 45 AD9914 Data Sheet Profile Registers There are 16 serial input/output addresses (Address 0x0B to Address 0x01A) dedicated to device profiles. Eight of the 16 profiles house up to eight single tone frequencies. The remaining eight profiles contain the corresponding phase offset and amplitude parameters relative to the profile pin setting. To enable profile mode, set the profile mode enable bit in CFR2 (0x01[23]) = 1. The active profile register is selected using the external PS[2:0] pins. Profile 0 to Profile 7, Single Tone Registers--0x0B, 0x0D, 0x0F, 0x11, 0x13, 0x15, 0x17, 0x19 Four bytes are assigned to each register. Table 26. Bit Descriptions for Profile 0 to Profile 7 Single Tone Registers Bit(s) [31:0] Mnemonic Frequency tuning word Description This 32-bit number controls the DDS frequency. Profile 0 to Profile 7, Phase Offset and Amplitude Registers--0x0C, 0x0E, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1A Four bytes are assigned to each register. Table 27. Bit Descriptions for Profile 0 to Profile 7 Phase Offset and Amplitude Registers Bit(s) [31:28] [27:16] Mnemonic Open Amplitude scale factor [15:0] Phase offset word Description Open. This 12-bit word controls the DDS frequency. Note that the OSK enable bit (0x00[8]) must be set to logic high to make amplitude adjustments. This 16-bit word controls the DDS frequency. USR0 Register--Address 0x1B Table 28. Bit Descriptions for USR0 Register Bit(s) [31:25] 24 [23:0] Mnemonic Open PLL lock (See description) Description This is a readback bit only. If Logic 1 is read back, the PLL is locked. Logic 0 represents a nonlocked state. These bits must always be programmed with the default values listed in the default column in Table 14. Rev. F | Page 44 of 45 Data Sheet AD9914 OUTLINE DIMENSIONS 12.10 12.00 SQ 11.90 0.30 0.23 0.18 0.60 MAX 0.60 MAX 88 67 66 1 PIN 1 INDICATOR PIN 1 INDICATOR 0.50 BSC 11.85 11.75 SQ 11.65 0.50 0.40 0.30 PKG-004081 SEATING PLANE 10.50 REF 0.045 0.025 0.005 COPLANARITY 0.08 0.138~0.194 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VRRD EXCEPT FOR MINIMUM THICKNESS AND LEAD COUNT. 07-03-2014-C 0.70 0.65 0.60 12 MAX 22 23 45 44 BOTTOM VIEW TOP VIEW *0.90 0.85 0.75 6.80 6.70 SQ 6.60 EXPOSED PAD Figure 48. 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 12 mm x 12 mm Body, Very Thin Quad (CP-88-5) Dimensions shown in millimeters ORDERING GUIDE Parameter1 AD9914BCPZ AD9914BCPZ-REEL7 AD9914/PCBZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 88-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. (c)2012-2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10836-0-6/16(F) Rev. F | Page 45 of 45 Package Option CP-88-5 CP-88-5