D DGK SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E P www.ti.com SLLS562G - AUGUST 2009 - REVISED MAY 2009 Low-Power RS-485 Transceivers, Available in a Small MSOP-8 Package FEATURES 1 * * Available in a Small MSOP-8 Package Meets or Exceeds the Requirements of the TIA/EIA-485A Standard Low Quiescent Power - 0.3 mA Active Mode - 1 nA Shutdown Mode 1/8 Unit Load--Up to 256 Nodes on a Bus Bus-Pin ESD Protection Up to 15 kV Industry-Standard SN75176 Footprint Failsafe Receiver (Bus Open, Bus Shorted, Bus Idle) Glitch-Free Power-Up/Down Bus Inputs and Outputs * * * * * * APPLICATIONS * * * * * * * DESCRIPTION These devices are half-duplex transceivers designed for RS-485 data bus networks. Powered by a 5-V supply, they are fully compliant with TIA/EIA-485A standard. With controlled transition times, these devices are suitable for transmitting data over long twisted-pair cables. SN65HVD3082E and SN75HVD3082E devices are optimized for signaling rates up to 200 kbps. SN65HVD3085E is suitable for data transmission up to 1 Mbps, whereas SN65HVD3088E is suitable for applications requiring signaling rates up to 20 Mbps. These devices are designed to operate with very low supply current, typically 0.3 mA, exclusive of the load. When in the inactive shutdown mode, the supply current drops to a few nanoamps, making these devices ideal for power-sensitive applications. The wide common-mode range and high ESD protection levels of these devices make them suitable for demanding applications such as energy meter networks, electrical inverters, status/command signals across telecom racks, cabled chassis interconnects, and industrial automation networks where noise tolerance is essential. These devices match the industry-standard footprint of SN75176. Power-on reset circuits keep the outputs in a high impedance state until the supply voltage has stabilized. A thermal shutdown function protects the device from damage due to system fault conditions. The SN75HVD3082E is characterized for operation from 0C to 70C and SN65HVD308xE are characterized for operation from -40C to 85C air temperature. Energy Meter Networks Motor Control Power Inverters Industrial Automation Building Automation Networks Battery-Powered Applications Telecommunications Equipment ORDERING INFORMATION: TA SIGNALING RATE (Mbps) 0C to 70C -40C to 85C (1) (2) PACKAGE TYPE P D (1) DGK (2) 0.2 SN75HVD3082EP Marked as 75HVD3082 SN75HVD3082ED Marked as VN3082 SN75HVD3082EDGK Marked as NWM 0.2 SN65HVD3082EP Marked as 65HVD3082 SN65HVD3082ED Marked as VP3082 SN65HVD3082EDGK Marked as NWN 1 SN65HVD3085ED Marked as VP3085 SN65HVD3085EDGK Marked as NWK 20 SN65HVD3088ED Marked as VP3088 SN65HVD3088EDGK Marked as NWH The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD3082EDR). The DGK package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD3082EDGKR). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2009, Texas Instruments Incorporated SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E SLLS562G - AUGUST 2009 - REVISED MAY 2009 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) (2) UNIT Supply voltage range, VCC -0.5 V to 7 V Voltage range at A or B -9 V to 14 V Voltage range at any logic pin -0.3 V to VCC + 0.3 V Receiver output current -24 mA to 24 mA Voltage input, transient pulse, A and B, through 100 . See Figure 13 -50 to 50 V Junction Temperature, TJ 170C Continuous total power dissipation (1) (2) See the Package Dissipation Table Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. PACKAGE DISSIPATION RATINGS PACKAGE D P DGK (1) (2) (3) 2 JEDEC BOARD MODEL TA < 25C POWER RATING Low k (2) 507 mW (3) Low k (2) (1) TA = 70C POWER RATING TA = 85C POWER RATING 4.82 mW/C 289 mW 217 mW 824 mW 7.85 mW/C 471 mW 353 mW 686 mW 6.53 mW/C 392 mW 294 mW Low k (2) 394 mW 3.76 mW/C 255 mW 169 mW (3) 583 mW 5.55 mW/C 333 mW 250 mW High k High k DERATING FACTOR ABOVE TA = 25C This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. In accordance with the low-k thermal metric definitions of EIA/JESD51-3 In accordance with the high-k thermal metric definitions of EIA/JESD51-7 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E www.ti.com SLLS562G - AUGUST 2009 - REVISED MAY 2009 RECOMMENDED OPERATING CONDITIONS (1) over operating free-air temperature range unless otherwise noted MIN NOM MAX UNIT Supply voltage, VCC 4.5 5.5 Voltage at any bus terminal (separately or common mode) , VI -7 12 High-level input voltage (D, DE, or RE inputs), VIH 2 VCC V Low-level input voltage (D, DE, or RE inputs), VIL 0 0.8 V -12 12 V -60 60 -8 8 Differential input voltage, VID Driver Output current, IO Receiver Differential load resistance, RL 54 1 SN65HVD3088E Junction temperature, TJ (1) (2) 0.2 SN65HVD3085E Operating free-air temperature, TA mA 60 SN65HVD3082E, SN75HVD3082E Signaling rate, 1/tUI V Mbps 20 SN65HVD3082E, SN65HVD3085E, SN65HVD3088E SN75HVD3082E (2) -40 85 0 70 -40 130 C C The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. See thermal characteristics table for information on maintenance of this specification for the DGK package. SUPPLY CURRENT over operating free-air temperature range (unless otherwise noted) TYP (1) MAX UNIT Driver and receiver enabled D at VCC or open, DE at VCC, RE at 0 V, No load 425 900 A Driver enabled, receiver disabled D at VCC or open, DE at VCC, RE at VCC, No load 330 600 A Receiver enabled, driver disabled D at VCC or open, DE at 0 V, RE at 0 V, No load 300 600 A Driver and receiver disabled D at VCC or open, DE at 0 V, RE at VCC 0.001 2 A PARAMETER ICC (1) TEST CONDITIONS MIN All typical values are at 25C and with a 5-V supply. ELECTROSTATIC DISCHARGE PROTECTION PARAMETER TEST CONDITIONS Human body model Bus terminals and GND Human body model (2) Charged-device-model (3) Electrical Fast Transient/Burst (1) (2) (3) (4) (4) MIN TYP (1) MAX UNIT 15 kV All pins 4 kV All pins 1 kV A, B, and GND 4 kV All typical values at 25C. Tested in accordance with JEDEC Standard 22, Test Method A114-A and IEC 60749-26. Tested in accordance with JEDEC Standard 22, Test Method C101. Tested in accordance with IEC 61000-4-4. Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E 3 SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E SLLS562G - AUGUST 2009 - REVISED MAY 2009 www.ti.com DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS IO = 0, No Load |VOD| Differential output voltage RL = 54 , See Figure 1 RL = 100 Change in magnitude of differential output voltage VOC(SS) Steady-state common-mode output voltage TYP (1) 3 4.3 1.5 2.3 MAX UNIT V 2 VTEST = -7 V to 12 V, See Figure 2 |VOD| MIN 1.5 See Figure 1 and Figure 2 -0.2 0 0.2 1 2.6 3 -0.1 0 0.1 See Figure 3 V V VOC(SS) Change in steady-state common-mode output voltage VOC(PP) Peak-to-peak common-mode output voltage See Figure 3 IOZ High-impedance output current See receiver input currents II Input current D, DE -100 100 A IOS Short-circuit output current -7 V VO 12 V, See Figure 7 -250 250 mA (1) 500 mV All typical values are at 25C and with a 5-V supply. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER tPLH tPHL TEST CONDITIONS Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output RL = 54 , CL = 50 pF, See Figure 4 Differential output signal rise time Differential output signal fall time RL = 54 , CL = 50 pF, See Figure 4 MIN TYP MAX HVD3082E 700 1300 HVD3085E 150 500 HVD3088E 12 20 HVD3082E tr tf tsk(p) Pulse skew (|tPHL - tPLH|) tPZH tPZL tPHZ tPLZ tPZH(SHDN) tPZL(SHDN) 4 RL = 54 , CL = 50 pF, See Figure 4 Propagation delay time, high-impedance-tohigh-level output Propagation delay time, high-impedance-tolow-level output RL = 110 , RE at 0 V, See Figure 5 and Figure 6 Propagation delay time, high-level-to-highimpedance output Propagation delay time, low-level-to-highimpedance output RL = 110 , RE at 0 V, See Figure 5 and Figure 6 Propagation delay time, shutdown-to-highlevel output Propagation delay time, shutdown-to-lowlevel output RL = 110 , RE at VCC, See Figure 5 Submit Documentation Feedback 900 1500 HVD3085E 500 200 300 HVD3088E 7 15 HVD3082E 20 200 HVD3085E 5 50 HVD3088E 1.4 2 HVD3082E 2500 7000 HVD3085E 1000 2500 HVD3088E 13 30 HVD3082E 80 200 HVD3085E 60 100 HVD3088E 12 30 HVD3082E 3500 7000 HVD3085E 2500 4500 HVD3088E 1600 2600 UNIT ns ns ns ns ns ns Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E www.ti.com SLLS562G - AUGUST 2009 - REVISED MAY 2009 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN VIT+ Positive-going differential input threshold voltage IO = -8 mA VIT- Negative-going differential input threshold voltage IO = 8 mA Vhys Hysteresis voltage (VIT+ - VIT-) VOH High-level output voltage VID = 200 mV, IOH = -8 mA, See Figure 8 VOL Low-level output voltage VID = -200 mV, IO = 8 mA, See Figure 8 IOZ High-impedance-state output current VO = 0 or VCC, RE = VCC TYP (1) MAX UNIT -85 -10 mV -200 -115 mV 30 mV 4 4.6 0.4 V 1 A 0.04 0.1 0.06 0.125 -1 VIH = 12 V, VCC = 5 V VIH = 12 V, VCC = 0 V II Bus input current IIH High-level input current, (RE) VIH = 2 V IIL Low-level Input current, (RE) VIL = 0.8 V Cdiff Differential input capacitance VI = 0.4 sin (4E6t) + 0.5 V, DE at 0 V (1) V 0.15 mA VIH = -7 V, VCC = 5 V -0.1 -0.04 VIH = -7 V, VCC = 0 V -0.05 -0.03 -60 -30 A -60 -30 A 7 pF All typical values are at 25C and with a 5-V supply. RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions unless otherwise noted PARAMETER tPLH tPHL tsk(p) TEST CONDITIONS HVD3082E HVD3085E Propagation delay time, low-to-highlevel output Propagation delay time, high-to-lowlevel output MIN TYP MAX 75 200 HVD3086E CL = 15 pF, See Figure 9 HVD3082E HVD3085E 79 Output signal rise time tf Output signal fall time tPZH VID = -1.5 V to 1.5 V, CL = 15 pF, See Figure 9 HVD3082E HVD3085E Output enable time to high level 4 tPHZ Output enable time to low level Output enable time from high level CL = 15 pF, DE at 3 V See Figure 10 and Figure 11 HVD3082E HVD3085E Output disable time from low level HVD3082E HVD3085E ns 1.8 3 ns 5 50 tPZL(SHDN) Propagation delay time, shutdown-tohigh-level output CL = 15 pF, DE at 0 V, Propagation delay time, shutdown-to-low- See Figure 12 level output Copyright (c) 2009, Texas Instruments Incorporated ns 30 10 50 ns 30 5 50 ns 30 8 HVD3088E tPZH(SHDN) ns 3 HVD3088E tPLZ 30 1.5 HVD3088E HVD3082E HVD3085E ns 10 HVD3088E tPZL 200 100 HVD3088E tr ns 100 HVD3088E HVD3082E HVD3085E Pulse skew (|tPHL - tPLH|) UNIT 50 ns 30 1600 3500 ns 1700 3500 ns Submit Documentation Feedback Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E 5 SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E SLLS562G - AUGUST 2009 - REVISED MAY 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION NOTE: Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 (unless otherwise specified). II A IOA 27 W VOD 0 V or 3 V B 50 pF 27 W IOB VOC Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading 375 W IOA VOD 0 V or 3 V 60 W 375 W IOB VTEST = -7 V to 12 V VTEST Figure 2. Driver Test Circuit, VOD With Common-Mode Loading 27 W A Signal Generator 50 W 27 W B 50 pF VA -3.25 V VB -1.75 V VOC VOC(PP) DVOC(SS) VOC Figure 3. Driver VOC Test Circuit and Waveforms 3V 1.5 V Input 1.5 V 0V RL = 50 W Signal Generator VOD tPHL tPLH CL = 50 pF 50 W 0V Output tr 90% 10% tf VOD(H) VOD(L) Figure 4. Driver Switching Test Circuit and Waveforms 6 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E www.ti.com SLLS562G - AUGUST 2009 - REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION (continued) A S1 D 0 V or 3 V 3 V if Testing A Output 0 V if Testing B Output 3V 1.5 V DE 1.5 V 0V 0.5 V tPZH RL = 110 W CL = 50 pF DE Signal Generator Output B VOH 2.5 V Output 50 W VOff0 tPHZ Figure 5. Driver Enable/Disable Test Circuit and Waveforms, High Output 5V A D 0 V or 3 V 0 V if Testing A Output 3 V if Testing B Output RL = 110 W S1 3V Output B 1.5 V DE DE 0V tPZL CL = 50 pF 1.5 V tPLZ 5V Output Signal Generator 2.5 V VOL 50 W 0.5 V Figure 6. Driver Enable/Disable Test Circuit and Waveforms, Low Output IOS IO VID VO VO Voltage Source Figure 8. Receiver Switching Test Circuit and Waveforms Figure 7. Driver Short-Circuit Signal Generator 50 W Input B VID 1.5 V A B Signal Generator 50 W R CL = 15 pF IO VO 50% Input A 0V tPHL tPLH VOH 90% Output 10% tr tf VOL Figure 9. Receiver Switching Test Circuit and Waveforms Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E 7 SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E SLLS562G - AUGUST 2009 - REVISED MAY 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) VCC D DE V CC A 54 W B 1 kW R 3V RE 1.5 V 0V 0V RE Signal Generator CL = 15 pF tPZH tPHZ 50 W 1.5 V R VOH VOH -0.5 V GND Figure 10. Receiver Enable/Disable Test Circuit and Waveforms, Data Output High 0V D DE V CC A 54 W B R RE 5V 1.5 V 0V CL = 15 pF RE Signal Generator 3V 1 kW tPLZ tPZL 50 W VCC R 1.5 V VOH +0.5 V VOL Figure 11. Receiver Enable/Disable Test Circuit and Waveforms, Data Output Low VCC A 1.5 V or -1.5 V R B RE Signal Generator Switch Down for V(A) = 1.5 V Switch Up for V(A) = -1.5 V 50 W 3V 1 kW RE 1.5 V CL = 15 pF 0V tPZH(SHDN) tPZL(SHDN) 5V VOH R 1.5 V VOL 0V Figure 12. Receiver Enable From Shutdown Test Circuit and Waveforms 8 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E www.ti.com SLLS562G - AUGUST 2009 - REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION (continued) VTEST 100 W 0V Pulse Generator, 15 ms Duration, 1% Duty Cycle 15 ms -VTEST 15 ms Figure 13. Test Circuit and Waveforms, Transient Overvoltage Test DEVICE INFORMATION PIN ASSIGNMENT LOGIC DIAGRAM (POSITIVE LOGIC) D, P OR DGK PACKAGE (TOP VIEW) R 1 8 VCC RE DE D 2 7 B 3 4 6 A 5 GND D 4 3 DE 2 RE R 6 1 7 A B FUNCTION TABLE DRIVER RECEIVER OUTPUTS INPUT D INPUT DE A DIFFERENTIAL INPUTS VID = VA - VB ENABLE RE OUTPUT R H H H L H L L VID -0.2 V L L H -0.2 V < VID < -0.01 V L X L Z Z ? -0.01 V VID L H Open H H X Open Z L X H Z Z Open circuit L H Short circuit L H IDLE Bus L H X Open Z B Receiver Failsafe The differential receiver is "failsafe" to invalid bus states caused by: * open bus conditions such as a disconnected connector, * shorted bus conditions such as cable damage shorting the twisted-pair together, or * idle bus conditions that occur when no driver on the bus is actively driving In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the receiver is not indeterminate. Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E 9 SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E SLLS562G - AUGUST 2009 - REVISED MAY 2009 www.ti.com Receiver failsafe is accomplished by offsetting the receiver thresholds so that the "input indeterminate" range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than +200 mV, and must output a Low when the VID is more negative than -200 mV. The receiver parameters which determine the failsafe performance are VIT+ and VIT-and VHYS. As seen in the RECEIVER ELECTRICAL CHARACTERISTICS table, differential signals more negative than -200 mV will always cause a Low receiver output. Similarly, differential signals more positive than +200 mV will always cause a High receiver output. When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output is High. Only when the differential input is more negative than VIT-will the receiver output transition to a Low state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT-) as well as the value of VIT+. EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS DE Input D and RE Input VCC Input 50 kW 500 W VCC Input 9V 500 W 50 kW 9V A Input B Input VCC VCC 36 kW 16 V 36 kW 16 V 180 kW 180 kW Input Input 16 V 36 kW 16 V 36 kW A and B Output R Output VCC VCC 16 V 5W Output Output 16 V 10 Submit Documentation Feedback 9V Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E www.ti.com SLLS562G - AUGUST 2009 - REVISED MAY 2009 PACKAGE THERMAL INFORMATION PARAMETER TEST CONDITIONS PACKAGE Low-k board, no air flow Junction-to-ambient thermal resistance JA High-k board, no air flow MIN TYP MOSP (DGK) 266 SOIC (D) 210 PDIP (P) 155 MOSP (DGK) 180 SOIC (D) 130 PDIP (P) 70 MOSP (DGK) Junction-to-board thermal resistance JB Low-k board, no air flow Junction-to-case thermal resistance JC Input to D is a 50% duty cycle square wave at max rec'd signal rate RL = 54 VCC = 5.5 V, TJ = 130C Average power dissipation P(AVG) Thermal shut-down junction temperature TSD MAX UNIT C/W C/W 110 SOIC (D) 55 PDIP (P) 40 MOSP (DGK) 66 SOIC (D) 80 PDIP (P) 80 C/W C/W ALL HVD3082E 203 ALL HVD3085E 205 ALL HVD3088E 276 ALL 165 mW C TYPICAL CHARACTERISTICS SN65HVD3082E RMS SUPPLY CURRENT vs SIGNALING RATE BUS INPUT CURRENT vs BUS INPUT VOLTAGE 80 10 No Load, VCC = 5 V, o TA = 25 C 50% Square Wave Input ICC - Supply Current - mA II - Input Bias Current - mA 60 40 VCC = 0 V 20 VCC = 5 V 0 -20 Driver and Receiver 1 Receiver Only -40 -60 0.1 -8 -6 -4 -2 0 2 4 6 VI - Bus Input Voltage - V Figure 14. Copyright (c) 2009, Texas Instruments Incorporated 8 10 12 1 10 100 Signal Rate - kbps Figure 15. Submit Documentation Feedback Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E 11 SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E SLLS562G - AUGUST 2009 - REVISED MAY 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) SN65HVD3085E RMS SUPPLY CURRENT vs SIGNALING RATE 100 No Load, VCC = 5 V, o TA = 25 C 50% Square Wave Input ICC - Supply Current - mA ICC - Supply Current - mA 100 SN65HVD3088E RMS SUPPLY CURRENT vs SIGNAL RATE 10 Driver and Receiver 1 Receiver Only No Load, VCC = 5 V, TA = 25oC 50% Square Wave Input 10 Driver and Receiver 1 Receiver Only 0.1 0.1 1 10 1000 100 Signal Rate - kbps Figure 16. Figure 17. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs DRIVER OUTPUT CURRENT RECEIVER OUTPUT VOLTAGE vs DIFFERENTIAL INPUT VOLTAGE 5 5 o VOD - Differential Output Voltage - V 4.5 4 4.5 RL = 120W VO - Receiver Output Voltage - V TA = 25 C VCC = 5 V 3.5 3 RL = 60W 2.5 2 1.5 1 0.5 3.5 3 2.5 2 1.5 1 0.5 0 0 10 20 30 40 IO - Differential Output Current - mA Figure 18. 12 4 TA = 25oC VCC = 5 V VIC = 0.75 V Submit Documentation Feedback 50 0 -200 -180 -160 -140 -120 -100 -80 -60 -40 -20 0 VID - Differential Input Voltage - V Figure 19. Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E www.ti.com SLLS562G - AUGUST 2009 - REVISED MAY 2009 TYPICAL CHARACTERISTICS (continued) SN65HVD3088E DRIVER RISE/FALL TIME vs TEMPERATURE 10 Rise/Fall Time - ns 9 VCC = 4.5 V 8 7 VCC = 5 V VCC = 5.5 V 6 5 -40 -20 0 20 40 60 80 o TA - Temperature - C Figure 20. APPLICATION INFORMATION RT RT Note: The line should be terminated at both ends with its characteristic impedance (RT = ZO). Note: Stub lengths off the main line should be kept as short as possible. Figure 21. Typical Application Circuit Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E 13 SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E SLLS562G - AUGUST 2009 - REVISED MAY 2009 www.ti.com POWER USAGE IN AN RS-485 TRANSCEIVER Power consumption is a concern in many applications. Power supply current is delivered to the bus load as well as to the transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must drive consists of all of the receiving nodes, plus the termination resistors at each end of the bus. The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A standard defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total current supplied to all receivers can be as high as 32 mA. The HVD308xE is rated as a 1/8 unit load device. As shown in , the bus input current is less than 1/8 mA, allowing up to 256 nodes on a single bus. The current in the termination resistors depends on the differential bus voltage. The standard requires active drivers to produce at least 1.5 V of differential signal. For a bus terminated with one standard 120- resistor at each end, this sums to 25 mA differential output current whenever the bus is active. Typically the HVD308xE can drive more than 25 mA to a 60 load, resulting in a differential output voltage higher than the minimum required by the standard. (See Figure 16.) Overall, the total load current can be 60 mA to a loaded RS-485 bus. This is in addition to the current required by the transceiver itself; the HVD308xE circuitry requires only about 0.4 mA with both driver and receiver enabled, and only 0.3 mA with either the driver enabled or with the receiver enabled. In low-power shutdown mode, neither the driver nor receiver is active, and the supply current is low. Supply current increases with signaling rate primarily due to the totum pole outputs of the driver (see Figure 15). When these outputs change state, there is a moment when both the high-side and low-side output transistors are conducting and this creates a short spike in the supply current. As the frequency of state changes increases, more power is used. LOW-POWER SHUTDOWN MODE When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against inadvertently entering shutdown mode during driver/receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode, most internal circuitry is powered down, and the supply current is typically 1 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the driver switching characteristics. If the D input is open when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature. If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the bus inputs (A and B) after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the receiver switching characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation section. If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus inputs (A and B) and the driver output is driven according to the D input. Note that the state of the active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid. 14 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E www.ti.com SLLS562G - AUGUST 2009 - REVISED MAY 2009 THERMAL CHARACTERISTICS OF IC PACKAGES JA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature divided by the operating power. JA is NOT a constant and is a strong function of: * the PCB design (50% variation) * altitude (20% variation) * device power (5% variation) JA can be used to compare the thermal performance of packages if the specific test conditions are defined and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. JA is often misused when it is used to calculate junction temperatures for other installations. TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in-use condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4% to 50% difference in JA can be measured between these two test cards. JC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block. JC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a nonstandard system and junction temperatures are backed out. It can be used with JB in 1-dimensional thermal simulation of a package system. JB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate structure. JB is only defined for the high-k test card. JB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance (especially for BGA's with thermal balls) and can be used for simple 1-dimensional network analysis of package system (see Figure 22). Ambient Node qCA Calculated Surface Node qJC Calculated/Measured Junction qJB Calculated/Measured PC Board Figure 22. Thermal Resistance Copyright (c) 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E 15 SN65HVD3082E, SN75HVD3082E SN65HVD3085E, SH65HVD3088E SLLS562G - AUGUST 2009 - REVISED MAY 2009 www.ti.com REVISION HISTORY Changes from Revision F (March 2009) to Revision G Page * Added IDLE Bus to the Function Table ................................................................................................................................ 9 * Added Receiver Failsafe section .......................................................................................................................................... 9 * Added Graph - DRIVER RISE/FALL TIME vs TEMPERATURE ........................................................................................ 13 16 Submit Documentation Feedback Copyright (c) 2009, Texas Instruments Incorporated Product Folder Link(s): SN65HVD3082E SN75HVD3082E SN65HVD3085E SH65HVD3088E PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SN65HVD3082ED ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3082EDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3082EDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3082EDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3082EDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3082EDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3082EP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65HVD3082EPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN65HVD3085ED ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3085EDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3085EDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3085EDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3085EDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3085EDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3085EDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3085EDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3088ED ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3088EDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device (1) 16-Aug-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp SN65HVD3088EDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3088EDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3088EDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3088EDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3088EDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD3088EDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75HVD3082ED ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75HVD3082EDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75HVD3082EDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75HVD3082EDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75HVD3082EDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75HVD3082EDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75HVD3082EDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75HVD3082EDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN75HVD3082EP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN75HVD3082EPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SNHVD3082EDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SNHVD3082EDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM The marketing status values are defined as follows: Addendum-Page 2 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 16-Aug-2012 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN65HVD3082EDGKR Package Package Pins Type Drawing VSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65HVD3082EDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD3085EDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65HVD3085EDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN65HVD3088EDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN65HVD3088EDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SN75HVD3082EDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SN75HVD3082EDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD3082EDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 SN65HVD3082EDR SOIC D 8 2500 340.5 338.1 20.6 SN65HVD3085EDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 SN65HVD3085EDR SOIC D 8 2500 340.5 338.1 20.6 SN65HVD3088EDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 SN65HVD3088EDR SOIC D 8 2500 340.5 338.1 20.6 SN75HVD3082EDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 SN75HVD3082EDR SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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